Ensure that c906 uses only the Xuantie MMU properties

Author: rcitach

libcpu/risc-v/t-head/c906/riscv_mmu.h

@@ -19,31 +19,12 @@
 
 #undef PAGE_SIZE
 
-#if !CONFIG_XUANTIE_SVPBMT
-/*
- * RISC-V Standard Svpbmt Extension (Bit 61-62)
- * 00: PMA (Normal Memory, Cacheable, No change to implied PMA memory type)
- * 01: NC  (Non-cacheable, Weakly-ordered)
- * 10: IO  (Strongly-ordered, Non-cacheable, Non-idempotent)
- * 11: Reserved
- */
-#define PTE_PBMT_PMA  (0UL << 61)
-#define PTE_PBMT_NC   (1UL << 61)
-#define PTE_PBMT_IO   (2UL << 61)
-#define PTE_PBMT_MASK (3UL << 61)
-#else
 /* XuanTie Extension (Bit 59-63) */
 #define PTE_SEC   (1UL << 59) /* Security */
 #define PTE_SHARE (1UL << 60) /* Shareable */
 #define PTE_BUF   (1UL << 61) /* Bufferable */
 #define PTE_CACHE (1UL << 62) /* Cacheable */
 #define PTE_SO    (1UL << 63) /* Strong Order */
-/* Compatible with Standard Svpbmt */
-#define PTE_PBMT_PMA  (PTE_CACHE | PTE_BUF | PTE_SHARE)
-#define PTE_PBMT_NC   (PTE_BUF | PTE_SHARE)
-#define PTE_PBMT_IO   (PTE_SO | PTE_SHARE)
-#define PTE_PBMT_MASK (PTE_PBMT_PMA | PTE_PBMT_IO | PTE_SEC)
-#endif
 
 #define PAGE_OFFSET_SHIFT 0
 #define PAGE_OFFSET_BIT   12
@@ -84,18 +65,9 @@
 #define PAGE_ATTR_CB  (PTE_BUF | PTE_CACHE)
 #define PAGE_ATTR_DEV (PTE_SO)
 
-#if !CONFIG_XUANTIE_SVPBMT
-/*
- * Default Leaf Attribute:
- * RWX + User + Valid + Global + Accessed + Dirty + PMA(Cacheable)
- */
-#define PAGE_DEFAULT_ATTR_LEAF \
-    (PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G | PTE_PBMT_PMA | PTE_A | PTE_D)
-#else
 #define PAGE_DEFAULT_ATTR_LEAF                                         \
     (PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D | PTE_G | PTE_U | \
      PAGE_ATTR_RWX | PTE_V)
-#endif
 
 #define PAGE_DEFAULT_ATTR_NEXT (PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G)
 
@@ -117,38 +89,6 @@
 #define ARCH_VADDR_WIDTH 39
 #define SATP_MODE        SATP_MODE_SV39
 
-#if !CONFIG_XUANTIE_SVPBMT
-/*
- * Kernel Mappings
- */
-/* Device: IO Mode (Strongly Ordered) */
-#define MMU_MAP_K_DEVICE (PTE_PBMT_IO | PTE_A | PTE_D | PTE_G | PTE_W | PTE_R | PTE_V)
-
-/* RW: Non-Cacheable (NC Mode) */
-#define MMU_MAP_K_RW     (PTE_PBMT_NC | PTE_A | PTE_D | PTE_G | PAGE_ATTR_RWX | PTE_V)
-
-/* RWCB: Cacheable (PMA Mode) - Normal RAM */
-#define MMU_MAP_K_RWCB   (PTE_PBMT_PMA | PTE_A | PTE_D | PTE_G | PAGE_ATTR_RWX | PTE_V)
-
-/*
- * User Mappings
- */
-/* User RW: Non-Cacheable */
-#define MMU_MAP_U_RW   (PTE_PBMT_NC | PTE_U | PTE_A | PTE_D | PAGE_ATTR_RWX | PTE_V)
-
-/* User RWCB: Cacheable */
-#define MMU_MAP_U_RWCB (PTE_PBMT_PMA | PTE_U | PTE_A | PTE_D | PAGE_ATTR_RWX | PTE_V)
-
-/* User ROCB: Cacheable */
-#define MMU_MAP_U_ROCB (PTE_PBMT_PMA | PTE_U | PTE_A | PTE_D | PAGE_ATTR_READONLY | PTE_V)
-
-/* User RWCB: Cacheable */
-#define MMU_MAP_U_RWCB_XN (PTE_PBMT_PMA | PTE_U | PTE_A | PTE_D | PAGE_ATTR_XN | PTE_V)
-
-/* Early Mapping: Cacheable */
-#define MMU_MAP_EARLY \
-    PTE_WRAP(PAGE_ATTR_RWX | PTE_G | PTE_V | PTE_PBMT_PMA)
-#else
 #define MMU_MAP_K_DEVICE PTE_WRAP(PAGE_ATTR_DEV | PTE_G | PAGE_ATTR_XN | PTE_V)
 #define MMU_MAP_K_RWCB   PTE_WRAP(PAGE_ATTR_CB | PTE_G | PAGE_ATTR_RWX | PTE_V)
 #define MMU_MAP_K_RW     PTE_WRAP(PTE_G | PAGE_ATTR_RWX | PTE_V)
@@ -159,7 +99,6 @@
 #define MMU_MAP_U_RW      PTE_WRAP(PTE_U | PAGE_ATTR_RWX | PTE_V)
 #define MMU_MAP_EARLY \
     PTE_WRAP(PAGE_ATTR_RWX | PTE_G | PTE_V | PTE_CACHE | PTE_SHARE | PTE_BUF)
-#endif
 
 #define MMU_MAP_TRACE(attr) (attr)