From 0109d7a6c663f23f4afb59ae2749f1dae5d832fe Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Sat, 1 Aug 2026 17:54:04 +0800 Subject: [PATCH 1/3] [dm][phye] Add Mode/State and MIPI D-PHY timing helper Extend the generic PHY framework with cached mode and submode state, avoiding redundant hardware mode changes. Add MIPI D-PHY default timing calculation helpers based on pixel clock or lane high-speed clock, and expose the new API through rtdevice.h. Signed-off-by: GuEe-GUI <2991707448@qq.com> --- .../drivers/include/drivers/phye-mipi-dphy.h | 39 ++++++++++ components/drivers/include/drivers/phye.h | 14 ++++ components/drivers/include/rtdevice.h | 1 + components/drivers/phye/SConscript | 2 +- components/drivers/phye/phye-mipi-dphy.c | 71 +++++++++++++++++++ components/drivers/phye/phye.c | 32 +++++++++ 6 files changed, 158 insertions(+), 1 deletion(-) create mode 100644 components/drivers/include/drivers/phye-mipi-dphy.h create mode 100644 components/drivers/phye/phye-mipi-dphy.c diff --git a/components/drivers/include/drivers/phye-mipi-dphy.h b/components/drivers/include/drivers/phye-mipi-dphy.h new file mode 100644 index 000000000000..226862711a35 --- /dev/null +++ b/components/drivers/include/drivers/phye-mipi-dphy.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-23 GuEe-GUI first version + */ + +#ifndef __PHYE_MIPI_DPHY_H__ +#define __PHYE_MIPI_DPHY_H__ + +#include + +struct rt_phye_configure_opts_mipi_dphy +{ + rt_uint64_t hs_clk_rate; /* lane HS bit rate, Hz */ + rt_uint32_t lanes; + + rt_uint32_t lpx; + rt_uint32_t hs_prepare; + rt_uint32_t hs_zero; + rt_uint32_t hs_trail; + rt_uint32_t hs_exit; + rt_uint32_t clk_prepare; + rt_uint32_t clk_zero; + rt_uint32_t clk_pre; + rt_uint32_t clk_post; + rt_uint32_t clk_trail; +}; + +rt_err_t rt_phye_mipi_dphy_get_default_config(rt_uint64_t pixel_clock, + rt_uint32_t bpp, rt_uint32_t lanes, + struct rt_phye_configure_opts_mipi_dphy *cfg); +rt_err_t rt_phye_mipi_dphy_get_default_config_for_hsclk(rt_uint64_t hs_clk_rate, + rt_uint32_t lanes, struct rt_phye_configure_opts_mipi_dphy *cfg); + +#endif /* __PHYE_MIPI_DPHY_H__ */ diff --git a/components/drivers/include/drivers/phye.h b/components/drivers/include/drivers/phye.h index 3776cdeac920..b898e16e8e38 100644 --- a/components/drivers/include/drivers/phye.h +++ b/components/drivers/include/drivers/phye.h @@ -13,6 +13,7 @@ #include #include +#include enum rt_phye_mode { @@ -47,12 +48,18 @@ enum rt_phye_mode struct rt_phye_ops; +union rt_phye_configure_opts +{ + struct rt_phye_configure_opts_mipi_dphy mipi_dphy; +}; + struct rt_phye { struct rt_device *dev; const struct rt_phye_ops *ops; + enum rt_phye_mode mode; int init_count; int power_count; struct rt_spinlock lock; @@ -66,6 +73,7 @@ struct rt_phye_ops rt_err_t (*power_on)(struct rt_phye *phye); rt_err_t (*power_off)(struct rt_phye *phye); rt_err_t (*set_mode)(struct rt_phye *phye, enum rt_phye_mode mode, int submode); + rt_err_t (*configure)(struct rt_phye *phye, union rt_phye_configure_opts *opts); rt_err_t (*ofw_parse)(struct rt_phye *phye, struct rt_ofw_cell_args *phye_args); }; @@ -78,12 +86,18 @@ rt_err_t rt_phye_reset(struct rt_phye *phye); rt_err_t rt_phye_power_on(struct rt_phye *phye); rt_err_t rt_phye_power_off(struct rt_phye *phye); rt_err_t rt_phye_set_mode(struct rt_phye *phye, enum rt_phye_mode mode, int submode); +rt_err_t rt_phye_configure(struct rt_phye *phye, union rt_phye_configure_opts *opts); rt_inline rt_err_t rt_phye_set_mode_simple(struct rt_phye *phye, enum rt_phye_mode mode) { return rt_phye_set_mode(phye, mode, RT_PHYE_MODE_INVALID); } +rt_inline enum rt_phye_mode rt_phye_get_mode(struct rt_phye *phye) +{ + return phye ? phye->mode : RT_PHYE_MODE_INVALID; +} + struct rt_phye *rt_phye_get_by_index(struct rt_device *dev, int index); struct rt_phye *rt_phye_get_by_name(struct rt_device *dev, const char *id); void rt_phye_put(struct rt_phye *phye); diff --git a/components/drivers/include/rtdevice.h b/components/drivers/include/rtdevice.h index a9da14d32206..01d51df76ddf 100644 --- a/components/drivers/include/rtdevice.h +++ b/components/drivers/include/rtdevice.h @@ -111,6 +111,7 @@ extern "C" { #ifdef RT_USING_PHYE #include "drivers/phye.h" +#include "drivers/phye-mipi-dphy.h" #endif /* RT_USING_PHYE */ #ifdef RT_USING_PIC diff --git a/components/drivers/phye/SConscript b/components/drivers/phye/SConscript index 5c5fbb08e65e..1332e4801542 100644 --- a/components/drivers/phye/SConscript +++ b/components/drivers/phye/SConscript @@ -8,7 +8,7 @@ if not GetDepend(['RT_USING_PHYE']): cwd = GetCurrentDir() CPPPATH = [cwd + '/../include'] -src = ['phye.c'] +src = ['phye.c', 'phye-mipi-dphy.c'] if GetDepend(['RT_PHYE_GENERIC_USB']): src += ['phye-generic-usb.c'] diff --git a/components/drivers/phye/phye-mipi-dphy.c b/components/drivers/phye/phye-mipi-dphy.c new file mode 100644 index 000000000000..f3f2985528c0 --- /dev/null +++ b/components/drivers/phye/phye-mipi-dphy.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-23 GuEe-GUI first version + */ + +#include + +#define PSEC_PER_SEC 1000000000000ULL + +static rt_err_t phye_mipi_dphy_calc_config(rt_uint64_t pixel_clock, + rt_uint32_t bpp, rt_uint32_t lanes, rt_uint64_t hs_clk_rate, + struct rt_phye_configure_opts_mipi_dphy *cfg) +{ + rt_uint64_t ui; + + if (!cfg) + { + return -RT_EINVAL; + } + + if (!hs_clk_rate) + { + if (!pixel_clock || !bpp || !lanes) + { + return -RT_EINVAL; + } + + hs_clk_rate = pixel_clock * bpp / lanes; + } + + ui = (PSEC_PER_SEC + hs_clk_rate - 1) / hs_clk_rate; + + cfg->clk_pre = 8; + cfg->clk_prepare = 38000; + cfg->clk_zero = 262000; + cfg->clk_post = 60000 + 52 * (rt_uint32_t)ui; + cfg->clk_trail = 60000; + cfg->lpx = 50000; + cfg->hs_prepare = 40000 + 4 * (rt_uint32_t)ui; + cfg->hs_zero = 105000 + 6 * (rt_uint32_t)ui; + cfg->hs_trail = (4 * 8 * ui > 60000 + 4 * 4 * ui) ? + 4 * 8 * (rt_uint32_t)ui : 60000 + 4 * 4 * (rt_uint32_t)ui; + cfg->hs_exit = 100000; + cfg->hs_clk_rate = hs_clk_rate; + cfg->lanes = lanes; + + return RT_EOK; +} + +rt_err_t rt_phye_mipi_dphy_get_default_config(rt_uint64_t pixel_clock, + rt_uint32_t bpp, rt_uint32_t lanes, + struct rt_phye_configure_opts_mipi_dphy *cfg) +{ + return phye_mipi_dphy_calc_config(pixel_clock, bpp, lanes, 0, cfg); +} + +rt_err_t rt_phye_mipi_dphy_get_default_config_for_hsclk(rt_uint64_t hs_clk_rate, + rt_uint32_t lanes, struct rt_phye_configure_opts_mipi_dphy *cfg) +{ + if (!hs_clk_rate) + { + return -RT_EINVAL; + } + + return phye_mipi_dphy_calc_config(0, 0, lanes, hs_clk_rate, cfg); +} diff --git a/components/drivers/phye/phye.c b/components/drivers/phye/phye.c index 7dc6709682c6..15cd0ed1f012 100644 --- a/components/drivers/phye/phye.c +++ b/components/drivers/phye/phye.c @@ -224,6 +224,11 @@ rt_err_t rt_phye_set_mode(struct rt_phye *phye, enum rt_phye_mode mode, int subm err = phye->ops->set_mode(phye, mode, submode); } + if (!err) + { + phye->mode = mode; + } + rt_spin_unlock(&phye->lock); } else @@ -234,6 +239,33 @@ rt_err_t rt_phye_set_mode(struct rt_phye *phye, enum rt_phye_mode mode, int subm return err; } +rt_err_t rt_phye_configure(struct rt_phye *phye, union rt_phye_configure_opts *opts) +{ + rt_err_t err; + + if (!phye || !opts) + { + return -RT_EINVAL; + } + + err = RT_EOK; + + rt_spin_lock(&phye->lock); + + if (phye->ops->configure) + { + err = phye->ops->configure(phye, opts); + } + else + { + err = -RT_ENOSYS; + } + + rt_spin_unlock(&phye->lock); + + return err; +} + static struct rt_phye *ofw_phye_get_by_index(struct rt_ofw_node *np, int index) { struct rt_phye *phye = RT_NULL; From 62002e09260e9b6921fde3ec51f91e3229311302 Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Thu, 6 Aug 2026 23:39:03 +0800 Subject: [PATCH 2/3] style: format code with clang-format --- .../drivers/include/drivers/phye-mipi-dphy.h | 6 ++-- components/drivers/include/drivers/phye.h | 2 +- components/drivers/phye/phye-mipi-dphy.c | 33 +++++++++---------- 3 files changed, 20 insertions(+), 21 deletions(-) diff --git a/components/drivers/include/drivers/phye-mipi-dphy.h b/components/drivers/include/drivers/phye-mipi-dphy.h index 226862711a35..d14245e0b3f6 100644 --- a/components/drivers/include/drivers/phye-mipi-dphy.h +++ b/components/drivers/include/drivers/phye-mipi-dphy.h @@ -31,9 +31,9 @@ struct rt_phye_configure_opts_mipi_dphy }; rt_err_t rt_phye_mipi_dphy_get_default_config(rt_uint64_t pixel_clock, - rt_uint32_t bpp, rt_uint32_t lanes, - struct rt_phye_configure_opts_mipi_dphy *cfg); + rt_uint32_t bpp, rt_uint32_t lanes, + struct rt_phye_configure_opts_mipi_dphy *cfg); rt_err_t rt_phye_mipi_dphy_get_default_config_for_hsclk(rt_uint64_t hs_clk_rate, - rt_uint32_t lanes, struct rt_phye_configure_opts_mipi_dphy *cfg); + rt_uint32_t lanes, struct rt_phye_configure_opts_mipi_dphy *cfg); #endif /* __PHYE_MIPI_DPHY_H__ */ diff --git a/components/drivers/include/drivers/phye.h b/components/drivers/include/drivers/phye.h index b898e16e8e38..f35630d415d4 100644 --- a/components/drivers/include/drivers/phye.h +++ b/components/drivers/include/drivers/phye.h @@ -59,7 +59,7 @@ struct rt_phye const struct rt_phye_ops *ops; - enum rt_phye_mode mode; + enum rt_phye_mode mode; int init_count; int power_count; struct rt_spinlock lock; diff --git a/components/drivers/phye/phye-mipi-dphy.c b/components/drivers/phye/phye-mipi-dphy.c index f3f2985528c0..63ec91f82626 100644 --- a/components/drivers/phye/phye-mipi-dphy.c +++ b/components/drivers/phye/phye-mipi-dphy.c @@ -10,11 +10,11 @@ #include -#define PSEC_PER_SEC 1000000000000ULL +#define PSEC_PER_SEC 1000000000000ULL static rt_err_t phye_mipi_dphy_calc_config(rt_uint64_t pixel_clock, - rt_uint32_t bpp, rt_uint32_t lanes, rt_uint64_t hs_clk_rate, - struct rt_phye_configure_opts_mipi_dphy *cfg) + rt_uint32_t bpp, rt_uint32_t lanes, rt_uint64_t hs_clk_rate, + struct rt_phye_configure_opts_mipi_dphy *cfg) { rt_uint64_t ui; @@ -35,32 +35,31 @@ static rt_err_t phye_mipi_dphy_calc_config(rt_uint64_t pixel_clock, ui = (PSEC_PER_SEC + hs_clk_rate - 1) / hs_clk_rate; - cfg->clk_pre = 8; + cfg->clk_pre = 8; cfg->clk_prepare = 38000; - cfg->clk_zero = 262000; - cfg->clk_post = 60000 + 52 * (rt_uint32_t)ui; - cfg->clk_trail = 60000; - cfg->lpx = 50000; - cfg->hs_prepare = 40000 + 4 * (rt_uint32_t)ui; - cfg->hs_zero = 105000 + 6 * (rt_uint32_t)ui; - cfg->hs_trail = (4 * 8 * ui > 60000 + 4 * 4 * ui) ? - 4 * 8 * (rt_uint32_t)ui : 60000 + 4 * 4 * (rt_uint32_t)ui; - cfg->hs_exit = 100000; + cfg->clk_zero = 262000; + cfg->clk_post = 60000 + 52 * (rt_uint32_t)ui; + cfg->clk_trail = 60000; + cfg->lpx = 50000; + cfg->hs_prepare = 40000 + 4 * (rt_uint32_t)ui; + cfg->hs_zero = 105000 + 6 * (rt_uint32_t)ui; + cfg->hs_trail = (4 * 8 * ui > 60000 + 4 * 4 * ui) ? 4 * 8 * (rt_uint32_t)ui : 60000 + 4 * 4 * (rt_uint32_t)ui; + cfg->hs_exit = 100000; cfg->hs_clk_rate = hs_clk_rate; - cfg->lanes = lanes; + cfg->lanes = lanes; return RT_EOK; } rt_err_t rt_phye_mipi_dphy_get_default_config(rt_uint64_t pixel_clock, - rt_uint32_t bpp, rt_uint32_t lanes, - struct rt_phye_configure_opts_mipi_dphy *cfg) + rt_uint32_t bpp, rt_uint32_t lanes, + struct rt_phye_configure_opts_mipi_dphy *cfg) { return phye_mipi_dphy_calc_config(pixel_clock, bpp, lanes, 0, cfg); } rt_err_t rt_phye_mipi_dphy_get_default_config_for_hsclk(rt_uint64_t hs_clk_rate, - rt_uint32_t lanes, struct rt_phye_configure_opts_mipi_dphy *cfg) + rt_uint32_t lanes, struct rt_phye_configure_opts_mipi_dphy *cfg) { if (!hs_clk_rate) { From 9d7a62bcc97d7d3dc2a40c5365b480aa6e645712 Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Fri, 7 Aug 2026 08:52:36 +0800 Subject: [PATCH 3/3] style: format complete changed files with clang-format --- components/drivers/include/drivers/phye.h | 4 ++-- components/drivers/include/rtdevice.h | 3 +-- components/drivers/phye/phye.c | 4 ++-- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/components/drivers/include/drivers/phye.h b/components/drivers/include/drivers/phye.h index f35630d415d4..143a7d75e191 100644 --- a/components/drivers/include/drivers/phye.h +++ b/components/drivers/include/drivers/phye.h @@ -60,8 +60,8 @@ struct rt_phye const struct rt_phye_ops *ops; enum rt_phye_mode mode; - int init_count; - int power_count; + int init_count; + int power_count; struct rt_spinlock lock; }; diff --git a/components/drivers/include/rtdevice.h b/components/drivers/include/rtdevice.h index 01d51df76ddf..1bcb23798e11 100644 --- a/components/drivers/include/rtdevice.h +++ b/components/drivers/include/rtdevice.h @@ -38,7 +38,7 @@ extern "C" { #endif -#define RT_DEVICE(device) ((rt_device_t)device) +#define RT_DEVICE(device) ((rt_device_t)device) #ifdef RT_USING_DM #include "drivers/core/dm.h" @@ -244,7 +244,6 @@ extern "C" { #endif /* RT_USING_DM && RT_USING_SDHCI */ #endif /* RT_USING_SDIO */ - #ifdef RT_USING_WDT #include "drivers/dev_watchdog.h" #endif /* RT_USING_WDT */ diff --git a/components/drivers/phye/phye.c b/components/drivers/phye/phye.c index 15cd0ed1f012..cf7aeca8f02c 100644 --- a/components/drivers/phye/phye.c +++ b/components/drivers/phye/phye.c @@ -270,8 +270,8 @@ static struct rt_phye *ofw_phye_get_by_index(struct rt_ofw_node *np, int index) { struct rt_phye *phye = RT_NULL; #ifdef RT_USING_OFW - rt_err_t err; - struct rt_ofw_node *phye_np; + rt_err_t err; + struct rt_ofw_node *phye_np; struct rt_ofw_cell_args phye_args; if (!rt_ofw_parse_phandle_cells(np, "phys", "#phy-cells", index, &phye_args))