diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 090b7c012905..f0543b97ad7c 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -464,7 +464,8 @@ "hpmicro/hpm6800evk", "hpmicro/hpm6e00evk", "hpmicro/hpm6p00evk", - "hpmicro/hpm5e00evk" + "hpmicro/hpm5e00evk", + "hpmicro/hpm5100evk" ] }, { diff --git a/.github/membrowse-targets.json b/.github/membrowse-targets.json index 10c12b7aa58e..a08a70283670 100644 --- a/.github/membrowse-targets.json +++ b/.github/membrowse-targets.json @@ -193,6 +193,20 @@ "bsp/hpmicro/tools" ] }, + { + "target_name": "hpmicro-hpm5100evk", + "toolchain": "riscv32-unknown-elf-multilib", + "bsp_path": "bsp/hpmicro/hpm5100evk", + "elf": "bsp/hpmicro/hpm5100evk/rtthread.elf", + "ld": "bsp/hpmicro/hpm5100evk/board/linker_scripts/gcc/flash_rtt.ld", + "map_file": "", + "linker_vars": "", + "watch_paths": [ + "bsp/hpmicro/hpm5100evk", + "bsp/hpmicro/libraries", + "bsp/hpmicro/tools" + ] + }, { "target_name": "xuantie-e901plus", "toolchain": "xuantie-elf-newlib", diff --git a/.github/workflows/manual_trigger_scons_except_STM32_all.yml b/.github/workflows/manual_trigger_scons_except_STM32_all.yml index 85ab16cb4999..cac5f842af58 100644 --- a/.github/workflows/manual_trigger_scons_except_STM32_all.yml +++ b/.github/workflows/manual_trigger_scons_except_STM32_all.yml @@ -124,8 +124,9 @@ jobs: - {RTT_BSP_NAME: "hc32l196", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hc32l196"} - {RTT_BSP_NAME: "hifive1", RTT_TOOL_CHAIN: "sourcery-riscv-none-embed", RTT_BSP: "hifive1"} #- {RTT_BSP_NAME: "hk32_hk32f030c8-mini", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hk32/hk32f030c8-mini"} #scons dist有问题 - - {RTT_BSP_NAME: "hpmicro_hpm6750evk", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hpmicro/hpm6750evk"} - - {RTT_BSP_NAME: "hpmicro_hpm6750evkmini", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hpmicro/hpm6750evkmini"} + - {RTT_BSP_NAME: "hpmicro_hpm5100evk", RTT_TOOL_CHAIN: "RISC-V-GCC-RV32", RTT_BSP: "hpmicro/hpm5100evk"} + - {RTT_BSP_NAME: "hpmicro_hpm6750evk", RTT_TOOL_CHAIN: "RISC-V-GCC-RV32", RTT_BSP: "hpmicro/hpm6750evk"} + - {RTT_BSP_NAME: "hpmicro_hpm6750evkmini", RTT_TOOL_CHAIN: "RISC-V-GCC-RV32", RTT_BSP: "hpmicro/hpm6750evkmini"} - {RTT_BSP_NAME: "ht32f12366", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "ht32/ht32f12366"} - {RTT_BSP_NAME: "ht32f52352", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "ht32/ht32f52352"} #- {RTT_BSP_NAME: "imx_imx6ull-smart", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imx/imx6ull-smart"} # toolchain还没支持 @@ -294,7 +295,7 @@ jobs: steps: - uses: actions/checkout@main - name: Set up Python - uses: actions/setup-python@v3 + uses: actions/setup-python@main with: python-version: 3.8 @@ -305,9 +306,11 @@ jobs: wget https://raw.githubusercontent.com/RT-Thread/env/master/install_ubuntu.sh chmod 777 install_ubuntu.sh ./install_ubuntu.sh + pip install -r tools/requirements.txt git config --global http.postBuffer 524288000 echo "RTT_ROOT=${{ github.workspace }}" >> $GITHUB_ENV echo "RTT_CC=gcc" >> $GITHUB_ENV + echo "export PATH=~/.env/tools/scripts:$PATH" > ~/.env/env.sh - name: Install Arm ToolChains if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-arm' && success() }} @@ -344,6 +347,14 @@ jobs: /opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc --version echo "RTT_EXEC_PATH=/opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin" >> $GITHUB_ENV + - name: Install riscv32-unknown-elf ToolChains + if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'RISC-V-GCC-RV32' && success() }} + run: | + wget -q https://github.com/hpmicro/riscv-gnu-toolchain/releases/download/2022.05.15/riscv32-unknown-elf-newlib-multilib_2022.05.15_linux.tar.gz + sudo tar zxf riscv32-unknown-elf-newlib-multilib_2022.05.15_linux.tar.gz -C /opt + /opt/riscv32-unknown-elf-newlib-multilib/bin/riscv32-unknown-elf-gcc --version + echo "RTT_EXEC_PATH=/opt/riscv32-unknown-elf-newlib-multilib/bin/" >> $GITHUB_ENV + - name: Install Riscv-none-embed ToolChains if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-riscv-none-embed' && success() }} run: | @@ -373,7 +384,7 @@ jobs: RTT_BSP: ${{ matrix.legs.RTT_BSP }} RTT_TOOL_CHAIN: ${{ matrix.legs.RTT_TOOL_CHAIN }} run: | - # source ~/.env/env.sh + source ~/.env/env.sh echo $RTT_BSP ls bsp/$RTT_BSP/Kconfig && scons -C bsp/$RTT_BSP --pyconfig-silent sed -i "s/# ${{ github.event.inputs.bsp_config }} is not set/${{ github.event.inputs.bsp_config }}=y/g" bsp/$RTT_BSP/.config @@ -386,7 +397,7 @@ jobs: cp bsp/$RTT_BSP/dist/project.zip ${{ github.workspace }}/$RTT_BSP/ ls bsp/$RTT_BSP/dist pwd - - uses: actions/upload-artifact@v3 + - uses: actions/upload-artifact@main if: ${{ github.event.inputs.dist_flag }} env: RTT_BSP: ${{ matrix.legs.RTT_BSP }} diff --git a/bsp/.clang-format-ignore b/bsp/.clang-format-ignore index 7286b8f79b15..befc415a75e5 100644 --- a/bsp/.clang-format-ignore +++ b/bsp/.clang-format-ignore @@ -1 +1,2 @@ rtconfig.h +rtconfig_preinc.h diff --git a/bsp/README.md b/bsp/README.md index ac704da3f7ae..62c88b1c2e9d 100644 --- a/bsp/README.md +++ b/bsp/README.md @@ -763,6 +763,7 @@ This document is based on the RT-Thread mainline repository and categorizes the | [hpm6800evk](hpmicro/hpm6800evk) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | | [hpm6e00evk](hpmicro/hpm6e00evk) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | | [hpm6p00evk](hpmicro/hpm6p00evk) | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [hpm5100evk](hpmicro/hpm5100evk) | ✅ | ✅ | ✅ | ✅ | - | - | - | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | #### 🟢 K230 (RT-Smart) diff --git a/bsp/hpmicro/.clang-format-ignore b/bsp/hpmicro/.clang-format-ignore index 8d88b7152f55..ee0d8d7fc645 100644 --- a/bsp/hpmicro/.clang-format-ignore +++ b/bsp/hpmicro/.clang-format-ignore @@ -1,3 +1,4 @@ # clang-format ignore file /**/startup/ -/libraries/hpm_sdk/ +/**/board/ +/libraries/ diff --git a/bsp/hpmicro/.gitignore b/bsp/hpmicro/.gitignore new file mode 100644 index 000000000000..f866a6c2e361 --- /dev/null +++ b/bsp/hpmicro/.gitignore @@ -0,0 +1,2 @@ +# HPMicro SDK is fetched as an RT-Thread package into the shared libraries dir +/libraries/hpm_sdk-*/ diff --git a/bsp/hpmicro/.ignore_format.yml b/bsp/hpmicro/.ignore_format.yml new file mode 100644 index 000000000000..276544a2499e --- /dev/null +++ b/bsp/hpmicro/.ignore_format.yml @@ -0,0 +1,36 @@ +# Exclude the files that are kept in sync with the upstream HPMicro sources +# (the all-in-one tree / hpm_sdk) from the changed-file checks, as already done +# for clang-format in .clang-format-ignore. +# +# tools/ci/cpp_check.py runs cppcheck with a minimal configuration (only +# '-I include -I thread/components/finsh'), so it cannot resolve the hpm_sdk +# macros used in these files (e.g. ATTR_PLACE_AT) and it reports the linker +# script symbol arithmetic in c_startup() as 'subtractPointers'; both are +# false positives for code that is not ours to restructure. + +dir_path: +- hpm5100evk/board +- hpm5100evk/startup +- hpm5300evk/board +- hpm5300evk/startup +- hpm5301evklite/board +- hpm5301evklite/startup +- hpm5e00evk/board +- hpm5e00evk/startup +- hpm6200evk/board +- hpm6200evk/startup +- hpm6300evk/board +- hpm6300evk/startup +- hpm6750evk/board +- hpm6750evk/startup +- hpm6750evk2/board +- hpm6750evk2/startup +- hpm6750evkmini/board +- hpm6750evkmini/startup +- hpm6800evk/board +- hpm6800evk/startup +- hpm6e00evk/board +- hpm6e00evk/startup +- hpm6p00evk/board +- hpm6p00evk/startup +- libraries diff --git a/bsp/hpmicro/README.md b/bsp/hpmicro/README.md index 5d21c2380e71..bc8cbf1d9643 100644 --- a/bsp/hpmicro/README.md +++ b/bsp/hpmicro/README.md @@ -33,6 +33,7 @@ Below is a comprehensive list of HPMicro BSPs currently supported: | hpm6800evk | HPM6800EVK | HPM6800 | Development board for HPM6800 series | | hpm6e00evk | HPM6E00EVK | HPM6E00 | Development board for HPM6E00 series | | hpm6p00evk | HPM6P00EVK | HPM6P00 | Development board for HPM6P00 series | +| hpm5100evk | HPM5100EVK | HPM5100 | Development board for HPM5100 series | ## Quick Start Guide @@ -120,7 +121,7 @@ Additional peripherals may be supported depending on the specific board: - HPM6E00EVK - HPM6P00EVK - HPM5E00EVK -- **CAN**: Available on HPM6750 series Development Boards, HPM5300EVK, HPM6800EVK, HPM6E00EVK, HPM6P00EVK and HPM5E00EVK +- **CAN**: Available on HPM6750 series Development Boards, HPM5300EVK, HPM6800EVK, HPM6E00EVK, HPM6P00EVK, HPM5E00EVK and HPM5100EVK - **SDIO**: Available on HPM6300EVK, HPM6750EVKMINI, HPM6750EVK, HPM6750EVK2 and HPM6800EVK - **Display/Audio**: Available on HPM6750EVK, HPM6800EVK, HPM6E00EVK，HPM6P00EVK @@ -153,6 +154,7 @@ Please refer to the individual BSP directories for detailed documentation: - `hpm6800evk/README.md` - `hpm6e00evk/README.md` - `hpm6p00evk/README.md` +- `hpm5100evk/README.md` ## Troubleshooting diff --git a/bsp/hpmicro/README_zh.md b/bsp/hpmicro/README_zh.md index ac006d2f9284..a2115c6a5505 100644 --- a/bsp/hpmicro/README_zh.md +++ b/bsp/hpmicro/README_zh.md @@ -33,6 +33,7 @@ | hpm6800evk | HPM6800EVK | HPM6800 | HPM6800 系列开发板 | | hpm6e00evk | HPM6E00EVK | HPM6E00 | HPM6E00 系列开发板 | | hpm6p00evk | HPM6P00EVK | HPM6P00 | HPM6P00 系列开发板 | +| hpm5100evk | HPM5100EVK | HPM5100 | HPM5100 系列开发板 | ## 快速开始指南 @@ -120,7 +121,7 @@ msh > - HPM6E00EVK - HPM6P00EVK - HPM5E00EVK -- **CAN**：HPM5300EVK、HPM6750系列开发板，HPM6300EVK，HPM6800EVK, HPM6E00EVK, HPM6P00EVK 和HPM5E00EVK +- **CAN**：HPM5300EVK、HPM6750系列开发板，HPM6300EVK，HPM6800EVK, HPM6E00EVK, HPM6P00EVK、HPM5E00EVK 和HPM5100EVK - **SDIO**：HPM6300EVK、HPM6750EVK 系列可用 - **显示/音频**：HPM6750EVK 系列可用 @@ -152,6 +153,7 @@ msh > - `hpm6800evk/README.md` - `hpm6e00evk/README.md` - `hpm6p00evk/README.md` +- `hpm5100evk/README.md` ## 故障排除 diff --git a/bsp/hpmicro/hpm5100evk/.config b/bsp/hpmicro/hpm5100evk/.config new file mode 100644 index 000000000000..aadef66475b3 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/.config @@ -0,0 +1,1573 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50301 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set +CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_CLOCK_TIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_NES_SIMULATOR is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_SORCH is not set +# CONFIG_PKG_USING_DICT is not set +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# CONFIG_PKG_USING_EVENT_LOOP is not set +# CONFIG_PKG_USING_THREAD_MANAGER is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +CONFIG_PKG_USING_HPM_SDK=y +CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_V113=y +# CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION is not set +CONFIG_PKG_HPM_SDK_VER="v1.13.0" +# end of HPMicro SDK + +# +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_SERIES_HPM5100=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HPM5100=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_GPIO_IRQ_PRIORITY=1 +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_UART0_RX_USING_DMA is not set +# CONFIG_BSP_UART0_TX_USING_DMA is not set +CONFIG_BSP_UART0_RX_BUFSIZE=128 +CONFIG_BSP_UART0_TX_BUFSIZE=0 +CONFIG_BSP_UART0_IRQ_PRIORITY=1 +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_PUART is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2S is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_GPTMRV2 is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_ACMP is not set +# CONFIG_BSP_USING_OPAMP is not set +# CONFIG_BSP_USING_MCAN is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_WDG is not set +# CONFIG_BSP_USING_EWDG is not set +# CONFIG_BSP_USING_TSNS is not set +# CONFIG_BSP_USING_PTPC is not set +# CONFIG_BSP_USING_MCHTMR is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SOFT_SPI is not set +# end of On-chip Peripheral Drivers + +# +# HPMicro Interrupt Config +# + +# +# HPMicro RT-Thread Interrupt Framework +# + +# +# HPMicro Use Generic Startup Implementation +# +# end of HPMicro Use Generic Startup Implementation + +# +# HPMicro RT-Thread backtrace configuration (experimental) +# +# CONFIG_HPM_ENABLE_RTTHREAD_BACKTRACE_PORT is not set +# CONFIG_HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER is not set +# end of HPMicro RT-Thread backtrace configuration (experimental) +# end of Hardware Drivers Config + +# +# Third-Party Add-ons +# + +# +# Segger SystemView Config +# +# CONFIG_BSP_USING_SYSTEMVIEW is not set +# end of Segger SystemView Config + +# +# RT-Thread Insight Config +# +# CONFIG_BSP_USING_RTI is not set +# end of RT-Thread Insight Config +# end of Third-Party Add-ons diff --git a/bsp/hpmicro/hpm5100evk/.cproject b/bsp/hpmicro/hpm5100evk/.cproject new file mode 100644 index 000000000000..b7f94f01bb2a --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/.cproject @@ -0,0 +1,227 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hpmicro/hpm5100evk/.project b/bsp/hpmicro/hpm5100evk/.project new file mode 100644 index 000000000000..0d08d5512da7 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/.project @@ -0,0 +1,27 @@ + + + blink_led + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.rt-thread.studio.rttnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/bsp/hpmicro/hpm5100evk/.settings/org.eclipse.core.runtime.prefs b/bsp/hpmicro/hpm5100evk/.settings/org.eclipse.core.runtime.prefs new file mode 100644 index 000000000000..9f1acfcfba24 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/.settings/org.eclipse.core.runtime.prefs @@ -0,0 +1,3 @@ +content-types/enabled=true +content-types/org.eclipse.cdt.core.asmSource/file-extensions=s +eclipse.preferences.version=1 \ No newline at end of file diff --git a/bsp/hpmicro/hpm5100evk/.settings/projcfg.ini b/bsp/hpmicro/hpm5100evk/.settings/projcfg.ini new file mode 100644 index 000000000000..671d4a8a91fd --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/.settings/projcfg.ini @@ -0,0 +1,20 @@ +#RT-Thread Studio Project Configuration +# Fri Apr 25 13:53:29 2025 +cfg_version=v3.0 + +board_name= +bsp_version= +bsp_path= +chip_name= +project_base_rtt_bsp=true +is_use_scons_build=true +hardware_adapter= +selected_rtt_version=latest +board_base_nano_proj=false +is_base_example_project=false +example_name= +project_type=rt-thread +os_branch=master +os_version=latest +project_name=blink_led +output_project_path=D:\oss\rt-thread\bsp\hpmicro\hpm5100evk \ No newline at end of file diff --git a/bsp/hpmicro/hpm5100evk/Kconfig b/bsp/hpmicro/hpm5100evk/Kconfig new file mode 100644 index 000000000000..73238d3a13b2 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/hpmicro/hpm5100evk/README.md b/bsp/hpmicro/hpm5100evk/README.md new file mode 100644 index 000000000000..cfed70162b03 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/README.md @@ -0,0 +1,115 @@ +# HPMicro HPM5100EVK BSP(Board Support Package) Introduction + +[中文页](README_zh.md) | + +## Introduction + +This document provides brief introduction of the BSP (board support package) for the HPM5100EVK development board. + +The document consists of the following parts: + +- HPM5100EVK Board Resources Introduction +- Quickly Getting Started +- Refreences + +By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + +## Board Resources Introduction + +HPM5100EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for Connectivity, motor control，etc. +![board](figures/board.png) + + +## Peripheral Condition + +Each peripheral supporting condition for this BSP is as follows: + + +| **On-board Peripherals** | **Support** | **Note** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| CAN | √ | | +| AUDIO | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| PWM | √ | | +| On-Board Debugger | √ | hslink-lite | + + +## Execution Instruction + +### Quickly Getting Started + +The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command + +#### Parpare Environment +- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` +- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` + - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` + - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` + - For example: `C:\DevTools\openocd-hpmicro\bin` + +#### Configure and Build project + +Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can: + +- Configure the project via `menuconfig` in `RT-Thread ENV` +- Build the project using `scons -jN`, `N` equals to the number of CPU cores +- Clean the project using `scons -c` + +#### Hardware Connection + +- Switch BOOT pin to 2'b00 +- Connect the `PWR_DEBUG` port to PC via TYPE-C cable + + +#### Dowload / Debug + +- Users can download the project via the below command: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm5100.cfg -f board\debug_scripts\openocd\boards\hpm5100evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- Users can debug the project via the below command: + + - Connect debugger via `OpenOCD`: + +```console +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm5100.cfg -f board\debug_scripts\openocd\boards\hpm5100evk.cfg +``` + - Start Debugger via `GDB`: + +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + - In the `gdb shell`, type the following commands: + +```console +load +c +``` + +### **Running Results** + +Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically. + +Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.2.2 build Aug 16 2025 18:18:18 + 2006 - 2025 Copyright by RT-Thread team +``` + +## **References** + +- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM5100EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm5100evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm5100evk/README_zh.md b/bsp/hpmicro/hpm5100evk/README_zh.md new file mode 100644 index 000000000000..810322fbb999 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/README_zh.md @@ -0,0 +1,112 @@ +# 先楫 HPM5100EVK BSP(板级支持包)说明 + +[English](README.md) | + +## 简介 + +本文档为 HPM5100EVK 的 BSP (板级支持包) 说明。 + +本文包含如下部分: + +- HPM5100EVK 板级资源介绍 +- 快速上手指南 +- 参考链接 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 板级资源介绍 + +HPM5100EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于网络互联和电机控制等应用。 + +开发板外观如下图所示： + +![board](figures/board.png) + + +## 板载外设 + +本 BSP 目前对外设的支持情况如下: + + +| **板载外设** | **支持情况** | **备注** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| PWM | √ | | +| 板载调试器 | √ | hslink-lite | + + +## 使用说明 + +### 快速开始 + +本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。 + +#### 准备环境 +- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` +- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` + - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` + +#### 配置和构建工程 + +通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以: + +- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能 +- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数 +- 通过 `scons -c` 命令清除构建 + +#### 硬件连接 + +- 将BOOT 引脚拨到2'b00 +- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑 + +#### 下载 和 调试 + +- 通过如下命令完成下载: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm5100.cfg -f board\debug_scripts\openocd\boards\hpm5100evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- 通过如下命令实现调试: + + - 通过 `OpenOCD` 来连接开发板: +```console +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm5100.cfg -f board\debug_scripts\openocd\boards\hpm5100evk.cfg +``` + - 通过 `GDB` 实现调试: +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + + - 在`GDB Shell`中使用如下命令来加载和运行: + +```console +load +c +``` + +### **运行结果** + +一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。 + +配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志： + +``` + \ | / +- RT - Thread Operating System + / | \ 5.2.2 build Aug 16 2025 18:18:18 + 2006 - 2025 Copyright by RT-Thread team +``` + +## **参考链接** + +- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM5100EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm5100evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm5100evk/SConscript b/bsp/hpmicro/hpm5100evk/SConscript new file mode 100644 index 000000000000..606b65445b0a --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/SConscript @@ -0,0 +1,16 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hpmicro/hpm5100evk/SConstruct b/bsp/hpmicro/hpm5100evk/SConstruct new file mode 100644 index 000000000000..c0ae22c1c28f --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/SConstruct @@ -0,0 +1,83 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + if GetOption('clean'): + return + + need_update = True + + if os.path.isdir("packages"): + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +AddOption('--run', + dest = 'run', + type='string', + nargs=1, + action = 'store', + default = "", + help = 'Upload or debug application using openocd') + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): + libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries') +else: + libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') + + +GDB = rtconfig.GDB + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + + + +# includes rtt drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'), variant_dir='build/libraries/drivers', duplicate=0)) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'misc', 'SConscript'), variant_dir='build/libraries/misc', duplicate=0)) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm5100evk/applications/SConscript b/bsp/hpmicro/hpm5100evk/applications/SConscript new file mode 100644 index 000000000000..00bf6b8d8f7e --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/applications/SConscript @@ -0,0 +1,12 @@ +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPDEFINES=[] +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5100evk/applications/main.c b/bsp/hpmicro/hpm5100evk/applications/main.c new file mode 100644 index 000000000000..ce90f2deffb7 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/applications/main.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * Change Logs: + * Date Author Notes + * 2021-08-13 Fan YANG first version + * + */ + +#include +#include +#include "rtt_board.h" + +void thread_entry(void *arg); + +int main(void) +{ + app_init_led_pins(); + + static uint32_t led_thread_arg = 0; + rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); + if (led_thread != RT_NULL) + { + rt_thread_startup(led_thread); + } + + return 0; +} + +void thread_entry(void *arg) +{ + while (1) + { + app_led_write(0, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(0, APP_LED_OFF); + rt_thread_mdelay(500); + } +} diff --git a/bsp/hpmicro/hpm5100evk/board/Kconfig b/bsp/hpmicro/hpm5100evk/board/Kconfig new file mode 100644 index 000000000000..8844405bb448 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/Kconfig @@ -0,0 +1,740 @@ +menu "Hardware Drivers Config" + +config SOC_HPM5100 + bool + select SOC_SERIES_HPM5100 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN if BSP_USING_GPIO + default n + if BSP_USING_GPIO + config BSP_GPIO_IRQ_PRIORITY + int "GPIO Interrupt Priority" + range 1 7 + default 1 + endif + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + + if BSP_USING_UART + menuconfig BSP_USING_UART0 + bool "Enable UART0 (Debugger)" + default y + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART0_IRQ_PRIORITY + int "UART0 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART0_DMA_PINGPONG_BUFSIZE + int "Set UART0 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART0_RX_USING_DMA + default 128 + endif + + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART1_IRQ_PRIORITY + int "UART1 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART1_DMA_PINGPONG_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 128 + endif + + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART2_IRQ_PRIORITY + int "UART2 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART2_DMA_PINGPONG_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 128 + endif + + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART3_IRQ_PRIORITY + int "UART3 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART3_DMA_PINGPONG_BUFSIZE + int "Set UART3 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA + default 128 + endif + + menuconfig BSP_USING_PUART + bool "Enable PUART" + default n + if BSP_USING_PUART + config BSP_PUART_RX_BUFSIZE + int "Set PUART RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_PUART_TX_BUFSIZE + int "Set PUART TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_PUART_IRQ_PRIORITY + int "PUART Interrupt Priority" + range 1 7 + default 1 + endif + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C" + default n + select RT_USING_I2C if BSP_USING_I2C + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default y + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + config BSP_I2C0_IRQ_PRIORITY + int "I2C0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool "Enable I2C1 DMA" + default n + config BSP_I2C1_IRQ_PRIORITY + int "I2C1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool "Enable I2C2 DMA" + default n + config BSP_I2C2_IRQ_PRIORITY + int "I2C2 Interrupt Priority" + range 1 7 + default 1 + endif + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI if BSP_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0" + default n + if BSP_USING_SPI0 + config BSP_SPI0_USING_DMA + bool "Enable SPI0 DMA" + default n + config BSP_SPI0_IRQ_PRIORITY + int "SPI0 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI0 CS TYPE" + default BSP_SPI0_USING_SOFT_CS + config BSP_SPI0_USING_SOFT_CS + bool "Enable SPI0 software cs" + config BSP_SPI0_USING_HARD_CS + bool "Enable SPI0 hardware cs" + endchoice + choice + prompt "Select SPI0 IO mode" + default BSP_SPI0_USING_SINGLE_IO + config BSP_SPI0_USING_SINGLE_IO + bool "Enable SPI0 single IO mode" + config BSP_SPI0_USING_DUAL_IO + bool "Enable SPI0 dual IO mode" + config BSP_SPI0_USING_QUAD_IO + bool "Enable SPI0 quad IO mode" + endchoice + endif + config BSP_USING_SPI1 + bool "Enable SPI1" + default n + if BSP_USING_SPI1 + config BSP_SPI1_USING_DMA + bool "Enable SPI1 DMA" + default n + config BSP_SPI1_IRQ_PRIORITY + int "SPI1 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI1 CS TYPE" + default BSP_SPI1_USING_SOFT_CS + config BSP_SPI1_USING_SOFT_CS + bool "Enable SPI1 software cs" + config BSP_SPI1_USING_HARD_CS + bool "Enable SPI1 hardware cs" + endchoice + choice + prompt "Select SPI1 IO mode" + default BSP_SPI1_USING_SINGLE_IO + config BSP_SPI1_USING_SINGLE_IO + bool "Enable SPI1 single IO mode" + config BSP_SPI1_USING_DUAL_IO + bool "Enable SPI1 dual IO mode" + config BSP_SPI1_USING_QUAD_IO + bool "Enable SPI1 quad IO mode" + endchoice + endif + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + if BSP_USING_SPI2 + config BSP_SPI2_USING_DMA + bool "Enable SPI2 DMA" + default n + config BSP_SPI2_IRQ_PRIORITY + int "SPI2 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI2 CS TYPE" + default BSP_SPI2_USING_SOFT_CS + config BSP_SPI2_USING_SOFT_CS + bool "Enable SPI2 software cs" + config BSP_SPI2_USING_HARD_CS + bool "Enable SPI2 hardware cs" + endchoice + choice + prompt "Select SPI2 IO mode" + default BSP_SPI2_USING_SINGLE_IO + config BSP_SPI2_USING_SINGLE_IO + bool "Enable SPI2 single IO mode" + config BSP_SPI2_USING_DUAL_IO + bool "Enable SPI2 dual IO mode" + config BSP_SPI2_USING_QUAD_IO + bool "Enable SPI2 quad IO mode" + endchoice + endif + config BSP_USING_SPI3 + bool "Enable SPI3" + default y + if BSP_USING_SPI3 + config BSP_SPI3_USING_DMA + bool "Enable SPI3 DMA" + default n + config BSP_SPI3_IRQ_PRIORITY + int "SPI3 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI3 CS TYPE" + default BSP_SPI3_USING_SOFT_CS + config BSP_SPI3_USING_SOFT_CS + bool "Enable SPI3 software cs" + config BSP_SPI3_USING_HARD_CS + bool "Enable SPI3 hardware cs" + endchoice + choice + prompt "Select SPI3 IO mode" + default BSP_SPI3_USING_SINGLE_IO + config BSP_SPI3_USING_SINGLE_IO + bool "Enable SPI3 single IO mode" + config BSP_SPI3_USING_DUAL_IO + bool "Enable SPI3 dual IO mode" + config BSP_SPI3_USING_QUAD_IO + bool "Enable SPI3 quad IO mode" + endchoice + endif + endif + + menuconfig BSP_USING_I2S + bool "Enable I2S" + default n + select RT_USING_I2S if BSP_USING_I2S + if BSP_USING_I2S + config BSP_USING_I2S0 + bool "Enable I2S0" + default n + if BSP_USING_I2S0 + config BSP_I2S0_USING_DMA + bool "Enable I2S0 DMA" + default n + config BSP_I2S0_IRQ_PRIORITY + int "I2S0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2S1 + bool "Enable I2S1" + default n + if BSP_USING_I2S1 + config BSP_I2S1_USING_DMA + bool "Enable I2S1 DMA" + default n + config BSP_I2S1_IRQ_PRIORITY + int "I2S1 Interrupt Priority" + range 1 7 + default 1 + endif + endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + + menuconfig BSP_USING_GPTMRV2 + bool "Enable GPTMR" + default n + select RT_USING_CLOCK_TIME if BSP_USING_GPTMRV2 + if BSP_USING_GPTMRV2 + config BSP_USING_GPTMR0 + bool "Enable GPTMR0" + depends on !HPM_USING_VECTOR_PREEMPTED_MODE + default n + if BSP_USING_GPTMR0 + config BSP_GPTMR0_IRQ_PRIORITY + int "GPTMR0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + if BSP_USING_GPTMR1 + config BSP_GPTMR1_IRQ_PRIORITY + int "GPTMR1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_PTMR + bool "Enable PTMR" + default n + if BSP_USING_PTMR + config BSP_PTMR_IRQ_PRIORITY + int "PTMR Interrupt Priority" + range 1 7 + default 1 + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" + default y + if BSP_USING_ADC16 + config BSP_USING_ADC0 + bool "Enable ADC0" + default y + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + config BSP_USING_ADC3 + bool "Enable ADC3" + default n + endif + endif + + menuconfig BSP_USING_ACMP + bool "Enable ACMP (Analog Comparator)" + default n + if BSP_USING_ACMP + config BSP_USING_ACMP0 + bool "Enable ACMP0" + default n + config BSP_USING_ACMP1 + bool "Enable ACMP1" + default n + endif + + menuconfig BSP_USING_OPAMP + bool "Enable OPAMP (Operational Amplifier)" + default n + if BSP_USING_OPAMP + config BSP_USING_OPAMP0 + bool "Enable OPAMP0" + default n + config BSP_USING_OPAMP1 + bool "Enable OPAMP1" + default n + config BSP_USING_OPAMP2 + bool "Enable OPAMP2" + default n + config BSP_USING_OPAMP3 + bool "Enable OPAMP3" + default n + endif + + menuconfig BSP_USING_MCAN + bool "Enable MCAN" + default n + select RT_USING_CAN if BSP_USING_MCAN + if BSP_USING_MCAN + config BSP_USING_MCAN0 + bool "Enable MCAN0" + default n + if BSP_USING_MCAN0 + config BSP_MCAN0_IRQ_PRIORITY + int "MCAN0 Interrupt Priority" + range 1 7 + default 1 + endif + endif + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + if BSP_USING_USB + config BSP_USING_USB_DEVICE + bool "Enable USB Device" + select RT_USING_CACHE + default n + config BSP_USING_USB_HOST + bool "Enable USB HOST" + select RT_USING_CACHE + default n + endif + + menuconfig BSP_USING_WDG + bool "Enable WDG" + default n + select RT_USING_WDT if BSP_USING_WDG + if BSP_USING_WDG + config BSP_USING_WDG0 + bool "Enable WDG0" + default y + config BSP_USING_WDG1 + bool "Enable WDG1" + default n + endif + + menuconfig BSP_USING_EWDG + bool "Enable EWDG" + default n + select RT_USING_WDT if BSP_USING_EWDG + if BSP_USING_EWDG + config BSP_USING_EWDG0 + bool "Enable EWDG0" + default n + config BSP_USING_EWDG1 + bool "Enable EWDG1" + default n + endif + + menuconfig BSP_USING_TSNS + bool "Enable TSNS (Temperature Sensor)" + default n + + menuconfig BSP_USING_PTPC + bool "Enable PTPC (PTP Controller)" + default n + + menuconfig BSP_USING_MCHTMR + bool "Enable MCHTMR (Machine Timer)" + default n + + menuconfig BSP_USING_SOFT_I2C + bool "Enable Software I2C" + default n + select RT_USING_I2C if BSP_USING_SOFT_I2C + if BSP_USING_SOFT_I2C + + config BSP_USING_SOFT_I2C_TIMING_DELAY_US + int "Soft I2C timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_I2C_TIMING_TIMEOUT + int "Soft I2C timing timeout" + range 10 10000 + default 100 + + config BSP_USING_SOFT_I2C0 + bool "Enable Soft I2C0" + default n + if BSP_USING_SOFT_I2C0 + config BSP_SOFT_I2C0_SCL_PIN + string "Soft I2C0 SCL pin name" + default "None" + config BSP_SOFT_I2C0_SDA_PIN + string "Soft I2C0 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C1 + bool "Enable Soft I2C1" + default n + if BSP_USING_SOFT_I2C1 + config BSP_SOFT_I2C1_SCL_PIN + string "Soft I2C1 SCL pin name" + default "None" + config BSP_SOFT_I2C1_SDA_PIN + string "Soft I2C1 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C2 + bool "Enable Soft I2C2" + default n + if BSP_USING_SOFT_I2C2 + config BSP_SOFT_I2C2_SCL_PIN + string "Soft I2C2 SCL pin name" + default "None" + config BSP_SOFT_I2C2_SDA_PIN + string "Soft I2C2 SDA pin name" + default "None" + endif + + endif + + menuconfig BSP_USING_SOFT_SPI + bool "Enable Software SPI" + default n + select RT_USING_SPI if BSP_USING_SOFT_SPI + select RT_USING_PIN if BSP_USING_SOFT_SPI + select RT_USING_SPI_BITOPS if BSP_USING_SOFT_SPI + if BSP_USING_SOFT_SPI + + config BSP_USING_SOFT_SPI_TIMING_DELAY_US + int "Soft SPI timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_SPI0 + bool "Enable Soft SPI0" + default n + if BSP_USING_SOFT_SPI0 + config BSP_SOFT_SPI0_SCK_PIN + string "Soft SPI0 SCK pin name" + default "None" + config BSP_SOFT_SPI0_MOSI_PIN + string "Soft SPI0 MOSI pin name" + default "None" + config BSP_SOFT_SPI0_MISO_PIN + string "Soft SPI0 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI1 + bool "Enable Soft SPI1" + default n + if BSP_USING_SOFT_SPI1 + config BSP_SOFT_SPI1_SCK_PIN + string "Soft SPI1 SCK pin name" + default "None" + config BSP_SOFT_SPI1_MOSI_PIN + string "Soft SPI1 MOSI pin name" + default "None" + config BSP_SOFT_SPI1_MISO_PIN + string "Soft SPI1 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI2 + bool "Enable Soft SPI2" + default n + if BSP_USING_SOFT_SPI2 + config BSP_SOFT_SPI2_SCK_PIN + string "Soft SPI2 SCK pin name" + default "None" + config BSP_SOFT_SPI2_MOSI_PIN + string "Soft SPI2 MOSI pin name" + default "None" + config BSP_SOFT_SPI2_MISO_PIN + string "Soft SPI2 MISO pin name" + default "None" + endif + + endif + +endmenu + +menu "HPMicro Interrupt Config" +endmenu + +menu "HPMicro RT-Thread Interrupt Framework" +endmenu + +menu "HPMicro Use Generic Startup Implementation" + config HPM_BSP_USING_GENERIC_STARTUP + bool "Enable this to use the common/startup/generic implementation" + default n + depends on HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + help + Enable this to use the common/startup/generic implementation. + This option is only available when RT-Thread Interrupt Framework is enabled. +endmenu + +menu "HPMicro RT-Thread backtrace configuration (experimental)" + config HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Enable RT-Thread Backtrace for HPMicro BSP" + default n + help + Enable RT-Thread Backtrace to support backtrace feature + + config HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER + select HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Use RT-Thread Backtrace in Exception Handler" + default n + help + Use RT-Thread Backtrace in Exception Handler to print backtrace information +endmenu + +endmenu + +menu "Third-Party Add-ons" + +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + endif +endmenu + +menu "RT-Thread Insight Config" + config BSP_USING_RTI + select BSP_USING_MCHTMR + select RT_USING_RTI + select RT_USING_RT_TUNNEL + bool "Enable RT-Thread Insight(experimental)" + default n + + if BSP_USING_RTI + config RT_TUNNEL_USE_NONCACHE_RAM + bool "Enable RT-Thread Insight Non-cacheable RAM support" + default y + help + Enable this to use non-cacheable RAM for RT-Thread Insight data transfer. + This option is useful when RT-Thread Insight is used with cache enabled. + + endif + +endmenu + +endmenu diff --git a/bsp/hpmicro/hpm5100evk/board/SConscript b/bsp/hpmicro/hpm5100evk/board/SConscript new file mode 100644 index 000000000000..aeb0cee8b26d --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/SConscript @@ -0,0 +1,19 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers +src = Split(""" + board.c + rtt_board.c + pinmux.c + fal_flash_port.c + fal_spi_flash_sfud_port.c +""") + +CPPPATH = [cwd] +CPPDEFINES=['D25', 'HPM5151'] + +group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5100evk/board/board.c b/bsp/hpmicro/hpm5100evk/board/board.c new file mode 100644 index 000000000000..d9515366de46 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/board.c @@ -0,0 +1,666 @@ +/* + * Copyright (c) 2026 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "hpm_uart_drv.h" +#include "hpm_gptmrv2_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_usb_drv.h" +#include "hpm_clock_drv.h" +#include "hpm_pllctlv2_drv.h" +#include "hpm_i2c_drv.h" +#include "hpm_pcfg_drv.h" +#include +#include + + +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 114MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +#if defined(FLASH_XIP) && FLASH_XIP +__attribute__ ((section(".nor_cfg_option"), used)) const uint32_t option[4] = {0xfcf90002, 0x00000005, 0x1000, 0x0}; +#endif + +#if defined(FLASH_UF2) && FLASH_UF2 +ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +#endif + +void board_init_console(void) +{ +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART + console_config_t cfg; + + /* uart needs to configure pin function before enabling clock, otherwise the level change of + * uart rx pin when configuring pin function will cause a wrong data to be received. + * And a uart rx dma request will be generated by default uart fifo dma trigger level. + */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); + + clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); + + cfg.type = BOARD_CONSOLE_TYPE; + cfg.base = (uint32_t)BOARD_CONSOLE_UART_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE; + + if (status_success != console_init(&cfg)) { + /* failed to initialize debug console */ + while (1) { + } + } +#else + while (1) + ; +#endif +#endif +} + +void board_print_banner(void) +{ + const uint8_t banner[] = "\n" +"----------------------------------------------------------------------\n" +"$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n" +"$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n" +"$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n" +"$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n" +"$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n" +"$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n" +"$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$\\ $$ | \\$$$$$$ |\n" +"\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n" +"----------------------------------------------------------------------\n"; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif + printf("%s", banner); +} + +void board_print_clock_freq(void) +{ + printf("==============================\n"); + printf(" %s clock summary\n", BOARD_NAME); + printf("==============================\n"); + printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb)); + printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); + printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); + printf("==============================\n"); +} + +void board_init(void) +{ + init_py_pins_as_pgpio(); + board_init_usb_dp_dm_pins(); + + board_init_clock(); + board_init_console(); + board_init_pmp(); +#if BOARD_SHOW_CLOCK + board_print_clock_freq(); +#endif +#if BOARD_SHOW_BANNER + board_print_banner(); +#endif +} + +void board_init_usb_dp_dm_pins(void) +{ + /* Disconnect usb dp/dm pins pull down 45ohm resistance */ + + while (sysctl_resource_any_is_busy(HPM_SYSCTL)) { + ; + } + if (pllctlv2_xtal_is_stable(HPM_PLLCTLV2) && pllctlv2_xtal_is_enabled(HPM_PLLCTLV2)) { + if (clock_check_in_group(clock_usb0, 0)) { + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + } else { + clock_add_to_group(clock_usb0, 0); + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + clock_remove_from_group(clock_usb0, 0); + } + } else { + uint8_t tmp; + tmp = sysctl_resource_target_get_mode(HPM_SYSCTL, sysctl_resource_xtal); + sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03); /* NOLINT */ + clock_add_to_group(clock_usb0, 0); + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + clock_remove_from_group(clock_usb0, 0); + while (sysctl_resource_target_is_busy(HPM_SYSCTL, sysctl_resource_usb0)) { + ; + } + sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, tmp); + } +} + +void board_init_clock(void) +{ + uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + + if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { + /* Configure the External OSC ramp-up time: ~9ms */ + pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U); + + /* Select clock setting preset1 */ + sysctl_clock_set_preset(HPM_SYSCTL, 2); + } + + /* group0[0] */ + clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_ahb, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_mchtmr0, 0); + clock_add_to_group(clock_rom, 0); + clock_add_to_group(clock_mot0, 0); + clock_add_to_group(clock_gpio, 0); + clock_add_to_group(clock_hdma0, 0); + clock_add_to_group(clock_hdma1, 0); + clock_add_to_group(clock_xpi0, 0); + clock_add_to_group(clock_ptpc, 0); + + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + + /* Bump up LDO voltage to 1175mv */ + pcfg_ldo1p1_set_voltage(HPM_PCFG, 1175); + + /* Configure CPU to 360MHz, AHB to 180MHz. */ + clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 2);; + + /* Configure mchtmr to 24MHz */ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); + + clock_update_core_clock(); +} + +/*============================================================================== + * RT-Thread peripheral pin dispatch wrappers + * These dispatch to the pinmux-generated init_xxx_pins() functions + *============================================================================*/ + +void init_py_pins_as_pgpio(void) +{ + /* Set PY00-PY07 default function to PGPIO */ + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_PGPIO_Y_00; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_PGPIO_Y_01; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_PGPIO_Y_02; + HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = PIOC_PY03_FUNC_CTL_PGPIO_Y_03; + HPM_PIOC->PAD[IOC_PAD_PY04].FUNC_CTL = PIOC_PY04_FUNC_CTL_PGPIO_Y_04; + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_PGPIO_Y_05; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_PGPIO_Y_06; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_PGPIO_Y_07; +} + +void init_uart_pins(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + init_uart0_pins(); + } else if (ptr == HPM_UART2) { + init_uart2_pins(); + } else if (ptr == HPM_UART3) { + init_uart3_pins(); + } +} + +hpm_stat_t init_i2c_pins(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + init_i2c0_pins(); + return status_success; + } else if (ptr == HPM_I2C1) { + init_i2c1_pins(); + return status_success; + } else if (ptr == HPM_I2C2) { + init_i2c2_pins(); + return status_success; + } + return status_invalid_argument; +} + +void init_can_pins(MCAN_Type *ptr) +{ + if (ptr == HPM_MCAN0) { + init_mcan0_pins(); + } +} + +void init_usb_pins(USB_Type *ptr) +{ + if (ptr == HPM_USB0) { + init_usb0_pins(); + } +} + +void init_spi_pins(SPI_Type *ptr) +{ + if (ptr == HPM_SPI3) { + init_spi3_pins(); + } else if (ptr == HPM_SPI0) { + init_spi_nor_flash_pins(); + } +} + +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI3) { + init_spi3_pins_with_gpio_as_cs(); + } else if (ptr == HPM_SPI0) { + init_spi_nor_flash_pins_with_gpio_as_cs(); + } +} + +void init_gptmr_channel_pin(GPTMRV2_Type *ptr, uint32_t channel, bool as_comp) +{ + if (ptr == HPM_GPTMR0) { + if (as_comp) { + if (channel == 0) { + init_gptmr0_channel0_pin_as_output(); + } else if (channel == 1) { + init_gptmr0_channel1_pin_as_output(); + } else if (channel == 3) { + init_gptmr0_channel3_pin_as_output(); + } + } else { + init_gptmr0_channel0_pin_as_capture(); + } + } +} + +void init_pwm_pins(PWM_Type *ptr) +{ + if (ptr == HPM_PWM0) { + init_pwm0_pins(); + } else if (ptr == HPM_PWM1) { + init_pwm1_pins(); + } else if (ptr == HPM_PWM2) { + init_pwm2_pins(); + } else if (ptr == HPM_PWM3) { + init_pwm3_pins(); + } +} + +void board_delay_us(uint32_t us) +{ + rt_hw_us_delay(us); +} + +void board_delay_ms(uint32_t ms) +{ + while (ms--) + { + rt_hw_us_delay(1000); + } +} + +#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT +static board_timer_cb timer_cb; +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr) +void board_timer_isr(void) +{ + if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { + gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); + timer_cb(); + } +} + +void board_timer_create(uint32_t ms, board_timer_cb cb) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + timer_cb = cb; + gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); + + clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000 * ms; + gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); + gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); + intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); + + gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); +} +#endif + +void board_init_gpio_pins(void) +{ + init_gpio_pins(); + gpio_set_pin_input(BOARD_APP_GPIO_CTRL, BOARD_APP_GPIO_INDEX, BOARD_APP_GPIO_PIN); +} + +void board_init_led_pins(void) +{ + init_led_pins_as_gpio(); + gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level()); +} + +void board_init_usb(USB_Type *ptr) +{ + if (ptr == HPM_USB0) { + init_usb_pins(ptr); + clock_add_to_group(clock_usb0, 0); + + usb_hcd_set_power_ctrl_polarity(ptr, true); + /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ + board_delay_ms(100); + + /* As QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */ + usb_phy_using_internal_vbus(ptr); + } +} + +void board_led_write(uint8_t state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +void board_led_toggle(void) +{ + gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); +} + +void board_init_uart(UART_Type *ptr) +{ + /* configure uart's pin before opening uart's clock */ + init_uart_pins(ptr); + board_init_uart_clock(ptr); +} + +void board_ungate_mchtmr_at_lp_mode(void) +{ + /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ + sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock); +} + +uint32_t board_init_spi_clock(SPI_Type *ptr) +{ + if (ptr == HPM_SPI3) { + clock_add_to_group(clock_spi3, 0); + return clock_get_frequency(clock_spi3); + } else if (ptr == HPM_SPI0) { + clock_add_to_group(clock_spi0, 0); + return clock_get_frequency(clock_spi0); + } + return 0; +} + +void board_init_spi_pins(SPI_Type *ptr) +{ + init_spi_pins(ptr); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus) +{ + uint32_t freq = 0; + + if (ptr == (void *)HPM_ADC0) { + if (clk_src_bus) { + /* Configure the ADC clock from AHB */ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk2, 2U); + } + clock_add_to_group(clock_adc0, 0); + freq = clock_get_frequency(clock_adc0); + } else if (ptr == (void *)HPM_ADC1) { + if (clk_src_bus) { + /* Configure the ADC clock from AHB */ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll1_clk2, 2U); + } + clock_add_to_group(clock_adc1, 0); + freq = clock_get_frequency(clock_adc1); + } + + return freq; +} + +void board_init_adc16_pins(void) +{ + init_adc_pins(); +} + +void board_init_acmp_pins(void) +{ + init_acmp_pins(); +} + +void board_init_acmp_clock(ACMP_Type *ptr) +{ + (void)ptr; + clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1); +} + +uint32_t board_init_dac_clock(void *ptr, bool clk_src_ahb) +{ + (void)ptr; + (void)clk_src_ahb; + return 0; +} + +void board_init_can(MCAN_Type *ptr) +{ + init_can_pins(ptr); +} + +uint32_t board_init_can_clock(MCAN_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_MCAN0) { + clock_add_to_group(clock_can0, 0); + clock_set_source_divider(clock_can0, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can0); + } + return freq; +} + +void board_init_rgb_pwm_pins(void) +{ + init_led_pins_as_pwm(); +} + +void board_disable_output_rgb_led(uint8_t color) +{ + (void) color; +} + +void board_enable_output_rgb_led(uint8_t color) +{ + (void) color; +} + +void board_init_dac_pins(void *ptr) +{ + (void)ptr; +} + +uint8_t board_get_led_pwm_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +uint8_t board_get_led_gpio_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +void board_init_pmp(void) +{ +} + +uint32_t board_init_uart_clock(UART_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_UART0) { + clock_add_to_group(clock_uart0, 0); + freq = clock_get_frequency(clock_uart0); + } else if (ptr == HPM_UART2) { + clock_add_to_group(clock_uart2, 0); + freq = clock_get_frequency(clock_uart2); + } else if (ptr == HPM_UART3) { + clock_add_to_group(clock_uart3, 0); + freq = clock_get_frequency(clock_uart3); + } + + return freq; +} + +void board_i2c_bus_clear(I2C_Type *ptr) +{ + if (i2c_get_line_scl_status(ptr) == false) { + printf("CLK is low, please power cycle the board\n"); + while (1) { + } + } + if (i2c_get_line_sda_status(ptr) == false) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + i2c_gen_reset_signal(ptr, 9); + board_delay_ms(100); + printf("I2C bus is cleared\n"); +} + +uint32_t board_init_i2c_clock(I2C_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2C0) { + clock_add_to_group(clock_i2c0, 0); + freq = clock_get_frequency(clock_i2c0); + } else if (ptr == HPM_I2C1) { + clock_add_to_group(clock_i2c1, 0); + freq = clock_get_frequency(clock_i2c1); + } else if (ptr == HPM_I2C2) { + clock_add_to_group(clock_i2c2, 0); + freq = clock_get_frequency(clock_i2c2); + } else { + ; + } + + return freq; +} + +void board_init_i2c(I2C_Type *ptr) +{ + i2c_config_t config; + hpm_stat_t stat; + uint32_t freq; + + freq = board_init_i2c_clock(ptr); + init_i2c_pins(ptr); + board_i2c_bus_clear(ptr); + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + stat = i2c_init_master(ptr, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); + while (1) { + } + } +} + +void board_init_adc_qeiv2_pins(void) +{ + init_adc_qeiv2_pins(); +} + +void board_init_gptmr_channel_pin(GPTMRV2_Type *ptr, uint32_t channel, bool as_comp) +{ + init_gptmr_channel_pin(ptr, channel, as_comp); +} + +void board_init_clk_ref_pin(void) +{ + init_clk_ref_pin(); +} + +uint32_t board_init_gptmr_clock(GPTMRV2_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr0); + } else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr1); + } else if (ptr == HPM_PTMR) { + clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_ptmr); + } else { + /* Not supported */ + } + return freq; +} diff --git a/bsp/hpmicro/hpm5100evk/board/board.h b/bsp/hpmicro/hpm5100evk/board/board.h new file mode 100644 index 000000000000..71ca2bea1e19 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/board.h @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2026 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_BOARD_H +#define _HPM_BOARD_H +#include +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_soc_feature.h" +#include "hpm_clock_drv.h" +#include "pinmux.h" +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif + +#define BOARD_NAME "hpm5100evk" +#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) + +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE HPM_CORE0 +#endif + +/* ACMP desction */ +#define BOARD_ACMP HPM_ACMP0 +#define BOARD_ACMP_CLK clock_acmp0 +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN0 +#define BOARD_ACMP_IRQ IRQn_ACMP0_0 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_1 /* align with used pin */ + +/* dma section */ +#define BOARD_APP_DMA0 HPM_HDMA0 +#define BOARD_APP_DMA1 HPM_HDMA1 +#define BOARD_APP_DMA0_IRQ IRQn_HDMA0 +#define BOARD_APP_DMA1_IRQ IRQn_HDMA1 +#define BOARD_APP_DMAMUX HPM_DMAMUX +#define TEST_DMA_CONTROLLER HPM_HDMA0 +#define TEST_DMA_IRQ IRQn_HDMA0 + +/* uart section */ +#ifndef BOARD_APP_UART_BASE +#define BOARD_APP_UART_BASE HPM_UART2 +#define BOARD_APP_UART_IRQ IRQn_UART2 +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart2 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART2_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART2_TX +#endif + +#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PC14 + +#define BOARD_APP_UART_TRIG HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 /* need to match UART instance */ +#define BOARD_UART_TRGM HPM_TRGM0 +#define BOARD_UART_TRGM_GPTMR HPM_GPTMR1 +#define BOARD_UART_TRGM_GPTMR_CLK clock_gptmr1 +#define BOARD_UART_TRGM_GPTMR_CH 2 +#define BOARD_UART_TRGM_GPTMR_INPUT HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 + +/* uart lin sample section */ +#define BOARD_UART_LIN HPM_UART3 +#define BOARD_UART_LIN_IRQ IRQn_UART3 +#define BOARD_UART_LIN_CLK_NAME clock_uart3 +#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOC +#define BOARD_UART_LIN_TX_PIN (0U) /* PC00 should align with used pin in pinmux configuration */ + +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#ifndef BOARD_CONSOLE_TYPE +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART +#endif + +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART +#ifndef BOARD_CONSOLE_UART_BASE +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX +#endif +#define BOARD_CONSOLE_UART_BAUDRATE (115200UL) +#endif +#endif + +/* usb cdc acm uart section */ +#define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE +#define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +/* rtthread-nano finsh section */ +#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE +#define BOARD_RT_CONSOLE_CLK_NAME BOARD_CONSOLE_UART_CLK_NAME +#define BOARD_RT_CONSOLE_IRQ BOARD_CONSOLE_UART_IRQ + +/* nor flash section */ +#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) +#define BOARD_FLASH_SIZE (SIZE_1MB) + +/* i2c section */ +#define BOARD_APP_I2C_BASE HPM_I2C1 +#define BOARD_APP_I2C_IRQ IRQn_I2C1 +#define BOARD_APP_I2C_CLK_NAME clock_i2c1 +#define BOARD_APP_I2C_DMA HPM_HDMA0 +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C1 + +/* gptmr section */ +#define BOARD_GPTMR HPM_GPTMR0 +#define BOARD_GPTMR_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_CHANNEL 0 +#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR0_0 +#define BOARD_GPTMR_CLK_NAME clock_gptmr0 +#define BOARD_GPTMR_PWM HPM_GPTMR0 +#define BOARD_GPTMR_PWM_CHANNEL 0 +#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR0_0 +#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr0 +#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR0 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 1 +#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr0 + +/* User LED */ +#define BOARD_LED_GPIO_CTRL HPM_GPIO0 +#define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_LED_GPIO_PIN 18 +#define BOARD_LED_GPIO_NAME "PA18" + +#define BOARD_LED_OFF_LEVEL 1 +#define BOARD_LED_ON_LEVEL 0 + +/* gpiom section */ +#define BOARD_APP_GPIOM_BASE HPM_GPIOM +#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO +#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast + +/* User button */ +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_APP_GPIO_PIN 15 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_A +#define BOARD_BUTTON_PRESSED_VALUE 0 + +/* spi section */ +#define BOARD_APP_SPI_BASE HPM_SPI3 +#define BOARD_APP_SPI_CLK_NAME clock_spi3 +#define BOARD_APP_SPI_IRQ IRQn_SPI3 +#define BOARD_APP_SPI_SCLK_FREQ (10000000UL) +#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) +#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI3_RX +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI3_TX +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PC06 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) + +/* ADC section */ +#define BOARD_APP_ADC16_NAME "ADC0" +#define BOARD_APP_ADC16_BASE HPM_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_CH_1 (2U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc0) +#define BOARD_APP_ADC16_CLK_BUS (clk_adc_src_ahb0) + +#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_pwm0 +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_TRIGO_8 +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A + +/* Flash section */ +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90002U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000006U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) + +/* MCAN section */ +#define BOARD_APP_CAN_BASE HPM_MCAN0 +#define BOARD_APP_CAN_IRQn IRQn_MCAN0 + +/* CALLBACK TIMER section */ +#define BOARD_CALLBACK_TIMER (HPM_GPTMR0) +#define BOARD_CALLBACK_TIMER_CH 3 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr0) + +/* APP PWM */ +#define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM HPM_PWM3 +#define BOARD_APP_PWM_CLOCK_NAME clock_pwm3 +#define BOARD_APP_PWM_OUT1 0 +#define BOARD_APP_PWM_OUT2 1 +#define BOARD_APP_PWM_IRQ IRQn_PWM3 +#define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM3_SYNCI +#define BOARD_APP_TRGM_PWM_INPUT HPM_TRGM0_INPUT_SRC_PWM3_TRIGO_8 + +/* moto */ +#define BOARD_MOTOR_CLK_NAME clock_mot0 + +/* OPAMP */ +#define BOARD_APP_OPAMP HPM_OPAMP3 +#define BOARD_APP_OPAMP_CLOCK clock_opa3 +#define BOARD_APP_OPAMP_INP_PAD inp_pad_vip1 + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*board_timer_cb)(void); + +void board_init(void); +void board_init_console(void); +void board_init_gpio_pins(void); +void board_init_led_pins(void); +void board_init_usb(USB_Type *ptr); +void board_led_write(uint8_t state); +void board_led_toggle(void); +void board_init_uart(UART_Type *ptr); +void board_init_spi_pins(SPI_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void board_init_adc16_pins(void); +void board_init_acmp_pins(void); +void board_init_acmp_clock(ACMP_Type *ptr); +void board_init_can(MCAN_Type *ptr); +void board_init_rgb_pwm_pins(void); +void board_disable_output_rgb_led(uint8_t color); +void board_enable_output_rgb_led(uint8_t color); +void board_init_dac_pins(void *ptr); +void board_init_usb_dp_dm_pins(void); +void board_init_clock(void); +void board_delay_us(uint32_t us); +void board_delay_ms(uint32_t ms); +void board_timer_create(uint32_t ms, board_timer_cb cb); +void board_ungate_mchtmr_at_lp_mode(void); +uint8_t board_get_led_gpio_off_level(void); +uint8_t board_get_led_pwm_off_level(void); +void board_init_pmp(void); +uint32_t board_init_uart_clock(UART_Type *ptr); +uint32_t board_init_i2c_clock(I2C_Type *ptr); +void board_init_i2c(I2C_Type *ptr); +void board_init_adc_qeiv2_pins(void); +void board_init_gptmr_channel_pin(GPTMRV2_Type *ptr, uint32_t channel, bool as_comp); +void board_init_clk_ref_pin(void); +uint32_t board_init_gptmr_clock(GPTMRV2_Type *ptr); + +/* Pin dispatch wrappers (used by RT-Thread drivers) */ +void init_pwm_pins(PWM_Type *ptr); +void init_py_pins_as_pgpio(void); +void init_uart_pins(UART_Type *ptr); +hpm_stat_t init_i2c_pins(I2C_Type *ptr); +void init_can_pins(MCAN_Type *ptr); +void init_usb_pins(USB_Type *ptr); +void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void init_gptmr_channel_pin(GPTMRV2_Type *ptr, uint32_t channel, bool as_comp); +uint32_t board_init_spi_clock(SPI_Type *ptr); +#ifdef __cplusplus +} +#endif + +#endif /* _HPM_BOARD_H */ diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/boards/hpm5100evk.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/boards/hpm5100evk.cfg new file mode 100644 index 000000000000..f46beeb8eb7e --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/boards/hpm5100evk.cfg @@ -0,0 +1,67 @@ +# Copyright (c) 2026 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# openocd flash driver argument: +# - option0: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - option1: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value + +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF00E0000 +# - base address: 0x80000000 +# - flash size: 0x2000000 +# - flash option0: 0x5 +# - flash option1: 0x1000 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF00E0000 0x5 0x1000 + +proc init_clock {} { + mww 0xF4000800 0xFFFFFFFF + mww 0xF4000810 0xFFFFFFFF + mww 0xF4000820 0xFFFFFFFF + mww 0xF4000830 0xFFFFFFFF + echo "clocks has been enabled!" +} + +$_TARGET0 configure -event reset-init { + init_clock +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg new file mode 100644 index 000000000000..d8b53cc006ff --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg @@ -0,0 +1,17 @@ +# Copyright (c) 2021-2026 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 8000 +adapter srst delay 500 + +source [find interface/cmsis-dap.cfg] + +# Transport selection, defaults to jtag +# Override with e.g.: -c "set TRANSPORT cjtag" BEFORE -f options +if { ![info exists TRANSPORT] } { + set TRANSPORT jtag +} +transport select $TRANSPORT + +reset_config srst_only diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/ft2232.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/ft2232.cfg new file mode 100644 index 000000000000..580d98ef853f --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/ft2232.cfg @@ -0,0 +1,15 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0208 0x020b +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800 + diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/ft232.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/ft232.cfg new file mode 100644 index 000000000000..4fb0fba2e70e --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/ft232.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6014 + +ftdi_layout_init 0x0018 0x001b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/jlink.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/jlink.cfg new file mode 100644 index 000000000000..fd8f04428c9b --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/jlink.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/jlink.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg new file mode 100644 index 000000000000..e9d6e6d69848 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 +reset_config srst_only + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x010b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/soc/hpm5300.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm5100.cfg similarity index 50% rename from bsp/hpmicro/hpm5300evk/board/debug_scripts/soc/hpm5300.cfg rename to bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm5100.cfg index c57a36d0174d..667aa1ae30bf 100644 --- a/bsp/hpmicro/hpm5300evk/board/debug_scripts/soc/hpm5300.cfg +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm5100.cfg @@ -1,7 +1,11 @@ -# Copyright (c) 2021 HPMicro +# Copyright (c) 2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause -set _CHIP hpm5301 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm5151 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -11,3 +15,10 @@ target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 targets $_TARGET0 + +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr_lite.cfg] + +proc reset_soc {} { + sba_write_mem 0xF410001C 24000000 +} diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common.cfg new file mode 100644 index 000000000000..ae9233e5e5b2 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common.cfg @@ -0,0 +1,29 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +source [file join [file dirname [info script]] hpm_reset.cfg] + +set dmsbcs 0x38 +set dmsbaddress0 0x39 +set dmsbdata0 0x3C + +proc target0_dmi_write_reg {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc target0_dmi_read_reg {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc sba_write_mem {addr value} { + target0_dmi_write_reg $::dmsbaddress0 ${addr} + target0_dmi_write_reg $::dmsbdata0 ${value} +} + +proc sba_read_mem {addr} { + set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }] + target0_dmi_write_reg $::dmsbcs ${sbcs} + target0_dmi_write_reg $::dmsbaddress0 ${addr} + set value [target0_dmi_read_reg $::dmsbdata0] + return ${value} +} diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg new file mode 100644 index 000000000000..4f4b6dcd86a1 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg @@ -0,0 +1,101 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# mslideleg +riscv expose_csrs 2005 +# mclk_ctl +riscv expose_csrs 2015 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# slie +riscv expose_csrs 2500 +# slip +riscv expose_csrs 2501 +# sdcause +riscv expose_csrs 2505 +# scctldata +riscv expose_csrs 2509 +# scounterinten +riscv expose_csrs 2511 +# scountermask_m +riscv expose_csrs 2513 +# scountermask_s +riscv expose_csrs 2514 +# scountermask_u +riscv expose_csrs 2515 +# scounterovf +riscv expose_csrs 2516 +# scountinhibit +riscv expose_csrs 2528 +# shpmevent3 +riscv expose_csrs 2531 +# shpmevent4 +riscv expose_csrs 2532 +# shpmevent5 +riscv expose_csrs 2533 +# shpmevent6 +riscv expose_csrs 2534 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg new file mode 100644 index 000000000000..096cee06355e --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg @@ -0,0 +1,69 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_reset.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_reset.cfg new file mode 100644 index 000000000000..681c59954789 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_reset.cfg @@ -0,0 +1,9 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +$_TARGET0 configure -event reset-deassert-pre { + sleep 1 + if {$halt} { + $::_TARGET0 arp_halt + } +} diff --git a/bsp/hpmicro/hpm5100evk/board/fal_cfg.h b/bsp/hpmicro/hpm5100evk/board/fal_cfg.h new file mode 100644 index 000000000000..07bb0c9e5318 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/fal_cfg.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#ifdef RT_USING_FAL +#define NOR_FLASH_DEV_NAME "norflash0" +#define NOR_FLASH_MEM_BASE 0x80000000UL +#define NOR_FLASH_SIZE_IN_BYTES 0x100000UL + +#define SPI_NOR_FLASH_DEV_NAME "spi_norflash0" + +/* ===================== Flash device Configuration ========================= */ +extern const struct fal_flash_dev stm32f2_onchip_flash; +extern struct fal_flash_dev nor_flash0; + +#if defined(RT_USING_SFUD) && defined(BSP_USING_SPI) +extern struct fal_flash_dev spi_nor_flash0; +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ + &spi_nor_flash0, \ +} +#else +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +#endif + +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +// #ifdef (BSP_USING_SPI) && defined(RT_USING_SFUD) && +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 256*1024, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 512*1024, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 768*1024, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "app", SPI_NOR_FLASH_DEV_NAME, 0, 6*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "fs", SPI_NOR_FLASH_DEV_NAME, 6*1024*1024, 10*1024*1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* RT_USING_FAL */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hpmicro/hpm5100evk/board/fal_flash_port.c b/bsp/hpmicro/hpm5100evk/board/fal_flash_port.c new file mode 100644 index 000000000000..6960ab7f6755 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/fal_flash_port.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-03-09 hpmicro First implementation + * 2022-08-01 hpmicro Fixed random crashing during kvdb_init + * 2022-08-03 hpmicro Improved erase speed + * 2023-05-15 hpmicro Disable global interrupt during FLASH operation for FLASH build + * + */ +#include +#include +#ifdef RT_USING_FAL +#include "fal.h" +#include "hpm_romapi.h" +#include "board.h" +#include "hpm_l1c_drv.h" + +#if defined(FLASH_XIP) && (FLASH_XIP == 1) + +static rt_base_t s_interrupt_level; +#define FAL_ENTER_CRITICAL() do {\ + rt_exit_critical();\ + fencei();\ + s_interrupt_level = rt_hw_interrupt_disable();\ + } while(0) + +#define FAL_EXIT_CRITICAL() do {\ + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\ + fencei();\ + rt_exit_critical();\ + rt_hw_interrupt_enable(s_interrupt_level);\ + } while(0) + +#define FAL_RAMFUNC __attribute__((section(".isr_vector"))) + +#else +#define FAL_ENTER_CRITICAL() rt_enter_critical() + +#define FAL_EXIT_CRITICAL() rt_exit_critical() + +#define FAL_RAMFUNC + +#endif + +/*************************************************************************************************** + * FAL Porting Guide + * + * 1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH + * must be placed at RAM or ROM code + * 2. During FLASH erase/program, it is recommended to disable the interrupt, or place the + * interrupt related codes to RAM + * + ***************************************************************************************************/ + +static int init(void); +static int read(long offset, uint8_t *buf, size_t size); +static int write(long offset, const uint8_t *buf, size_t size); +static int erase(long offset, size_t size); + +static xpi_nor_config_t s_flashcfg; + +/** + * @brief FAL Flash device context + */ +struct fal_flash_dev nor_flash0 = + { + .name = NOR_FLASH_DEV_NAME, + /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */ + .addr = NOR_FLASH_MEM_BASE, + .len = 8 * 1024 * 1024, + .blk_size = 4096, + .ops = { .init = init, .read = read, .write = write, .erase = erase }, + .write_gran = 1 + }; + +/** + * @brief FAL initialization + * This function probes the FLASH using the ROM API + */ +FAL_RAMFUNC static int init(void) +{ + int ret = RT_EOK; + xpi_nor_config_option_t cfg_option; + cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR; + cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0; + cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option); + FAL_EXIT_CRITICAL(); + if (status != status_success) + { + ret = -RT_ERROR; + } + else + { + /* update the flash chip information */ + uint32_t sector_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + uint32_t flash_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size); + nor_flash0.blk_size = sector_size; + nor_flash0.len = flash_size; + } + + return ret; +} + +/** + * @brief FAL read function + * Read data from FLASH + * @param offset FLASH offset + * @param buf Buffer to hold data read by this API + * @param size Size of data to be read + * @return actual read bytes + */ +FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size) +{ + uint32_t flash_addr = nor_flash0.addr + offset; + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size); + uint32_t aligned_size = aligned_end - aligned_start; + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_invalidate(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); + + (void) rt_memcpy(buf, (void*) flash_addr, size); + + return size; +} + +/** + * @brief Write unaligned data to the page + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size) +{ + hpm_stat_t status; + + FAL_ENTER_CRITICAL(); + status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + return -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + } + + return size; +} + +/** + * @brief FAL write function + * Write data to specified FLASH address + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size) +{ + uint32_t *src = NULL; + uint32_t buf_32[64]; + uint32_t write_size; + size_t remaining_size = size; + int ret = (int)size; + + uint32_t page_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size); + uint32_t offset_in_page = offset % page_size; + if (offset_in_page != 0) + { + uint32_t write_size_in_page = page_size - offset_in_page; + uint32_t write_page_size = MIN(write_size_in_page, size); + (void) rt_memcpy(buf_32, buf, write_page_size); + write_size = write_unaligned_page_data(offset, buf_32, write_page_size); + if (write_size < 0) + { + ret = -RT_ERROR; + goto write_quit; + } + + remaining_size -= write_page_size; + offset += write_page_size; + buf += write_page_size; + } + + while (remaining_size > 0) + { + write_size = MIN(remaining_size, sizeof(buf_32)); + rt_memcpy(buf_32, buf, write_size); + src = &buf_32[0]; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src, + offset, write_size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + break; + } + + remaining_size -= write_size; + buf += write_size; + offset += write_size; + } + +write_quit: + return ret; +} + +/** + * @brief FAL erase function + * Erase specified FLASH region + * @param offset the start FLASH address to be erased + * @param size size of the region to be erased + * @ret RT_EOK Erase operation is successful + * @retval -RT_ERROR Erase operation failed + */ +FAL_RAMFUNC static int erase(long offset, size_t size) +{ + uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U); + hpm_stat_t status; + int ret = (int)size; + + uint32_t block_size; + uint32_t sector_size; + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size); + uint32_t erase_unit; + while (aligned_size > 0) + { + FAL_ENTER_CRITICAL(); + if ((offset % block_size == 0) && (aligned_size >= block_size)) + { + erase_unit = block_size; + status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + else + { + erase_unit = sector_size; + status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + break; + } + offset += erase_unit; + aligned_size -= erase_unit; + } + + return ret; +} +#endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm5100evk/board/fal_spi_flash_sfud_port.c b/bsp/hpmicro/hpm5100evk/board/fal_spi_flash_sfud_port.c new file mode 100644 index 000000000000..7eb0b417de95 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/fal_spi_flash_sfud_port.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2026-07-02 hpmicro First implementation + * + */ +#include +#if defined(RT_USING_SFUD) && defined(BSP_USING_SPI) && defined(RT_USING_FAL) +#include +#include +#include + +static int init(void); +static int read(long offset, rt_uint8_t *buf, rt_size_t size); +static int write(long offset, const rt_uint8_t *buf, rt_size_t size); +static int erase(long offset, rt_size_t size); + +static sfud_flash_t sfud_dev = NULL; +struct fal_flash_dev spi_nor_flash0 = +{ + .name = SPI_NOR_FLASH_DEV_NAME, + .addr = 0, + .len = 16 * 1024 * 1024, + .blk_size = 4096, + .ops = {init, read, write, erase}, + .write_gran = 1 +}; + +static int init(void) +{ + +#ifdef RT_USING_SFUD + /* RT-Thread RTOS platform */ + sfud_dev = rt_sfud_flash_find_by_dev_name(SPI_NOR_FLASH_DEV_NAME); +#endif + + if (NULL == sfud_dev) + { + return -1; + } + + /* update the flash chip information */ + spi_nor_flash0.blk_size = sfud_dev->chip.erase_gran; + spi_nor_flash0.len = sfud_dev->chip.capacity; + + return 0; +} + +static int read(long offset, rt_uint8_t *buf, rt_size_t size) +{ + RT_ASSERT(sfud_dev); + RT_ASSERT(sfud_dev->init_ok); + sfud_read(sfud_dev, spi_nor_flash0.addr + offset, size, buf); + + return size; +} + +static int write(long offset, const rt_uint8_t *buf, rt_size_t size) +{ + RT_ASSERT(sfud_dev); + RT_ASSERT(sfud_dev->init_ok); + if (sfud_write(sfud_dev, spi_nor_flash0.addr + offset, size, buf) != SFUD_SUCCESS) + { + return -1; + } + + return size; +} + +static int erase(long offset, rt_size_t size) +{ + RT_ASSERT(sfud_dev); + RT_ASSERT(sfud_dev->init_ok); + if (sfud_erase(sfud_dev, spi_nor_flash0.addr + offset, size) != SFUD_SUCCESS) + { + return -1; + } + + return size; +} + +#endif \ No newline at end of file diff --git a/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_usb_nic.ld b/bsp/hpmicro/hpm5100evk/board/linker_scripts/gcc/flash_rtt.ld similarity index 85% rename from bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_usb_nic.ld rename to bsp/hpmicro/hpm5100evk/board/linker_scripts/gcc/flash_rtt.ld index 366923d61aff..45bbaf5a2d80 100644 --- a/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_usb_nic.ld +++ b/bsp/hpmicro/hpm5100evk/board/linker_scripts/gcc/flash_rtt.ld @@ -1,24 +1,20 @@ /* - * Copyright 2021-2025 HPMicro + * Copyright 2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ ENTRY(_start) STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 144K; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 32K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 1M; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (w) : ORIGIN = 0x80000, LENGTH = 128K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x01080000, LENGTH = 64K - AXI_SRAM (wx) : ORIGIN = 0x01090000, LENGTH = 176K - SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xF0200000, LENGTH = 32k } __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; @@ -29,6 +25,15 @@ __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; SECTIONS { + /* Anchor the lowest LMA at the flash base address (0x80000000): objcopy takes the + * lowest LMA as the start address of the generated .bin, so without this marker the + * .bin starts at .nor_cfg_option (0x80000400). The value is all ones (erased flash), + * so programming it does not change the flash state. + */ + .flash_base ORIGIN(XPI0) : { + LONG(0xFFFFFFFF) + } > XPI0 + .nor_cfg_option __nor_cfg_option_load_addr__ : { KEEP(*(.nor_cfg_option)) } > XPI0 @@ -53,7 +58,6 @@ SECTIONS __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(16); __vector_ram_end__ = .; } > ILM @@ -84,6 +88,9 @@ SECTIONS KEEP(*mempool.o (.text .text* .rodata .rodata*)) /* RT-Thread Core End */ + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + . = ALIGN(16); __ramfunc_end__ = .; } > ILM @@ -171,10 +178,10 @@ SECTIONS .fast_ram (NOLOAD) : { KEEP(*(.fast_ram)) - } > ILM + } > DLM - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); __fast_ram_init_start__ = .; KEEP(*(.fast_ram.init)) @@ -183,19 +190,13 @@ SECTIONS . = ALIGN(8); } > DLM - .bss(NOLOAD) : { + .fast_ram.bss (NOLOAD) : { . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; . = ALIGN(8); - _end = .; - __bss_end__ = .; } > DLM /* Note: the .tbss and .tdata section should be adjacent */ @@ -274,18 +275,32 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > DLM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM .heap(NOLOAD) : { . = ALIGN(8); __heap_start__ = .; . += HEAP_SIZE; __heap_end__ = .; - } > AXI_SRAM - + } > DLM .stack(NOLOAD) : { . = ALIGN(8); @@ -297,14 +312,14 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > DLM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; . = ALIGN(8); - } > NONCACHEABLE_RAM + } > DLM .noncacheable.bss (NOLOAD) : { . = ALIGN(8); @@ -316,15 +331,9 @@ SECTIONS KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); - } > NONCACHEABLE_RAM + } > DLM .ahb_sram (NOLOAD) : { KEEP(*(.ahb_sram)) } > AHB_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - } diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/ram_sdram_rtt.ld b/bsp/hpmicro/hpm5100evk/board/linker_scripts/gcc/ram_rtt.ld similarity index 82% rename from bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/ram_sdram_rtt.ld rename to bsp/hpmicro/hpm5100evk/board/linker_scripts/gcc/ram_rtt.ld index 7b04b9be3290..e2e457c583b6 100644 --- a/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/ram_sdram_rtt.ld +++ b/bsp/hpmicro/hpm5100evk/board/linker_scripts/gcc/ram_rtt.ld @@ -1,23 +1,18 @@ /* - * Copyright 2021-2025 HPMicro + * Copyright 2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ ENTRY(_start) STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 32K; MEMORY { - ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (w) : ORIGIN = 0x80000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xF0200000, LENGTH = 32k } SECTIONS @@ -25,14 +20,14 @@ SECTIONS .start : { . = ALIGN(8); KEEP(*(.start)) - } > AXI_SRAM + } > ILM .vectors : { . = ALIGN(8); KEEP(*(.isr_vector)) KEEP(*(.vector_table)) . = ALIGN(8); - } > AXI_SRAM + } > ILM .text : { . = ALIGN(8); @@ -91,33 +86,37 @@ SECTIONS __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; - PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - } > AXI_SRAM + + } > ILM .rel : { KEEP(*(.rel*)) - } > AXI_SRAM + } > DLM .fast_ram (NOLOAD) : { KEEP(*(.fast_ram)) } > DLM - .bss(NOLOAD) : { + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; . = ALIGN(8); - _end = .; - __bss_end__ = .; } > DLM /* Note: .tbss and .tdata should be adjacent */ @@ -125,6 +124,7 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; @@ -137,6 +137,7 @@ SECTIONS __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > DLM @@ -188,7 +189,6 @@ SECTIONS KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) - . = ALIGN(8); __data_end__ = .; PROVIDE (__edata = .); @@ -201,18 +201,51 @@ SECTIONS . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > ILM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > DLM + + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; . = ALIGN(8); - } > NONCACHEABLE_RAM + } > DLM .noncacheable.bss (NOLOAD) : { . = ALIGN(8); @@ -224,33 +257,9 @@ SECTIONS KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); - } > NONCACHEABLE_RAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + } > DLM - .ahb_sram (NOLOAD) : { + .ahb_sram (NOLOAD) : { KEEP(*(.ahb_sram)) } > AHB_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE (__rt_rvstack = .); - } > DLM - - .framebuffer (NOLOAD) : { - KEEP(*(.framebuffer)) - } > SDRAM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - - } > SDRAM } diff --git a/bsp/hpmicro/hpm5100evk/board/pinmux.c b/bsp/hpmicro/hpm5100evk/board/pinmux.c new file mode 100644 index 000000000000..8c372161f5e0 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/pinmux.c @@ -0,0 +1,345 @@ + +/* + * Copyright (c) 2026 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * + * Automatically generated by HPM Pinmux Tool + * + * + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + */ + +#include "pinmux.h" +#include "board.h" +#include "hpm_trgm_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_gpiom_drv.h" + + +void init_uart0_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD; + + HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD; +} + +void init_uart2_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART2_RXD; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_SOC_GPIO_Y_06; + + HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART2_TXD; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_GPIO_Y_07; +} + +void init_uart3_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_UART3_RXD; + + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_UART3_TXD; +} + +void init_uart3_pin_as_gpio(void) +{ + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_GPIO_C_05; + HPM_IOC->PAD[IOC_PAD_PC05].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_GPIO_C_00; + HPM_IOC->PAD[IOC_PAD_PC00].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); +} + +void init_i2c0_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01; + HPM_IOC->PAD[IOC_PAD_PY01].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1); + + HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00; + HPM_IOC->PAD[IOC_PAD_PY00].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1); +} + +void init_i2c1_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PY03].FUNC_CTL = IOC_PY03_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = PIOC_PY03_FUNC_CTL_SOC_GPIO_Y_03; + HPM_IOC->PAD[IOC_PAD_PY03].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1); + + HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_I2C1_SDA; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02; + HPM_IOC->PAD[IOC_PAD_PY02].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1); +} + +void init_i2c2_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_I2C2_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PA23].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(0) | IOC_PAD_PAD_CTL_OD_SET(1); + + HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_I2C2_SDA; + HPM_IOC->PAD[IOC_PAD_PA22].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(0) | IOC_PAD_PAD_CTL_OD_SET(1); +} + +void init_i2s0_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_I2S0_BCLK; + + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_I2S0_FCLK; + + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_I2S0_MCLK; + + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_I2S0_RXD_3; + + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_I2S0_TXD_0; +} + +void init_spi3_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_SPI3_CS_0; + HPM_IOC->PAD[IOC_PAD_PC06].PAD_CTL = IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC10].PAD_CTL = IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_SPI3_MISO; + HPM_IOC->PAD[IOC_PAD_PC15].PAD_CTL = IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_SPI3_MOSI; + HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL = IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); +} + +void init_spi3_pins_with_gpio_as_cs(void) +{ + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_GPIO_C_06; + HPM_IOC->PAD[IOC_PAD_PC06].PAD_CTL = IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_DS_SET(7); + + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC10].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_SPI3_MOSI; + HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_SPI3_MISO; + HPM_IOC->PAD[IOC_PAD_PC15].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); +} + +void init_gptmr0_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_GPTMR0_CAPT_0; + + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_GPTMR0_COMP_0; + + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_GPTMR0_COMP_1; + + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_GPTMR0_COMP_3; +} + +void init_gpio_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_GPIO_A_15; + HPM_IOC->PAD[IOC_PAD_PA15].PAD_CTL = IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); +} + +void init_butn_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_GPIO_A_15; + HPM_IOC->PAD[IOC_PAD_PA15].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); +} + +void init_acmp_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_pwm0_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_PWM0_P_6; + + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_PWM0_P_5; +} + +void init_pwm1_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_PWM1_P_6; + + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_PWM1_P_7; +} + +void init_pwm2_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_PWM2_P_1; + + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_PWM2_P_5; +} + +void init_pwm3_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_PWM3_P_0; + + HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_PWM3_P_1; + + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_PWM3_P_4; + + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_PWM3_P_5; + + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_PWM3_P_6; + + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_PWM3_P_7; +} + +void init_adc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc16_diff_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc_bldc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc_qeiv2_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_usb0_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_USB0_ID; + + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_USB0_OC; + + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_USB0_PWR; +} + +void init_mcan0_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_MCAN0_RXD; + + HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_MCAN0_TXD; +} + +void init_led_pins_as_gpio(void) +{ + HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_GPIO_A_18; +} + +void init_led_pins_as_pwm(void) +{ +} + +void init_opamp_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_uart_break_signal_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_GPIO_C_14; + HPM_IOC->PAD[IOC_PAD_PC14].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); +} + +void init_gptmr0_channel0_pin_as_output(void) +{ + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_GPTMR0_COMP_0; +} + +void init_gptmr0_channel1_pin_as_output(void) +{ + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_GPTMR0_COMP_1; +} + +void init_gptmr0_channel3_pin_as_output(void) +{ + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_GPTMR0_COMP_3; +} + +void init_gptmr0_channel0_pin_as_capture(void) +{ + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_GPTMR0_CAPT_0; +} + +void init_clk_ref_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_SOC_REF1; +} + +void init_brownout_indicate_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_GPIO_A_27; +} + +void init_trgm_gptmr0_cap2_invert_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_TRGM_P_02; + + trgm_output_t trgm0_io_config0 = {0}; + trgm0_io_config0.invert = 1; + trgm0_io_config0.type = trgm_output_same_as_input; + trgm0_io_config0.input = HPM_TRGM0_INPUT_SRC_TRGM0_P02; + trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2, &trgm0_io_config0); +} + +void init_spi_nor_flash_pins_with_gpio_as_cs(void) +{ + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_SPI0_DAT2; + HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_SPI0_DAT3; + HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_SPI0_MISO; + HPM_IOC->PAD[IOC_PAD_PA12].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_SPI0_MOSI; + HPM_IOC->PAD[IOC_PAD_PA13].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_SPI0_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PA10].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_GPIO_A_11; + + gpiom_set_pin_controller(HPM_GPIOM, GPIOM_ASSIGN_GPIOA, 11, gpiom_soc_gpio0); + gpio_set_pin_output(HPM_GPIO0, GPIO_OE_GPIOA, 11); + gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 11, 1); +} + +void init_spi_nor_flash_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_SPI0_DAT2; + HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_SPI0_DAT3; + HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_SPI0_MISO; + HPM_IOC->PAD[IOC_PAD_PA12].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_SPI0_MOSI; + HPM_IOC->PAD[IOC_PAD_PA13].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_SPI0_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PA10].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_SPI0_CS_0; +} diff --git a/bsp/hpmicro/hpm5100evk/board/pinmux.h b/bsp/hpmicro/hpm5100evk/board/pinmux.h new file mode 100644 index 000000000000..496d97f2e6c0 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/pinmux.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2026 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * + * Automatically generated by HPM Pinmux Tool + * + * + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + */ + +#ifndef HPM_PINMUX_H +#define HPM_PINMUX_H + +#ifdef __cplusplus +extern "C" { +#endif + +void init_uart0_pins(void); +void init_uart2_pins(void); +void init_uart3_pins(void); +void init_uart3_pin_as_gpio(void); +void init_i2c0_pins(void); +void init_i2c1_pins(void); +void init_i2c2_pins(void); +void init_i2s0_pins(void); +void init_spi3_pins(void); +void init_spi3_pins_with_gpio_as_cs(void); +void init_gptmr0_pins(void); +void init_gpio_pins(void); +void init_butn_pins(void); +void init_acmp_pins(void); +void init_pwm0_pins(void); +void init_pwm1_pins(void); +void init_pwm2_pins(void); +void init_pwm3_pins(void); +void init_adc_pins(void); +void init_adc16_diff_pins(void); +void init_adc_bldc_pins(void); +void init_adc_qeiv2_pins(void); +void init_usb0_pins(void); +void init_mcan0_pins(void); +void init_led_pins_as_gpio(void); +void init_led_pins_as_pwm(void); +void init_opamp_pins(void); +void init_uart_break_signal_pin(void); +void init_gptmr0_channel0_pin_as_output(void); +void init_gptmr0_channel1_pin_as_output(void); +void init_gptmr0_channel3_pin_as_output(void); +void init_gptmr0_channel0_pin_as_capture(void); +void init_clk_ref_pin(void); +void init_brownout_indicate_pin(void); +void init_trgm_gptmr0_cap2_invert_pins(void); +void init_spi_nor_flash_pins(void); +void init_spi_nor_flash_pins_with_gpio_as_cs(void); + +#ifdef __cplusplus +} +#endif +#endif /* HPM_PINMUX_H */ diff --git a/bsp/hpmicro/hpm5100evk/board/rtt_board.c b/bsp/hpmicro/hpm5100evk/board/rtt_board.c new file mode 100644 index 000000000000..412a10747fbd --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/rtt_board.c @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2023-2025 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "rtt_board.h" +#include "hpm_uart_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include +#include +#include "hpm_dma_mgr.h" +#include "hpm_mchtmr_drv.h" + +extern int rt_hw_uart_init(void); +void os_tick_config(void); +void rtt_board_init(void); + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + enable_mchtmr_irq(); +} + +void rtt_board_init(void) +{ + board_init_clock(); + + /* initialize memory system + * NOTE: this must happen before board_init_console(), because the SDK console_init() + * calls setvbuf(), which allocates through the C library malloc() -> rt_malloc() and + * therefore requires the RT-Thread heap to be ready. Otherwise RT_ASSERT() fires in + * rt_smem_alloc() whenever RT_USING_DEBUG is enabled. + */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + + board_init_console(); + board_init_pmp(); + + dma_mgr_init(); + + /* Configure the OS Tick */ + os_tick_config(); + + /* Configure the USB pins*/ + board_init_usb(HPM_USB0); + + /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */ + rt_hw_uart_init(); + + /* Set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + +void app_init_led_pins(void) +{ + board_init_led_pins(); + gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN); + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, APP_LED_OFF); +} + +void app_led_write(uint32_t index, bool state) +{ + switch (index) + { + case 0: + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, state); + break; + default: + /* Suppress the toolchain warnings */ + break; + } +} + +void rt_hw_console_output(const char *str) +{ + while (*str != '\0') + { + uart_send_byte(BOARD_APP_UART_BASE, *str++); + } +} + +void app_init_usb_pins(void) +{ + board_init_usb(HPM_USB0); +} + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_tick_increase(); +} + +void rt_hw_cpu_reset(void) +{ + HPM_PPOR->RESET_ENABLE |= (1UL << 31); + HPM_PPOR->SOFTWARE_RESET = 1000U; + while(1) { + + } +} + +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); + +#ifdef RT_USING_CACHE +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) { + l1c_dc_flush((uint32_t)addr, size); + } else { + l1c_dc_invalidate((uint32_t)addr, size); + } +} +#endif + +uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk0 divided by 4 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + clock_add_to_group(clock_adc0, 0); + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk0 divided by 4 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + clock_add_to_group(clock_adc1, 0); + freq = clock_get_frequency(clock_adc1); + } + + return freq; +} + +uint32_t rtt_board_init_pwm_clock(PWM_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_PWM0) { + clock_add_to_group(clock_pwm0, 0); + freq = clock_get_frequency(clock_pwm0); + } else if (ptr == HPM_PWM1) { + clock_add_to_group(clock_pwm1, 0); + freq = clock_get_frequency(clock_pwm1); + } else if (ptr == HPM_PWM2) { + clock_add_to_group(clock_pwm2, 0); + freq = clock_get_frequency(clock_pwm2); + } else if (ptr == HPM_PWM3) { + clock_add_to_group(clock_pwm3, 0); + freq = clock_get_frequency(clock_pwm3); + } else { + + } + return freq; +} + +#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER +extern void hpm_isr_usb0(void); +RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0) +#endif \ No newline at end of file diff --git a/bsp/hpmicro/hpm5100evk/board/rtt_board.h b/bsp/hpmicro/hpm5100evk/board/rtt_board.h new file mode 100644 index 000000000000..39e627cc8dc8 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/rtt_board.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _RTT_BOARD_H +#define _RTT_BOARD_H +#include "hpm_common.h" +#include "hpm_soc.h" +#include "board.h" + +/* gpio section */ +#define APP_LED0 (0U) +#define APP_LED0_GPIO_CTRL HPM_GPIO0 +#define APP_LED0_GPIO_INDEX GPIO_DI_GPIOA +#define APP_LED0_GPIO_PIN 18 +#define APP_LED_ON (0) +#define APP_LED_OFF (1) + +/* mchtimer section */ +#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) + +/* gptmr as os_tick */ +#define BOARD_OS_TIMER HPM_GPTMR0 +#define BOARD_OS_TIMER_CH 1 +#define BOARD_OS_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0) + +/* UART section */ +#define BOARD_UART_NAME "uart2" +#define BOARD_UART_RX_BUFFER_SIZE BSP_UART2_RX_BUFSIZE + +/* PWM section */ +#define BOARD_PWM_NAME "pwm3" +#define BOARD_PWM_CHANNEL (0U) + +/* ADC section */ +#define BOARD_ADC_NAME BOARD_APP_ADC16_NAME +#define BOARD_ADC_CHANNEL BOARD_APP_ADC16_CH_1 + +#define IRQn_PendSV IRQn_DEBUG0 + +/* CAN section */ +#define BOARD_CAN_NAME "can0" +#define BOARD_CAN_HWFILTER_INDEX (1U) + +/*************************************************************** + * + * RT-Thread related definitions + * + **************************************************************/ +extern unsigned int __heap_start__; +extern unsigned int __heap_end__; + +#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__) +#define RT_HW_HEAP_END ((void*)&__heap_end__) + + +typedef struct { + uint16_t vdd; + uint8_t bus_width; + uint8_t drive_strength; +}sdxc_io_cfg_t; + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + +void app_init_led_pins(void); +void app_led_write(uint32_t index, bool state); +void app_init_usb_pins(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _RTT_BOARD_H */ diff --git a/bsp/hpmicro/hpm5100evk/figures/board.png b/bsp/hpmicro/hpm5100evk/figures/board.png new file mode 100644 index 000000000000..6783e4efb685 Binary files /dev/null and b/bsp/hpmicro/hpm5100evk/figures/board.png differ diff --git a/bsp/hpmicro/hpm5100evk/makefile.targets b/bsp/hpmicro/hpm5100evk/makefile.targets new file mode 100644 index 000000000000..8469d7d2aaf3 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/makefile.targets @@ -0,0 +1,6 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' + +*.elf: $(wildcard board/linker_scripts/gcc/*.ld) \ No newline at end of file diff --git a/bsp/hpmicro/hpm5100evk/rtconfig.h b/bsp/hpmicro/hpm5100evk/rtconfig.h new file mode 100644 index 000000000000..4ade257d72ff --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/rtconfig.h @@ -0,0 +1,475 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 16 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50301 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define ARCH_RISCV +#define ARCH_RISCV32 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 1024 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_BUF_STRATEGY_OVERWRITE +#define RT_SERIAL_USING_DMA +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +#define PKG_USING_HPM_SDK +#define PKG_USING_HPM_SDK_V113 +/* end of HPMicro SDK */ + +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_SERIES_HPM5100 + +/* Hardware Drivers Config */ + +#define SOC_HPM5100 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_GPIO_IRQ_PRIORITY 1 +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_UART0_RX_BUFSIZE 128 +#define BSP_UART0_TX_BUFSIZE 0 +#define BSP_UART0_IRQ_PRIORITY 1 +/* end of On-chip Peripheral Drivers */ + +/* HPMicro Interrupt Config */ + +/* HPMicro RT-Thread Interrupt Framework */ + +/* HPMicro Use Generic Startup Implementation */ + +/* end of HPMicro Use Generic Startup Implementation */ + +/* HPMicro RT-Thread backtrace configuration (experimental) */ + +/* end of HPMicro RT-Thread backtrace configuration (experimental) */ +/* end of Hardware Drivers Config */ + +/* Third-Party Add-ons */ + +/* Segger SystemView Config */ + +/* end of Segger SystemView Config */ + +/* RT-Thread Insight Config */ + +/* end of RT-Thread Insight Config */ +/* end of Third-Party Add-ons */ + +#endif diff --git a/bsp/hpmicro/hpm5100evk/rtconfig.py b/bsp/hpmicro/hpm5100evk/rtconfig.py new file mode 100644 index 000000000000..5febf5ae4b35 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/rtconfig.py @@ -0,0 +1,131 @@ +# Copyright 2021-2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +import os +import sys + + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path.insert(0, os.path.join(RTT_ROOT, 'tools')) + +# toolchains options +ARCH='risc-v' +CPU='hpmicro' +SOC_FAMILY='HPM5100' +CHIP_NAME='HPM5151' + +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +# Fallback toolchain info +FALLBACK_TOOLCHAIN_VENDOR='RISC-V' +FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32' +FALLBACK_TOOLCHAIN_VER='2022-04-12' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH') +if RTT_EXEC_PATH != None: + folders = RTT_EXEC_PATH.split(os.sep) + # If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO` + if 'arm_gcc' in folders and 'platform' in folders: + RTT_EXEC_PATH = '' + for path in folders: + if path != 'platform': + RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep + else: + break + RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin') + # Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio + if 'platform' in folders: + os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_RISCV_TOOLCHAIN'): + EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN') + elif RTT_EXEC_PATH: + EXEC_PATH = RTT_EXEC_PATH + else: + EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' +else: + print("CROSS_TOOL = {} not yet supported, only gcc is supported".format(CROSS_TOOL)) + exit(-1) + +if os.getenv('RTT_BUILD_TYPE'): + BUILD = os.getenv('RTT_BUILD_TYPE') +else: + BUILD = 'flash_debug' + +if PLATFORM == 'gcc': + PREFIX = 'riscv32-unknown-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + GDB = PREFIX + 'gdb' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + ARCH_ABI = ' -mcmodel=medlow ' + DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' + CFLAGS = DEVICE + AFLAGS = CFLAGS + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' + + CPATH = '' + LPATH = '' + + if BUILD == 'ram_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -Og' + LFLAGS += ' -Og' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' + elif BUILD == 'ram_release': + CFLAGS += ' -O2' + LFLAGS += ' -O2' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' + elif BUILD == 'flash_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -Og' + LFLAGS += ' -Og' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' + elif BUILD == 'flash_release': + CFLAGS += ' -O2' + LFLAGS += ' -O2' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' + else: + CFLAGS += ' -O2' + LFLAGS += ' -O2' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' + LFLAGS += ' -T ' + LINKER_FILE + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + CFLAGS = CFLAGS + ' -std=gnu11' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) \ No newline at end of file diff --git a/bsp/hpmicro/hpm5100evk/rtconfig_preinc.h b/bsp/hpmicro/hpm5100evk/rtconfig_preinc.h new file mode 100644 index 000000000000..4de2806b542e --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/rtconfig_preinc.h @@ -0,0 +1,21 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define D25 +#define HPM5151 +#define HPMSOC_HAS_HPMSDK_DMAV2 +#define HPM_SDK_L1C_NO_REENTRANT 1 +#define HPM_SOC_ISR_NUM 59 +#define RT_HW_ISR_NUM HPM_SOC_ISR_NUM +#define RT_USING_LIBC +#define RT_USING_NEWLIBC +#define USE_DMA_DECLARE_EXT_ISR_M 1 +#define _POSIX_C_SOURCE 1 +#define _REENT_SMALL +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/hpmicro/hpm5100evk/startup/HPM5151/SConscript b/bsp/hpmicro/hpm5100evk/startup/HPM5151/SConscript new file mode 100644 index 000000000000..7ade8d38e433 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/startup/HPM5151/SConscript @@ -0,0 +1,19 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the startup files + +src = Glob('*.c') + +if rtconfig.PLATFORM == 'gcc': + src += [os.path.join('toolchains', 'gcc', 'start.S')] + src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')] + +CPPPATH = [cwd] +CPPDEFINES=['D25', rtconfig.CHIP_NAME] + +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5100evk/startup/HPM5151/startup.c b/bsp/hpmicro/hpm5100evk/startup/HPM5151/startup.c new file mode 100644 index 000000000000..78705526d884 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/startup/HPM5151/startup.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include + +void system_init(void); + +extern int entry(void); + +extern void __libc_init_array(void); +extern void __libc_fini_array(void); + +void system_init(void) +{ + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); +#endif +} + +__attribute__((weak)) void c_startup(void) +{ +#ifndef __SES_RISCV + uint32_t i, size; +#ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __fast_load_addr__[]; + extern uint8_t __noncacheable_init_load_addr__[]; + extern uint8_t __data_load_addr__[]; + extern uint8_t __tdata_load_addr__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; + extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__data_load_addr__ + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); + } + + /* fast_ram bss section */ + size = __fast_ram_bss_end__ - __fast_ram_bss_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_bss_start__ + i) = 0; + } + + /* fast_ram init section LMA: etext + data length + ramfunc length + tdata length */ + size = __fast_ram_init_end__ - __fast_ram_init_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); + } +#endif +} + +__attribute__((weak)) int main(void) +{ + while(1); +} + +void reset_handler(void) +{ + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + +#ifndef __SES_RISCV + /* Do global constructors */ + __libc_init_array(); +#endif + + /* Entry function */ + entry(); +} + + +__attribute__((weak)) void _init(void) +{ +} diff --git a/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/port_gcc.S new file mode 100644 index 000000000000..fa7e7f9c1cd5 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/port_gcc.S @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "cpuport.h" + .section .text.entry, "ax" + .globl rt_hw_do_after_save_above + .type rt_hw_do_after_save_above,@function +rt_hw_do_after_save_above: + addi sp, sp, -4 + STORE ra, 0 * REGBYTES(sp) + + csrr t1, mcause + andi t1, t1, 0x3FF + /* get ISR */ + la t2, trap_entry + jalr t2 + + LOAD ra, 0 * REGBYTES(sp) + addi sp, sp, 4 + ret diff --git a/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/start.S b/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/start.S new file mode 100644 index 000000000000..4774dbd092b0 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/start.S @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + #include + #include "hpm_csr_regs.h" + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + la tp, __thread_pointer + .option pop + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef HPM_USING_VECTOR_PREEMPTED_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, SW_handler + csrw mtvec, t0 + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidently */ +1: j 1b + + .weak nmi_handler +nmi_handler: +1: j 1b + +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + .weak default_irq_handler + .align 2 +default_irq_handler: +1: j 1b + + .macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq + .endm + +#include "vectors.S" +#else + .section .vector_table, "a" + .global __vector_table + .align 9 + +__vector_table: + .rept RT_HW_ISR_NUM + .long handle_trap + .endr +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ diff --git a/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/vectors.S new file mode 100644 index 000000000000..5703e223309e --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/vectors.S @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +.section .vector_table, "a" +.global __vector_table +.align 9 + +__vector_table: + .weak default_isr_trap + .set default_isr_trap, SW_handler + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 8 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 9 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 10 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 11 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 15 /* ADC0 IRQ handler */ + IRQ_HANDLER 16 /* ADC1 IRQ handler */ + IRQ_HANDLER 17 /* ADC2 IRQ handler */ + IRQ_HANDLER 18 /* SDFM IRQ handler */ + IRQ_HANDLER 19 /* DAC0 IRQ handler */ + IRQ_HANDLER 20 /* DAC1 IRQ handler */ + IRQ_HANDLER 21 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 22 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 23 /* ACMP[2] IRQ handler */ + IRQ_HANDLER 24 /* ACMP[3] IRQ handler */ + IRQ_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_HANDLER 29 /* UART0 IRQ handler */ + IRQ_HANDLER 30 /* UART1 IRQ handler */ + IRQ_HANDLER 31 /* UART2 IRQ handler */ + IRQ_HANDLER 32 /* UART3 IRQ handler */ + IRQ_HANDLER 33 /* UART4 IRQ handler */ + IRQ_HANDLER 34 /* UART5 IRQ handler */ + IRQ_HANDLER 35 /* UART6 IRQ handler */ + IRQ_HANDLER 36 /* UART7 IRQ handler */ + IRQ_HANDLER 37 /* CAN0 IRQ handler */ + IRQ_HANDLER 38 /* CAN1 IRQ handler */ + IRQ_HANDLER 39 /* CAN2 IRQ handler */ + IRQ_HANDLER 40 /* CAN3 IRQ handler */ + IRQ_HANDLER 41 /* PTPC IRQ handler */ + IRQ_HANDLER 42 /* WDG0 IRQ handler */ + IRQ_HANDLER 43 /* WDG1 IRQ handler */ + IRQ_HANDLER 44 /* TSNS IRQ handler */ + IRQ_HANDLER 45 /* MBX0A IRQ handler */ + IRQ_HANDLER 46 /* MBX0B IRQ handler */ + IRQ_HANDLER 47 /* MBX1A IRQ handler */ + IRQ_HANDLER 48 /* MBX1B IRQ handler */ + IRQ_HANDLER 49 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 50 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 51 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 52 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 53 /* I2C0 IRQ handler */ + IRQ_HANDLER 54 /* I2C1 IRQ handler */ + IRQ_HANDLER 55 /* I2C2 IRQ handler */ + IRQ_HANDLER 56 /* I2C3 IRQ handler */ + IRQ_HANDLER 57 /* PWM0 IRQ handler */ + IRQ_HANDLER 58 /* HALL0 IRQ handler */ + IRQ_HANDLER 59 /* QEI0 IRQ handler */ + IRQ_HANDLER 60 /* PWM1 IRQ handler */ + IRQ_HANDLER 61 /* HALL1 IRQ handler */ + IRQ_HANDLER 62 /* QEI1 IRQ handler */ + IRQ_HANDLER 63 /* PWM2 IRQ handler */ + IRQ_HANDLER 64 /* HALL2 IRQ handler */ + IRQ_HANDLER 65 /* QEI2 IRQ handler */ + IRQ_HANDLER 66 /* PWM3 IRQ handler */ + IRQ_HANDLER 67 /* HALL3 IRQ handler */ + IRQ_HANDLER 68 /* QEI3 IRQ handler */ + IRQ_HANDLER 69 /* SDP IRQ handler */ + IRQ_HANDLER 70 /* XPI0 IRQ handler */ + IRQ_HANDLER 71 /* XDMA IRQ handler */ + IRQ_HANDLER 72 /* HDMA IRQ handler */ + IRQ_HANDLER 73 /* RNG IRQ handler */ + IRQ_HANDLER 74 /* USB0 IRQ handler */ + IRQ_HANDLER 75 /* PSEC IRQ handler */ + IRQ_HANDLER 76 /* PGPIO IRQ handler */ + IRQ_HANDLER 77 /* PWDG IRQ handler */ + IRQ_HANDLER 78 /* PTMR IRQ handler */ + IRQ_HANDLER 79 /* PUART IRQ handler */ + IRQ_HANDLER 80 /* FUSE IRQ handler */ + IRQ_HANDLER 81 /* SECMON IRQ handler */ + IRQ_HANDLER 82 /* RTC IRQ handler */ + IRQ_HANDLER 83 /* BUTN IRQ handler */ + IRQ_HANDLER 84 /* BGPIO IRQ handler */ + IRQ_HANDLER 85 /* BVIO IRQ handler */ + IRQ_HANDLER 86 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 87 /* SYSCTL IRQ handler */ + IRQ_HANDLER 88 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 89 /* DEBUG[1] IRQ handler */ + IRQ_HANDLER 90 /* LIN0 IRQ handler */ + IRQ_HANDLER 91 /* LIN1 IRQ handler */ + IRQ_HANDLER 92 /* LIN2 IRQ handler */ + IRQ_HANDLER 93 /* LIN3 IRQ handler */ + diff --git a/bsp/hpmicro/hpm5100evk/startup/HPM5151/trap.c b/bsp/hpmicro/hpm5100evk/startup/HPM5151/trap.c new file mode 100644 index 000000000000..470b3fe26627 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/startup/HPM5151/trap.c @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include +#include "rt_hw_stack_frame.h" + +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned +#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault +#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction +#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned +#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault +#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode +#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault +#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#ifdef DEBUG +#define RT_EXCEPTION_TRACE rt_kprintf +#else +#define RT_EXCEPTION_TRACE(...) +#endif + +typedef void (*isr_func_t)(void); + +static volatile rt_hw_stack_frame_t *s_stack_frame; + +__attribute((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void mswi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3) +{ +} + +void rt_show_stack_frame(void) +{ + RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n"); + RT_EXCEPTION_TRACE("ra : 0x%08x\r\n", s_stack_frame->ra); + RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus + RT_EXCEPTION_TRACE("t0 : 0x%08x\r\n", s_stack_frame->t0); + RT_EXCEPTION_TRACE("t1 : 0x%08x\r\n", s_stack_frame->t1); + RT_EXCEPTION_TRACE("t2 : 0x%08x\r\n", s_stack_frame->t2); + RT_EXCEPTION_TRACE("a0 : 0x%08x\r\n", s_stack_frame->a0); + RT_EXCEPTION_TRACE("a1 : 0x%08x\r\n", s_stack_frame->a1); + RT_EXCEPTION_TRACE("a2 : 0x%08x\r\n", s_stack_frame->a2); + RT_EXCEPTION_TRACE("a3 : 0x%08x\r\n", s_stack_frame->a3); + RT_EXCEPTION_TRACE("a4 : 0x%08x\r\n", s_stack_frame->a4); + RT_EXCEPTION_TRACE("a5 : 0x%08x\r\n", s_stack_frame->a5); +#ifndef __riscv_32e + RT_EXCEPTION_TRACE("a6 : 0x%08x\r\n", s_stack_frame->a6); + RT_EXCEPTION_TRACE("a7 : 0x%08x\r\n", s_stack_frame->a7); + RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); + RT_EXCEPTION_TRACE("t4 : 0x%08x\r\n", s_stack_frame->t4); + RT_EXCEPTION_TRACE("t5 : 0x%08x\r\n", s_stack_frame->t5); + RT_EXCEPTION_TRACE("t6 : 0x%08x\r\n", s_stack_frame->t6); +#endif +} + +uint32_t exception_handler(uint32_t cause, uint32_t epc) +{ + /* Unhandled Trap */ + uint32_t mdcause = read_csr(CSR_MDCAUSE); + uint32_t mtval = read_csr(CSR_MTVAL); + rt_uint32_t mscratch = read_csr(0x340); + + s_stack_frame = (rt_hw_stack_frame_t *)mscratch; + rt_show_stack_frame(); + + switch (cause) + { + case MCAUSE_INSTR_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_INSTR_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_ILLEGAL_INSTR: + RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + switch (mdcause & 0x07) + { + case 0: + RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + break; + case 1: + RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_BREAKPOINT: + RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc); + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + case 7: + RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n"); + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + default: + RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause); + break; + } + + rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra); + while(1) { + } +} + +void trap_entry(void); + +void trap_entry(void) +{ + uint32_t mcause = read_csr(CSR_MCAUSE); + uint32_t mepc = read_csr(CSR_MEPC); + uint32_t mstatus = read_csr(CSR_MSTATUS); + +#if SUPPORT_PFT_ARCH + uint32_t mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK; + uint32_t irq_index; + if (mcause & CSR_MCAUSE_INTERRUPT_MASK) + { + switch (cause_type) + { + /* Machine timer interrupt */ + case IRQ_M_TIMER: + mchtmr_isr(); + break; + /* Machine EXT interrupt */ + case IRQ_M_EXT: + /* Claim interrupt */ + irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + /* Execute EXT interrupt handler */ + if (irq_index > 0) + { + ((isr_func_t) __vector_table[irq_index])(); + /* Complete interrupt */ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + break; + /* Machine SWI interrupt */ + case IRQ_M_SOFT: + mswi_isr(); + intc_m_complete_swi(); + break; + } + } + else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE) + { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" +#ifdef __riscv_32e + "mv a0, t0\n" +#else + "mv a0, a7\n" +#endif + "call syscall_handler\n" + : : : "a4" + ); + mepc += 4; + } + else + { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} + +/** + * Trap Handler + */ +rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp) +{ +} \ No newline at end of file diff --git a/bsp/hpmicro/hpm5100evk/startup/SConscript b/bsp/hpmicro/hpm5100evk/startup/SConscript new file mode 100644 index 000000000000..11a9d203d4ce --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/startup/SConscript @@ -0,0 +1,12 @@ +# for module compiling +import os +Import('rtconfig') +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] + +objs = objs + SConscript(os.path.join(rtconfig.CHIP_NAME, 'SConscript')) + +Return('objs') \ No newline at end of file diff --git a/bsp/hpmicro/hpm5300evk/.config b/bsp/hpmicro/hpm5300evk/.config index da0ebf1b1f24..81fe5184e513 100644 --- a/bsp/hpmicro/hpm5300evk/.config +++ b/bsp/hpmicro/hpm5300evk/.config @@ -11,8 +11,18 @@ # rt_vsnprintf options # # CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_vsnprintf options # @@ -177,7 +187,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y -CONFIG_RT_VER_NUM=0x50300 +CONFIG_RT_VER_NUM=0x50301 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -236,11 +246,11 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_SERIAL_USING_DMA is not set # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -261,10 +271,10 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -457,6 +467,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -572,6 +583,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set # end of multimedia packages # @@ -631,6 +643,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set # end of tools packages # @@ -779,6 +793,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set # end of STM32 HAL & SDK Drivers # @@ -812,7 +828,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -891,11 +921,18 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HPM_SDK=y CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" -CONFIG_PKG_USING_HPM_SDK_V110=y +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_V113=y # CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION is not set -CONFIG_PKG_HPM_SDK_VER="v1.10.0" +CONFIG_PKG_HPM_SDK_VER="v1.13.0" # end of HPMicro SDK +# +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + # # FT32 HAL & SDK Drivers # @@ -904,6 +941,23 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -983,6 +1037,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set # CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set # end of sensors drivers # @@ -1037,6 +1092,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1087,6 +1143,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1104,6 +1161,9 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set # CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set # end of AI packages # @@ -1161,6 +1221,8 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set @@ -1186,6 +1248,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1425,12 +1488,12 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # end of Arduino libraries # end of RT-Thread online packages -CONFIG_SOC_HPM5300_SERIES=y +CONFIG_SOC_SERIES_HPM5300=y # # Hardware Drivers Config # -CONFIG_SOC_HPM5300=y +CONFIG_SOC_HPM5000=y # # On-chip Peripheral Drivers @@ -1442,12 +1505,14 @@ CONFIG_BSP_USING_UART0=y CONFIG_BSP_UART0_RX_BUFSIZE=128 CONFIG_BSP_UART0_TX_BUFSIZE=0 CONFIG_BSP_UART0_IRQ_PRIORITY=1 +# CONFIG_BSP_USING_UART1 is not set # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_UART4 is not set # CONFIG_BSP_USING_UART5 is not set # CONFIG_BSP_USING_UART6 is not set # CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_PUART is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_GPTMR is not set # CONFIG_BSP_USING_I2C is not set @@ -1457,5 +1522,60 @@ CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_EWDG is not set # CONFIG_BSP_USING_MCAN is not set # CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_WDG is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_TSNS is not set +# CONFIG_BSP_USING_ACMP is not set +# CONFIG_BSP_USING_OPAMP is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_QEIV2 is not set +# CONFIG_BSP_USING_QEO is not set +# CONFIG_BSP_USING_RDC is not set +# CONFIG_BSP_USING_SEI is not set +# CONFIG_BSP_USING_PLB is not set +# CONFIG_BSP_USING_MMC is not set +# CONFIG_BSP_USING_PTPC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_SDP is not set +# CONFIG_BSP_USING_MCHTMR is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SOFT_SPI is not set # end of On-chip Peripheral Drivers + +# +# HPMicro Interrupt Config +# + +# +# HPMicro RT-Thread Interrupt Framework +# + +# +# HPMicro Use Generic Startup Implementation +# +# end of HPMicro Use Generic Startup Implementation + +# +# HPMicro RT-Thread backtrace configuration (experimental) +# +# CONFIG_HPM_ENABLE_RTTHREAD_BACKTRACE_PORT is not set +# CONFIG_HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER is not set +# end of HPMicro RT-Thread backtrace configuration (experimental) # end of Hardware Drivers Config + +# +# Third-Party Add-ons +# + +# +# Segger SystemView Config +# +# CONFIG_BSP_USING_SYSTEMVIEW is not set +# end of Segger SystemView Config + +# +# RT-Thread Insight Config +# +# CONFIG_BSP_USING_RTI is not set +# end of RT-Thread Insight Config +# end of Third-Party Add-ons diff --git a/bsp/hpmicro/hpm5300evk/README.md b/bsp/hpmicro/hpm5300evk/README.md index 4e6ad210a662..b51709900c92 100644 --- a/bsp/hpmicro/hpm5300evk/README.md +++ b/bsp/hpmicro/hpm5300evk/README.md @@ -71,7 +71,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Users can download the project via the below command: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm5300.cfg -f board\debug_scripts\openocd\boards\hpm5300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - Users can debug the project via the below command: @@ -79,7 +79,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Connect debugger via `OpenOCD`: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5300evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm5300.cfg -f board\debug_scripts\openocd\boards\hpm5300evk.cfg ``` - Start Debugger via `GDB`: diff --git a/bsp/hpmicro/hpm5300evk/README_zh.md b/bsp/hpmicro/hpm5300evk/README_zh.md index 2da65d7f9d75..29d4fb396ecf 100644 --- a/bsp/hpmicro/hpm5300evk/README_zh.md +++ b/bsp/hpmicro/hpm5300evk/README_zh.md @@ -71,14 +71,14 @@ - 通过如下命令完成下载: ```console - %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\probes\ft2232.cfg -f board\debug_scripts\soc\hpm5300.cfg -f board\debug_scripts\boards\hpm5300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm5300.cfg -f board\debug_scripts\openocd\boards\hpm5300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - 通过如下命令实现调试: - 通过 `OpenOCD` 来连接开发板: ```console -%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\probes\ft2232.cfg -f board\debug_scripts\soc\hpm5300.cfg -f board\debug_scripts\boards\hpm5300evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm5300.cfg -f board\debug_scripts\openocd\boards\hpm5300evk.cfg ``` - 通过 `GDB` 实现调试: ```console diff --git a/bsp/hpmicro/hpm5300evk/SConscript b/bsp/hpmicro/hpm5300evk/SConscript index 014c428d0a37..606b65445b0a 100644 --- a/bsp/hpmicro/hpm5300evk/SConscript +++ b/bsp/hpmicro/hpm5300evk/SConscript @@ -7,7 +7,6 @@ cwd = GetCurrentDir() objs = [] list = os.listdir(cwd) -ASFLAGS = ' -I' + cwd for d in list: path = os.path.join(cwd, d) diff --git a/bsp/hpmicro/hpm5300evk/SConstruct b/bsp/hpmicro/hpm5300evk/SConstruct index 601a33ec9183..de5155656d6b 100644 --- a/bsp/hpmicro/hpm5300evk/SConstruct +++ b/bsp/hpmicro/hpm5300evk/SConstruct @@ -16,13 +16,16 @@ except: exit(-1) def bsp_pkg_check(): - import subprocess - + if GetOption('clean'): + return + need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break + + if os.path.isdir("packages"): + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break if need_update: print("\n===============================================================================") print("Dependency packages missing, please running 'pkgs --update'...") @@ -64,9 +67,6 @@ if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): else: libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - GDB = rtconfig.GDB @@ -76,6 +76,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # includes rtt drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'), variant_dir='build/libraries/drivers', duplicate=0)) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'misc', 'SConscript'), variant_dir='build/libraries/misc', duplicate=0)) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm5300evk/applications/SConscript b/bsp/hpmicro/hpm5300evk/applications/SConscript index a65aa4d8553b..00bf6b8d8f7e 100644 --- a/bsp/hpmicro/hpm5300evk/applications/SConscript +++ b/bsp/hpmicro/hpm5300evk/applications/SConscript @@ -1,5 +1,3 @@ -import rtconfig - from building import * cwd = GetCurrentDir() diff --git a/bsp/hpmicro/hpm5300evk/applications/main.c b/bsp/hpmicro/hpm5300evk/applications/main.c index 0bbf6370382c..98ea3be7a378 100644 --- a/bsp/hpmicro/hpm5300evk/applications/main.c +++ b/bsp/hpmicro/hpm5300evk/applications/main.c @@ -19,7 +19,10 @@ int main(void) { static uint32_t led_thread_arg = 0; rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); - rt_thread_startup(led_thread); + if (led_thread != RT_NULL) + { + rt_thread_startup(led_thread); + } return 0; } diff --git a/bsp/hpmicro/hpm5300evk/board/Kconfig b/bsp/hpmicro/hpm5300evk/board/Kconfig index ba0d903c261c..5763d1a2b4ba 100644 --- a/bsp/hpmicro/hpm5300evk/board/Kconfig +++ b/bsp/hpmicro/hpm5300evk/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_HPM5300 +config SOC_HPM5000 bool - select SOC_HPM5300_SERIES + select SOC_SERIES_HPM5300 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -51,6 +51,43 @@ menu "On-chip Peripheral Drivers" int "UART0 Interrupt Priority" range 1 7 default 1 + config BSP_UART0_DMA_PINGPONG_BUFSIZE + int "Set UART0 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART0_RX_USING_DMA + default 128 + endif + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default y + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART1_IRQ_PRIORITY + int "UART1 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART1_DMA_PINGPONG_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART2 bool "Enable UART2" @@ -78,6 +115,11 @@ menu "On-chip Peripheral Drivers" int "UART2 Interrupt Priority" range 1 7 default 1 + config BSP_UART2_DMA_PINGPONG_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART3 bool "Enable UART3" @@ -105,6 +147,11 @@ menu "On-chip Peripheral Drivers" int "UART3 Interrupt Priority" range 1 7 default 1 + config BSP_UART3_DMA_PINGPONG_BUFSIZE + int "Set UART3 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART4 bool "Enable UART4" @@ -132,6 +179,11 @@ menu "On-chip Peripheral Drivers" int "UART4 Interrupt Priority" range 1 7 default 1 + config BSP_UART4_DMA_PINGPONG_BUFSIZE + int "Set UART4 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART4_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART5 bool "Enable UART5" @@ -159,6 +211,11 @@ menu "On-chip Peripheral Drivers" int "UART5 Interrupt Priority" range 1 7 default 1 + config BSP_UART5_DMA_PINGPONG_BUFSIZE + int "Set UART5 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART5_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART6 bool "Enable UART6" @@ -186,6 +243,11 @@ menu "On-chip Peripheral Drivers" int "UART6 Interrupt Priority" range 1 7 default 1 + config BSP_UART6_DMA_PINGPONG_BUFSIZE + int "Set UART6 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART7 bool "Enable UART7" @@ -209,6 +271,30 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART7_DMA_PINGPONG_BUFSIZE + int "Set UART7 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA + default 128 + endif + menuconfig BSP_USING_PUART + bool "Enable PUART" + default n + if BSP_USING_PUART + config BSP_PUART_RX_BUFSIZE + int "Set PUART RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_PUART_TX_BUFSIZE + int "Set PUART TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_PUART_IRQ_PRIORITY + int "PUART Interrupt Priority" + range 1 7 + default 1 endif endif @@ -228,7 +314,7 @@ menu "On-chip Peripheral Drivers" int "SPI0 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI0_CS_SEL + choice prompt "Select SPI0 CS TYPE" default BSP_SPI0_USING_SOFT_CS config BSP_SPI0_USING_SOFT_CS @@ -236,7 +322,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI0_USING_HARD_CS bool "Enable SPI0 hardware cs" endchoice - choice BSP_SPI0_IO_MODE_SEL + choice prompt "Select SPI0 IO mode" default BSP_SPI0_USING_SINGLE_IO config BSP_SPI0_USING_SINGLE_IO @@ -258,7 +344,7 @@ menu "On-chip Peripheral Drivers" int "SPI1 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI1_CS_SEL + choice prompt "Select SPI1 CS TYPE" default BSP_SPI1_USING_SOFT_CS config BSP_SPI1_USING_SOFT_CS @@ -266,7 +352,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI1_USING_HARD_CS bool "Enable SPI1 hardware cs" endchoice - choice BSP_SPI1_IO_MODE_SEL + choice prompt "Select SPI1 IO mode" default BSP_SPI1_USING_SINGLE_IO config BSP_SPI1_USING_SINGLE_IO @@ -288,7 +374,7 @@ menu "On-chip Peripheral Drivers" int "SPI2 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI2_CS_SEL + choice prompt "Select SPI2 CS TYPE" default BSP_SPI2_USING_SOFT_CS config BSP_SPI2_USING_SOFT_CS @@ -296,7 +382,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI2_USING_HARD_CS bool "Enable SPI2 hardware cs" endchoice - choice BSP_SPI2_IO_MODE_SEL + choice prompt "Select SPI2 IO mode" default BSP_SPI2_USING_SINGLE_IO config BSP_SPI2_USING_SINGLE_IO @@ -318,7 +404,7 @@ menu "On-chip Peripheral Drivers" int "SPI3 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI3_CS_SEL + choice prompt "Select SPI3 CS TYPE" default BSP_SPI3_USING_SOFT_CS config BSP_SPI3_USING_SOFT_CS @@ -326,7 +412,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI3_USING_HARD_CS bool "Enable SPI3 hardware cs" endchoice - choice BSP_SPI3_IO_MODE_SEL + choice prompt "Select SPI3 IO mode" default BSP_SPI3_USING_SINGLE_IO config BSP_SPI3_USING_SINGLE_IO @@ -381,6 +467,15 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + config BSP_USING_PTMR + bool "Enable PTMR" + default n + if BSP_USING_PTMR + config BSP_PTMR_IRQ_PRIORITY + int "PTMR Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C @@ -446,7 +541,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_PWM bool "Enable PWM" default n - select RT_USING_PWM if BSP_USING_PWM + select RT_USING_PWM menuconfig BSP_USING_USB bool "Enable USB" @@ -521,7 +616,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_ADC bool "Enable ADC" default n - select RT_USING_ADC if BSP_USING_ADC + select RT_USING_ADC if BSP_USING_ADC menuconfig BSP_USING_ADC16 bool "Enable ADC16" @@ -535,5 +630,338 @@ menu "On-chip Peripheral Drivers" default n endif endif + + menuconfig BSP_USING_WDG + bool "Enable WDG" + default n + select RT_USING_WDT if BSP_USING_WDG + + menuconfig BSP_USING_CRC + bool "Enable CRC" + default n + + menuconfig BSP_USING_TSNS + bool "Enable TSNS (Temperature Sensor)" + default n + + menuconfig BSP_USING_ACMP + bool "Enable ACMP (Analog Comparator)" + default n + + menuconfig BSP_USING_OPAMP + bool "Enable OPAMP (Operational Amplifier)" + default n + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + + menuconfig BSP_USING_QEIV2 + bool "Enable QEIV2 (Quadrature Encoder Interface V2)" + default n + + menuconfig BSP_USING_QEO + bool "Enable QEO (Quadrature Encoder Output)" + default n + + menuconfig BSP_USING_RDC + bool "Enable RDC (Resolver to Digital Converter)" + default n + + menuconfig BSP_USING_SEI + bool "Enable SEI (Synchronous Encoder Interface)" + default n + + menuconfig BSP_USING_PLB + bool "Enable PLB" + default n + + menuconfig BSP_USING_MMC + bool "Enable MMC (Motor Control Module)" + default n + + menuconfig BSP_USING_PTPC + bool "Enable PTPC (PTP Controller)" + default n + + menuconfig BSP_USING_RNG + bool "Enable RNG (Random Number Generator)" + default n + + menuconfig BSP_USING_SDP + bool "Enable SDP (Secure Data Processing)" + default n + + menuconfig BSP_USING_MCHTMR + bool "Enable MCHTMR (Maichine Timer)" + default n + + menuconfig BSP_USING_SOFT_I2C + bool "Enable Software I2C" + default n + select RT_USING_I2C if BSP_USING_SOFT_I2C + if BSP_USING_SOFT_I2C + + config BSP_USING_SOFT_I2C_TIMING_DELAY_US + int "Soft I2C timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_I2C_TIMING_TIMEOUT + int "Soft I2C timing timeout" + range 10 10000 + default 100 + + config BSP_USING_SOFT_I2C0 + bool "Enable Soft I2C0" + default n + if BSP_USING_SOFT_I2C0 + config BSP_SOFT_I2C0_SCL_PIN + string "Soft I2C0 SCL pin name" + default "None" + config BSP_SOFT_I2C0_SDA_PIN + string "Soft I2C0 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C1 + bool "Enable Soft I2C1" + default n + if BSP_USING_SOFT_I2C1 + config BSP_SOFT_I2C1_SCL_PIN + string "Soft I2C1 SCL pin name" + default "None" + config BSP_SOFT_I2C1_SDA_PIN + string "Soft I2C1 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C2 + bool "Enable Soft I2C2" + default n + if BSP_USING_SOFT_I2C2 + config BSP_SOFT_I2C2_SCL_PIN + string "Soft I2C2 SCL pin name" + default "None" + config BSP_SOFT_I2C2_SDA_PIN + string "Soft I2C2 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C3 + bool "Enable Soft I2C3" + default n + if BSP_USING_SOFT_I2C3 + config BSP_SOFT_I2C3_SCL_PIN + string "Soft I2C3 SCL pin name" + default "None" + config BSP_SOFT_I2C3_SDA_PIN + string "Soft I2C3 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C4 + bool "Enable Soft I2C4" + default n + if BSP_USING_SOFT_I2C4 + config BSP_SOFT_I2C4_SCL_PIN + string "Soft I2C4 SCL pin name" + default "None" + config BSP_SOFT_I2C4_SDA_PIN + string "Soft I2C4 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C5 + bool "Enable Soft I2C5" + default n + if BSP_USING_SOFT_I2C5 + config BSP_SOFT_I2C5_SCL_PIN + string "Soft I2C5 SCL pin name" + default "None" + config BSP_SOFT_I2C5_SDA_PIN + string "Soft I2C5 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C6 + bool "Enable Soft I2C6" + default n + if BSP_USING_SOFT_I2C6 + config BSP_SOFT_I2C6_SCL_PIN + string "Soft I2C6 SCL pin name" + default "None" + config BSP_SOFT_I2C6_SDA_PIN + string "Soft I2C6 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C7 + bool "Enable Soft I2C7" + default n + if BSP_USING_SOFT_I2C7 + config BSP_SOFT_I2C7_SCL_PIN + string "Soft I2C7 SCL pin name" + default "None" + config BSP_SOFT_I2C7_SDA_PIN + string "Soft I2C7 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C8 + bool "Enable Soft I2C8" + default n + if BSP_USING_SOFT_I2C8 + config BSP_SOFT_I2C8_SCL_PIN + string "Soft I2C8 SCL pin name" + default "None" + config BSP_SOFT_I2C8_SDA_PIN + string "Soft I2C8 SDA pin name" + default "None" + endif + + endif + + menuconfig BSP_USING_SOFT_SPI + bool "Enable Software SPI" + default n + select RT_USING_SPI if BSP_USING_SOFT_SPI + select RT_USING_PIN if BSP_USING_SOFT_SPI + select RT_USING_SPI_BITOPS if BSP_USING_SOFT_SPI + if BSP_USING_SOFT_SPI + + config BSP_USING_SOFT_SPI_TIMING_DELAY_US + int "Soft SPI timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_SPI0 + bool "Enable Soft SPI0" + default n + if BSP_USING_SOFT_SPI0 + config BSP_SOFT_SPI0_SCK_PIN + string "Soft SPI0 SCK pin name" + default "None" + config BSP_SOFT_SPI0_MOSI_PIN + string "Soft SPI0 MOSI pin name" + default "None" + config BSP_SOFT_SPI0_MISO_PIN + string "Soft SPI0 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI1 + bool "Enable Soft SPI1" + default n + if BSP_USING_SOFT_SPI1 + config BSP_SOFT_SPI1_SCK_PIN + string "Soft SPI1 SCK pin name" + default "None" + config BSP_SOFT_SPI1_MOSI_PIN + string "Soft SPI1 MOSI pin name" + default "None" + config BSP_SOFT_SPI1_MISO_PIN + string "Soft SPI1 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI2 + bool "Enable Soft SPI2" + default n + if BSP_USING_SOFT_SPI2 + config BSP_SOFT_SPI2_SCK_PIN + string "Soft SPI2 SCK pin name" + default "None" + config BSP_SOFT_SPI2_MOSI_PIN + string "Soft SPI2 MOSI pin name" + default "None" + config BSP_SOFT_SPI2_MISO_PIN + string "Soft SPI2 MISO pin name" + default "None" + endif + + endif + +endmenu + +menu "HPMicro Interrupt Config" +endmenu + +menu "HPMicro RT-Thread Interrupt Framework" +endmenu + +menu "HPMicro Use Generic Startup Implementation" + config HPM_BSP_USING_GENERIC_STARTUP + bool "Enable this to use the common/startup/generic implementation" + default n + depends on HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + help + Enable this to use the common/startup/generic implementation. + This option is only available when RT-Thread Interrupt Framework is enabled. +endmenu + +menu "HPMicro RT-Thread backtrace configuration (experimental)" + config HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Enable RT-Thread Backtrace for HPMicro BSP" + default n + help + Enable RT-Thread Backtrace to support backtrace feature + + config HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER + select HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Use RT-Thread Backtrace in Exception Handler" + default n + help + Use RT-Thread Backtrace in Exception Handler to print backtrace information endmenu + +endmenu + +menu "Third-Party Add-ons" + +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + endif +endmenu + +menu "RT-Thread Insight Config" + config BSP_USING_RTI + select BSP_USING_MCHTMR + select RT_USING_RTI + select RT_USING_RT_TUNNEL + bool "Enable RT-Thread Insight(experimental)" + default n + + if BSP_USING_RTI + config RT_TUNNEL_USE_NONCACHE_RAM + bool "Enable RT-Thread Insight Non-cacheable RAM support" + default y + help + Enable this to use non-cacheable RAM for RT-Thread Insight data transfer. + This option is useful when RT-Thread Insight is used with cache enabled. + + endif + +endmenu + endmenu diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/boards/hpm5300evk.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/boards/hpm5300evk.cfg similarity index 78% rename from bsp/hpmicro/hpm5300evk/board/debug_scripts/boards/hpm5300evk.cfg rename to bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/boards/hpm5300evk.cfg index 7d495f5b380c..7bb2e8c77344 100644 --- a/bsp/hpmicro/hpm5300evk/board/debug_scripts/boards/hpm5300evk.cfg +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/boards/hpm5300evk.cfg @@ -46,27 +46,15 @@ # - flash ctrl index: 0xF3000000 # - base address: 0x80000000 # - flash size: 0x2000000 -# - flash option0: 0x7 -flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x6 0x1000 +# - flash option0: 0x5 +# - flash option1: 0x1000 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000 proc init_clock {} { - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x1 - - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x2 - - $::_TARGET0 riscv dmi_write 0x39 0xF4000800 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000810 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000820 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000830 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + mww 0xF4000800 0xFFFFFFFF + mww 0xF4000810 0xFFFFFFFF + mww 0xF4000820 0xFFFFFFFF + mww 0xF4000830 0xFFFFFFFF echo "clocks has been enabled!" } diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg similarity index 100% rename from bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/cmsis_dap.cfg rename to bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/ft2232.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft2232.cfg similarity index 100% rename from bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/ft2232.cfg rename to bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft2232.cfg diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/ft232.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft232.cfg similarity index 100% rename from bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/ft232.cfg rename to bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft232.cfg diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/jlink.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/jlink.cfg similarity index 100% rename from bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/jlink.cfg rename to bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/jlink.cfg diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg similarity index 100% rename from bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/nds_aice_micro.cfg rename to bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm5300.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm5300.cfg new file mode 100644 index 000000000000..935b5e87dd7e --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm5300.cfg @@ -0,0 +1,24 @@ +# Copyright (c) 2023,2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm5361 +} +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 + +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr_lite.cfg] + +proc reset_soc {} { + sba_write_mem 0xF410001C 24000000 +} diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common.cfg new file mode 100644 index 000000000000..ae9233e5e5b2 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common.cfg @@ -0,0 +1,29 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +source [file join [file dirname [info script]] hpm_reset.cfg] + +set dmsbcs 0x38 +set dmsbaddress0 0x39 +set dmsbdata0 0x3C + +proc target0_dmi_write_reg {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc target0_dmi_read_reg {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc sba_write_mem {addr value} { + target0_dmi_write_reg $::dmsbaddress0 ${addr} + target0_dmi_write_reg $::dmsbdata0 ${value} +} + +proc sba_read_mem {addr} { + set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }] + target0_dmi_write_reg $::dmsbcs ${sbcs} + target0_dmi_write_reg $::dmsbaddress0 ${addr} + set value [target0_dmi_read_reg $::dmsbdata0] + return ${value} +} diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg new file mode 100644 index 000000000000..4f4b6dcd86a1 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg @@ -0,0 +1,101 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# mslideleg +riscv expose_csrs 2005 +# mclk_ctl +riscv expose_csrs 2015 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# slie +riscv expose_csrs 2500 +# slip +riscv expose_csrs 2501 +# sdcause +riscv expose_csrs 2505 +# scctldata +riscv expose_csrs 2509 +# scounterinten +riscv expose_csrs 2511 +# scountermask_m +riscv expose_csrs 2513 +# scountermask_s +riscv expose_csrs 2514 +# scountermask_u +riscv expose_csrs 2515 +# scounterovf +riscv expose_csrs 2516 +# scountinhibit +riscv expose_csrs 2528 +# shpmevent3 +riscv expose_csrs 2531 +# shpmevent4 +riscv expose_csrs 2532 +# shpmevent5 +riscv expose_csrs 2533 +# shpmevent6 +riscv expose_csrs 2534 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg new file mode 100644 index 000000000000..096cee06355e --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg @@ -0,0 +1,69 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_reset.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_reset.cfg new file mode 100644 index 000000000000..681c59954789 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_reset.cfg @@ -0,0 +1,9 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +$_TARGET0 configure -event reset-deassert-pre { + sleep 1 + if {$halt} { + $::_TARGET0 arp_halt + } +} diff --git a/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/flash_rtt.ld b/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/flash_rtt.ld index 12af13362ed3..6591432556e5 100644 --- a/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/flash_rtt.ld +++ b/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/flash_rtt.ld @@ -14,7 +14,7 @@ MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080300, LENGTH = 128K - 768 + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K } @@ -26,6 +26,15 @@ __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; SECTIONS { + /* Anchor the lowest LMA at the flash base address (0x80000000): objcopy takes the + * lowest LMA as the start address of the generated .bin, so without this marker the + * .bin starts at .nor_cfg_option (0x80000400). The value is all ones (erased flash), + * so programming it does not change the flash state. + */ + .flash_base ORIGIN(XPI0) : { + LONG(0xFFFFFFFF) + } > XPI0 + .nor_cfg_option __nor_cfg_option_load_addr__ : { KEEP(*(.nor_cfg_option)) } > XPI0 @@ -165,11 +174,19 @@ SECTIONS PROVIDE (_etext = .); PROVIDE (etext = .); + /* The first 0x300 bytes of DLM are reserved; keep them as an explicit NOLOAD + * placeholder. This also keeps the DLM region 4KB aligned so that the linker does + * not emit an extra file-backed PT_LOAD (which made "program rtthread.elf" fail). + */ + .dlm_reserved (NOLOAD) : { + . = . + 0x300; + } > DLM + .fast_ram (NOLOAD) : { KEEP(*(.fast_ram)) } > DLM - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); __fast_ram_init_start__ = .; @@ -179,6 +196,15 @@ SECTIONS . = ALIGN(8); } > DLM + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + /* Note: the .tbss and .tdata section should be adjacent */ .tbss(NOLOAD) : { . = ALIGN(8); @@ -256,7 +282,7 @@ SECTIONS PROVIDE (edata = .); } > DLM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); @@ -295,7 +321,7 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > DLM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; diff --git a/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/ram_rtt.ld b/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/ram_rtt.ld index 26d57856025f..6753ecbafdb2 100644 --- a/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/ram_rtt.ld +++ b/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/ram_rtt.ld @@ -112,6 +112,16 @@ SECTIONS . = ALIGN(8); } > ILM + + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > ILM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -213,7 +223,7 @@ SECTIONS *(.fast) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); - } > DLM + } > ILM __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { diff --git a/bsp/hpmicro/hpm5300evk/board/pinmux.c b/bsp/hpmicro/hpm5300evk/board/pinmux.c index 268926772e92..f4e655a73254 100644 --- a/bsp/hpmicro/hpm5300evk/board/pinmux.c +++ b/bsp/hpmicro/hpm5300evk/board/pinmux.c @@ -66,7 +66,7 @@ void init_uart_pin_as_gpio(UART_Type *ptr) } } -void init_i2c_pins(I2C_Type *ptr) +hpm_stat_t init_i2c_pins(I2C_Type *ptr) { if (ptr == HPM_I2C0) { HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; @@ -79,8 +79,9 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB06].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); HPM_IOC->PAD[IOC_PAD_PB07].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); } else { - ; + return status_invalid_argument; } + return status_success; } void init_gpio_pins(void) diff --git a/bsp/hpmicro/hpm5300evk/board/pinmux.h b/bsp/hpmicro/hpm5300evk/board/pinmux.h index 738593a2b649..aaa5b391cf6b 100644 --- a/bsp/hpmicro/hpm5300evk/board/pinmux.h +++ b/bsp/hpmicro/hpm5300evk/board/pinmux.h @@ -14,7 +14,7 @@ extern "C" { void init_py_pins_as_pgpio(void); void init_uart_pins(UART_Type *ptr); void init_uart_pin_as_gpio(UART_Type *ptr); -void init_i2c_pins(I2C_Type *ptr); +hpm_stat_t init_i2c_pins(I2C_Type *ptr); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); diff --git a/bsp/hpmicro/hpm5300evk/board/rtt_board.c b/bsp/hpmicro/hpm5300evk/board/rtt_board.c index e5b5d95897ec..d4cd474e10a1 100644 --- a/bsp/hpmicro/hpm5300evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm5300evk/board/rtt_board.c @@ -40,14 +40,20 @@ void os_tick_config(void) void rtt_board_init(void) { board_init_clock(); + + /* initialize memory system + * NOTE: this must happen before board_init_console(), because the SDK console_init() + * calls setvbuf(), which allocates through the C library malloc() -> rt_malloc() and + * therefore requires the RT-Thread heap to be ready. Otherwise RT_ASSERT() fires in + * rt_smem_alloc() whenever RT_USING_DEBUG is enabled. + */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + board_init_console(); board_init_pmp(); dma_mgr_init(); - /* initialize memory system */ - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); - /* Configure the OS Tick */ os_tick_config(); diff --git a/bsp/hpmicro/hpm5300evk/makefile.targets b/bsp/hpmicro/hpm5300evk/makefile.targets new file mode 100644 index 000000000000..4583a13f1cd3 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/makefile.targets @@ -0,0 +1,6 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' + +*.elf: $(wildcard board/linker_scripts/gcc/*.ld) diff --git a/bsp/hpmicro/hpm5300evk/rtconfig.h b/bsp/hpmicro/hpm5300evk/rtconfig.h index 1793c387c0cf..b75bcbad96a9 100644 --- a/bsp/hpmicro/hpm5300evk/rtconfig.h +++ b/bsp/hpmicro/hpm5300evk/rtconfig.h @@ -7,6 +7,16 @@ /* rt_vsnprintf options */ +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 /* end of rt_vsnprintf options */ /* rt_vsscanf options */ @@ -102,7 +112,7 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50301 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define ARCH_RISCV @@ -288,6 +298,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -315,12 +329,24 @@ /* HPMicro SDK */ #define PKG_USING_HPM_SDK -#define PKG_USING_HPM_SDK_V110 +#define PKG_USING_HPM_SDK_V113 /* end of HPMicro SDK */ +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -400,11 +426,11 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ -#define SOC_HPM5300_SERIES +#define SOC_SERIES_HPM5300 /* Hardware Drivers Config */ -#define SOC_HPM5300 +#define SOC_HPM5000 /* On-chip Peripheral Drivers */ @@ -416,6 +442,29 @@ #define BSP_UART0_TX_BUFSIZE 0 #define BSP_UART0_IRQ_PRIORITY 1 /* end of On-chip Peripheral Drivers */ + +/* HPMicro Interrupt Config */ + +/* HPMicro RT-Thread Interrupt Framework */ + +/* HPMicro Use Generic Startup Implementation */ + +/* end of HPMicro Use Generic Startup Implementation */ + +/* HPMicro RT-Thread backtrace configuration (experimental) */ + +/* end of HPMicro RT-Thread backtrace configuration (experimental) */ /* end of Hardware Drivers Config */ +/* Third-Party Add-ons */ + +/* Segger SystemView Config */ + +/* end of Segger SystemView Config */ + +/* RT-Thread Insight Config */ + +/* end of RT-Thread Insight Config */ +/* end of Third-Party Add-ons */ + #endif diff --git a/bsp/hpmicro/hpm5300evk/rtconfig.py b/bsp/hpmicro/hpm5300evk/rtconfig.py index ab7d843770fc..1ea9e310de11 100644 --- a/bsp/hpmicro/hpm5300evk/rtconfig.py +++ b/bsp/hpmicro/hpm5300evk/rtconfig.py @@ -3,7 +3,6 @@ import os import sys -import rtconfig if os.getenv('RTT_ROOT'): @@ -11,7 +10,7 @@ else: RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +sys.path.insert(0, os.path.join(RTT_ROOT, 'tools')) # toolchains options @@ -60,9 +59,13 @@ else: EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' else: - print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + print("CROSS_TOOL = {} not yet supported, only gcc is supported".format(CROSS_TOOL)) + exit(-1) -BUILD = 'flash_debug' +if os.getenv('RTT_BUILD_TYPE'): + BUILD = os.getenv('RTT_BUILD_TYPE') +else: + BUILD = 'flash_debug' if PLATFORM == 'gcc': PREFIX = 'riscv32-unknown-elf-' @@ -82,7 +85,7 @@ DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' CFLAGS = DEVICE AFLAGS = CFLAGS - LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' CPATH = '' LPATH = '' @@ -90,8 +93,8 @@ if BUILD == 'ram_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' @@ -100,8 +103,8 @@ elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': diff --git a/bsp/hpmicro/hpm5300evk/rtconfig_preinc.h b/bsp/hpmicro/hpm5300evk/rtconfig_preinc.h new file mode 100644 index 000000000000..85109511cd3f --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/rtconfig_preinc.h @@ -0,0 +1,20 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define D25 +#define HPM5361 +#define HPMSOC_HAS_HPMSDK_DMAV2 +#define HPM_SDK_L1C_NO_REENTRANT 1 +#define HPM_SOC_ISR_NUM 73 +#define RT_USING_LIBC +#define RT_USING_NEWLIBC +#define USE_DMA_DECLARE_EXT_ISR_M 1 +#define _POSIX_C_SOURCE 1 +#define _REENT_SMALL +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c b/bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c index 36ec0334321b..96699f5bfd52 100644 --- a/bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c +++ b/bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c @@ -54,6 +54,8 @@ extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; + extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; /* tbss section */ size = __tbss_end__ - __tbss_start__; @@ -96,6 +98,18 @@ for (i = 0; i < size; i++) { *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } + + /* fast_ram bss section */ + size = __fast_ram_bss_end__ - __fast_ram_bss_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_bss_start__ + i) = 0; + } + + /* fast_ram init section LMA: etext + data length + ramfunc length + tdata length */ + size = __fast_ram_init_end__ - __fast_ram_init_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); + } #endif } diff --git a/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S b/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S index 2ba3169ea4c0..4774dbd092b0 100644 --- a/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S @@ -19,14 +19,6 @@ _start: la tp, __thread_pointer .option pop -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif /* Initialize stack pointer */ la t0, _stack mv sp, t0 @@ -45,12 +37,20 @@ _start: /* Initialize FCSR */ fscsr zero #endif - /* Disable Vector mode */ - csrci CSR_MMISC_CTL, 2 - /* Initialize trap_entry base */ + +#ifdef HPM_USING_VECTOR_PREEMPTED_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ la t0, SW_handler csrw mtvec, t0 - + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif /* System reset handler */ call reset_handler @@ -62,6 +62,7 @@ _start: nmi_handler: 1: j 1b +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK .weak default_irq_handler .align 2 default_irq_handler: @@ -74,3 +75,13 @@ default_irq_handler: .endm #include "vectors.S" +#else + .section .vector_table, "a" + .global __vector_table + .align 9 + +__vector_table: + .rept RT_HW_ISR_NUM + .long handle_trap + .endr +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ diff --git a/bsp/hpmicro/hpm5300evk/startup/SConscript b/bsp/hpmicro/hpm5300evk/startup/SConscript index 10776376b717..11a9d203d4ce 100644 --- a/bsp/hpmicro/hpm5300evk/startup/SConscript +++ b/bsp/hpmicro/hpm5300evk/startup/SConscript @@ -8,6 +8,5 @@ cwd = GetCurrentDir() objs = [] objs = objs + SConscript(os.path.join(rtconfig.CHIP_NAME, 'SConscript')) -ASFLAGS = ' -I' + cwd Return('objs') \ No newline at end of file diff --git a/bsp/hpmicro/hpm5301evklite/.config b/bsp/hpmicro/hpm5301evklite/.config index 19cd38cfbcda..c028e0baa6ef 100644 --- a/bsp/hpmicro/hpm5301evklite/.config +++ b/bsp/hpmicro/hpm5301evklite/.config @@ -11,8 +11,18 @@ # rt_vsnprintf options # # CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_vsnprintf options # @@ -178,7 +188,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y -CONFIG_RT_VER_NUM=0x50300 +CONFIG_RT_VER_NUM=0x50301 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -237,11 +247,11 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_SERIAL_USING_DMA is not set # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -262,10 +272,10 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -458,6 +468,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -573,6 +584,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set # end of multimedia packages # @@ -632,6 +644,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set # end of tools packages # @@ -780,6 +794,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set # end of STM32 HAL & SDK Drivers # @@ -813,7 +829,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -892,11 +922,18 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HPM_SDK=y CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" -CONFIG_PKG_USING_HPM_SDK_V110=y +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_V113=y # CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION is not set -CONFIG_PKG_HPM_SDK_VER="v1.10.0" +CONFIG_PKG_HPM_SDK_VER="v1.13.0" # end of HPMicro SDK +# +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + # # FT32 HAL & SDK Drivers # @@ -905,6 +942,23 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -984,6 +1038,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set # CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set # end of sensors drivers # @@ -1038,6 +1093,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1088,6 +1144,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1105,6 +1162,9 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set # CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set # end of AI packages # @@ -1162,6 +1222,8 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set @@ -1187,6 +1249,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1426,12 +1489,12 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # end of Arduino libraries # end of RT-Thread online packages -CONFIG_SOC_HPM5300_SERIES=y +CONFIG_SOC_SERIES_HPM5300=y # # Hardware Drivers Config # -CONFIG_SOC_HPM5300=y +CONFIG_SOC_HPM5000=y # # On-chip Peripheral Drivers @@ -1446,6 +1509,7 @@ CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_UART1 is not set # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_PUART is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_GPTMR is not set # CONFIG_BSP_USING_I2C is not set @@ -1453,5 +1517,49 @@ CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_USB is not set # CONFIG_BSP_USING_EWDG is not set # CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_WDG is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_TSNS is not set +# CONFIG_BSP_USING_ACMP is not set +# CONFIG_BSP_USING_MCHTMR is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SOFT_SPI is not set # end of On-chip Peripheral Drivers + +# +# HPMicro Interrupt Config +# + +# +# HPMicro RT-Thread Interrupt Framework +# + +# +# HPMicro Use Generic Startup Implementation +# +# end of HPMicro Use Generic Startup Implementation + +# +# HPMicro RT-Thread backtrace configuration (experimental) +# +# CONFIG_HPM_ENABLE_RTTHREAD_BACKTRACE_PORT is not set +# CONFIG_HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER is not set +# end of HPMicro RT-Thread backtrace configuration (experimental) # end of Hardware Drivers Config + +# +# Third-Party Add-ons +# + +# +# Segger SystemView Config +# +# CONFIG_BSP_USING_SYSTEMVIEW is not set +# end of Segger SystemView Config + +# +# RT-Thread Insight Config +# +# CONFIG_BSP_USING_RTI is not set +# end of RT-Thread Insight Config +# end of Third-Party Add-ons diff --git a/bsp/hpmicro/hpm5301evklite/README.md b/bsp/hpmicro/hpm5301evklite/README.md index ba4ad0b50fbd..f1deec4a81af 100644 --- a/bsp/hpmicro/hpm5301evklite/README.md +++ b/bsp/hpmicro/hpm5301evklite/README.md @@ -70,7 +70,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Users can download the project via the below command: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5301evklite.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm5300.cfg -f board\debug_scripts\openocd\boards\hpm5301evklite.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - Users can debug the project via the below command: @@ -78,7 +78,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Connect debugger via `OpenOCD`: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5301evklite.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm5300.cfg -f board\debug_scripts\openocd\boards\hpm5301evklite.cfg ``` - Start Debugger via `GDB`: diff --git a/bsp/hpmicro/hpm5301evklite/README_zh.md b/bsp/hpmicro/hpm5301evklite/README_zh.md index 905d16490811..a32ce56e57a5 100644 --- a/bsp/hpmicro/hpm5301evklite/README_zh.md +++ b/bsp/hpmicro/hpm5301evklite/README_zh.md @@ -70,14 +70,14 @@ - 通过如下命令完成下载: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5301evklite.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm5300.cfg -f board\debug_scripts\openocd\boards\hpm5301evklite.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - 通过如下命令实现调试: - 通过 `OpenOCD` 来连接开发板: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5301evklite.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm5300.cfg -f board\debug_scripts\openocd\boards\hpm5301evklite.cfg ``` - 通过 `GDB` 实现调试: ```console diff --git a/bsp/hpmicro/hpm5301evklite/SConscript b/bsp/hpmicro/hpm5301evklite/SConscript index 014c428d0a37..606b65445b0a 100644 --- a/bsp/hpmicro/hpm5301evklite/SConscript +++ b/bsp/hpmicro/hpm5301evklite/SConscript @@ -7,7 +7,6 @@ cwd = GetCurrentDir() objs = [] list = os.listdir(cwd) -ASFLAGS = ' -I' + cwd for d in list: path = os.path.join(cwd, d) diff --git a/bsp/hpmicro/hpm5301evklite/SConstruct b/bsp/hpmicro/hpm5301evklite/SConstruct index d41dbd7584a1..69d7c1ccf70d 100644 --- a/bsp/hpmicro/hpm5301evklite/SConstruct +++ b/bsp/hpmicro/hpm5301evklite/SConstruct @@ -16,13 +16,16 @@ except: exit(-1) def bsp_pkg_check(): - import subprocess - + if GetOption('clean'): + return + need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break + + if os.path.isdir("packages"): + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break if need_update: print("\n===============================================================================") print("Dependency packages missing, please running 'pkgs --update'...") @@ -64,9 +67,6 @@ if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): else: libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - GDB = rtconfig.GDB @@ -78,6 +78,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # includes rtt drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'), variant_dir='build/libraries/drivers', duplicate=0)) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'misc', 'SConscript'), variant_dir='build/libraries/misc', duplicate=0)) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm5301evklite/applications/SConscript b/bsp/hpmicro/hpm5301evklite/applications/SConscript index a65aa4d8553b..00bf6b8d8f7e 100644 --- a/bsp/hpmicro/hpm5301evklite/applications/SConscript +++ b/bsp/hpmicro/hpm5301evklite/applications/SConscript @@ -1,5 +1,3 @@ -import rtconfig - from building import * cwd = GetCurrentDir() diff --git a/bsp/hpmicro/hpm5301evklite/applications/main.c b/bsp/hpmicro/hpm5301evklite/applications/main.c index 0bbf6370382c..98ea3be7a378 100644 --- a/bsp/hpmicro/hpm5301evklite/applications/main.c +++ b/bsp/hpmicro/hpm5301evklite/applications/main.c @@ -19,7 +19,10 @@ int main(void) { static uint32_t led_thread_arg = 0; rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); - rt_thread_startup(led_thread); + if (led_thread != RT_NULL) + { + rt_thread_startup(led_thread); + } return 0; } diff --git a/bsp/hpmicro/hpm5301evklite/board/Kconfig b/bsp/hpmicro/hpm5301evklite/board/Kconfig index b900b8e34e2b..77dec23981a6 100644 --- a/bsp/hpmicro/hpm5301evklite/board/Kconfig +++ b/bsp/hpmicro/hpm5301evklite/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_HPM5300 +config SOC_HPM5000 bool - select SOC_HPM5300_SERIES + select SOC_SERIES_HPM5300 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -78,6 +78,11 @@ menu "On-chip Peripheral Drivers" int "UART1 Interrupt Priority" range 1 7 default 1 + config BSP_UART1_DMA_PINGPONG_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART2 bool "Enable UART2" @@ -105,6 +110,11 @@ menu "On-chip Peripheral Drivers" int "UART2 Interrupt Priority" range 1 7 default 1 + config BSP_UART2_DMA_PINGPONG_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART3 bool "Enable UART3" @@ -132,6 +142,30 @@ menu "On-chip Peripheral Drivers" int "UART3 Interrupt Priority" range 1 7 default 1 + config BSP_UART3_DMA_PINGPONG_BUFSIZE + int "Set UART3 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA + default 128 + endif + menuconfig BSP_USING_PUART + bool "Enable PUART" + default n + if BSP_USING_PUART + config BSP_PUART_RX_BUFSIZE + int "Set PUART RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_PUART_TX_BUFSIZE + int "Set PUART TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_PUART_IRQ_PRIORITY + int "PUART Interrupt Priority" + range 1 7 + default 1 endif endif @@ -151,7 +185,7 @@ menu "On-chip Peripheral Drivers" int "SPI0 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI0_CS_SEL + choice prompt "Select SPI0 CS TYPE" default BSP_SPI0_USING_SOFT_CS config BSP_SPI0_USING_SOFT_CS @@ -159,7 +193,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI0_USING_HARD_CS bool "Enable SPI0 hardware cs" endchoice - choice BSP_SPI0_IO_MODE_SEL + choice prompt "Select SPI0 IO mode" default BSP_SPI0_USING_SINGLE_IO config BSP_SPI0_USING_SINGLE_IO @@ -181,7 +215,7 @@ menu "On-chip Peripheral Drivers" int "SPI1 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI1_CS_SEL + choice prompt "Select SPI1 CS TYPE" default BSP_SPI1_USING_SOFT_CS config BSP_SPI1_USING_SOFT_CS @@ -189,7 +223,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI1_USING_HARD_CS bool "Enable SPI1 hardware cs" endchoice - choice BSP_SPI1_IO_MODE_SEL + choice prompt "Select SPI1 IO mode" default BSP_SPI1_USING_SINGLE_IO config BSP_SPI1_USING_SINGLE_IO @@ -211,7 +245,7 @@ menu "On-chip Peripheral Drivers" int "SPI2 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI2_CS_SEL + choice prompt "Select SPI2 CS TYPE" default BSP_SPI2_USING_SOFT_CS config BSP_SPI2_USING_SOFT_CS @@ -219,7 +253,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI2_USING_HARD_CS bool "Enable SPI2 hardware cs" endchoice - choice BSP_SPI2_IO_MODE_SEL + choice prompt "Select SPI2 IO mode" default BSP_SPI2_USING_SINGLE_IO config BSP_SPI2_USING_SINGLE_IO @@ -241,7 +275,7 @@ menu "On-chip Peripheral Drivers" int "SPI3 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI3_CS_SEL + choice prompt "Select SPI3 CS TYPE" default BSP_SPI3_USING_SOFT_CS config BSP_SPI3_USING_SOFT_CS @@ -249,7 +283,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI3_USING_HARD_CS bool "Enable SPI3 hardware cs" endchoice - choice BSP_SPI3_IO_MODE_SEL + choice prompt "Select SPI3 IO mode" default BSP_SPI3_USING_SINGLE_IO config BSP_SPI3_USING_SINGLE_IO @@ -262,7 +296,6 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_GPTMR bool "Enable GPTMR" default n @@ -270,6 +303,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" + depends on !HPM_USING_VECTOR_PREEMPTED_MODE default n if BSP_USING_GPTMR0 config BSP_GPTMR0_IRQ_PRIORITY @@ -304,6 +338,15 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + config BSP_USING_PTMR + bool "Enable PTMR" + default n + if BSP_USING_PTMR + config BSP_PTMR_IRQ_PRIORITY + int "PTMR Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C @@ -396,7 +439,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_ADC bool "Enable ADC" default n - select RT_USING_ADC if BSP_USING_ADC + select RT_USING_ADC if BSP_USING_ADC menuconfig BSP_USING_ADC16 bool "Enable ADC16" @@ -407,6 +450,294 @@ menu "On-chip Peripheral Drivers" default y endif endif + + menuconfig BSP_USING_WDG + bool "Enable WDG" + default n + select RT_USING_WDT if BSP_USING_WDG + + menuconfig BSP_USING_CRC + bool "Enable CRC" + default n + + menuconfig BSP_USING_TSNS + bool "Enable TSNS (Temperature Sensor)" + default n + + menuconfig BSP_USING_ACMP + bool "Enable ACMP (Analog Comparator)" + default n + + menuconfig BSP_USING_MCHTMR + bool "Enable MCHTMR (Machine Timer)" + default n + + menuconfig BSP_USING_SOFT_I2C + bool "Enable Software I2C" + default n + select RT_USING_I2C if BSP_USING_SOFT_I2C + if BSP_USING_SOFT_I2C + + config BSP_USING_SOFT_I2C_TIMING_DELAY_US + int "Soft I2C timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_I2C_TIMING_TIMEOUT + int "Soft I2C timing timeout" + range 10 10000 + default 100 + + config BSP_USING_SOFT_I2C0 + bool "Enable Soft I2C0" + default n + if BSP_USING_SOFT_I2C0 + config BSP_SOFT_I2C0_SCL_PIN + string "Soft I2C0 SCL pin name" + default "None" + config BSP_SOFT_I2C0_SDA_PIN + string "Soft I2C0 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C1 + bool "Enable Soft I2C1" + default n + if BSP_USING_SOFT_I2C1 + config BSP_SOFT_I2C1_SCL_PIN + string "Soft I2C1 SCL pin name" + default "None" + config BSP_SOFT_I2C1_SDA_PIN + string "Soft I2C1 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C2 + bool "Enable Soft I2C2" + default n + if BSP_USING_SOFT_I2C2 + config BSP_SOFT_I2C2_SCL_PIN + string "Soft I2C2 SCL pin name" + default "None" + config BSP_SOFT_I2C2_SDA_PIN + string "Soft I2C2 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C3 + bool "Enable Soft I2C3" + default n + if BSP_USING_SOFT_I2C3 + config BSP_SOFT_I2C3_SCL_PIN + string "Soft I2C3 SCL pin name" + default "None" + config BSP_SOFT_I2C3_SDA_PIN + string "Soft I2C3 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C4 + bool "Enable Soft I2C4" + default n + if BSP_USING_SOFT_I2C4 + config BSP_SOFT_I2C4_SCL_PIN + string "Soft I2C4 SCL pin name" + default "None" + config BSP_SOFT_I2C4_SDA_PIN + string "Soft I2C4 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C5 + bool "Enable Soft I2C5" + default n + if BSP_USING_SOFT_I2C5 + config BSP_SOFT_I2C5_SCL_PIN + string "Soft I2C5 SCL pin name" + default "None" + config BSP_SOFT_I2C5_SDA_PIN + string "Soft I2C5 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C6 + bool "Enable Soft I2C6" + default n + if BSP_USING_SOFT_I2C6 + config BSP_SOFT_I2C6_SCL_PIN + string "Soft I2C6 SCL pin name" + default "None" + config BSP_SOFT_I2C6_SDA_PIN + string "Soft I2C6 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C7 + bool "Enable Soft I2C7" + default n + if BSP_USING_SOFT_I2C7 + config BSP_SOFT_I2C7_SCL_PIN + string "Soft I2C7 SCL pin name" + default "None" + config BSP_SOFT_I2C7_SDA_PIN + string "Soft I2C7 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C8 + bool "Enable Soft I2C8" + default n + if BSP_USING_SOFT_I2C8 + config BSP_SOFT_I2C8_SCL_PIN + string "Soft I2C8 SCL pin name" + default "None" + config BSP_SOFT_I2C8_SDA_PIN + string "Soft I2C8 SDA pin name" + default "None" + endif + + endif + + menuconfig BSP_USING_SOFT_SPI + bool "Enable Software SPI" + default n + select RT_USING_SPI if BSP_USING_SOFT_SPI + select RT_USING_PIN if BSP_USING_SOFT_SPI + select RT_USING_SPI_BITOPS if BSP_USING_SOFT_SPI + if BSP_USING_SOFT_SPI + + config BSP_USING_SOFT_SPI_TIMING_DELAY_US + int "Soft SPI timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_SPI0 + bool "Enable Soft SPI0" + default n + if BSP_USING_SOFT_SPI0 + config BSP_SOFT_SPI0_SCK_PIN + string "Soft SPI0 SCK pin name" + default "None" + config BSP_SOFT_SPI0_MOSI_PIN + string "Soft SPI0 MOSI pin name" + default "None" + config BSP_SOFT_SPI0_MISO_PIN + string "Soft SPI0 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI1 + bool "Enable Soft SPI1" + default n + if BSP_USING_SOFT_SPI1 + config BSP_SOFT_SPI1_SCK_PIN + string "Soft SPI1 SCK pin name" + default "None" + config BSP_SOFT_SPI1_MOSI_PIN + string "Soft SPI1 MOSI pin name" + default "None" + config BSP_SOFT_SPI1_MISO_PIN + string "Soft SPI1 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI2 + bool "Enable Soft SPI2" + default n + if BSP_USING_SOFT_SPI2 + config BSP_SOFT_SPI2_SCK_PIN + string "Soft SPI2 SCK pin name" + default "None" + config BSP_SOFT_SPI2_MOSI_PIN + string "Soft SPI2 MOSI pin name" + default "None" + config BSP_SOFT_SPI2_MISO_PIN + string "Soft SPI2 MISO pin name" + default "None" + endif + + endif + +endmenu + +menu "HPMicro Interrupt Config" +endmenu + +menu "HPMicro RT-Thread Interrupt Framework" +endmenu + +menu "HPMicro Use Generic Startup Implementation" + config HPM_BSP_USING_GENERIC_STARTUP + bool "Enable this to use the common/startup/generic implementation" + default n + depends on HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + help + Enable this to use the common/startup/generic implementation. + This option is only available when RT-Thread Interrupt Framework is enabled. +endmenu + +menu "HPMicro RT-Thread backtrace configuration (experimental)" + config HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Enable RT-Thread Backtrace for HPMicro BSP" + default n + help + Enable RT-Thread Backtrace to support backtrace feature + + config HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER + select HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Use RT-Thread Backtrace in Exception Handler" + default n + help + Use RT-Thread Backtrace in Exception Handler to print backtrace information +endmenu + +endmenu + +menu "Third-Party Add-ons" + +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + endif +endmenu + +menu "RT-Thread Insight Config" + config BSP_USING_RTI + select BSP_USING_MCHTMR + select RT_USING_RTI + select RT_USING_RT_TUNNEL + bool "Enable RT-Thread Insight(experimental)" + default n + + if BSP_USING_RTI + config RT_TUNNEL_USE_NONCACHE_RAM + bool "Enable RT-Thread Insight Non-cacheable RAM support" + default y + help + Enable this to use non-cacheable RAM for RT-Thread Insight data transfer. + This option is useful when RT-Thread Insight is used with cache enabled. + + endif + endmenu endmenu diff --git a/bsp/hpmicro/hpm5301evklite/board/SConscript b/bsp/hpmicro/hpm5301evklite/board/SConscript index dcd1e3543fd7..31b197126b7d 100644 --- a/bsp/hpmicro/hpm5301evklite/board/SConscript +++ b/bsp/hpmicro/hpm5301evklite/board/SConscript @@ -11,7 +11,7 @@ src = Split(""" """) CPPPATH = [cwd] -CPPDEFINES=['D25', 'HPM5361'] +CPPDEFINES=['D25', 'HPM5301'] group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/boards/hpm5301evklite.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/boards/hpm5301evklite.cfg index 7d495f5b380c..fbe2379e96ff 100644 --- a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/boards/hpm5301evklite.cfg +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/boards/hpm5301evklite.cfg @@ -16,7 +16,7 @@ # 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI # [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) # 0 - Not needed -# 1 - QE bit is at bit 6 in Status Register 1 +# 1 - QE bit is at bit6 in Status Register 1 # 2 - QE bit is at bit1 in Status Register 2 # 3 - QE bit is at bit7 in Status Register 2 # 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 @@ -46,27 +46,15 @@ # - flash ctrl index: 0xF3000000 # - base address: 0x80000000 # - flash size: 0x2000000 -# - flash option0: 0x7 -flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x6 0x1000 +# - flash option0: 0x5 +# - flash option1: 0x1000 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000 proc init_clock {} { - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x1 - - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x2 - - $::_TARGET0 riscv dmi_write 0x39 0xF4000800 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000810 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000820 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000830 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + mww 0xF4000800 0xFFFFFFFF + mww 0xF4000810 0xFFFFFFFF + mww 0xF4000820 0xFFFFFFFF + mww 0xF4000830 0xFFFFFFFF echo "clocks has been enabled!" } diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm5300.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm5300.cfg index c57a36d0174d..935b5e87dd7e 100644 --- a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm5300.cfg +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm5300.cfg @@ -1,7 +1,11 @@ -# Copyright (c) 2021 HPMicro +# Copyright (c) 2023,2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause -set _CHIP hpm5301 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm5361 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -11,3 +15,10 @@ target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 targets $_TARGET0 + +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr_lite.cfg] + +proc reset_soc {} { + sba_write_mem 0xF410001C 24000000 +} diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common.cfg new file mode 100644 index 000000000000..ae9233e5e5b2 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common.cfg @@ -0,0 +1,29 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +source [file join [file dirname [info script]] hpm_reset.cfg] + +set dmsbcs 0x38 +set dmsbaddress0 0x39 +set dmsbdata0 0x3C + +proc target0_dmi_write_reg {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc target0_dmi_read_reg {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc sba_write_mem {addr value} { + target0_dmi_write_reg $::dmsbaddress0 ${addr} + target0_dmi_write_reg $::dmsbdata0 ${value} +} + +proc sba_read_mem {addr} { + set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }] + target0_dmi_write_reg $::dmsbcs ${sbcs} + target0_dmi_write_reg $::dmsbaddress0 ${addr} + set value [target0_dmi_read_reg $::dmsbdata0] + return ${value} +} diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common_csr.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common_csr.cfg new file mode 100644 index 000000000000..4f4b6dcd86a1 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common_csr.cfg @@ -0,0 +1,101 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# mslideleg +riscv expose_csrs 2005 +# mclk_ctl +riscv expose_csrs 2015 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# slie +riscv expose_csrs 2500 +# slip +riscv expose_csrs 2501 +# sdcause +riscv expose_csrs 2505 +# scctldata +riscv expose_csrs 2509 +# scounterinten +riscv expose_csrs 2511 +# scountermask_m +riscv expose_csrs 2513 +# scountermask_s +riscv expose_csrs 2514 +# scountermask_u +riscv expose_csrs 2515 +# scounterovf +riscv expose_csrs 2516 +# scountinhibit +riscv expose_csrs 2528 +# shpmevent3 +riscv expose_csrs 2531 +# shpmevent4 +riscv expose_csrs 2532 +# shpmevent5 +riscv expose_csrs 2533 +# shpmevent6 +riscv expose_csrs 2534 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg new file mode 100644 index 000000000000..096cee06355e --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg @@ -0,0 +1,69 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_reset.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_reset.cfg new file mode 100644 index 000000000000..681c59954789 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_reset.cfg @@ -0,0 +1,9 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +$_TARGET0 configure -event reset-deassert-pre { + sleep 1 + if {$halt} { + $::_TARGET0 arp_halt + } +} diff --git a/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/flash_rtt.ld b/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/flash_rtt.ld index 12af13362ed3..6591432556e5 100644 --- a/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/flash_rtt.ld +++ b/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/flash_rtt.ld @@ -14,7 +14,7 @@ MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080300, LENGTH = 128K - 768 + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K } @@ -26,6 +26,15 @@ __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; SECTIONS { + /* Anchor the lowest LMA at the flash base address (0x80000000): objcopy takes the + * lowest LMA as the start address of the generated .bin, so without this marker the + * .bin starts at .nor_cfg_option (0x80000400). The value is all ones (erased flash), + * so programming it does not change the flash state. + */ + .flash_base ORIGIN(XPI0) : { + LONG(0xFFFFFFFF) + } > XPI0 + .nor_cfg_option __nor_cfg_option_load_addr__ : { KEEP(*(.nor_cfg_option)) } > XPI0 @@ -165,11 +174,19 @@ SECTIONS PROVIDE (_etext = .); PROVIDE (etext = .); + /* The first 0x300 bytes of DLM are reserved; keep them as an explicit NOLOAD + * placeholder. This also keeps the DLM region 4KB aligned so that the linker does + * not emit an extra file-backed PT_LOAD (which made "program rtthread.elf" fail). + */ + .dlm_reserved (NOLOAD) : { + . = . + 0x300; + } > DLM + .fast_ram (NOLOAD) : { KEEP(*(.fast_ram)) } > DLM - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); __fast_ram_init_start__ = .; @@ -179,6 +196,15 @@ SECTIONS . = ALIGN(8); } > DLM + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + /* Note: the .tbss and .tdata section should be adjacent */ .tbss(NOLOAD) : { . = ALIGN(8); @@ -256,7 +282,7 @@ SECTIONS PROVIDE (edata = .); } > DLM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); @@ -295,7 +321,7 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > DLM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; diff --git a/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/ram_rtt.ld b/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/ram_rtt.ld index 26d57856025f..6753ecbafdb2 100644 --- a/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/ram_rtt.ld +++ b/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/ram_rtt.ld @@ -112,6 +112,16 @@ SECTIONS . = ALIGN(8); } > ILM + + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > ILM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -213,7 +223,7 @@ SECTIONS *(.fast) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); - } > DLM + } > ILM __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { diff --git a/bsp/hpmicro/hpm5301evklite/board/pinmux.c b/bsp/hpmicro/hpm5301evklite/board/pinmux.c index 439a57dd452e..596b052e2a2e 100644 --- a/bsp/hpmicro/hpm5301evklite/board/pinmux.c +++ b/bsp/hpmicro/hpm5301evklite/board/pinmux.c @@ -53,7 +53,7 @@ void init_uart_pin_as_gpio(UART_Type *ptr) } } -void init_i2c_pins(I2C_Type *ptr) +hpm_stat_t init_i2c_pins(I2C_Type *ptr) { if (ptr == HPM_I2C2) { HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_I2C2_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; @@ -65,7 +65,10 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_I2C3_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + } else { + return status_invalid_argument; } + return status_success; } void init_gpio_pins(void) diff --git a/bsp/hpmicro/hpm5301evklite/board/pinmux.h b/bsp/hpmicro/hpm5301evklite/board/pinmux.h index 3e37d1bf1bcf..f78644611756 100644 --- a/bsp/hpmicro/hpm5301evklite/board/pinmux.h +++ b/bsp/hpmicro/hpm5301evklite/board/pinmux.h @@ -14,7 +14,7 @@ extern "C" { void init_py_pins_as_pgpio(void); void init_uart_pins(UART_Type *ptr); void init_uart_pin_as_gpio(UART_Type *ptr); -void init_i2c_pins(I2C_Type *ptr); +hpm_stat_t init_i2c_pins(I2C_Type *ptr); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); diff --git a/bsp/hpmicro/hpm5301evklite/board/rtt_board.c b/bsp/hpmicro/hpm5301evklite/board/rtt_board.c index 3c1ef45f2b59..ac7edf6d44e2 100644 --- a/bsp/hpmicro/hpm5301evklite/board/rtt_board.c +++ b/bsp/hpmicro/hpm5301evklite/board/rtt_board.c @@ -40,14 +40,20 @@ void os_tick_config(void) void rtt_board_init(void) { board_init_clock(); + + /* initialize memory system + * NOTE: this must happen before board_init_console(), because the SDK console_init() + * calls setvbuf(), which allocates through the C library malloc() -> rt_malloc() and + * therefore requires the RT-Thread heap to be ready. Otherwise RT_ASSERT() fires in + * rt_smem_alloc() whenever RT_USING_DEBUG is enabled. + */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + board_init_console(); board_init_pmp(); dma_mgr_init(); - /* initialize memory system */ - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); - /* Configure the OS Tick */ os_tick_config(); diff --git a/bsp/hpmicro/hpm5301evklite/makefile.targets b/bsp/hpmicro/hpm5301evklite/makefile.targets new file mode 100644 index 000000000000..4583a13f1cd3 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/makefile.targets @@ -0,0 +1,6 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' + +*.elf: $(wildcard board/linker_scripts/gcc/*.ld) diff --git a/bsp/hpmicro/hpm5301evklite/rtconfig.h b/bsp/hpmicro/hpm5301evklite/rtconfig.h index a2b1da3c1637..77da4e4121b5 100644 --- a/bsp/hpmicro/hpm5301evklite/rtconfig.h +++ b/bsp/hpmicro/hpm5301evklite/rtconfig.h @@ -7,6 +7,16 @@ /* rt_vsnprintf options */ +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 /* end of rt_vsnprintf options */ /* rt_vsscanf options */ @@ -104,7 +114,7 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50301 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define ARCH_RISCV @@ -290,6 +300,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -317,12 +331,24 @@ /* HPMicro SDK */ #define PKG_USING_HPM_SDK -#define PKG_USING_HPM_SDK_V110 +#define PKG_USING_HPM_SDK_V113 /* end of HPMicro SDK */ +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -402,11 +428,11 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ -#define SOC_HPM5300_SERIES +#define SOC_SERIES_HPM5300 /* Hardware Drivers Config */ -#define SOC_HPM5300 +#define SOC_HPM5000 /* On-chip Peripheral Drivers */ @@ -418,6 +444,29 @@ #define BSP_UART0_TX_BUFSIZE 0 #define BSP_UART0_IRQ_PRIORITY 1 /* end of On-chip Peripheral Drivers */ + +/* HPMicro Interrupt Config */ + +/* HPMicro RT-Thread Interrupt Framework */ + +/* HPMicro Use Generic Startup Implementation */ + +/* end of HPMicro Use Generic Startup Implementation */ + +/* HPMicro RT-Thread backtrace configuration (experimental) */ + +/* end of HPMicro RT-Thread backtrace configuration (experimental) */ /* end of Hardware Drivers Config */ +/* Third-Party Add-ons */ + +/* Segger SystemView Config */ + +/* end of Segger SystemView Config */ + +/* RT-Thread Insight Config */ + +/* end of RT-Thread Insight Config */ +/* end of Third-Party Add-ons */ + #endif diff --git a/bsp/hpmicro/hpm5301evklite/rtconfig.py b/bsp/hpmicro/hpm5301evklite/rtconfig.py index dc209cee21f5..b7720eadf3ee 100644 --- a/bsp/hpmicro/hpm5301evklite/rtconfig.py +++ b/bsp/hpmicro/hpm5301evklite/rtconfig.py @@ -3,7 +3,6 @@ import os import sys -import rtconfig if os.getenv('RTT_ROOT'): @@ -11,7 +10,7 @@ else: RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +sys.path.insert(0, os.path.join(RTT_ROOT, 'tools')) # toolchains options ARCH='risc-v' @@ -59,9 +58,13 @@ else: EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' else: - print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + print("CROSS_TOOL = {} not yet supported, only gcc is supported".format(CROSS_TOOL)) + exit(-1) -BUILD = 'flash_debug' +if os.getenv('RTT_BUILD_TYPE'): + BUILD = os.getenv('RTT_BUILD_TYPE') +else: + BUILD = 'flash_debug' if PLATFORM == 'gcc': PREFIX = 'riscv32-unknown-elf-' @@ -81,7 +84,7 @@ DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' CFLAGS = DEVICE AFLAGS = CFLAGS - LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' CPATH = '' LPATH = '' @@ -89,8 +92,8 @@ if BUILD == 'ram_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' @@ -99,8 +102,8 @@ elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': diff --git a/bsp/hpmicro/hpm5301evklite/rtconfig_preinc.h b/bsp/hpmicro/hpm5301evklite/rtconfig_preinc.h new file mode 100644 index 000000000000..f2f33d8ed185 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/rtconfig_preinc.h @@ -0,0 +1,20 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define D25 +#define HPM5301 +#define HPMSOC_HAS_HPMSDK_DMAV2 +#define HPM_SDK_L1C_NO_REENTRANT 1 +#define HPM_SOC_ISR_NUM 73 +#define RT_USING_LIBC +#define RT_USING_NEWLIBC +#define USE_DMA_DECLARE_EXT_ISR_M 1 +#define _POSIX_C_SOURCE 1 +#define _REENT_SMALL +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/SConscript b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/SConscript index 3e8dd931d383..406b1414099a 100644 --- a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/SConscript +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/SConscript @@ -15,7 +15,7 @@ if rtconfig.PLATFORM == 'gcc': src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')] CPPPATH = [cwd] -CPPDEFINES=['D45', rtconfig.CHIP_NAME] +CPPDEFINES=['D25', rtconfig.CHIP_NAME] group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c index 36ec0334321b..96699f5bfd52 100644 --- a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c @@ -54,6 +54,8 @@ extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; + extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; /* tbss section */ size = __tbss_end__ - __tbss_start__; @@ -96,6 +98,18 @@ for (i = 0; i < size; i++) { *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } + + /* fast_ram bss section */ + size = __fast_ram_bss_end__ - __fast_ram_bss_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_bss_start__ + i) = 0; + } + + /* fast_ram init section LMA: etext + data length + ramfunc length + tdata length */ + size = __fast_ram_init_end__ - __fast_ram_init_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); + } #endif } diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/start.S b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/start.S index 76463936442f..d4e7a4fd61b4 100644 --- a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/start.S @@ -19,14 +19,6 @@ _start: la tp, __thread_pointer .option pop -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif /* Initialize stack pointer */ la t0, _stack mv sp, t0 @@ -45,12 +37,20 @@ _start: /* Initialize FCSR */ fscsr zero #endif - /* Disable Vector mode */ - csrci CSR_MMISC_CTL, 2 - /* Initialize trap_entry base */ + +#ifdef HPM_USING_VECTOR_PREEMPTED_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ la t0, SW_handler csrw mtvec, t0 - + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif /* System reset handler */ call reset_handler @@ -62,7 +62,7 @@ _start: nmi_handler: 1: j 1b - .global default_irq_handler +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK .weak default_irq_handler .align 2 default_irq_handler: @@ -75,3 +75,13 @@ default_irq_handler: .endm #include "vectors.S" +#else + .section .vector_table, "a" + .global __vector_table + .align 9 + +__vector_table: + .rept RT_HW_ISR_NUM + .long handle_trap + .endr +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ \ No newline at end of file diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/vectors.S index 8f10ab7bddf3..5703e223309e 100644 --- a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/vectors.S +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/vectors.S @@ -20,74 +20,90 @@ __vector_table: IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ - IRQ_HANDLER 8 /* ADC0 IRQ handler */ - IRQ_HANDLER 9 /* ADC1 IRQ handler */ - IRQ_HANDLER 10 /* ADC2 IRQ handler */ - IRQ_HANDLER 11 /* DAC IRQ handler */ - IRQ_HANDLER 12 /* ACMP[0] IRQ handler */ - IRQ_HANDLER 13 /* ACMP[1] IRQ handler */ - IRQ_HANDLER 14 /* SPI0 IRQ handler */ - IRQ_HANDLER 15 /* SPI1 IRQ handler */ - IRQ_HANDLER 16 /* SPI2 IRQ handler */ - IRQ_HANDLER 17 /* SPI3 IRQ handler */ - IRQ_HANDLER 18 /* UART0 IRQ handler */ - IRQ_HANDLER 19 /* UART1 IRQ handler */ - IRQ_HANDLER 20 /* UART2 IRQ handler */ - IRQ_HANDLER 21 /* UART3 IRQ handler */ - IRQ_HANDLER 22 /* UART4 IRQ handler */ - IRQ_HANDLER 23 /* UART5 IRQ handler */ - IRQ_HANDLER 24 /* UART6 IRQ handler */ - IRQ_HANDLER 25 /* UART7 IRQ handler */ - IRQ_HANDLER 26 /* CAN0 IRQ handler */ - IRQ_HANDLER 27 /* CAN1 IRQ handler */ - IRQ_HANDLER 28 /* PTPC IRQ handler */ - IRQ_HANDLER 29 /* WDG0 IRQ handler */ - IRQ_HANDLER 30 /* WDG1 IRQ handler */ - IRQ_HANDLER 31 /* TSNS IRQ handler */ - IRQ_HANDLER 32 /* MBX0A IRQ handler */ - IRQ_HANDLER 33 /* MBX0B IRQ handler */ - IRQ_HANDLER 34 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 35 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 36 /* GPTMR2 IRQ handler */ - IRQ_HANDLER 37 /* GPTMR3 IRQ handler */ - IRQ_HANDLER 38 /* I2C0 IRQ handler */ - IRQ_HANDLER 39 /* I2C1 IRQ handler */ - IRQ_HANDLER 40 /* I2C2 IRQ handler */ - IRQ_HANDLER 41 /* I2C3 IRQ handler */ - IRQ_HANDLER 42 /* PWM0 IRQ handler */ - IRQ_HANDLER 43 /* HALL0 IRQ handler */ - IRQ_HANDLER 44 /* QEI0 IRQ handler */ - IRQ_HANDLER 45 /* PWM1 IRQ handler */ - IRQ_HANDLER 46 /* HALL1 IRQ handler */ - IRQ_HANDLER 47 /* QEI1 IRQ handler */ - IRQ_HANDLER 48 /* SDP IRQ handler */ - IRQ_HANDLER 49 /* XPI0 IRQ handler */ - IRQ_HANDLER 50 /* XPI1 IRQ handler */ - IRQ_HANDLER 51 /* XDMA IRQ handler */ - IRQ_HANDLER 52 /* HDMA IRQ handler */ - IRQ_HANDLER 53 /* DRAM IRQ handler */ - IRQ_HANDLER 54 /* RNG IRQ handler */ - IRQ_HANDLER 55 /* I2S0 IRQ handler */ - IRQ_HANDLER 56 /* I2S1 IRQ handler */ - IRQ_HANDLER 57 /* DAO IRQ handler */ - IRQ_HANDLER 58 /* PDM IRQ handler */ - IRQ_HANDLER 59 /* FFA IRQ handler */ - IRQ_HANDLER 60 /* NTMR0 IRQ handler */ - IRQ_HANDLER 61 /* USB0 IRQ handler */ - IRQ_HANDLER 62 /* ENET0 IRQ handler */ - IRQ_HANDLER 63 /* SDXC0 IRQ handler */ - IRQ_HANDLER 64 /* PSEC IRQ handler */ - IRQ_HANDLER 65 /* PGPIO IRQ handler */ - IRQ_HANDLER 66 /* PWDG IRQ handler */ - IRQ_HANDLER 67 /* PTMR IRQ handler */ - IRQ_HANDLER 68 /* PUART IRQ handler */ - IRQ_HANDLER 69 /* FUSE IRQ handler */ - IRQ_HANDLER 70 /* SECMON IRQ handler */ - IRQ_HANDLER 71 /* RTC IRQ handler */ - IRQ_HANDLER 72 /* BUTN IRQ handler */ - IRQ_HANDLER 73 /* BGPIO IRQ handler */ - IRQ_HANDLER 74 /* BVIO IRQ handler */ - IRQ_HANDLER 75 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 76 /* SYSCTL IRQ handler */ - IRQ_HANDLER 77 /* DEBUG[0] IRQ handler */ - IRQ_HANDLER 78 /* DEBUG[1] IRQ handler */ + IRQ_HANDLER 8 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 9 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 10 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 11 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 15 /* ADC0 IRQ handler */ + IRQ_HANDLER 16 /* ADC1 IRQ handler */ + IRQ_HANDLER 17 /* ADC2 IRQ handler */ + IRQ_HANDLER 18 /* SDFM IRQ handler */ + IRQ_HANDLER 19 /* DAC0 IRQ handler */ + IRQ_HANDLER 20 /* DAC1 IRQ handler */ + IRQ_HANDLER 21 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 22 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 23 /* ACMP[2] IRQ handler */ + IRQ_HANDLER 24 /* ACMP[3] IRQ handler */ + IRQ_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_HANDLER 29 /* UART0 IRQ handler */ + IRQ_HANDLER 30 /* UART1 IRQ handler */ + IRQ_HANDLER 31 /* UART2 IRQ handler */ + IRQ_HANDLER 32 /* UART3 IRQ handler */ + IRQ_HANDLER 33 /* UART4 IRQ handler */ + IRQ_HANDLER 34 /* UART5 IRQ handler */ + IRQ_HANDLER 35 /* UART6 IRQ handler */ + IRQ_HANDLER 36 /* UART7 IRQ handler */ + IRQ_HANDLER 37 /* CAN0 IRQ handler */ + IRQ_HANDLER 38 /* CAN1 IRQ handler */ + IRQ_HANDLER 39 /* CAN2 IRQ handler */ + IRQ_HANDLER 40 /* CAN3 IRQ handler */ + IRQ_HANDLER 41 /* PTPC IRQ handler */ + IRQ_HANDLER 42 /* WDG0 IRQ handler */ + IRQ_HANDLER 43 /* WDG1 IRQ handler */ + IRQ_HANDLER 44 /* TSNS IRQ handler */ + IRQ_HANDLER 45 /* MBX0A IRQ handler */ + IRQ_HANDLER 46 /* MBX0B IRQ handler */ + IRQ_HANDLER 47 /* MBX1A IRQ handler */ + IRQ_HANDLER 48 /* MBX1B IRQ handler */ + IRQ_HANDLER 49 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 50 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 51 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 52 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 53 /* I2C0 IRQ handler */ + IRQ_HANDLER 54 /* I2C1 IRQ handler */ + IRQ_HANDLER 55 /* I2C2 IRQ handler */ + IRQ_HANDLER 56 /* I2C3 IRQ handler */ + IRQ_HANDLER 57 /* PWM0 IRQ handler */ + IRQ_HANDLER 58 /* HALL0 IRQ handler */ + IRQ_HANDLER 59 /* QEI0 IRQ handler */ + IRQ_HANDLER 60 /* PWM1 IRQ handler */ + IRQ_HANDLER 61 /* HALL1 IRQ handler */ + IRQ_HANDLER 62 /* QEI1 IRQ handler */ + IRQ_HANDLER 63 /* PWM2 IRQ handler */ + IRQ_HANDLER 64 /* HALL2 IRQ handler */ + IRQ_HANDLER 65 /* QEI2 IRQ handler */ + IRQ_HANDLER 66 /* PWM3 IRQ handler */ + IRQ_HANDLER 67 /* HALL3 IRQ handler */ + IRQ_HANDLER 68 /* QEI3 IRQ handler */ + IRQ_HANDLER 69 /* SDP IRQ handler */ + IRQ_HANDLER 70 /* XPI0 IRQ handler */ + IRQ_HANDLER 71 /* XDMA IRQ handler */ + IRQ_HANDLER 72 /* HDMA IRQ handler */ + IRQ_HANDLER 73 /* RNG IRQ handler */ + IRQ_HANDLER 74 /* USB0 IRQ handler */ + IRQ_HANDLER 75 /* PSEC IRQ handler */ + IRQ_HANDLER 76 /* PGPIO IRQ handler */ + IRQ_HANDLER 77 /* PWDG IRQ handler */ + IRQ_HANDLER 78 /* PTMR IRQ handler */ + IRQ_HANDLER 79 /* PUART IRQ handler */ + IRQ_HANDLER 80 /* FUSE IRQ handler */ + IRQ_HANDLER 81 /* SECMON IRQ handler */ + IRQ_HANDLER 82 /* RTC IRQ handler */ + IRQ_HANDLER 83 /* BUTN IRQ handler */ + IRQ_HANDLER 84 /* BGPIO IRQ handler */ + IRQ_HANDLER 85 /* BVIO IRQ handler */ + IRQ_HANDLER 86 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 87 /* SYSCTL IRQ handler */ + IRQ_HANDLER 88 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 89 /* DEBUG[1] IRQ handler */ + IRQ_HANDLER 90 /* LIN0 IRQ handler */ + IRQ_HANDLER 91 /* LIN1 IRQ handler */ + IRQ_HANDLER 92 /* LIN2 IRQ handler */ + IRQ_HANDLER 93 /* LIN3 IRQ handler */ + diff --git a/bsp/hpmicro/hpm5301evklite/startup/SConscript b/bsp/hpmicro/hpm5301evklite/startup/SConscript index 10776376b717..11a9d203d4ce 100644 --- a/bsp/hpmicro/hpm5301evklite/startup/SConscript +++ b/bsp/hpmicro/hpm5301evklite/startup/SConscript @@ -8,6 +8,5 @@ cwd = GetCurrentDir() objs = [] objs = objs + SConscript(os.path.join(rtconfig.CHIP_NAME, 'SConscript')) -ASFLAGS = ' -I' + cwd Return('objs') \ No newline at end of file diff --git a/bsp/hpmicro/hpm5e00evk/.config b/bsp/hpmicro/hpm5e00evk/.config index 56353cc1ce3c..a5e80f410516 100644 --- a/bsp/hpmicro/hpm5e00evk/.config +++ b/bsp/hpmicro/hpm5e00evk/.config @@ -11,8 +11,18 @@ # rt_vsnprintf options # # CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_vsnprintf options # @@ -178,7 +188,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y -CONFIG_RT_VER_NUM=0x50300 +CONFIG_RT_VER_NUM=0x50301 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -237,11 +247,11 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -262,10 +272,10 @@ CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -458,6 +468,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -573,6 +584,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set # end of multimedia packages # @@ -632,6 +644,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set # end of tools packages # @@ -780,6 +794,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set # end of STM32 HAL & SDK Drivers # @@ -813,7 +829,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -892,11 +922,18 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HPM_SDK=y CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" -CONFIG_PKG_USING_HPM_SDK_V110=y +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_V113=y # CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION is not set -CONFIG_PKG_HPM_SDK_VER="v1.10.0" +CONFIG_PKG_HPM_SDK_VER="v1.13.0" # end of HPMicro SDK +# +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + # # FT32 HAL & SDK Drivers # @@ -905,6 +942,23 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -984,6 +1038,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set # CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set # end of sensors drivers # @@ -1038,6 +1093,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1088,6 +1144,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1105,6 +1162,9 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set # CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set # end of AI packages # @@ -1162,6 +1222,8 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set @@ -1187,6 +1249,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1426,7 +1489,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # end of Arduino libraries # end of RT-Thread online packages -CONFIG_SOC_HPM5E00_SERIES=y +CONFIG_SOC_SERIES_HPM5E00=y # # Hardware Drivers Config @@ -1452,15 +1515,72 @@ CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_UART5 is not set # CONFIG_BSP_USING_UART6 is not set # CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_PUART is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_GPTMR is not set # CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_XPI_FLASH is not set +# CONFIG_BSP_USING_DAO is not set +# CONFIG_BSP_USING_PDM is not set +# CONFIG_BSP_USING_I2S is not set # CONFIG_BSP_USING_USB is not set # CONFIG_BSP_USING_EWDG is not set # CONFIG_BSP_USING_PWMV2 is not set # CONFIG_BSP_USING_MCAN is not set # CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_WDG is not set +# CONFIG_BSP_USING_ACMP is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_TSNS is not set +# CONFIG_BSP_USING_OWR is not set +# CONFIG_BSP_USING_QEIV2 is not set +# CONFIG_BSP_USING_QEOV2 is not set +# CONFIG_BSP_USING_SDM is not set +# CONFIG_BSP_USING_PLB is not set +# CONFIG_BSP_USING_PPI is not set +# CONFIG_BSP_USING_LOBS is not set +# CONFIG_BSP_USING_PTPC is not set +# CONFIG_BSP_USING_ESC is not set +# CONFIG_BSP_USING_MCHTMR is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SOFT_SPI is not set # end of On-chip Peripheral Drivers + +# +# HPMicro Interrupt Config +# + +# +# HPMicro RT-Thread Interrupt Framework +# + +# +# HPMicro Use Generic Startup Implementation +# +# end of HPMicro Use Generic Startup Implementation + +# +# HPMicro RT-Thread backtrace configuration (experimental) +# +# CONFIG_HPM_ENABLE_RTTHREAD_BACKTRACE_PORT is not set +# CONFIG_HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER is not set +# end of HPMicro RT-Thread backtrace configuration (experimental) # end of Hardware Drivers Config + +# +# Third-Party Add-ons +# + +# +# Segger SystemView Config +# +# CONFIG_BSP_USING_SYSTEMVIEW is not set +# end of Segger SystemView Config + +# +# RT-Thread Insight Config +# +# CONFIG_BSP_USING_RTI is not set +# end of RT-Thread Insight Config +# end of Third-Party Add-ons diff --git a/bsp/hpmicro/hpm5e00evk/.cproject b/bsp/hpmicro/hpm5e00evk/.cproject index eafefd8ef55a..437444787bf8 100644 --- a/bsp/hpmicro/hpm5e00evk/.cproject +++ b/bsp/hpmicro/hpm5e00evk/.cproject @@ -20,7 +20,7 @@ @@ -111,7 +111,7 @@