diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/SConscript b/bsp/stm32/libraries/HAL_Drivers/drivers/SConscript index 0a9ceb24da50..cdeae73b9bd5 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/SConscript +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/SConscript @@ -36,6 +36,9 @@ if GetDepend(['RT_USING_SPI']): if GetDepend(['RT_USING_QSPI']): src += ['drv_qspi.c'] +if GetDepend(['RT_USING_OSPI']): + src += ['drv_ospi.c'] + if GetDepend(['RT_USING_I2C']): if GetDepend('BSP_USING_HARD_I2C1') or GetDepend('BSP_USING_HARD_I2C2') or GetDepend('BSP_USING_HARD_I2C3') or GetDepend('BSP_USING_HARD_I2C4'): src += ['drv_hard_i2c.c'] diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/ospi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/ospi_config.h new file mode 100644 index 000000000000..da61e09db816 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/ospi_config.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-08-17 CliffLL first version + */ + +#ifndef __OSPI_CONFIG_H__ +#define __OSPI_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_OSPI +#ifndef OSPI_INSTANCE +#define OSPI_INSTANCE OCTOSPI1 +#endif + +#ifndef OSPI_MEMORY_TYPE +#define OSPI_MEMORY_TYPE HAL_OSPI_MEMTYPE_MACRONIX +#endif + +#ifndef OSPI_CLK_PORT +#define OSPI_CLK_PORT 1U +#endif + +#ifndef OSPI_DQS_PORT +#define OSPI_DQS_PORT 1U +#endif + +#ifndef OSPI_NCS_PORT +#define OSPI_NCS_PORT 1U +#endif + +#ifndef OSPI_IO_LOW_PORT +#define OSPI_IO_LOW_PORT HAL_OSPIM_IOPORT_1_LOW +#endif + +#ifndef OSPI_IO_HIGH_PORT +#define OSPI_IO_HIGH_PORT HAL_OSPIM_IOPORT_1_HIGH +#endif + +#ifndef OSPI_BUS_CONFIG +#define OSPI_BUS_CONFIG \ + { \ + .Instance = OSPI_INSTANCE, \ + .Init.FifoThreshold = 4, \ + .Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE, \ + .Init.ChipSelectHighTime = 2, \ + .Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE, \ + .Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE, \ + .Init.ChipSelectBoundary = 0, \ + .Init.MemoryType = OSPI_MEMORY_TYPE, \ + } +#endif /* OSPI_BUS_CONFIG */ +#endif /* BSP_USING_OSPI */ + +#ifdef __cplusplus +} +#endif + +#endif /* __OSPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h index 80a2897ecdfd..5e7b0e7a8d79 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-10-30 SummerGift first version * 2020-10-14 PeakRacing Porting for stm32wbxx + * 2026-08-18 CliffLL add l4/ospi_config.h */ #ifndef __DRV_CONFIG_H__ @@ -88,6 +89,7 @@ extern "C" { #include "l4/uart_config.h" #include "l4/spi_config.h" #include "l4/qspi_config.h" +#include "l4/ospi_config.h" #include "l4/adc_config.h" #include "l4/adc_config_v2.h" #include "l4/dac_config.h" diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_ospi.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_ospi.c new file mode 100644 index 000000000000..71d5c6012548 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_ospi.c @@ -0,0 +1,504 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-08-17 CliffLL first version + */ + +#include "board.h" +#include "drv_ospi.h" +#include "drv_dma.h" +#include "drv_config.h" + +#ifdef RT_USING_OSPI + +#define DRV_DEBUG +#define LOG_TAG "drv.ospi" +#include + +#if defined(BSP_USING_OSPI) + +struct stm32_ospi_bus +{ + OSPI_HandleTypeDef OSPI_Handler; + char *bus_name; +}; + +struct rt_spi_bus _ospi_bus1; +struct stm32_ospi_bus _stm32_ospi_bus; + +static int stm32_ospi_init(struct rt_ospi_device *device, struct rt_ospi_configuration *ospi_cfg) +{ + int result = RT_EOK; + unsigned int i = 1; + + OSPIM_CfgTypeDef OSPIM_Cfg_Struct = { 0 }; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(ospi_cfg != RT_NULL); + + struct rt_spi_configuration *cfg = &ospi_cfg->parent; + struct stm32_ospi_bus *ospi_bus = device->parent.bus->parent.user_data; + rt_memset(&ospi_bus->OSPI_Handler, 0, sizeof(ospi_bus->OSPI_Handler)); + + OSPI_HandleTypeDef OSPI_Handler_config = OSPI_BUS_CONFIG; + ospi_bus->OSPI_Handler = OSPI_Handler_config; + + while (cfg->max_hz < HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_OSPI) / (i + 1)) + { + i++; + if (i == 255) + { + LOG_E("OSPI init failed, OSPI frequency(%d) is too low.", cfg->max_hz); + return -RT_ERROR; + } + } + + ospi_bus->OSPI_Handler.Init.ClockPrescaler = i; + + if (!(cfg->mode & RT_SPI_CPOL)) + { + /* OSPI MODE0 */ + ospi_bus->OSPI_Handler.Init.ClockMode = HAL_OSPI_CLOCK_MODE_0; + } + else + { + /* OSPI MODE3 */ + ospi_bus->OSPI_Handler.Init.ClockMode = HAL_OSPI_CLOCK_MODE_3; + } + + /* flash size */ + ospi_bus->OSPI_Handler.Init.DeviceSize = POSITION_VAL(ospi_cfg->medium_size); + + /* dqs mode */ + if (ospi_cfg->dtr_mode) + { + /* OSPI DTR MODE */ + ospi_bus->OSPI_Handler.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE; + } + else + { + /* OSPI STR MODE */ + ospi_bus->OSPI_Handler.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_DISABLE; + } + + result = HAL_OSPI_Init(&ospi_bus->OSPI_Handler); + if (result == HAL_OK) + { + LOG_D("ospi init success!"); + } + else + { + LOG_E("ospi init failed (%d)!", result); + return -RT_EIO; + } + + OSPIM_Cfg_Struct.ClkPort = OSPI_CLK_PORT; + OSPIM_Cfg_Struct.DQSPort = OSPI_DQS_PORT; + OSPIM_Cfg_Struct.NCSPort = OSPI_NCS_PORT; + OSPIM_Cfg_Struct.IOLowPort = OSPI_IO_LOW_PORT; + OSPIM_Cfg_Struct.IOHighPort = OSPI_IO_HIGH_PORT; + + if (HAL_OSPIM_Config(&ospi_bus->OSPI_Handler, &OSPIM_Cfg_Struct, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + LOG_E("ospim init failed !"); + return -RT_EIO; + } + + return result; +} + +static rt_err_t stm32_ospi_recover(struct rt_spi_device *device) +{ + HAL_StatusTypeDef status; + struct rt_ospi_device *ospi_device; + struct stm32_ospi_bus *ospi_bus; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + + ospi_device = (struct rt_ospi_device *)device; + ospi_bus = device->bus->parent.user_data; + + RT_ASSERT(ospi_bus != RT_NULL); + + /* + * Abort may fail if the previous command did not enter a transferable + * state, but DeInit is still attempted for controller recovery. + */ + status = HAL_OSPI_Abort(&ospi_bus->OSPI_Handler); + if (status != HAL_OK) + { + LOG_W("HAL_OSPI_Abort failed, status=%d, error=0x%08X", (int)status, (unsigned int)ospi_bus->OSPI_Handler.ErrorCode); + } + + status = HAL_OSPI_DeInit(&ospi_bus->OSPI_Handler); + if (status != HAL_OK) + { + LOG_E("HAL_OSPI_DeInit failed, status=%d, error=0x%08X", (int)status, (unsigned int)ospi_bus->OSPI_Handler.ErrorCode); + return -RT_EIO; + } + + /* + * Rebuild OSPI Handle and configure OSPIM routing using the current + * OSPI device configuration. + */ + return stm32_ospi_init(ospi_device, &ospi_device->config); +} + +static rt_err_t ospi_send_cmd(struct stm32_ospi_bus *ospi_bus, struct rt_ospi_message *message) +{ + RT_ASSERT(ospi_bus != RT_NULL); + RT_ASSERT(message != RT_NULL); + + OSPI_RegularCmdTypeDef Cmdhandler = { 0 }; + HAL_StatusTypeDef status; + + /* set OSPI cmd struct */ + Cmdhandler.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; + Cmdhandler.FlashId = HAL_OSPI_FLASH_ID_1; + Cmdhandler.Instruction = message->instruction.content; + Cmdhandler.Address = message->address.content; + Cmdhandler.DummyCycles = message->dummy_cycles; + if (message->instruction.ospi_lines == 0) + { + Cmdhandler.InstructionMode = HAL_OSPI_INSTRUCTION_NONE; + } + else if (message->instruction.ospi_lines == 1) + { + Cmdhandler.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE; + } + else if (message->instruction.ospi_lines == 2) + { + Cmdhandler.InstructionMode = HAL_OSPI_INSTRUCTION_2_LINES; + } + else if (message->instruction.ospi_lines == 4) + { + Cmdhandler.InstructionMode = HAL_OSPI_INSTRUCTION_4_LINES; + } + else if (message->instruction.ospi_lines == 8) + { + Cmdhandler.InstructionMode = HAL_OSPI_INSTRUCTION_8_LINES; + } + else + { + return -RT_EINVAL; + } + + if (message->instruction.dtrmode == 0) + { + Cmdhandler.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE; + } + else if (message->instruction.dtrmode == 1) + { + Cmdhandler.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_ENABLE; + } + else + { + return -RT_EINVAL; + } + + if (message->instruction.size == 8) + { + Cmdhandler.InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS; + } + else if (message->instruction.size == 16) + { + Cmdhandler.InstructionSize = HAL_OSPI_INSTRUCTION_16_BITS; + } + else + { + return -RT_EINVAL; + } + + if (message->address.ospi_lines == 0) + { + Cmdhandler.AddressMode = HAL_OSPI_ADDRESS_NONE; + } + else + { + if (message->address.ospi_lines == 1) + { + Cmdhandler.AddressMode = HAL_OSPI_ADDRESS_1_LINE; + } + else if (message->address.ospi_lines == 2) + { + Cmdhandler.AddressMode = HAL_OSPI_ADDRESS_2_LINES; + } + else if (message->address.ospi_lines == 4) + { + Cmdhandler.AddressMode = HAL_OSPI_ADDRESS_4_LINES; + } + else if (message->address.ospi_lines == 8) + { + Cmdhandler.AddressMode = HAL_OSPI_ADDRESS_8_LINES; + } + else + { + return -RT_EINVAL; + } + + if (message->address.dtrmode == 0) + { + Cmdhandler.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE; + } + else if (message->address.dtrmode == 1) + { + Cmdhandler.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_ENABLE; + } + else + { + return -RT_EINVAL; + } + + if (message->address.size == 24) + { + Cmdhandler.AddressSize = HAL_OSPI_ADDRESS_24_BITS; + } + else if (message->address.size == 32) + { + Cmdhandler.AddressSize = HAL_OSPI_ADDRESS_32_BITS; + } + else + { + return -RT_EINVAL; + } + } + + if (message->ospi_data_lines == 0) + { + Cmdhandler.DataMode = HAL_OSPI_DATA_NONE; + } + else if (message->ospi_data_lines == 1) + { + Cmdhandler.DataMode = HAL_OSPI_DATA_1_LINE; + } + else if (message->ospi_data_lines == 2) + { + Cmdhandler.DataMode = HAL_OSPI_DATA_2_LINES; + } + else if (message->ospi_data_lines == 4) + { + Cmdhandler.DataMode = HAL_OSPI_DATA_4_LINES; + } + else if (message->ospi_data_lines == 8) + { + Cmdhandler.DataMode = HAL_OSPI_DATA_8_LINES; + } + else + { + return -RT_EINVAL; + } + + if (message->ospi_data_dtrmode == 0) + { + Cmdhandler.DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE; + } + else if (message->ospi_data_dtrmode == 1) + { + Cmdhandler.DataDtrMode = HAL_OSPI_DATA_DTR_ENABLE; + } + else + { + return -RT_EINVAL; + } + + if (message->dqs_mode == 0) + { + Cmdhandler.DQSMode = HAL_OSPI_DQS_DISABLE; + } + else if (message->dqs_mode == 1) + { + Cmdhandler.DQSMode = HAL_OSPI_DQS_ENABLE; + } + else + { + return -RT_EINVAL; + } + + Cmdhandler.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD; + + /* Alternate bytes are not required by currently supported */ + Cmdhandler.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; + Cmdhandler.NbData = message->parent.length; + + status = HAL_OSPI_Command(&ospi_bus->OSPI_Handler, &Cmdhandler, 5000); + if (status != HAL_OK) + { + LOG_E("HAL_OSPI_Command failed, status=%d, error=0x%08X", (int)status, (unsigned int)ospi_bus->OSPI_Handler.ErrorCode); + if (HAL_OSPI_Abort(&ospi_bus->OSPI_Handler) != HAL_OK) + { + LOG_E("HAL_OSPI_Abort failed, error=0x%08X", (unsigned int)ospi_bus->OSPI_Handler.ErrorCode); + } + return -RT_EIO; + } + + return RT_EOK; +} + +static rt_ssize_t ospixfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + rt_ssize_t result = 0; + rt_err_t cmd_result; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + + struct rt_ospi_message *ospi_message = (struct rt_ospi_message *)message; + struct stm32_ospi_bus *ospi_bus = device->bus->parent.user_data; + + const rt_uint8_t *sndb = message->send_buf; + rt_uint8_t *rcvb = message->recv_buf; + rt_int32_t length = message->length; + + /* Length < 0 is invalid */ + if (length < 0) + { + return -RT_EINVAL; + } + + /* Length > 0 but neither TX or RX buffer exists is invalid */ + if ((length > 0) && (sndb == RT_NULL) && (rcvb == RT_NULL)) + { + return -RT_EINVAL; + } + + /* TX and RX buffer exists at the same time is invalid */ + if ((sndb != RT_NULL) && (rcvb != RT_NULL)) + { + return -RT_EINVAL; + } + + /* Execute HAL_OSPI_Command */ + cmd_result = ospi_send_cmd(ospi_bus, ospi_message); + if (cmd_result != RT_EOK) + { + if (stm32_ospi_recover(device) != RT_EOK) + { + LOG_W("OSPI controller recovery failed after command error."); + } + return cmd_result; + } + + /* send only header */ + if (length == 0) + { + /* rt_ospi_transfer_message() treats zero as failure, return a positive value for a successful command-only transfer */ + return 1; + } + else if (sndb)/* send data */ + { + if (HAL_OSPI_Transmit(&ospi_bus->OSPI_Handler, (rt_uint8_t *)sndb, 5000) == HAL_OK) + { + return length; + } + else + { + LOG_E("OSPI send data failed(%d)!", ospi_bus->OSPI_Handler.ErrorCode); + if (stm32_ospi_recover(device) != RT_EOK) + { + LOG_W("OSPI controller recovery failed after transmit error."); + } + return -RT_EIO; + } + } + else if (rcvb)/* recv data */ + { + if (HAL_OSPI_Receive(&ospi_bus->OSPI_Handler, rcvb, 5000) == HAL_OK) + { + return length; + } + else + { + LOG_E("OSPI recv data failed(%d)!", ospi_bus->OSPI_Handler.ErrorCode); + if (stm32_ospi_recover(device) != RT_EOK) + { + LOG_W("OSPI controller recovery failed after transmit error."); + } + return -RT_EIO; + } + } + + return -RT_EINVAL; +} + +static rt_err_t ospi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + struct rt_ospi_device *ospi_device = (struct rt_ospi_device *)device; + return stm32_ospi_init(ospi_device, &ospi_device->config); +} + +static const struct rt_spi_ops stm32_ospi_ops = { + .configure = ospi_configure, + .xfer = ospixfer, +}; + +static int stm32_ospi_register_bus(struct stm32_ospi_bus *ospi_bus, const char *name) +{ + RT_ASSERT(ospi_bus != RT_NULL); + RT_ASSERT(name != RT_NULL); + + _ospi_bus1.parent.user_data = ospi_bus; + return rt_ospi_bus_register(&_ospi_bus1, name, &stm32_ospi_ops); +} + +/** + * @brief This function attach device to OSPI bus. + * @param device_name OSPI device name + * @param enter_ospi_str_mode Callback function that lets FLASH enter STR-OPI mode + * @param enter_ospi_dtr_mode Callback function that lets FLASH enter DTR-OPI mode + * @param exit_ospi_mode Callback function that lets FLASH exit OSPI mode + * @retval 0 : success + * -1 : failed + */ +rt_err_t rt_hw_ospi_device_attach(const char *bus_name, const char *device_name, rt_err_t (*enter_ospi_str_mode)(struct rt_ospi_device *device), rt_err_t (*enter_ospi_dtr_mode)(struct rt_ospi_device *device), rt_err_t (*exit_ospi_mode)(struct rt_ospi_device *device)) +{ + struct rt_ospi_device *ospi_device = RT_NULL; + rt_err_t result = RT_EOK; + + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + + ospi_device = (struct rt_ospi_device *)rt_malloc(sizeof(struct rt_ospi_device)); + if (ospi_device == RT_NULL) + { + LOG_E("no memory, ospi bus attach device failed!"); + result = -RT_ENOMEM; + goto __exit; + } + rt_memset(ospi_device, 0, sizeof(struct rt_ospi_device)); + ospi_device->config.dtr_mode = 0; + ospi_device->ospi_mode = RT_OSPI_MODE_OFF; + + ospi_device->enter_ospi_str_mode = enter_ospi_str_mode; + ospi_device->enter_ospi_dtr_mode = enter_ospi_dtr_mode; + ospi_device->exit_ospi_mode = exit_ospi_mode; + + result = rt_spi_bus_attach_device_cspin(&ospi_device->parent, device_name, bus_name, PIN_NONE, RT_NULL); + +__exit: + if (result != RT_EOK) + { + if (ospi_device) + { + rt_free(ospi_device); + } + } + + return result; +} + +static int rt_hw_ospi_bus_init(void) +{ + return stm32_ospi_register_bus(&_stm32_ospi_bus, "ospi1"); +} +INIT_BOARD_EXPORT(rt_hw_ospi_bus_init); + +#endif /* BSP_USING_OSPI */ +#endif /* RT_USING_OSPI */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_ospi.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_ospi.h new file mode 100644 index 000000000000..19a07a83c73e --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_ospi.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-08-17 CliffLL first version + */ + +#ifndef __DRV_OSPI_H__ +#define __DRV_OSPI_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct rt_ospi_device; +rt_err_t rt_hw_ospi_device_attach(const char *bus_name, const char *device_name, rt_err_t (*enter_ospi_str_mode)(struct rt_ospi_device *device), rt_err_t (*enter_ospi_dtr_mode)(struct rt_ospi_device *device), rt_err_t (*exit_ospi_mode)(struct rt_ospi_device *device)); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_OSPI_H__ */ diff --git a/bsp/stm32/stm32l4r9-st-eval/.config b/bsp/stm32/stm32l4r9-st-eval/.config index 36d50770b621..42c2fb5019e7 100644 --- a/bsp/stm32/stm32l4r9-st-eval/.config +++ b/bsp/stm32/stm32l4r9-st-eval/.config @@ -242,10 +242,11 @@ CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set -CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set @@ -254,7 +255,6 @@ CONFIG_RT_USING_I2C_BITOPS=y # CONFIG_RT_USING_SOFT_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -267,7 +267,22 @@ CONFIG_RT_USING_I2C_BITOPS=y # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set +CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set +# CONFIG_RT_USING_SOFT_SPI is not set +# CONFIG_RT_USING_QSPI is not set +CONFIG_RT_USING_OSPI=y +# CONFIG_RT_USING_SPI_MSD is not set +CONFIG_RT_USING_SFUD=y +# CONFIG_RT_SFUD_USING_SFDP is not set +CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y +# CONFIG_RT_SFUD_USING_QSPI is not set +CONFIG_RT_SFUD_USING_OSPI=y +CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 +# CONFIG_RT_DEBUG_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set @@ -275,10 +290,10 @@ CONFIG_RT_USING_I2C_BITOPS=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -471,6 +486,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -647,6 +663,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set # end of tools packages # @@ -836,7 +853,21 @@ CONFIG_PKG_STM32L4_CMSIS_DRIVER_VER="latest" # CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -924,6 +955,23 @@ CONFIG_PKG_STM32L4_CMSIS_DRIVER_VER="latest" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -1057,6 +1105,7 @@ CONFIG_PKG_STM32L4_CMSIS_DRIVER_VER="latest" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1107,6 +1156,7 @@ CONFIG_PKG_STM32L4_CMSIS_DRIVER_VER="latest" # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1209,6 +1259,7 @@ CONFIG_PKG_STM32L4_CMSIS_DRIVER_VER="latest" # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_GET_IRQ_PRIORITY is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1460,6 +1511,7 @@ CONFIG_SOC_SERIES_STM32L4=y # CONFIG_BSP_USING_STLINK_TO_USART=y # CONFIG_BSP_USING_DSI is not set +# CONFIG_BSP_USING_OSPI_FLASH is not set # # Enable Touch @@ -1475,10 +1527,10 @@ CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART=y CONFIG_BSP_STM32_UART_V1_TX_TIMEOUT=2000 CONFIG_BSP_USING_UART3=y -# CONFIG_BSP_UART3_RX_USING_DMA is not set -# CONFIG_BSP_UART3_TX_USING_DMA is not set +# CONFIG_BSP_USING_OSPI is not set # CONFIG_BSP_USING_SRAM is not set -# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_ADC_V2 is not set # CONFIG_BSP_USING_CRC is not set # CONFIG_BSP_USING_RNG is not set # CONFIG_BSP_USING_UDID is not set diff --git a/bsp/stm32/stm32l4r9-st-eval/README.md b/bsp/stm32/stm32l4r9-st-eval/README.md index e91aced25cf0..5734ad921d05 100644 --- a/bsp/stm32/stm32l4r9-st-eval/README.md +++ b/bsp/stm32/stm32l4r9-st-eval/README.md @@ -40,9 +40,11 @@ | LCD | 支持 | DSI mode round lcd | | TOUCH | 支持 | touch for round lcd | | SRAM | 支持 | | +| OSPI Flash | 支持 | | | **片上外设** | **支持情况** | **备注** | | GPIO | 支持 | | | UART | 支持 | USART3 | +| OCTOSPI | 支持 | OCTOSPI1 | diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/.mxproject index c20f8463309d..c358cca04d30 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/.mxproject @@ -1,13 +1,14 @@ [PreviousGenFiles] -HeaderPath=E:/0423/rt-thread/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc +HeaderPath=D:/rt-thread/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc HeaderFiles=stm32l4xx_it.h;stm32l4xx_hal_conf.h;main.h;gfxmmu_lut.h; -SourcePath=E:/0423/rt-thread/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src +SourcePath=D:/rt-thread/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src SourceFiles=stm32l4xx_it.c;stm32l4xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dsi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gfxmmu.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gfxmmu.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dsi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gfxmmu.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h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+SourceFiles=..\Src\main.c;..\Src\stm32l4xx_it.c;..\Src\stm32l4xx_hal_msp.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gfxmmu.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;../\Src/system_stm32l4xx.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gfxmmu.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;../\Src/system_stm32l4xx.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;null; +HeaderPath=C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers\STM32L4xx_HAL_Driver\Inc;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers\CMSIS\Device\ST\STM32L4xx\Include;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers\CMSIS\Include;..\Inc; +CDefines=USE_HAL_DRIVER;STM32L4R9xx;USE_HAL_DRIVER;STM32L4R9xx; diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/CubeMX_Config.ioc index b5a954c18e0e..b839ca7ed9f0 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/CubeMX_Config.ioc @@ -20,87 +20,123 @@ Mcu.IP2=FMC Mcu.IP3=GFXMMU Mcu.IP4=LTDC Mcu.IP5=NVIC -Mcu.IP6=RCC -Mcu.IP7=SYS -Mcu.IP8=USART3 -Mcu.IPNb=9 +Mcu.IP6=OCTOSPI1 +Mcu.IP7=RCC +Mcu.IP8=SYS +Mcu.IP9=USART3 +Mcu.IPNb=10 Mcu.Name=STM32L4R9A(G-I)Ix Mcu.Package=UFBGA169 -Mcu.Pin0=PE0 -Mcu.Pin1=PE1 -Mcu.Pin10=PF2 -Mcu.Pin11=PF1 -Mcu.Pin12=PF0 -Mcu.Pin13=PD7 -Mcu.Pin14=PC15-OSC32_OUT (PC15) -Mcu.Pin15=PF3 -Mcu.Pin16=PF4 -Mcu.Pin17=PF5 -Mcu.Pin18=PG4 -Mcu.Pin19=PG3 -Mcu.Pin2=PD0 -Mcu.Pin20=PG5 -Mcu.Pin21=PH0-OSC_IN (PH0) -Mcu.Pin22=PG1 -Mcu.Pin23=PE10 -Mcu.Pin24=PB11 -Mcu.Pin25=PD13 -Mcu.Pin26=PG2 -Mcu.Pin27=PD15 -Mcu.Pin28=PD14 -Mcu.Pin29=PH1-OSC_OUT (PH1) -Mcu.Pin3=PD4 -Mcu.Pin30=PG0 -Mcu.Pin31=PE9 -Mcu.Pin32=PE15 -Mcu.Pin33=PD12 -Mcu.Pin34=PD11 -Mcu.Pin35=PD10 -Mcu.Pin36=DSIHOST_D1P -Mcu.Pin37=DSIHOST_D1N -Mcu.Pin38=PF15 -Mcu.Pin39=PE8 -Mcu.Pin4=PD1 -Mcu.Pin40=PE14 -Mcu.Pin41=PD9 -Mcu.Pin42=PD8 -Mcu.Pin43=DSIHOST_CKP -Mcu.Pin44=DSIHOST_CKN -Mcu.Pin45=PF14 -Mcu.Pin46=PE7 -Mcu.Pin47=PE13 -Mcu.Pin48=DSIHOST_D0P -Mcu.Pin49=DSIHOST_D0N -Mcu.Pin5=PE4 -Mcu.Pin50=PF13 -Mcu.Pin51=PE12 -Mcu.Pin52=PF12 -Mcu.Pin53=PE11 -Mcu.Pin54=PB10 -Mcu.Pin55=VP_DMA2D_VS_DMA2D -Mcu.Pin56=VP_GFXMMU_VS_GFXMMU -Mcu.Pin57=VP_LTDC_DSIMode -Mcu.Pin58=VP_SYS_VS_Systick -Mcu.Pin6=PE3 -Mcu.Pin7=PD5 -Mcu.Pin8=PE5 -Mcu.Pin9=PC14-OSC32_IN (PC14) -Mcu.PinsNb=59 +Mcu.Pin0=PH2 +Mcu.Pin1=PE0 +Mcu.Pin10=PG11 +Mcu.Pin11=PC14-OSC32_IN (PC14) +Mcu.Pin12=PF2 +Mcu.Pin13=PF1 +Mcu.Pin14=PF0 +Mcu.Pin15=PD7 +Mcu.Pin16=PC15-OSC32_OUT (PC15) +Mcu.Pin17=PF3 +Mcu.Pin18=PF4 +Mcu.Pin19=PF5 +Mcu.Pin2=PE1 +Mcu.Pin20=PG4 +Mcu.Pin21=PG3 +Mcu.Pin22=PG5 +Mcu.Pin23=PH0-OSC_IN (PH0) +Mcu.Pin24=PG1 +Mcu.Pin25=PE10 +Mcu.Pin26=PB11 +Mcu.Pin27=PD13 +Mcu.Pin28=PG2 +Mcu.Pin29=PD15 +Mcu.Pin3=PD0 +Mcu.Pin30=PD14 +Mcu.Pin31=PH1-OSC_OUT (PH1) +Mcu.Pin32=PG0 +Mcu.Pin33=PE9 +Mcu.Pin34=PE15 +Mcu.Pin35=PD12 +Mcu.Pin36=PD11 +Mcu.Pin37=PD10 +Mcu.Pin38=DSIHOST_D1P +Mcu.Pin39=DSIHOST_D1N +Mcu.Pin4=PD4 +Mcu.Pin40=PC3 +Mcu.Pin41=PC4 +Mcu.Pin42=PF15 +Mcu.Pin43=PE8 +Mcu.Pin44=PE14 +Mcu.Pin45=PD9 +Mcu.Pin46=PD8 +Mcu.Pin47=DSIHOST_CKP +Mcu.Pin48=DSIHOST_CKN +Mcu.Pin49=PA6 +Mcu.Pin5=PD1 +Mcu.Pin50=PB1 +Mcu.Pin51=PF14 +Mcu.Pin52=PE7 +Mcu.Pin53=PE13 +Mcu.Pin54=DSIHOST_D0P +Mcu.Pin55=DSIHOST_D0N +Mcu.Pin56=PA3 +Mcu.Pin57=PA7 +Mcu.Pin58=PF13 +Mcu.Pin59=PE12 +Mcu.Pin6=PE4 +Mcu.Pin60=PA2 +Mcu.Pin61=PB0 +Mcu.Pin62=PB2 +Mcu.Pin63=PF12 +Mcu.Pin64=PE11 +Mcu.Pin65=PB10 +Mcu.Pin66=VP_DMA2D_VS_DMA2D +Mcu.Pin67=VP_GFXMMU_VS_GFXMMU +Mcu.Pin68=VP_LTDC_DSIMode +Mcu.Pin69=VP_OCTOSPI1_VS_octo +Mcu.Pin7=PE3 +Mcu.Pin70=VP_SYS_VS_Systick +Mcu.Pin8=PD5 +Mcu.Pin9=PE5 +Mcu.PinsNb=71 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32L4R9AIIx -MxCube.Version=5.0.1 -MxDb.Version=DB.5.0.1 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false +MxCube.Version=5.3.0 +MxDb.Version=DB.5.0.30 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +OCTOSPI1.ChipSelectBoundary=0 +OCTOSPI1.ChipSelectHighTime=2 +OCTOSPI1.ClockPrescaler=3 +OCTOSPI1.DeviceSize=26 +OCTOSPI1.FifoThreshold=4 +OCTOSPI1.IPParameters=FifoThreshold,DeviceSize,ChipSelectHighTime,ClockPrescaler,OperationType,ChipSelectBoundary +OCTOSPI1.OperationType=HAL_OSPI_OPTYPE_COMMON_CFG +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP +PA2.Locked=true +PA2.Mode=OCTOSPI1_Port1_NCS +PA2.Signal=OCTOSPIM_P1_NCS +PA3.Locked=true +PA3.Mode=OCTOSPI1_Port1_CLK +PA3.Signal=OCTOSPIM_P1_CLK +PA6.Locked=true +PA6.Signal=OCTOSPIM_P1_IO3 +PA7.Locked=true +PA7.Signal=OCTOSPIM_P1_IO2 +PB0.Locked=true +PB0.Signal=OCTOSPIM_P1_IO1 +PB1.Locked=true +PB1.Signal=OCTOSPIM_P1_IO0 PB10.GPIOParameters=GPIO_PuPd PB10.GPIO_PuPd=GPIO_PULLUP PB10.Mode=Asynchronous @@ -109,10 +145,17 @@ PB11.GPIOParameters=GPIO_PuPd PB11.GPIO_PuPd=GPIO_PULLUP PB11.Mode=Asynchronous PB11.Signal=USART3_RX +PB2.Locked=true +PB2.Mode=OCTOSPI1_Port1_DQS +PB2.Signal=OCTOSPIM_P1_DQS PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT +PC3.Locked=true +PC3.Signal=OCTOSPIM_P1_IO6 +PC4.Locked=true +PC4.Signal=OCTOSPIM_P1_IO7 PCC.Checker=true PCC.Line=STM32L4R9/S9 PCC.MCU=STM32L4R9A(G-I)Ix @@ -120,7 +163,7 @@ PCC.PartNumber=STM32L4R9AIIx PCC.Seq0=0 PCC.Series=STM32L4 PCC.Temperature=25 -PCC.Vdd=null +PCC.Vdd=3.0 PD0.Signal=FMC_D2_DA2 PD1.Signal=FMC_D3_DA3 PD10.Signal=FMC_D15_DA15 @@ -163,6 +206,8 @@ PF4.Signal=FMC_A4 PF5.Signal=FMC_A5 PG0.Signal=FMC_A10 PG1.Signal=FMC_A11 +PG11.Locked=true +PG11.Signal=OCTOSPIM_P1_IO5 PG2.Signal=FMC_A12 PG3.Signal=FMC_A13 PG4.Signal=FMC_A14 @@ -171,6 +216,8 @@ PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT +PH2.Locked=true +PH2.Signal=OCTOSPIM_P1_IO4 PinOutPanel.CurrentBGAView=Top PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true @@ -182,7 +229,7 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32L4R9AIIx -ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.13.0 +ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.14.0 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 @@ -199,7 +246,7 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=MDK-ARM V5 ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_LTDC_Init-LTDC-false-HAL-true,5-MX_FMC_Init-FMC-false-HAL-true,6-MX_DMA2D_Init-DMA2D-false-HAL-true,7-MX_DSIHOST_DSI_Init-DSIHOST-false-HAL-true,8-MX_GFXMMU_Init-GFXMMU-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_LTDC_Init-LTDC-false-HAL-true,5-MX_FMC_Init-FMC-false-HAL-true,6-MX_DMA2D_Init-DMA2D-false-HAL-true,7-MX_DSIHOST_DSI_Init-DSIHOST-false-HAL-true,8-MX_GFXMMU_Init-GFXMMU-false-HAL-true,9-MX_OCTOSPI1_Init-OCTOSPI1-false-HAL-true RCC.ADCFreq_Value=64000000 RCC.AHBFreq_Value=120000000 RCC.APB1Freq_Value=120000000 @@ -359,6 +406,8 @@ VP_GFXMMU_VS_GFXMMU.Mode=GFXMMU_Activate VP_GFXMMU_VS_GFXMMU.Signal=GFXMMU_VS_GFXMMU VP_LTDC_DSIMode.Mode=RGB888 VP_LTDC_DSIMode.Signal=LTDC_DSIMode +VP_OCTOSPI1_VS_octo.Mode=octo_mode +VP_OCTOSPI1_VS_octo.Signal=OCTOSPI1_VS_octo VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick board=custom diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h index 9a78d0cd72b3..a80615c3dead 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h @@ -5,7 +5,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2019 STMicroelectronics

+ *

© COPYRIGHT(c) 2026 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -30,14 +30,14 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_CONF_H #define __STM32L4xx_HAL_CONF_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Exported types ------------------------------------------------------------*/ @@ -48,7 +48,7 @@ * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED /*#define HAL_ADC_MODULE_ENABLED */ /*#define HAL_CRYP_MODULE_ENABLED */ /*#define HAL_CAN_MODULE_ENABLED */ @@ -70,11 +70,12 @@ #define HAL_LTDC_MODULE_ENABLED /*#define HAL_LCD_MODULE_ENABLED */ /*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ /*#define HAL_NAND_MODULE_ENABLED */ /*#define HAL_NOR_MODULE_ENABLED */ /*#define HAL_OPAMP_MODULE_ENABLED */ /*#define HAL_OSPI_MODULE_ENABLED */ -/*#define HAL_OSPI_MODULE_ENABLED */ +#define HAL_OSPI_MODULE_ENABLED /*#define HAL_PCD_MODULE_ENABLED */ /*#define HAL_QSPI_MODULE_ENABLED */ /*#define HAL_QSPI_MODULE_ENABLED */ @@ -94,6 +95,7 @@ /*#define HAL_WWDG_MODULE_ENABLED */ /*#define HAL_EXTI_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED @@ -107,28 +109,28 @@ * This value is used by the RCC HAL module to compute the system frequency * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)16000000U) /*!< Value of the External oscillator in Hz */ +#if !defined(HSE_VALUE) +#define HSE_VALUE ((uint32_t)16000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#if !defined(HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** * @brief Internal Multiple Speed oscillator (MSI) default value. * This value is the default MSI range value after Reset. */ -#if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/ +#if !defined(MSI_VALUE) +#define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency * (when HSI is used as system clock source, directly or through the PLL). */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#if !defined(HSI_VALUE) +#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** @@ -138,16 +140,16 @@ * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency * which is subject to manufacturing process variations. */ -#if !defined (HSI48_VALUE) - #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. +#if !defined(HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. The real value my vary depending on manufacturing process variations.*/ #endif /* HSI48_VALUE */ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#if !defined(LSI_VALUE) +#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ @@ -156,12 +158,12 @@ * @brief External Low Speed oscillator (LSE) value. * This value is used by the UART, RTC HAL module to compute the system frequency */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ +#if !defined(LSE_VALUE) +#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ #endif /* LSE_VALUE */ -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#if !defined(LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -169,8 +171,8 @@ * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source * frequency. */ -#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) - #define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI1 External clock source in Hz*/ +#if !defined(EXTERNAL_SAI1_CLOCK_VALUE) +#define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI1 External clock source in Hz*/ #endif /* EXTERNAL_SAI1_CLOCK_VALUE */ /** @@ -178,8 +180,8 @@ * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source * frequency. */ -#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) - #define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI2 External clock source in Hz*/ +#if !defined(EXTERNAL_SAI2_CLOCK_VALUE) +#define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI2 External clock source in Hz*/ #endif /* EXTERNAL_SAI2_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -188,14 +190,14 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ - -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 0U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U + */ + +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U /* ########################## Assert Selection ############################## */ /** @@ -211,7 +213,7 @@ * Deactivated: CRC code cleaned from driver */ -#define USE_SPI_CRC 0U +#define USE_SPI_CRC 0U /* Includes ------------------------------------------------------------------*/ /** @@ -219,197 +221,201 @@ */ #ifdef HAL_RCC_MODULE_ENABLED - #include "stm32l4xx_hal_rcc.h" - #include "stm32l4xx_hal_rcc_ex.h" +#include "stm32l4xx_hal_rcc.h" +#include "stm32l4xx_hal_rcc_ex.h" #endif /* HAL_RCC_MODULE_ENABLED */ #ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32l4xx_hal_exti.h" +#include "stm32l4xx_hal_exti.h" #endif /* HAL_EXTI_MODULE_ENABLED */ #ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32l4xx_hal_gpio.h" +#include "stm32l4xx_hal_gpio.h" #endif /* HAL_GPIO_MODULE_ENABLED */ #ifdef HAL_DMA_MODULE_ENABLED - #include "stm32l4xx_hal_dma.h" - #include "stm32l4xx_hal_dma_ex.h" +#include "stm32l4xx_hal_dma.h" +#include "stm32l4xx_hal_dma_ex.h" #endif /* HAL_DMA_MODULE_ENABLED */ #ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32l4xx_hal_dfsdm.h" +#include "stm32l4xx_hal_dfsdm.h" #endif /* HAL_DFSDM_MODULE_ENABLED */ #ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32l4xx_hal_cortex.h" +#include "stm32l4xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ #ifdef HAL_ADC_MODULE_ENABLED - #include "stm32l4xx_hal_adc.h" +#include "stm32l4xx_hal_adc.h" #endif /* HAL_ADC_MODULE_ENABLED */ #ifdef HAL_CAN_MODULE_ENABLED - #include "stm32l4xx_hal_can.h" +#include "stm32l4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ #ifdef HAL_COMP_MODULE_ENABLED - #include "stm32l4xx_hal_comp.h" +#include "stm32l4xx_hal_comp.h" #endif /* HAL_COMP_MODULE_ENABLED */ #ifdef HAL_CRC_MODULE_ENABLED - #include "stm32l4xx_hal_crc.h" +#include "stm32l4xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32l4xx_hal_cryp.h" +#include "stm32l4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DAC_MODULE_ENABLED - #include "stm32l4xx_hal_dac.h" +#include "stm32l4xx_hal_dac.h" #endif /* HAL_DAC_MODULE_ENABLED */ #ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32l4xx_hal_dcmi.h" +#include "stm32l4xx_hal_dcmi.h" #endif /* HAL_DCMI_MODULE_ENABLED */ #ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32l4xx_hal_dma2d.h" +#include "stm32l4xx_hal_dma2d.h" #endif /* HAL_DMA2D_MODULE_ENABLED */ #ifdef HAL_DSI_MODULE_ENABLED - #include "stm32l4xx_hal_dsi.h" +#include "stm32l4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ #ifdef HAL_FIREWALL_MODULE_ENABLED - #include "stm32l4xx_hal_firewall.h" +#include "stm32l4xx_hal_firewall.h" #endif /* HAL_FIREWALL_MODULE_ENABLED */ #ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32l4xx_hal_flash.h" +#include "stm32l4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED - #include "stm32l4xx_hal_hash.h" +#include "stm32l4xx_hal_hash.h" #endif /* HAL_HASH_MODULE_ENABLED */ #ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32l4xx_hal_sram.h" +#include "stm32l4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ +#ifdef HAL_MMC_MODULE_ENABLED +#include "stm32l4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + #ifdef HAL_NOR_MODULE_ENABLED - #include "stm32l4xx_hal_nor.h" +#include "stm32l4xx_hal_nor.h" #endif /* HAL_NOR_MODULE_ENABLED */ #ifdef HAL_NAND_MODULE_ENABLED - #include "stm32l4xx_hal_nand.h" +#include "stm32l4xx_hal_nand.h" #endif /* HAL_NAND_MODULE_ENABLED */ #ifdef HAL_I2C_MODULE_ENABLED - #include "stm32l4xx_hal_i2c.h" +#include "stm32l4xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ #ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32l4xx_hal_iwdg.h" +#include "stm32l4xx_hal_iwdg.h" #endif /* HAL_IWDG_MODULE_ENABLED */ #ifdef HAL_LCD_MODULE_ENABLED - #include "stm32l4xx_hal_lcd.h" +#include "stm32l4xx_hal_lcd.h" #endif /* HAL_LCD_MODULE_ENABLED */ #ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32l4xx_hal_lptim.h" +#include "stm32l4xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ #ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32l4xx_hal_ltdc.h" +#include "stm32l4xx_hal_ltdc.h" #endif /* HAL_LTDC_MODULE_ENABLED */ #ifdef HAL_OPAMP_MODULE_ENABLED - #include "stm32l4xx_hal_opamp.h" +#include "stm32l4xx_hal_opamp.h" #endif /* HAL_OPAMP_MODULE_ENABLED */ #ifdef HAL_OSPI_MODULE_ENABLED - #include "stm32l4xx_hal_ospi.h" +#include "stm32l4xx_hal_ospi.h" #endif /* HAL_OSPI_MODULE_ENABLED */ #ifdef HAL_PWR_MODULE_ENABLED - #include "stm32l4xx_hal_pwr.h" +#include "stm32l4xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ #ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32l4xx_hal_qspi.h" +#include "stm32l4xx_hal_qspi.h" #endif /* HAL_QSPI_MODULE_ENABLED */ #ifdef HAL_RNG_MODULE_ENABLED - #include "stm32l4xx_hal_rng.h" +#include "stm32l4xx_hal_rng.h" #endif /* HAL_RNG_MODULE_ENABLED */ #ifdef HAL_RTC_MODULE_ENABLED - #include "stm32l4xx_hal_rtc.h" +#include "stm32l4xx_hal_rtc.h" #endif /* HAL_RTC_MODULE_ENABLED */ #ifdef HAL_SAI_MODULE_ENABLED - #include "stm32l4xx_hal_sai.h" +#include "stm32l4xx_hal_sai.h" #endif /* HAL_SAI_MODULE_ENABLED */ #ifdef HAL_SD_MODULE_ENABLED - #include "stm32l4xx_hal_sd.h" +#include "stm32l4xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ #ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32l4xx_hal_smbus.h" +#include "stm32l4xx_hal_smbus.h" #endif /* HAL_SMBUS_MODULE_ENABLED */ #ifdef HAL_SPI_MODULE_ENABLED - #include "stm32l4xx_hal_spi.h" +#include "stm32l4xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ #ifdef HAL_SWPMI_MODULE_ENABLED - #include "stm32l4xx_hal_swpmi.h" +#include "stm32l4xx_hal_swpmi.h" #endif /* HAL_SWPMI_MODULE_ENABLED */ #ifdef HAL_TIM_MODULE_ENABLED - #include "stm32l4xx_hal_tim.h" +#include "stm32l4xx_hal_tim.h" #endif /* HAL_TIM_MODULE_ENABLED */ #ifdef HAL_TSC_MODULE_ENABLED - #include "stm32l4xx_hal_tsc.h" +#include "stm32l4xx_hal_tsc.h" #endif /* HAL_TSC_MODULE_ENABLED */ #ifdef HAL_UART_MODULE_ENABLED - #include "stm32l4xx_hal_uart.h" +#include "stm32l4xx_hal_uart.h" #endif /* HAL_UART_MODULE_ENABLED */ #ifdef HAL_USART_MODULE_ENABLED - #include "stm32l4xx_hal_usart.h" +#include "stm32l4xx_hal_usart.h" #endif /* HAL_USART_MODULE_ENABLED */ #ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l4xx_hal_irda.h" +#include "stm32l4xx_hal_irda.h" #endif /* HAL_IRDA_MODULE_ENABLED */ #ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l4xx_hal_smartcard.h" +#include "stm32l4xx_hal_smartcard.h" #endif /* HAL_SMARTCARD_MODULE_ENABLED */ #ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32l4xx_hal_wwdg.h" +#include "stm32l4xx_hal_wwdg.h" #endif /* HAL_WWDG_MODULE_ENABLED */ #ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l4xx_hal_pcd.h" +#include "stm32l4xx_hal_pcd.h" #endif /* HAL_PCD_MODULE_ENABLED */ #ifdef HAL_HCD_MODULE_ENABLED - #include "stm32l4xx_hal_hcd.h" +#include "stm32l4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ #ifdef HAL_GFXMMU_MODULE_ENABLED - #include "stm32l4xx_hal_gfxmmu.h" +#include "stm32l4xx_hal_gfxmmu.h" #endif /* HAL_GFXMMU_MODULE_ENABLED */ /* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. * @param expr: If expr is false, it calls assert_failed function @@ -418,11 +424,11 @@ * If expr is true, it returns no value. * @retval None */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ - void assert_failed(char *file, uint32_t line); +void assert_failed(char *file, uint32_t line); #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ #ifdef __cplusplus diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index e8da0f73bc79..f57fb1909193 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -87,8 +87,8 @@ void HAL_MspInit(void) /* USER CODE END MspInit 0 */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); /* System interrupt init*/ @@ -103,21 +103,19 @@ void HAL_MspInit(void) * @param hdma2d: DMA2D handle pointer * @retval None */ -void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) +void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d) { - - if(hdma2d->Instance==DMA2D) - { + if (hdma2d->Instance == DMA2D) + { /* USER CODE BEGIN DMA2D_MspInit 0 */ /* USER CODE END DMA2D_MspInit 0 */ /* Peripheral clock enable */ - __HAL_RCC_DMA2D_CLK_ENABLE(); + __HAL_RCC_DMA2D_CLK_ENABLE(); /* USER CODE BEGIN DMA2D_MspInit 1 */ /* USER CODE END DMA2D_MspInit 1 */ - } - + } } /** @@ -126,22 +124,19 @@ void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) * @param hdma2d: DMA2D handle pointer * @retval None */ - -void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) +void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d) { - - if(hdma2d->Instance==DMA2D) - { + if (hdma2d->Instance == DMA2D) + { /* USER CODE BEGIN DMA2D_MspDeInit 0 */ /* USER CODE END DMA2D_MspDeInit 0 */ /* Peripheral clock disable */ - __HAL_RCC_DMA2D_CLK_DISABLE(); + __HAL_RCC_DMA2D_CLK_DISABLE(); /* USER CODE BEGIN DMA2D_MspDeInit 1 */ /* USER CODE END DMA2D_MspDeInit 1 */ - } - + } } /** @@ -150,21 +145,19 @@ void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) * @param hdsi: DSI handle pointer * @retval None */ -void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) +void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi) { - - if(hdsi->Instance==DSI) - { + if (hdsi->Instance == DSI) + { /* USER CODE BEGIN DSI_MspInit 0 */ /* USER CODE END DSI_MspInit 0 */ /* Peripheral clock enable */ - __HAL_RCC_DSI_CLK_ENABLE(); + __HAL_RCC_DSI_CLK_ENABLE(); /* USER CODE BEGIN DSI_MspInit 1 */ /* USER CODE END DSI_MspInit 1 */ - } - + } } /** @@ -173,22 +166,19 @@ void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) * @param hdsi: DSI handle pointer * @retval None */ - -void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) +void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi) { - - if(hdsi->Instance==DSI) - { + if (hdsi->Instance == DSI) + { /* USER CODE BEGIN DSI_MspDeInit 0 */ /* USER CODE END DSI_MspDeInit 0 */ /* Peripheral clock disable */ - __HAL_RCC_DSI_CLK_DISABLE(); + __HAL_RCC_DSI_CLK_DISABLE(); /* USER CODE BEGIN DSI_MspDeInit 1 */ /* USER CODE END DSI_MspDeInit 1 */ - } - + } } /** @@ -197,21 +187,19 @@ void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) * @param hgfxmmu: GFXMMU handle pointer * @retval None */ -void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef* hgfxmmu) +void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu) { - - if(hgfxmmu->Instance==GFXMMU) - { + if (hgfxmmu->Instance == GFXMMU) + { /* USER CODE BEGIN GFXMMU_MspInit 0 */ /* USER CODE END GFXMMU_MspInit 0 */ /* Peripheral clock enable */ - __HAL_RCC_GFXMMU_CLK_ENABLE(); + __HAL_RCC_GFXMMU_CLK_ENABLE(); /* USER CODE BEGIN GFXMMU_MspInit 1 */ /* USER CODE END GFXMMU_MspInit 1 */ - } - + } } /** @@ -220,22 +208,19 @@ void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef* hgfxmmu) * @param hgfxmmu: GFXMMU handle pointer * @retval None */ - -void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef* hgfxmmu) +void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu) { - - if(hgfxmmu->Instance==GFXMMU) - { + if (hgfxmmu->Instance == GFXMMU) + { /* USER CODE BEGIN GFXMMU_MspDeInit 0 */ /* USER CODE END GFXMMU_MspDeInit 0 */ /* Peripheral clock disable */ - __HAL_RCC_GFXMMU_CLK_DISABLE(); + __HAL_RCC_GFXMMU_CLK_DISABLE(); /* USER CODE BEGIN GFXMMU_MspDeInit 1 */ /* USER CODE END GFXMMU_MspDeInit 1 */ - } - + } } /** @@ -244,21 +229,19 @@ void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef* hgfxmmu) * @param hltdc: LTDC handle pointer * @retval None */ -void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) +void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc) { - - if(hltdc->Instance==LTDC) - { + if (hltdc->Instance == LTDC) + { /* USER CODE BEGIN LTDC_MspInit 0 */ /* USER CODE END LTDC_MspInit 0 */ /* Peripheral clock enable */ - __HAL_RCC_LTDC_CLK_ENABLE(); + __HAL_RCC_LTDC_CLK_ENABLE(); /* USER CODE BEGIN LTDC_MspInit 1 */ /* USER CODE END LTDC_MspInit 1 */ - } - + } } /** @@ -267,22 +250,148 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) * @param hltdc: LTDC handle pointer * @retval None */ - -void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) +void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc) { - - if(hltdc->Instance==LTDC) - { + if (hltdc->Instance == LTDC) + { /* USER CODE BEGIN LTDC_MspDeInit 0 */ /* USER CODE END LTDC_MspDeInit 0 */ /* Peripheral clock disable */ - __HAL_RCC_LTDC_CLK_DISABLE(); + __HAL_RCC_LTDC_CLK_DISABLE(); /* USER CODE BEGIN LTDC_MspDeInit 1 */ /* USER CODE END LTDC_MspDeInit 1 */ - } + } +} + +/** +* @brief OSPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hospi: OSPI handle pointer +* @retval None +*/ +void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi) +{ + GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + if (hospi->Instance == OCTOSPI1) + { + /* USER CODE BEGIN OCTOSPI1_MspInit 0 */ + + /* USER CODE END OCTOSPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_OSPI1_CLK_ENABLE(); + + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + HAL_PWREx_EnableVddIO2(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**OCTOSPI1 GPIO Configuration + PH2 ------> OCTOSPIM_P1_IO4 + PG11 ------> OCTOSPIM_P1_IO5 + PC3 ------> OCTOSPIM_P1_IO6 + PC4 ------> OCTOSPIM_P1_IO7 + PA6 ------> OCTOSPIM_P1_IO3 + PB1 ------> OCTOSPIM_P1_IO0 + PA3 ------> OCTOSPIM_P1_CLK + PA7 ------> OCTOSPIM_P1_IO2 + PA2 ------> OCTOSPIM_P1_NCS + PB0 ------> OCTOSPIM_P1_IO1 + PB2 ------> OCTOSPIM_P1_DQS + */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF3_OCTOSPIM_P1; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF3_OCTOSPIM_P1; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_3 | GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPIM_P1; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6 | GPIO_PIN_3 | GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPIM_P1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_1 | GPIO_PIN_0 | GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPIM_P1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPIM_P1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN OCTOSPI1_MspInit 1 */ + + /* USER CODE END OCTOSPI1_MspInit 1 */ + } +} + +/** +* @brief OSPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hospi: OSPI handle pointer +* @retval None +*/ +void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi) +{ + if (hospi->Instance == OCTOSPI1) + { + /* USER CODE BEGIN OCTOSPI1_MspDeInit 0 */ + + /* USER CODE END OCTOSPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_OSPI1_CLK_DISABLE(); + + /**OCTOSPI1 GPIO Configuration + PH2 ------> OCTOSPIM_P1_IO4 + PG11 ------> OCTOSPIM_P1_IO5 + PC3 ------> OCTOSPIM_P1_IO6 + PC4 ------> OCTOSPIM_P1_IO7 + PA6 ------> OCTOSPIM_P1_IO3 + PB1 ------> OCTOSPIM_P1_IO0 + PA3 ------> OCTOSPIM_P1_CLK + PA7 ------> OCTOSPIM_P1_IO2 + PA2 ------> OCTOSPIM_P1_NCS + PB0 ------> OCTOSPIM_P1_IO1 + PB2 ------> OCTOSPIM_P1_DQS + */ + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_2); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11); + + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_3 | GPIO_PIN_4); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_6 | GPIO_PIN_3 | GPIO_PIN_7 | GPIO_PIN_2); + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1 | GPIO_PIN_0 | GPIO_PIN_2); + + /* USER CODE BEGIN OCTOSPI1_MspDeInit 1 */ + + /* USER CODE END OCTOSPI1_MspDeInit 1 */ + } } /** @@ -291,35 +400,33 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) * @param huart: UART handle pointer * @retval None */ -void HAL_UART_MspInit(UART_HandleTypeDef* huart) +void HAL_UART_MspInit(UART_HandleTypeDef *huart) { - - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(huart->Instance==USART3) - { + GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + if (huart->Instance == USART3) + { /* USER CODE BEGIN USART3_MspInit 0 */ /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ - __HAL_RCC_USART3_CLK_ENABLE(); + __HAL_RCC_USART3_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**USART3 GPIO Configuration PB11 ------> USART3_RX - PB10 ------> USART3_TX + PB10 ------> USART3_TX */ - GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_10; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF7_USART3; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ - } - + } } /** @@ -328,46 +435,45 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) * @param huart: UART handle pointer * @retval None */ - -void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) { - - if(huart->Instance==USART3) - { + if (huart->Instance == USART3) + { /* USER CODE BEGIN USART3_MspDeInit 0 */ /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ - __HAL_RCC_USART3_CLK_DISABLE(); + __HAL_RCC_USART3_CLK_DISABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PB11 ------> USART3_RX - PB10 ------> USART3_TX + PB10 ------> USART3_TX */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_11|GPIO_PIN_10); + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_11 | GPIO_PIN_10); /* USER CODE BEGIN USART3_MspDeInit 1 */ /* USER CODE END USART3_MspDeInit 1 */ - } - + } } static uint32_t FMC_Initialized = 0; -static void HAL_FMC_MspInit(void){ +static void HAL_FMC_MspInit(void) +{ /* USER CODE BEGIN FMC_MspInit 0 */ /* USER CODE END FMC_MspInit 0 */ - GPIO_InitTypeDef GPIO_InitStruct; - if (FMC_Initialized) { - return; - } - FMC_Initialized = 1; + GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + if (FMC_Initialized) + { + return; + } + FMC_Initialized = 1; /* Peripheral clock enable */ - __HAL_RCC_FMC_CLK_ENABLE(); + __HAL_RCC_FMC_CLK_ENABLE(); - /** FMC GPIO Configuration + /** FMC GPIO Configuration PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 PD0 ------> FMC_D2 @@ -412,53 +518,45 @@ static void HAL_FMC_MspInit(void){ PF12 ------> FMC_A6 PE11 ------> FMC_D8 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_3 - |GPIO_PIN_5|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_15 - |GPIO_PIN_8|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_13 - |GPIO_PIN_12|GPIO_PIN_11; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF12_FMC; - HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_4|GPIO_PIN_1|GPIO_PIN_5 - |GPIO_PIN_7|GPIO_PIN_13|GPIO_PIN_15|GPIO_PIN_14 - |GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 - |GPIO_PIN_8; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF12_FMC; - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_15|GPIO_PIN_14 - |GPIO_PIN_13|GPIO_PIN_12; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF12_FMC; - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_1 - |GPIO_PIN_2|GPIO_PIN_0; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF12_FMC; - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_5 | GPIO_PIN_10 | GPIO_PIN_9 | GPIO_PIN_15 | GPIO_PIN_8 | GPIO_PIN_14 | GPIO_PIN_7 | GPIO_PIN_13 | GPIO_PIN_12 | GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_4 | GPIO_PIN_1 | GPIO_PIN_5 | GPIO_PIN_7 | GPIO_PIN_13 | GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_12 | GPIO_PIN_11 | GPIO_PIN_10 | GPIO_PIN_9 | GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_1 | GPIO_PIN_0 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13 | GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_5 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); /* USER CODE BEGIN FMC_MspInit 1 */ /* USER CODE END FMC_MspInit 1 */ } -void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){ +void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) +{ /* USER CODE BEGIN SRAM_MspInit 0 */ /* USER CODE END SRAM_MspInit 0 */ - HAL_FMC_MspInit(); + HAL_FMC_MspInit(); /* USER CODE BEGIN SRAM_MspInit 1 */ /* USER CODE END SRAM_MspInit 1 */ @@ -466,18 +564,20 @@ void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){ static uint32_t FMC_DeInitialized = 0; -static void HAL_FMC_MspDeInit(void){ +static void HAL_FMC_MspDeInit(void) +{ /* USER CODE BEGIN FMC_MspDeInit 0 */ /* USER CODE END FMC_MspDeInit 0 */ - if (FMC_DeInitialized) { - return; - } - FMC_DeInitialized = 1; + if (FMC_DeInitialized) + { + return; + } + FMC_DeInitialized = 1; /* Peripheral clock enable */ - __HAL_RCC_FMC_CLK_DISABLE(); + __HAL_RCC_FMC_CLK_DISABLE(); - /** FMC GPIO Configuration + /** FMC GPIO Configuration PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 PD0 ------> FMC_D2 @@ -522,33 +622,25 @@ static void HAL_FMC_MspDeInit(void){ PF12 ------> FMC_A6 PE11 ------> FMC_D8 */ - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_3 - |GPIO_PIN_5|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_15 - |GPIO_PIN_8|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_13 - |GPIO_PIN_12|GPIO_PIN_11); + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_5 | GPIO_PIN_10 | GPIO_PIN_9 | GPIO_PIN_15 | GPIO_PIN_8 | GPIO_PIN_14 | GPIO_PIN_7 | GPIO_PIN_13 | GPIO_PIN_12 | GPIO_PIN_11); - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_4|GPIO_PIN_1|GPIO_PIN_5 - |GPIO_PIN_7|GPIO_PIN_13|GPIO_PIN_15|GPIO_PIN_14 - |GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 - |GPIO_PIN_8); + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0 | GPIO_PIN_4 | GPIO_PIN_1 | GPIO_PIN_5 | GPIO_PIN_7 | GPIO_PIN_13 | GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_12 | GPIO_PIN_11 | GPIO_PIN_10 | GPIO_PIN_9 | GPIO_PIN_8); - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_15|GPIO_PIN_14 - |GPIO_PIN_13|GPIO_PIN_12); + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_2 | GPIO_PIN_1 | GPIO_PIN_0 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13 | GPIO_PIN_12); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_1 - |GPIO_PIN_2|GPIO_PIN_0); + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_5 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_0); /* USER CODE BEGIN FMC_MspDeInit 1 */ /* USER CODE END FMC_MspDeInit 1 */ } -void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef* hsram){ +void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) +{ /* USER CODE BEGIN SRAM_MspDeInit 0 */ /* USER CODE END SRAM_MspDeInit 0 */ - HAL_FMC_MspDeInit(); + HAL_FMC_MspDeInit(); /* USER CODE BEGIN SRAM_MspDeInit 1 */ /* USER CODE END SRAM_MspDeInit 1 */ diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_it.c b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_it.c index d8515c43de70..181114145d58 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_it.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_it.c @@ -47,7 +47,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN PD */ - + /* USER CODE END PD */ /* Private macro -------------------------------------------------------------*/ @@ -71,12 +71,13 @@ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ + /* USER CODE BEGIN EV */ /* USER CODE END EV */ /******************************************************************************/ -/* Cortex-M4 Processor Interruption and Exception Handlers */ +/* Cortex-M4 Processor Interruption and Exception Handlers */ /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. @@ -99,11 +100,11 @@ void HardFault_Handler(void) /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ - while (1) - { + while (1) + { /* USER CODE BEGIN W1_HardFault_IRQn 0 */ /* USER CODE END W1_HardFault_IRQn 0 */ - } + } } /** @@ -114,11 +115,11 @@ void MemManage_Handler(void) /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) - { + while (1) + { /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ /* USER CODE END W1_MemoryManagement_IRQn 0 */ - } + } } /** @@ -129,11 +130,11 @@ void BusFault_Handler(void) /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ - while (1) - { + while (1) + { /* USER CODE BEGIN W1_BusFault_IRQn 0 */ /* USER CODE END W1_BusFault_IRQn 0 */ - } + } } /** @@ -144,11 +145,11 @@ void UsageFault_Handler(void) /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ - while (1) - { + while (1) + { /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ /* USER CODE END W1_UsageFault_IRQn 0 */ - } + } } /** @@ -198,7 +199,7 @@ void SysTick_Handler(void) /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); + HAL_IncTick(); /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ diff --git a/bsp/stm32/stm32l4r9-st-eval/board/Kconfig b/bsp/stm32/stm32l4r9-st-eval/board/Kconfig index e29ec26b817c..adc0cc3b8b9a 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/Kconfig +++ b/bsp/stm32/stm32l4r9-st-eval/board/Kconfig @@ -14,6 +14,13 @@ menu "Onboard Peripheral Drivers" select BSP_USING_GFXMMU default n + config BSP_USING_OSPI_FLASH + bool "Enable OctoSPI Flash (MX25LM51245GXDI00)" + select BSP_USING_OSPI + select RT_USING_SFUD + select RT_SFUD_USING_OSPI + default n + menu "Enable Touch" config BSP_USING_TOUCH @@ -102,6 +109,12 @@ menu "On-chip Peripheral Drivers" endif endif + config BSP_USING_OSPI + bool "Enable OSPI BUS" + select RT_USING_OSPI + select RT_USING_SPI + default n + config BSP_USING_SRAM bool "Enable SRAM" select BSP_USING_FMC diff --git a/bsp/stm32/stm32l4r9-st-eval/board/SConscript b/bsp/stm32/stm32l4r9-st-eval/board/SConscript index d67ba57356aa..bfb21f8784b4 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/SConscript +++ b/bsp/stm32/stm32l4r9-st-eval/board/SConscript @@ -18,6 +18,9 @@ if GetDepend(['BSP_USING_TOUCH']): src += Glob('ports/drv_touch.c') src += Glob('ports/drv_touch_ft.c') +if GetDepend(['BSP_USING_OSPI_FLASH']): + src += Glob('ports/drv_ospi_flash.c') + path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] path += [cwd + '/ports/include'] diff --git a/bsp/stm32/stm32l4r9-st-eval/board/board.c b/bsp/stm32/stm32l4r9-st-eval/board/board.c index 179ccf08ae3d..da14afb4f49e 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/board.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/board.c @@ -13,18 +13,18 @@ void SystemClock_Config(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; + RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; + RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 }; - /**Configure the main internal regulator output voltage - */ + /** Configure the main internal regulator output voltage + */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks - */ + /** Initializes the CPU, AHB and APB busses clocks + */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; @@ -38,9 +38,9 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; @@ -50,9 +50,10 @@ void SystemClock_Config(void) { Error_Handler(); } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_DSI|RCC_PERIPHCLK_LTDC; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_LTDC; PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; PeriphClkInit.DsiClockSelection = RCC_DSICLKSOURCE_DSIPHY; + PeriphClkInit.OspiClockSelection = RCC_OSPICLKSOURCE_SYSCLK; PeriphClkInit.LtdcClockSelection = RCC_LTDCCLKSOURCE_PLLSAI2_DIV2; PeriphClkInit.PLLSAI2.PLLSAI2Source = RCC_PLLSOURCE_HSE; PeriphClkInit.PLLSAI2.PLLSAI2M = 2; diff --git a/bsp/stm32/stm32l4r9-st-eval/board/board.h b/bsp/stm32/stm32l4r9-st-eval/board/board.h index 4552dd794c38..cd831e8c0611 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/board.h +++ b/bsp/stm32/stm32l4r9-st-eval/board/board.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-11-5 SummerGift first version * 2019-04-09 jhb + * 2026-09-03 CliffLL modify HEAP_BEGIN for GCC */ #ifndef __BOARD_H__ @@ -18,16 +19,32 @@ extern "C" { #endif -#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) -#define STM32_FLASH_SIZE (2048 * 1024) -#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) - -#define STM32_SRAM3_SIZE (384) -#define STM32_SRAM3_START (0x20040000) -#define STM32_SRAM3_END (STM32_SRAM3_START + STM32_SRAM3_SIZE * 1024) - -#define HEAP_BEGIN STM32_SRAM3_START -#define HEAP_END STM32_SRAM3_END +#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define STM32_FLASH_SIZE (2048 * 1024) +#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) + +#define STM32_SRAM3_SIZE (384) +#define STM32_SRAM3_START (0x20040000) +#define STM32_SRAM3_END (STM32_SRAM3_START + STM32_SRAM3_SIZE * 1024) + +#define STM32_SRAM1_SIZE (192) +#define STM32_SRAM1_START (0x20000000U) +#define STM32_SRAM1_END (STM32_SRAM1_START + STM32_SRAM1_SIZE * 1024U) + +#if defined(__ARMCC_VERSION) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#define HEAP_END ((void *)STM32_SRAM1_END) +#elif __ICCARM__ +#pragma section = "HEAP" +#pragma section = "CSTACK" +#define HEAP_BEGIN (__segment_begin("HEAP")) +#define HEAP_END (__segment_begin("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#define HEAP_END STM32_SRAM3_END +#endif void SystemClock_Config(void); diff --git a/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.icf b/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.icf index f94036f50406..a18dfc5fb3aa 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.icf @@ -22,6 +22,7 @@ define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __I define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; initialize by copy { readwrite }; do not initialize { section .noinit }; @@ -30,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM1_region { section .sram }; -place in RAM2_region { readwrite, last block CSTACK}; +place in RAM2_region { readwrite, block HEAP, last block CSTACK}; diff --git a/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct b/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct index 75aad352202c..fabfaff8bfb4 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct @@ -9,7 +9,7 @@ LR_IROM1 0x08000000 0x00200000 { ; load region size_region .ANY (+RO) } - RW_IRAM1 0x20000000 0x00040000 { ; RW data + RW_IRAM1 0x20000000 0x00030000 { ; RW data .ANY (+RW +ZI) } diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_ospi_flash.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_ospi_flash.c new file mode 100644 index 000000000000..90055828a9c7 --- /dev/null +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_ospi_flash.c @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-08-20 CliffLL first version + */ + +#include +#include +#include +#include +#include + +#ifdef BSP_USING_OSPI_FLASH + +#include "dev_spi_flash.h" +#include "dev_spi_flash_sfud.h" + +static rt_err_t mx25lm51245g_read_configuration_register2_reg1(struct rt_ospi_device *device, rt_uint8_t *reg) +{ + rt_ssize_t ret; + + /* 0x718E read configuration register2 reg1 (address 00000000h) */ + rt_uint8_t instruction = 0x71; + struct rt_ospi_message message = { 0 }; + rt_uint16_t ospi_instruction = 0x718E; + uint8_t cr2_reg1[2] = { 0 }; + rt_uint8_t send_buf[5] = { 0 }; + send_buf[0] = instruction; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(reg != RT_NULL); + + if (device->ospi_mode != RT_OSPI_MODE_OFF) + { + /* set message struct */ + message.instruction.content = ospi_instruction; + message.instruction.size = 16; + message.instruction.ospi_lines = 8; + message.instruction.dtrmode = (device->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + + message.address.content = 0; + message.address.size = 32; + message.address.ospi_lines = 8; + message.address.dtrmode = (device->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + + message.alternate_bytes.content = 0; + message.alternate_bytes.size = 0; + message.alternate_bytes.ospi_lines = 0; + message.alternate_bytes.dtrmode = 0; + + message.dummy_cycles = 6; + + message.parent.send_buf = RT_NULL; + message.parent.recv_buf = cr2_reg1; + message.parent.length = (device->ospi_mode == RT_OSPI_MODE_DTR) ? 2 : 1; + message.parent.cs_release = 1; + message.parent.cs_take = 1; + message.ospi_data_lines = 8; + message.ospi_data_dtrmode = (device->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + message.dqs_mode = (device->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + message.parent.next = RT_NULL; + + ret = rt_ospi_transfer_message(device, &message); + if (ret != (rt_ssize_t)message.parent.length) + { + return -RT_EIO; + } + + /* MX25LM51245G returns duplicated register data in OPI-DTR mode */ + if ((device->ospi_mode == RT_OSPI_MODE_DTR) && (cr2_reg1[0] != cr2_reg1[1])) + { + return -RT_EIO; + } + } + else + { + ret = rt_ospi_send_then_recv(device, send_buf, 5, cr2_reg1, 1); + if (ret != 1) + { + return -RT_EIO; + } + } + *reg = cr2_reg1[0]; + + return RT_EOK; +} + +static rt_err_t mx25lm51245g_write_enable(struct rt_ospi_device *device) +{ + rt_ssize_t ret; + struct rt_ospi_message message = { 0 }; + + /* 0x06F9 write enable */ + rt_uint8_t instruction = 0x06; + rt_uint16_t ospi_instruction = 0x06F9; + + if (device->ospi_mode != RT_OSPI_MODE_OFF) + { + /* set message struct */ + message.instruction.content = ospi_instruction; + message.instruction.size = 16; + message.instruction.ospi_lines = 8; + message.instruction.dtrmode = (device->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + + message.address.content = 0; + message.address.size = 0; + message.address.ospi_lines = 0; + message.address.dtrmode = (device->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + + message.alternate_bytes.content = 0; + message.alternate_bytes.size = 0; + message.alternate_bytes.ospi_lines = 0; + message.alternate_bytes.dtrmode = 0; + + message.dummy_cycles = 0; + + message.parent.send_buf = RT_NULL; + message.parent.recv_buf = RT_NULL; + message.parent.length = 0; + message.parent.cs_release = 1; + message.parent.cs_take = 1; + message.ospi_data_lines = 0; + message.ospi_data_dtrmode = (device->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + message.dqs_mode = 0; + message.parent.next = RT_NULL; + + ret = rt_ospi_transfer_message(device, &message); + } + else + { + ret = rt_ospi_send(device, &instruction, 1); + } + + if (ret <= 0) + { + return -RT_EIO; + } + + return RT_EOK; +} + +static rt_err_t mx25lm51245g_enter_ospi_str_mode(struct rt_ospi_device *device) +{ + rt_uint8_t reg; + rt_err_t result; + rt_ssize_t ret; + struct rt_ospi_message message = { 0 }; + + /* 0x728D write configuration register2 */ + rt_uint8_t instruction = 0x72; + rt_uint16_t ospi_instruction = 0x728D; + + /* write SOPI mode dummy cycles (0x07 set DC 6 cycles) */ + char write_cr2_reg3_buf[6] = { 0 }; + char dtr_cr2_reg3_buf[2] = { 0 }; + write_cr2_reg3_buf[0] = instruction; + write_cr2_reg3_buf[3] = 0x03; + write_cr2_reg3_buf[5] = 0x07; + dtr_cr2_reg3_buf[0] = 0x07; + dtr_cr2_reg3_buf[1] = 0x07; + + /* write configuration register2 reg1 enter ospi-str mode*/ + char write_cr2_reg1_buf[6] = { 0 }; + char dtr_cr2_reg1_buf[2] = { 0 }; + write_cr2_reg1_buf[0] = instruction; + write_cr2_reg1_buf[5] = 0x01; + dtr_cr2_reg1_buf[0] = 0x01; + dtr_cr2_reg1_buf[1] = 0x01; + + result = mx25lm51245g_read_configuration_register2_reg1(device, ®); + if (result != RT_EOK) + { + return result; + } + + if (reg == 0x02) + { + /* ospi-dtr to ospi-str */ + result = mx25lm51245g_write_enable(device); + if (result != RT_EOK) + { + return result; + } + + /* set message struct */ + message.instruction.content = ospi_instruction; + message.instruction.size = 16; + message.instruction.ospi_lines = 8; + message.instruction.dtrmode = 1; + + message.address.content = 0x00000300; + message.address.size = 32; + message.address.ospi_lines = 8; + message.address.dtrmode = 1; + + message.alternate_bytes.content = 0; + message.alternate_bytes.size = 0; + message.alternate_bytes.ospi_lines = 0; + message.alternate_bytes.dtrmode = 0; + + message.dummy_cycles = 0; + + message.parent.send_buf = dtr_cr2_reg3_buf; + message.parent.recv_buf = RT_NULL; + message.parent.length = 2; + message.parent.cs_release = 1; + message.parent.cs_take = 1; + message.ospi_data_lines = 8; + message.ospi_data_dtrmode = 1; + message.dqs_mode = 0; + message.parent.next = RT_NULL; + + ret = rt_ospi_transfer_message(device, &message); + if (ret != message.parent.length) + { + return -RT_EIO; + } + + result = mx25lm51245g_write_enable(device); + if (result != RT_EOK) + { + return result; + } + + message.address.content = 0x00000000; + message.parent.send_buf = dtr_cr2_reg1_buf; + ret = rt_ospi_transfer_message(device, &message); + if (ret != message.parent.length) + { + return -RT_EIO; + } + + rt_thread_mdelay(10); + } + else if (reg == 0x00) + { + /* spi to ospi-str */ + result = mx25lm51245g_write_enable(device); + if (result != RT_EOK) + { + return result; + } + + ret = rt_ospi_send(device, write_cr2_reg3_buf, 6); + if (ret != 6) + { + return -RT_EIO; + } + + result = mx25lm51245g_write_enable(device); + if (result != RT_EOK) + { + return result; + } + + ret = rt_ospi_send(device, write_cr2_reg1_buf, 6); + if (ret != 6) + { + return -RT_EIO; + } + + rt_thread_mdelay(10); + } + + + device->config.dtr_mode = 0; + result = rt_ospi_configure(device, &device->config); + if (result != RT_EOK) + { + return result; + } + device->ospi_mode = RT_OSPI_MODE_STR; + + /* check if flash enter OPI-STR mode */ + result = mx25lm51245g_read_configuration_register2_reg1(device, ®); + if (result != RT_EOK) + { + return result; + } + if (reg != 0x01) + { + return -RT_EIO; + } + + rt_kprintf("flash already enter ospi str mode\n"); + return RT_EOK; +} + +static rt_err_t mx25lm51245g_enter_ospi_dtr_mode(struct rt_ospi_device *device) +{ + rt_uint8_t reg; + rt_err_t result; + rt_ssize_t ret; + struct rt_ospi_message message = { 0 }; + /* 0x728D write configuration register2 */ + rt_uint8_t instruction = 0x72; + rt_uint16_t ospi_instruction = 0x728D; + + /* write SOPI mode dummy cycles (0x07 set DC 6 cycles) */ + char write_cr2_reg3_buf[6] = { 0 }; + write_cr2_reg3_buf[0] = instruction; + write_cr2_reg3_buf[3] = 0x03; + write_cr2_reg3_buf[5] = 0x07; + + /* write configuration register2 reg1 enter ospi-str mode*/ + char write_cr2_reg1_buf[6] = { 0 }; + write_cr2_reg1_buf[0] = instruction; + write_cr2_reg1_buf[5] = 0x02; + + result = mx25lm51245g_read_configuration_register2_reg1(device, ®); + if (result != RT_EOK) + { + return result; + } + + if (reg == 0x01) + { + /* ospi-str to ospi-dtr */ + result = mx25lm51245g_write_enable(device); + if (result != RT_EOK) + { + return result; + } + + /* set message struct */ + message.instruction.content = ospi_instruction; + message.instruction.size = 16; + message.instruction.ospi_lines = 8; + message.instruction.dtrmode = 0; + + message.address.content = 0x00000300; + message.address.size = 32; + message.address.ospi_lines = 8; + message.address.dtrmode = 0; + + message.alternate_bytes.content = 0; + message.alternate_bytes.size = 0; + message.alternate_bytes.ospi_lines = 0; + message.alternate_bytes.dtrmode = 0; + + message.dummy_cycles = 0; + + message.parent.send_buf = write_cr2_reg3_buf + 5; + message.parent.recv_buf = RT_NULL; + message.parent.length = 1; + message.parent.cs_release = 1; + message.parent.cs_take = 1; + message.ospi_data_lines = 8; + message.ospi_data_dtrmode = 0; + message.dqs_mode = 0; + message.parent.next = RT_NULL; + + ret = rt_ospi_transfer_message(device, &message); + if (ret != message.parent.length) + { + return -RT_EIO; + } + + result = mx25lm51245g_write_enable(device); + if (result != RT_EOK) + { + return result; + } + + message.address.content = 0x00000000; + message.parent.send_buf = write_cr2_reg1_buf + 5; + ret = rt_ospi_transfer_message(device, &message); + if (ret != message.parent.length) + { + return -RT_EIO; + } + + rt_thread_mdelay(10); + } + else if (reg == 0x00) + { + /* spi to ospi-dtr */ + result = mx25lm51245g_write_enable(device); + if (result != RT_EOK) + { + return result; + } + + ret = rt_ospi_send(device, write_cr2_reg3_buf, 6); + if (ret != 6) + { + return -RT_EIO; + } + + result = mx25lm51245g_write_enable(device); + if (result != RT_EOK) + { + return result; + } + + ret = rt_ospi_send(device, write_cr2_reg1_buf, 6); + if (ret != 6) + { + return -RT_EIO; + } + + rt_thread_mdelay(10); + } + + + device->config.dtr_mode = 1; + result = rt_ospi_configure(device, &device->config); + if (result != RT_EOK) + { + return result; + } + device->ospi_mode = RT_OSPI_MODE_DTR; + + /* check if flash enter OPI-DTR mode */ + result = mx25lm51245g_read_configuration_register2_reg1(device, ®); + if (result != RT_EOK) + { + return result; + } + if (reg != 0x02) + { + return -RT_EIO; + } + + rt_kprintf("flash already enter ospi dtr mode\n"); + return RT_EOK; +} + +static int rt_hw_ospi_flash_with_sfud_init(void) +{ + return rt_hw_ospi_device_attach("ospi1", "ospi10", mx25lm51245g_enter_ospi_str_mode, mx25lm51245g_enter_ospi_dtr_mode, RT_NULL); +} +INIT_DEVICE_EXPORT(rt_hw_ospi_flash_with_sfud_init); + +#endif/* BSP_USING_OSPI_FLASH */ diff --git a/bsp/stm32/stm32l4r9-st-eval/project.ewp b/bsp/stm32/stm32l4r9-st-eval/project.ewp index be1b40f1ded4..1ea534a78e8b 100644 --- a/bsp/stm32/stm32l4r9-st-eval/project.ewp +++ b/bsp/stm32/stm32l4r9-st-eval/project.ewp @@ -224,13 +224,13 @@ @@ -358,29 +358,33 @@ @@ -1425,29 +1429,33 @@