From 225441065967f1ff4f51eed48287e34d46d11792 Mon Sep 17 00:00:00 2001 From: clifflin Date: Mon, 28 Sep 2026 14:02:12 +0800 Subject: [PATCH 1/4] [drivers][ospi] Add OctaFlash support Purpose: 1. Introduce a native OSPI path into RT-Thread SPI driver layer, enabling OSPI alongside existing SPI/QSPI. 2. Make SFUD work over OSPI (read/write/erase/WREN/WRSR/RDSR) while keeping SPI/QSPI behavior unchanged. 3. Keep existing SPI/QSPI behavior unchanged. Description: 1. components/drivers/spi/Kconfig: Add OSPI build options. 2. components/drivers/spi/SConscript: Include "dev_ospi_core.c". 3. components/drivers/spi/dev_ospi_core.c: Implement OSPI core transfer helpers. 4. components/drivers/spi/dev_spi_flash_sfud.c/.h: Add OSPI 1-1-1/8-8-8 paths for transferring messages and probing OSPI device. 5. components/drivers/spi/sfud/inc/sfud_cfg.h, sfud_def.h: Add OSPI enable macros and related definitions. 6. components/drivers/spi/sfud/inc/sfud_flash_def.h: Add MX25LM51245G (OctaFlash, 512Mbit) to device table for testing/verification. 7. components/drivers/spi/sfud/src/sfud.c: Integrate the OSPI path into SFUD for read, write, erase, WREN, WRSR, and RDSR operations while retaining the existing SPI/QSPI paths. 8. components/drivers/include/drivers/dev_spi.h: Add OSPI bus/config/message/device structs. Tested in stm32l4r9-st-eval BSP project: Using "sf probe/read/write/erase/status/bench" to test 1-1-1 and 8-8-8 (OPI STR/DTR) data paths. Signed-off-by: CliffLL --- components/drivers/include/drivers/dev_spi.h | 136 +++++++- components/drivers/spi/Kconfig | 9 + components/drivers/spi/SConscript | 3 + components/drivers/spi/dev_ospi_core.c | 320 ++++++++++++++++++ components/drivers/spi/dev_spi_flash_sfud.c | 216 +++++++++++- components/drivers/spi/dev_spi_flash_sfud.h | 17 +- components/drivers/spi/sfud/inc/sfud_cfg.h | 7 + components/drivers/spi/sfud/inc/sfud_def.h | 59 ++++ .../drivers/spi/sfud/inc/sfud_flash_def.h | 1 + components/drivers/spi/sfud/src/sfud.c | 263 +++++++++++++- 10 files changed, 1004 insertions(+), 27 deletions(-) create mode 100644 components/drivers/spi/dev_ospi_core.c diff --git a/components/drivers/include/drivers/dev_spi.h b/components/drivers/include/drivers/dev_spi.h index d7acf1810c71..9ff8693b4c1c 100644 --- a/components/drivers/include/drivers/dev_spi.h +++ b/components/drivers/include/drivers/dev_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2025 RT-Thread Development Team + * Copyright (c) 2006-2026 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,6 +9,7 @@ * 2020-06-13 armink fix the 3 wires issue * 2022-09-01 liYony fix api rt_spi_sendrecv16 about MSB and LSB bug * 2025-10-30 wdfk-prog enable interrupt-safe operations using spinlocks + * 2026-08-14 CliffLL add OSPI device's config */ #ifndef __DEV_SPI_H__ @@ -129,6 +130,7 @@ extern "C"{ #define RT_SPI_BUS_MODE_SPI (1<<0) #define RT_SPI_BUS_MODE_QSPI (1<<1) +#define RT_SPI_BUS_MODE_OSPI (1<<2) #define RT_SPI_CS_CNT_MAX 16 @@ -294,6 +296,83 @@ struct rt_qspi_device void (*exit_qspi_mode)(struct rt_qspi_device *device); }; +/** + * @brief OSPI message structure + */ +struct rt_ospi_message +{ + struct rt_spi_message parent; + + /* instruction stage */ + struct + { + rt_uint16_t content; + rt_uint8_t size; + rt_uint8_t ospi_lines; + rt_uint8_t dtrmode; + } instruction; + + /* address and alternate_bytes stage */ + struct + { + rt_uint32_t content; + rt_uint8_t size; + rt_uint8_t ospi_lines; + rt_uint8_t dtrmode; + } address, alternate_bytes; + + /* dummy_cycles stage */ + rt_uint32_t dummy_cycles; + + rt_uint8_t ospi_data_dtrmode; + /* dqs required in OPI-DTR mode */ + rt_uint8_t dqs_mode; + + /* number of lines in ospi data stage, the other configuration items are in parent */ + rt_uint8_t ospi_data_lines; +}; + +/** + * @brief OSPI configuration structure + */ +struct rt_ospi_configuration +{ + struct rt_spi_configuration parent; + /* The size of medium */ + rt_uint32_t medium_size; + /* double data transfer rate mode */ + rt_uint8_t dtr_mode; +}; + +/** + * @brief OSPI mode + */ +typedef enum +{ + RT_OSPI_MODE_OFF = 0, + RT_OSPI_MODE_STR = 1, + RT_OSPI_MODE_DTR = 2, +} rt_ospi_mode_t; + +/** + * @brief OSPI operators + */ +struct rt_ospi_device +{ + struct rt_spi_device parent; + + struct rt_ospi_configuration config; + + /* OSPI mode */ + rt_ospi_mode_t ospi_mode; + + rt_err_t (*enter_ospi_str_mode)(struct rt_ospi_device *device); + + rt_err_t (*enter_ospi_dtr_mode)(struct rt_ospi_device *device); + + rt_err_t (*exit_ospi_mode)(struct rt_ospi_device *device); +}; + #define SPI_DEVICE(dev) ((struct rt_spi_device *)(dev)) #ifdef RT_USING_DM @@ -663,6 +742,61 @@ rt_ssize_t rt_qspi_send_then_recv(struct rt_qspi_device *device, const void *sen */ rt_ssize_t rt_qspi_send(struct rt_qspi_device *device, const void *send_buf, rt_size_t length); +/** + * @brief This function can set configuration on OSPI device. + * + * @param device the OSPI device attached to OSPI bus. + * @param cfg the configuration pointer. + * + * @return the actual length of transmitted. + */ +rt_err_t rt_ospi_configure(struct rt_ospi_device *device, struct rt_ospi_configuration *cfg); + +/** + * @brief This function can register a SPI bus for OSPI mode. + * + * @param bus the SPI bus for OSPI mode. + * @param name The name of the spi bus. + * @param ops the SPI bus instance to be registered. + * + * @return the actual length of transmitted. + */ +rt_err_t rt_ospi_bus_register(struct rt_spi_bus *bus, const char *name, const struct rt_spi_ops *ops); + +/** + * @brief This function transmits data to OSPI device. + * + * @param device the OSPI device attached to OSPI bus. + * @param message the message pointer. + * + * @return the actual length of transmitted. + */ +rt_ssize_t rt_ospi_transfer_message(struct rt_ospi_device *device, struct rt_ospi_message *message); + +/** + * @brief This function can send data then receive data from OSPI device + * + * @param device the OSPI device attached to OSPI bus. + * @param send_buf the buffer to be transmitted to OSPI device. + * @param send_length the number of data to be transmitted. + * @param recv_buf the buffer to be recivied from OSPI device. + * @param recv_length the data to be recivied. + * + * @return the status of transmit. + */ +rt_ssize_t rt_ospi_send_then_recv(struct rt_ospi_device *device, const void *send_buf, rt_size_t send_length, void *recv_buf, rt_size_t recv_length); + +/** + * @brief This function can send data to OSPI device + * + * @param device the OSPI device attached to OSPI bus. + * @param send_buf the buffer to be transmitted to OSPI device. + * @param length the number of data to be transmitted. + * + * @return the status of transmit. + */ +rt_ssize_t rt_ospi_send(struct rt_ospi_device *device, const void *send_buf, rt_size_t length); + #ifdef __cplusplus } #endif diff --git a/components/drivers/spi/Kconfig b/components/drivers/spi/Kconfig index 455db9e3bed4..2a3bcd6e8faa 100644 --- a/components/drivers/spi/Kconfig +++ b/components/drivers/spi/Kconfig @@ -351,6 +351,10 @@ menuconfig RT_USING_SPI bool "Enable QSPI mode" default n + config RT_USING_OSPI + bool "Enable OSPI mode" + default n + config RT_USING_SPI_MSD bool "Using SD/TF card driver with spi" select RT_USING_DFS @@ -376,6 +380,11 @@ menuconfig RT_USING_SPI select RT_USING_QSPI default n + config RT_SFUD_USING_OSPI + bool "Using OSPI mode support" + select RT_USING_OSPI + default n + config RT_SFUD_SPI_MAX_HZ int "Default spi maximum speed(HZ)" range 0 50000000 diff --git a/components/drivers/spi/SConscript b/components/drivers/spi/SConscript index 29499e7e4d77..cfc941c034db 100644 --- a/components/drivers/spi/SConscript +++ b/components/drivers/spi/SConscript @@ -17,6 +17,9 @@ if GetDepend('RT_USING_SOFT_SPI'): if GetDepend('RT_USING_QSPI'): src += ['dev_qspi_core.c'] +if GetDepend('RT_USING_OSPI'): + src += ['dev_ospi_core.c'] + src_device = [] if GetDepend('RT_USING_SPI_WIFI'): diff --git a/components/drivers/spi/dev_ospi_core.c b/components/drivers/spi/dev_ospi_core.c new file mode 100644 index 000000000000..b1c30b7f0dc4 --- /dev/null +++ b/components/drivers/spi/dev_ospi_core.c @@ -0,0 +1,320 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-09-03 cliffLL first version. + */ + +#include "drivers/dev_spi.h" + +extern rt_err_t spi_bus_register(struct rt_spi_bus *bus, + const char *name, + const struct rt_spi_ops *ops); + +rt_err_t rt_ospi_configure(struct rt_ospi_device *device, struct rt_ospi_configuration *cfg) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + /* reset the CS pin */ + if (device->parent.cs_pin != PIN_NONE) + { + rt_err_t result = rt_mutex_take(&(device->parent.bus->lock), RT_WAITING_FOREVER); + if (result == RT_EOK) + { + if (cfg->parent.mode & RT_SPI_CS_HIGH) + { + rt_pin_write(device->parent.cs_pin, PIN_LOW); + } + else + { + rt_pin_write(device->parent.cs_pin, PIN_HIGH); + } + rt_mutex_release(&(device->parent.bus->lock)); + } + else + { + return result; + } + } + + /* copy configuration items */ + device->config.parent.mode = cfg->parent.mode; + device->config.parent.max_hz = cfg->parent.max_hz; + device->config.parent.data_width = cfg->parent.data_width; +#ifdef RT_USING_DM + device->config.parent.data_width_tx = cfg->parent.data_width_tx; + device->config.parent.data_width_rx = cfg->parent.data_width_rx; +#else + device->config.parent.reserved = cfg->parent.reserved; +#endif + device->config.medium_size = cfg->medium_size; + device->config.dtr_mode = cfg->dtr_mode; + + return rt_spi_bus_configure(&device->parent); +} + +rt_err_t rt_ospi_bus_register(struct rt_spi_bus *bus, const char *name, const struct rt_spi_ops *ops) +{ + /* set SPI bus to ospi modes */ + bus->mode = RT_SPI_BUS_MODE_OSPI; + + return spi_bus_register(bus, name, ops); +} + +rt_ssize_t rt_ospi_transfer_message(struct rt_ospi_device *device, struct rt_ospi_message *message) +{ + rt_ssize_t result; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(message != RT_NULL); + + result = rt_mutex_take(&(device->parent.bus->lock), RT_WAITING_FOREVER); + if (result != RT_EOK) + { + rt_set_errno(-RT_EBUSY); + + return 0; + } + + /* reset errno */ + rt_set_errno(RT_EOK); + + /* configure SPI bus */ + if (device->parent.bus->owner != &device->parent) + { + /* not the same owner as current, re-configure SPI bus */ + result = device->parent.bus->ops->configure(&device->parent, &device->parent.config); + if (result == RT_EOK) + { + /* set SPI bus owner */ + device->parent.bus->owner = &device->parent; + } + else + { + /* configure SPI bus failed */ + rt_set_errno(-RT_EIO); + goto __exit; + } + } + + /* transmit each SPI message */ + + result = device->parent.bus->ops->xfer(&device->parent, &message->parent); + if (result == 0) + { + rt_set_errno(-RT_EIO); + } + +__exit: + /* release bus lock */ + rt_mutex_release(&(device->parent.bus->lock)); + + return result; +} + +rt_ssize_t rt_ospi_send_then_recv(struct rt_ospi_device *device, const void *send_buf, rt_size_t send_length, void *recv_buf, rt_size_t recv_length) +{ + RT_ASSERT(send_buf); + RT_ASSERT(recv_buf); + RT_ASSERT(send_length != 0); + + struct rt_ospi_message message; + unsigned char *ptr = (unsigned char *)send_buf; + rt_size_t count = 0; + rt_ssize_t result = 0; + + message.instruction.content = ptr[0]; + message.instruction.size = 8; + message.instruction.ospi_lines = 1; + message.instruction.dtrmode = 0; + count++; + + /* get address */ + if (send_length > 1) + { + if ((send_length >= 5) && (message.instruction.content != 0x5A)) + { + /* 4 Byte command, address size is 4 Byte */ + message.address.content = (ptr[1] << 24) | (ptr[2] << 16) | (ptr[3] << 8) | (ptr[4]); + message.address.size = 32; + message.address.ospi_lines = 1; + message.address.dtrmode = 0; + count += 4; + } + else if (send_length >= 4) + { + /* + * JEDEC Read SFDP (0x5A) uses: + * 1-byte instruction + 3-byte address + 1-byte dummy. + * + * The fifth byte in the SPI buffer is a dummy byte, not a fourth + * address byte. Parse the address as 24-bit so that dummy_cycles + * is calculated correctly. + */ + message.address.content = (ptr[1] << 16) | (ptr[2] << 8) | (ptr[3]); + message.address.size = 24; + message.address.ospi_lines = 1; + message.address.dtrmode = 0; + count += 3; + } + else + { + return -RT_ERROR; + } + } + else + { + /* no address stage */ + message.address.content = 0; + message.address.ospi_lines = 0; + message.address.size = 0; + message.address.dtrmode = 0; + } + + message.alternate_bytes.content = 0; + message.alternate_bytes.size = 0; + message.alternate_bytes.ospi_lines = 0; + message.alternate_bytes.dtrmode = 0; + + /* if send_length is not equal to count, dummy cycles exit and should be set */ + if (count != send_length) + { + message.dummy_cycles = (send_length - count) * 8; + } + else + { + message.dummy_cycles = 0; + } + + /* set recv buf and recv size */ + message.parent.recv_buf = recv_buf; + message.parent.send_buf = RT_NULL; + message.parent.length = recv_length; + message.parent.cs_take = 1; + message.parent.cs_release = 1; + + message.ospi_data_lines = 1; + message.ospi_data_dtrmode = 0; + message.dqs_mode = 0; + /* set next */ + /* Ensure correct OSPI message chaining by setting next pointer to NULL, preventing unintended data transmission issues.*/ + message.parent.next = RT_NULL; + + result = rt_ospi_transfer_message(device, &message); + if (result == 0) + { + result = -RT_EIO; + } + else if (result > 0) + { + result = recv_length; + } + + return result; +} + +rt_ssize_t rt_ospi_send(struct rt_ospi_device *device, const void *send_buf, rt_size_t length) +{ + RT_ASSERT(send_buf); + RT_ASSERT(length != 0); + + struct rt_ospi_message message; + unsigned char *ptr = (unsigned char *)send_buf; + rt_size_t count = 0; + rt_ssize_t result = 0; + + message.instruction.content = ptr[0]; + message.instruction.size = 8; + message.instruction.ospi_lines = 1; + message.instruction.dtrmode = 0; + count++; + + /* get address */ + if (length > 1) + { + if (length >= 5) + { + /* 4 Byte command, address size is 4 Byte */ + message.address.content = (ptr[1] << 24) | (ptr[2] << 16) | (ptr[3] << 8) | (ptr[4]); + message.address.size = 32; + message.address.ospi_lines = 1; + message.address.dtrmode = 0; + count += 4; + } + else if (length >= 4) + { + /* address size is 3 Byte */ + message.address.content = (ptr[1] << 16) | (ptr[2] << 8) | (ptr[3]); + message.address.size = 24; + message.address.ospi_lines = 1; + message.address.dtrmode = 0; + count += 3; + } + else if (length >= 2) + { + /* no address but send data */ + message.address.content = 0; + message.address.ospi_lines = 0; + message.address.size = 0; + message.address.dtrmode = 0; + } + else + { + return -RT_ERROR; + } + } + else + { + /* no address stage */ + message.address.content = 0; + message.address.ospi_lines = 0; + message.address.size = 0; + message.address.dtrmode = 0; + } + + message.alternate_bytes.content = 0; + message.alternate_bytes.size = 0; + message.alternate_bytes.ospi_lines = 0; + message.alternate_bytes.dtrmode = 0; + + message.dummy_cycles = 0; + + /* determine if there is data to send */ + if (length - count > 0) + { + message.ospi_data_lines = 1; + } + else + { + message.ospi_data_lines = 0; + } + + /* set send buf and send size */ + message.parent.send_buf = ptr + count; + message.parent.recv_buf = RT_NULL; + message.parent.length = length - count; + message.parent.cs_take = 1; + message.parent.cs_release = 1; + + message.ospi_data_dtrmode = 0; + message.dqs_mode = 0; + /* set next */ + /* Ensure correct OSPI message chaining by setting next pointer to NULL, preventing unintended data transmission issues.*/ + message.parent.next = RT_NULL; + + result = rt_ospi_transfer_message(device, &message); + if (result == 0) + { + result = -RT_EIO; + } + else if (result > 0) + { + result = length; + } + + return result; +} diff --git a/components/drivers/spi/dev_spi_flash_sfud.c b/components/drivers/spi/dev_spi_flash_sfud.c index 7efb6e594b60..bb86dedbbba8 100644 --- a/components/drivers/spi/dev_spi_flash_sfud.c +++ b/components/drivers/spi/dev_spi_flash_sfud.c @@ -7,6 +7,7 @@ * Date Author Notes * 2016-09-28 armink first version. * 2025-10-30 wdfk-prog enable interrupt-safe operations using spinlocks + * 2026-09-03 CliffLL add OSPI operations */ #include @@ -42,6 +43,15 @@ } #endif /* SFUD_USING_QSPI */ +#ifdef SFUD_USING_OSPI +#define RT_SFUD_DEFAULT_OSPI_CFG \ +{ \ + RT_SFUD_DEFAULT_SPI_CFG, \ + .medium_size = 0x2000000, \ + .dtr_mode = 0, \ +} +#endif /* SFUD_USING_OSPI */ + static rt_err_t rt_sfud_control(rt_device_t dev, int cmd, void *args) { RT_ASSERT(dev); @@ -137,6 +147,9 @@ static sfud_err spi_write_read(const sfud_spi *spi, const uint8_t *write_buf, si RT_ASSERT(rtt_dev); #ifdef SFUD_USING_QSPI struct rt_qspi_device *qspi_dev = RT_NULL; +#endif +#ifdef SFUD_USING_OSPI + struct rt_ospi_device *ospi_dev = RT_NULL; #endif if (write_size) { RT_ASSERT(write_buf); @@ -144,8 +157,25 @@ static sfud_err spi_write_read(const sfud_spi *spi, const uint8_t *write_buf, si if (read_size) { RT_ASSERT(read_buf); } +#ifdef SFUD_USING_OSPI + if (rtt_dev->rt_spi_device->bus->mode & RT_SPI_BUS_MODE_OSPI) { + ospi_dev = (struct rt_ospi_device *) (rtt_dev->rt_spi_device); + } + if ((ospi_dev != RT_NULL) && (ospi_dev->ospi_mode == RT_OSPI_MODE_OFF)) { + if (write_size && read_size) { + if (rt_ospi_send_then_recv(ospi_dev, write_buf, write_size, read_buf, read_size) <= 0) { + result = SFUD_ERR_TIMEOUT; + } + } else if (write_size) { + if (rt_ospi_send(ospi_dev, write_buf, write_size) <= 0) { + result = SFUD_ERR_TIMEOUT; + } + } + } + else +#endif #ifdef SFUD_USING_QSPI - if(rtt_dev->rt_spi_device->bus->mode & RT_SPI_BUS_MODE_QSPI) { + if (rtt_dev->rt_spi_device->bus->mode & RT_SPI_BUS_MODE_QSPI) { qspi_dev = (struct rt_qspi_device *) (rtt_dev->rt_spi_device); if (write_size && read_size) { if (rt_qspi_send_then_recv(qspi_dev, write_buf, write_size, read_buf, read_size) <= 0) { @@ -226,6 +256,89 @@ static sfud_err qspi_read(const struct __sfud_spi *spi, uint32_t addr, sfud_qspi } #endif +#ifdef SFUD_USING_OSPI +/** + * OSPI write data or read data + */ +static sfud_err ospi_write_read(const struct __sfud_spi *spi, uint32_t addr, sfud_ospi_cmd_format *ospi_cmd_format, const uint8_t *send_buf, size_t send_size, uint8_t *read_buf, size_t read_size) { + struct rt_ospi_message message; + sfud_err result = SFUD_SUCCESS; + rt_memset(&message, 0, sizeof(message)); + + sfud_flash *sfud_dev = (sfud_flash *) (spi->user_data); + struct spi_flash_device *rtt_dev = (struct spi_flash_device *) (sfud_dev->user_data); + struct rt_ospi_device *ospi_dev = (struct rt_ospi_device *) (rtt_dev->rt_spi_device); + + RT_ASSERT(spi); + RT_ASSERT(sfud_dev); + RT_ASSERT(rtt_dev); + RT_ASSERT(ospi_dev); + + /* set message struct */ + message.instruction.content = ospi_cmd_format->instruction; + message.instruction.size = ospi_cmd_format->instruction_size; + message.instruction.ospi_lines = ospi_cmd_format->instruction_lines; + message.instruction.dtrmode = (ospi_dev->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + + message.address.content = addr; + message.address.size = ospi_cmd_format->address_size; + message.address.ospi_lines = ospi_cmd_format->address_lines; + message.address.dtrmode = (ospi_dev->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + + message.alternate_bytes.content = 0; + message.alternate_bytes.size = 0; + message.alternate_bytes.ospi_lines = 0; + message.alternate_bytes.dtrmode = 0; + + message.dummy_cycles = ospi_cmd_format->dummy_cycles; + + message.parent.send_buf = (send_size > 0) ? send_buf : RT_NULL; + message.parent.recv_buf = (read_size > 0) ? read_buf : RT_NULL; + message.parent.length = (send_size > 0) ? send_size : read_size; + message.parent.cs_release = 1; + message.parent.cs_take = 1; + message.ospi_data_lines = ospi_cmd_format->data_lines; + message.ospi_data_dtrmode = (ospi_dev->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + message.dqs_mode = ((read_size > 0) && (ospi_dev->ospi_mode == RT_OSPI_MODE_DTR)) ? 1 : 0; + /* set next */ + /* Ensure correct OSPI message chaining by setting next pointer to NULL, preventing unintended data transmission issues.*/ + message.parent.next = RT_NULL; + rt_ssize_t ret = rt_ospi_transfer_message(ospi_dev, &message); + if ((send_size && (ret!= message.parent.length)) || (read_size && (ret!= message.parent.length)) || (ret < 0)) { + result = SFUD_ERR_TIMEOUT; + } + + return result; +} + +/** + * get OSPI mode + */ +static sfud_ospi_mode_t get_ospi_mode(const struct __sfud_spi *spi) { + const sfud_flash *sfud_dev = (const sfud_flash *)spi->user_data; + struct spi_flash_device *rtt_dev = (struct spi_flash_device *) (sfud_dev->user_data); + + RT_ASSERT(spi); + RT_ASSERT(sfud_dev); + RT_ASSERT(rtt_dev); + + if (!(rtt_dev->rt_spi_device->bus->mode & RT_SPI_BUS_MODE_OSPI)) { + return SFUD_OSPI_MODE_OFF; + } + + struct rt_ospi_device *ospi_dev = (struct rt_ospi_device *) (rtt_dev->rt_spi_device); + switch (ospi_dev->ospi_mode) { + case RT_OSPI_MODE_STR: + return SFUD_OSPI_MODE_STR; + case RT_OSPI_MODE_DTR: + return SFUD_OSPI_MODE_DTR; + default: + return SFUD_OSPI_MODE_OFF; + } + +} +#endif + static void spi_lock(const sfud_spi *spi) { sfud_flash *sfud_dev = (sfud_flash *) (spi->user_data); struct spi_flash_device *rtt_dev = (struct spi_flash_device *) (sfud_dev->user_data); @@ -292,6 +405,10 @@ sfud_err sfud_spi_port_init(sfud_flash *flash) { flash->spi.wr = spi_write_read; #ifdef SFUD_USING_QSPI flash->spi.qspi_read = qspi_read; +#endif +#ifdef SFUD_USING_OSPI + flash->spi.ospi_write_read = ospi_write_read; + flash->spi.get_ospi_mode = get_ospi_mode; #endif flash->spi.lock = spi_lock; flash->spi.unlock = spi_unlock; @@ -320,25 +437,30 @@ const static struct rt_device_ops flash_device_ops = #endif /** - * Probe SPI flash by SFUD (Serial Flash Universal Driver) driver library and though SPI device by specified configuration. + * Probe an SPI/QSPI/OSPI flash by SFUD (Serial Flash Universal Driver) driver library and through SPI device by specified configuration. * * @param spi_flash_dev_name the name which will create SPI flash device * @param spi_dev_name using SPI device name * @param spi_cfg SPI device configuration * @param qspi_cfg QSPI device configuration + * @param ospi_cfg OSPI device configuration * * @return probed SPI flash device, probe failed will return RT_NULL */ -rt_spi_flash_device_t rt_sfud_flash_probe_ex(const char *spi_flash_dev_name, const char *spi_dev_name, - struct rt_spi_configuration *spi_cfg, struct rt_qspi_configuration *qspi_cfg) +static rt_spi_flash_device_t rt_sfud_flash_probe_internal(const char *spi_flash_dev_name, const char *spi_dev_name, + struct rt_spi_configuration *spi_cfg, struct rt_qspi_configuration *qspi_cfg, struct rt_ospi_configuration *ospi_cfg) { rt_spi_flash_device_t rtt_dev = RT_NULL; sfud_flash *sfud_dev = RT_NULL; char *spi_flash_dev_name_bak = RT_NULL, *spi_dev_name_bak = RT_NULL; + void *old_spi_user_data = RT_NULL; extern sfud_err sfud_device_init(sfud_flash *flash); #ifdef SFUD_USING_QSPI struct rt_qspi_device *qspi_dev = RT_NULL; #endif +#ifdef SFUD_USING_OSPI + struct rt_ospi_device *ospi_dev = RT_NULL; +#endif RT_ASSERT(spi_flash_dev_name); RT_ASSERT(spi_dev_name); @@ -374,6 +496,21 @@ rt_spi_flash_device_t rt_sfud_flash_probe_ex(const char *spi_flash_dev_name, con } sfud_dev->spi.name = spi_dev_name_bak; +#ifdef SFUD_USING_OSPI + /* set the ospi line number and configure the OSPI bus */ + if (rtt_dev->rt_spi_device->bus->mode &RT_SPI_BUS_MODE_OSPI) { + ospi_dev = (struct rt_ospi_device *)rtt_dev->rt_spi_device; + if (ospi_cfg == RT_NULL) { + LOG_E("ERROR: OSPI configuration is NULL."); + goto error; + } + if (rt_ospi_configure(ospi_dev, ospi_cfg) != RT_EOK) { + LOG_E("ERROR: Configure OSPI device %s failed.", spi_dev_name); + goto error; + } + } + else +#endif #ifdef SFUD_USING_QSPI /* set the qspi line number and configure the QSPI bus */ if(rtt_dev->rt_spi_device->bus->mode &RT_SPI_BUS_MODE_QSPI) { @@ -389,6 +526,7 @@ rt_spi_flash_device_t rt_sfud_flash_probe_ex(const char *spi_flash_dev_name, con { sfud_dev->name = spi_flash_dev_name_bak; /* accessed each other */ + old_spi_user_data = rtt_dev->rt_spi_device->user_data; rtt_dev->user_data = sfud_dev; rtt_dev->rt_spi_device->user_data = rtt_dev; rtt_dev->flash_device.user_data = rtt_dev; @@ -402,6 +540,22 @@ rt_spi_flash_device_t rt_sfud_flash_probe_ex(const char *spi_flash_dev_name, con rtt_dev->geometry.sector_count = sfud_dev->chip.capacity / sfud_dev->chip.erase_gran; rtt_dev->geometry.bytes_per_sector = sfud_dev->chip.erase_gran; rtt_dev->geometry.block_size = sfud_dev->chip.erase_gran; +#ifdef SFUD_USING_OSPI + /* reconfigure the OSPI bus for medium size */ + if(rtt_dev->rt_spi_device->bus->mode &RT_SPI_BUS_MODE_OSPI) { + ospi_cfg->medium_size = sfud_dev->chip.capacity; + if (rt_ospi_configure(ospi_dev, ospi_cfg) != RT_EOK) { + LOG_E("ERROR: Reconfigure OSPI device %s failed.", spi_dev_name); + goto error; + } + if (ospi_dev->enter_ospi_str_mode != RT_NULL) { + if (ospi_dev->enter_ospi_str_mode(ospi_dev) != RT_EOK) { + LOG_E("ERROR: Enter OSPI STR mode failed."); + goto error; + } + } + } +#endif /* SFUD_USING_OSPI */ #ifdef SFUD_USING_QSPI /* reconfigure the QSPI bus for medium size */ if(rtt_dev->rt_spi_device->bus->mode &RT_SPI_BUS_MODE_QSPI) { @@ -441,6 +595,9 @@ rt_spi_flash_device_t rt_sfud_flash_probe_ex(const char *spi_flash_dev_name, con error: if (rtt_dev) { + if (rtt_dev->rt_spi_device && rtt_dev->rt_spi_device->user_data == rtt_dev) { + rtt_dev->rt_spi_device->user_data = old_spi_user_data; + } rt_mutex_detach(&(rtt_dev->lock)); } /* may be one of objects memory was malloc success, so need free all */ @@ -453,7 +610,41 @@ rt_spi_flash_device_t rt_sfud_flash_probe_ex(const char *spi_flash_dev_name, con } /** - * Probe SPI flash by SFUD(Serial Flash Universal Driver) driver library and though SPI device. + * Probe SPI/QSPI flash by SFUD (Serial Flash Universal Driver) driver library and through SPI device by specified configuration. + * + * @param spi_flash_dev_name the name which will create SPI flash device + * @param spi_dev_name using SPI device name + * @param spi_cfg SPI device configuration + * @param qspi_cfg QSPI device configuration + * + * @return probed SPI flash device, probe failed will return RT_NULL + */ +rt_spi_flash_device_t rt_sfud_flash_probe_ex(const char *spi_flash_dev_name, const char *spi_dev_name, + struct rt_spi_configuration *spi_cfg, struct rt_qspi_configuration *qspi_cfg) +{ + return rt_sfud_flash_probe_internal(spi_flash_dev_name, spi_dev_name, spi_cfg, qspi_cfg, RT_NULL); +} + +#ifdef SFUD_USING_OSPI +/** + * Probe SPI/OSPI flash by SFUD (Serial Flash Universal Driver) driver library and through SPI device by specified configuration. + * + * @param spi_flash_dev_name the name which will create SPI flash device + * @param spi_dev_name using SPI device name + * @param spi_cfg SPI device configuration + * @param ospi_cfg OSPI device configuration + * + * @return probed SPI flash device, probe failed will return RT_NULL + */ +rt_spi_flash_device_t rt_sfud_flash_probe_ospi_ex(const char *spi_flash_dev_name, const char *spi_dev_name, + struct rt_spi_configuration *spi_cfg, struct rt_ospi_configuration *ospi_cfg) +{ + return rt_sfud_flash_probe_internal(spi_flash_dev_name, spi_dev_name, spi_cfg, RT_NULL, ospi_cfg); +} +#endif + +/** + * Probe SPI flash by SFUD(Serial Flash Universal Driver) driver library and through SPI device. * * @param spi_flash_dev_name the name which will create SPI flash device * @param spi_dev_name using SPI device name @@ -463,12 +654,21 @@ rt_spi_flash_device_t rt_sfud_flash_probe_ex(const char *spi_flash_dev_name, con rt_spi_flash_device_t rt_sfud_flash_probe(const char *spi_flash_dev_name, const char *spi_dev_name) { struct rt_spi_configuration cfg = RT_SFUD_DEFAULT_SPI_CFG; -#ifndef SFUD_USING_QSPI - return rt_sfud_flash_probe_ex(spi_flash_dev_name, spi_dev_name, &cfg, RT_NULL); -#else +#if defined(SFUD_USING_OSPI) && defined(SFUD_USING_QSPI) + struct rt_ospi_configuration ospi_cfg = RT_SFUD_DEFAULT_OSPI_CFG; + struct rt_qspi_configuration qspi_cfg = RT_SFUD_DEFAULT_QSPI_CFG; + + return rt_sfud_flash_probe_internal(spi_flash_dev_name, spi_dev_name, &cfg, &qspi_cfg, &ospi_cfg); +#elif defined(SFUD_USING_OSPI) && !defined(SFUD_USING_QSPI) + struct rt_ospi_configuration ospi_cfg = RT_SFUD_DEFAULT_OSPI_CFG; + + return rt_sfud_flash_probe_ospi_ex(spi_flash_dev_name, spi_dev_name, &cfg, &ospi_cfg); +#elif !defined(SFUD_USING_OSPI) && defined(SFUD_USING_QSPI) struct rt_qspi_configuration qspi_cfg = RT_SFUD_DEFAULT_QSPI_CFG; return rt_sfud_flash_probe_ex(spi_flash_dev_name, spi_dev_name, &cfg, &qspi_cfg); +#else + return rt_sfud_flash_probe_ex(spi_flash_dev_name, spi_dev_name, &cfg, RT_NULL); #endif } diff --git a/components/drivers/spi/dev_spi_flash_sfud.h b/components/drivers/spi/dev_spi_flash_sfud.h index 5c3236fcce6f..e1fb8566825f 100644 --- a/components/drivers/spi/dev_spi_flash_sfud.h +++ b/components/drivers/spi/dev_spi_flash_sfud.h @@ -32,7 +32,7 @@ extern "C" { rt_spi_flash_device_t rt_sfud_flash_probe(const char *spi_flash_dev_name, const char *spi_dev_name); /** - * Probe SPI flash by SFUD (Serial Flash Universal Driver) driver library and though SPI device by specified configuration. + * Probe SPI/QSPI flash by SFUD (Serial Flash Universal Driver) driver library and through SPI device by specified configuration. * * @param spi_flash_dev_name the name which will create SPI flash device * @param spi_dev_name using SPI device name @@ -44,6 +44,21 @@ rt_spi_flash_device_t rt_sfud_flash_probe(const char *spi_flash_dev_name, const rt_spi_flash_device_t rt_sfud_flash_probe_ex(const char *spi_flash_dev_name, const char *spi_dev_name, struct rt_spi_configuration *spi_cfg, struct rt_qspi_configuration *qspi_cfg); +#ifdef SFUD_USING_OSPI +/** + * Probe SPI/OSPI flash by SFUD (Serial Flash Universal Driver) driver library and through SPI device by specified configuration. + * + * @param spi_flash_dev_name the name which will create SPI flash device + * @param spi_dev_name using SPI device name + * @param spi_cfg SPI device configuration + * @param ospi_cfg OSPI device configuration + * + * @return probed SPI flash device, probe failed will return RT_NULL + */ +rt_spi_flash_device_t rt_sfud_flash_probe_ospi_ex(const char *spi_flash_dev_name, const char *spi_dev_name, + struct rt_spi_configuration *spi_cfg, struct rt_ospi_configuration *ospi_cfg); +#endif + /** * Delete SPI flash device * diff --git a/components/drivers/spi/sfud/inc/sfud_cfg.h b/components/drivers/spi/sfud/inc/sfud_cfg.h index 59859149aab5..75aa89f185ef 100644 --- a/components/drivers/spi/sfud/inc/sfud_cfg.h +++ b/components/drivers/spi/sfud/inc/sfud_cfg.h @@ -63,6 +63,13 @@ #define SFUD_USING_QSPI #endif +/** + * SFUD will support OSPI mode. + */ +#ifdef RT_SFUD_USING_OSPI +#define SFUD_USING_OSPI +#endif + /** * Using probe flash JEDEC ID then query defined supported flash chip information table. @see SFUD_FLASH_CHIP_TABLE */ diff --git a/components/drivers/spi/sfud/inc/sfud_def.h b/components/drivers/spi/sfud/inc/sfud_def.h index c06f9b12954b..7d0eee0528b5 100644 --- a/components/drivers/spi/sfud/inc/sfud_def.h +++ b/components/drivers/spi/sfud/inc/sfud_def.h @@ -106,6 +106,10 @@ if (!(EXPR)) \ #define SFUD_CMD_PAGE_PROGRAM 0x02 #endif +#ifndef SFUD_CMD_PAGE_PROGRAM_4B +#define SFUD_CMD_PAGE_PROGRAM_4B 0x12 +#endif + #ifndef SFUD_CMD_AAI_WORD_PROGRAM #define SFUD_CMD_AAI_WORD_PROGRAM 0xAD #endif @@ -114,10 +118,22 @@ if (!(EXPR)) \ #define SFUD_CMD_ERASE_CHIP 0xC7 #endif +#ifndef SFUD_CMD_ERASE_SECTOR_4B +#define SFUD_CMD_ERASE_SECTOR_4B 0x21 +#endif + #ifndef SFUD_CMD_READ_DATA #define SFUD_CMD_READ_DATA 0x03 #endif +#ifndef SFUD_CMD_READ_DATA_OSPI_STR +#define SFUD_CMD_READ_DATA_OSPI_STR 0xEC +#endif + +#ifndef SFUD_CMD_READ_DATA_OSPI_DTR +#define SFUD_CMD_READ_DATA_OSPI_DTR 0xEE +#endif + #ifndef SFUD_CMD_DUAL_OUTPUT_READ_DATA #define SFUD_CMD_DUAL_OUTPUT_READ_DATA 0x3B #endif @@ -175,6 +191,11 @@ if (!(EXPR)) \ #define SFUD_DUMMY_DATA 0xFF #endif +/* default dummy cycles in OPI mode*/ +#ifndef SFUD_OSPI_6_DUMMY_CYCLES +#define SFUD_OSPI_6_DUMMY_CYCLES 6 +#endif + /* maximum number of erase type support on JESD216 (V1.0) */ #define SFUD_SFDP_ERASE_TYPE_MAX_NUM 4 @@ -214,6 +235,33 @@ typedef struct { } sfud_qspi_read_cmd_format; #endif /* SFUD_USING_QSPI */ +#ifdef SFUD_USING_OSPI +/** + * OSPI flash read cmd format + */ +typedef struct { + uint16_t instruction; + uint8_t instruction_lines; + uint8_t instruction_size; + uint8_t address_size; + uint8_t address_lines; + uint8_t alternate_bytes_lines; + uint8_t dummy_cycles; + uint8_t dtr_mode; + uint8_t data_lines; + uint8_t dqs_mode; +} sfud_ospi_cmd_format; + +/** + * OSPI flash mode + */ +typedef enum { + SFUD_OSPI_MODE_OFF = 0, + SFUD_OSPI_MODE_STR = 1, + SFUD_OSPI_MODE_DTR = 2, +} sfud_ospi_mode_t; +#endif /* SFUD_USING_OSPI */ + /* SPI bus write read data function type */ typedef sfud_err (*spi_write_read_func)(const uint8_t *write_buf, size_t write_size, uint8_t *read_buf, size_t read_size); @@ -254,6 +302,13 @@ typedef struct __sfud_spi { /* QSPI fast read function */ sfud_err (*qspi_read)(const struct __sfud_spi *spi, uint32_t addr, sfud_qspi_read_cmd_format *qspi_read_cmd_format, uint8_t *read_buf, size_t read_size); +#endif +#ifdef SFUD_USING_OSPI + /* OSPI write or read function */ + sfud_err (*ospi_write_read)(const struct __sfud_spi *spi, uint32_t addr, sfud_ospi_cmd_format *ospi_cmd_format, + const uint8_t *send_buf, size_t send_size, uint8_t *read_buf, size_t read_size); + /* get OSPI mode function */ + sfud_ospi_mode_t (*get_ospi_mode)(const struct __sfud_spi *spi); #endif /* lock SPI bus */ void (*lock)(const struct __sfud_spi *spi); @@ -283,6 +338,10 @@ typedef struct { sfud_qspi_read_cmd_format read_cmd_format; /**< fast read cmd format */ #endif +#ifdef SFUD_USING_OSPI + sfud_ospi_cmd_format ospi_cmd_format; /**< ospi cmd format */ +#endif + #ifdef SFUD_USING_SFDP sfud_sfdp sfdp; /**< serial flash discoverable parameters by JEDEC standard */ #endif diff --git a/components/drivers/spi/sfud/inc/sfud_flash_def.h b/components/drivers/spi/sfud/inc/sfud_flash_def.h index 03f164551f1e..c4621967a66b 100644 --- a/components/drivers/spi/sfud/inc/sfud_flash_def.h +++ b/components/drivers/spi/sfud/inc/sfud_flash_def.h @@ -149,6 +149,7 @@ typedef struct { {"PCT25VF016B", SFUD_MF_ID_SST, 0x25, 0x41, 2L*1024L*1024L, SFUD_WM_BYTE|SFUD_WM_AAI, 4096, 0x20}, \ {"NM25Q128EVB", SFUD_MF_ID_NOR_MEM, 0x21, 0x18, 16L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0x20}, \ {"W25Q128JWPIM", SFUD_MF_ID_MACRONIX, 0x25, 0x38, 16L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0x20}, \ + {"MX25LM51245G", SFUD_MF_ID_MACRONIX, 0x85, 0x3A, 64L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0x21}, \ } #endif /* SFUD_USING_FLASH_INFO_TABLE */ diff --git a/components/drivers/spi/sfud/src/sfud.c b/components/drivers/spi/sfud/src/sfud.c index 2f920cf67a5a..1fec166facbb 100644 --- a/components/drivers/spi/sfud/src/sfud.c +++ b/components/drivers/spi/sfud/src/sfud.c @@ -78,6 +78,20 @@ static void make_address_byte_array(const sfud_flash *flash, uint32_t addr, uint extern void sfud_log_debug(const char *file, const long line, const char *format, ...); extern void sfud_log_info(const char *format, ...); +#ifdef SFUD_USING_OSPI +/** + * Convert the 8-bit SPI command to a 16-bit OSPI command + * + * @param flash flash device + * + * @return result + */ +static inline uint16_t sfud_ospi_cmd_value(uint8_t ins) +{ + return (uint16_t)(((uint16_t)ins << 8) | (uint16_t)(ins ^ 0xFF)); +} +#endif + /** * SFUD initialize by flash device * @@ -162,6 +176,52 @@ const sfud_flash *sfud_get_device_table(void) { return flash_table; } +#ifdef SFUD_USING_OSPI +static void ospi_set_cmd_format(sfud_flash *flash, uint8_t ins, uint8_t dummy_cycles) { + flash->ospi_cmd_format.instruction = sfud_ospi_cmd_value(ins); + flash->ospi_cmd_format.instruction_size = 16; + flash->ospi_cmd_format.instruction_lines = 8; + flash->ospi_cmd_format.address_lines = 0; + flash->ospi_cmd_format.address_size = 0; + flash->ospi_cmd_format.data_lines = 0; + switch (ins) { + case SFUD_CMD_WRITE_ENABLE: + case SFUD_CMD_WRITE_DISABLE: + flash->ospi_cmd_format.address_lines = 0; + flash->ospi_cmd_format.address_size = 0; + flash->ospi_cmd_format.data_lines = 0; + break; + case SFUD_CMD_READ_STATUS_REGISTER: + case SFUD_CMD_WRITE_STATUS_REGISTER: + case SFUD_CMD_READ_DATA_OSPI_STR: + case SFUD_CMD_READ_DATA_OSPI_DTR: + case SFUD_CMD_PAGE_PROGRAM_4B: + flash->ospi_cmd_format.address_lines = 8; + flash->ospi_cmd_format.address_size = 32; + flash->ospi_cmd_format.data_lines = 8; + break; + case SFUD_CMD_ERASE_CHIP: + flash->ospi_cmd_format.address_lines = 0; + flash->ospi_cmd_format.address_size = 0; + flash->ospi_cmd_format.data_lines = 0; + break; + case SFUD_CMD_ERASE_SECTOR_4B: + flash->ospi_cmd_format.address_lines = 8; + flash->ospi_cmd_format.address_size = 32; + flash->ospi_cmd_format.data_lines = 0; + break; + } + if (ins == flash->chip.erase_gran_cmd) { + flash->ospi_cmd_format.address_lines = 8; + flash->ospi_cmd_format.address_size = 32; + flash->ospi_cmd_format.data_lines = 0; + } + + flash->ospi_cmd_format.alternate_bytes_lines = 0; + flash->ospi_cmd_format.dummy_cycles = dummy_cycles; +} +#endif + #ifdef SFUD_USING_QSPI static void qspi_set_read_cmd_format(sfud_flash *flash, uint8_t ins, uint8_t ins_lines, uint8_t addr_lines, uint8_t dummy_cycles, uint8_t data_lines) { @@ -366,6 +426,12 @@ static sfud_err hardware_init(sfud_flash *flash) { return result; } +#ifdef SFUD_USING_OSPI + SFUD_ASSERT(flash->spi.get_ospi_mode); + if (flash->spi.get_ospi_mode(&flash->spi) != SFUD_OSPI_MODE_OFF) { + flash->addr_in_4_byte = true; + } else +#endif /* if the flash is large than 16MB (256Mb) then enter in 4-Byte addressing mode */ if (flash->chip.capacity > (1L << 24)) { result = set_4_byte_address_mode(flash, true); @@ -423,6 +489,35 @@ sfud_err sfud_read(const sfud_flash *flash, uint32_t addr, size_t size, uint8_t result = wait_busy(flash); if (result == SFUD_SUCCESS) { +#ifdef SFUD_USING_OSPI + if (spi->ospi_write_read && spi->get_ospi_mode && (spi->get_ospi_mode(spi) != SFUD_OSPI_MODE_OFF)) { + sfud_flash *f = (sfud_flash *)flash; + uint8_t cmd = (spi->get_ospi_mode(spi) == SFUD_OSPI_MODE_DTR) ? SFUD_CMD_READ_DATA_OSPI_DTR : SFUD_CMD_READ_DATA_OSPI_STR; + ospi_set_cmd_format(f, cmd, SFUD_OSPI_6_DUMMY_CYCLES); + + /* OPI-DTR requires an even transfer length */ + if ((spi->get_ospi_mode(spi) == SFUD_OSPI_MODE_DTR) && (size % 2)) { + uint8_t *dtr_databuf = NULL; + size_t dtr_datasize; + dtr_datasize = size + 1; + /* check the flash address bound */ + if (addr + dtr_datasize > flash->chip.capacity) { + SFUD_INFO("Error: DTR read exceeds flash boundary."); + result = SFUD_ERR_ADDR_OUT_OF_BOUND; + } else { + dtr_databuf = (uint8_t *)rt_malloc(dtr_datasize); + result = spi->ospi_write_read(&flash->spi, addr, &f->ospi_cmd_format, NULL, 0, dtr_databuf, dtr_datasize); + if (result == SFUD_SUCCESS) { + rt_memcpy(data, dtr_databuf, size); + } + rt_free(dtr_databuf); + } + } else { + result = spi->ospi_write_read(&flash->spi, addr, &f->ospi_cmd_format, NULL, 0, data, size); + } + } + else +#endif #ifdef SFUD_USING_QSPI if (flash->read_cmd_format.instruction != SFUD_CMD_READ_DATA) { result = spi->qspi_read(spi, addr, (sfud_qspi_read_cmd_format *)&flash->read_cmd_format, data, size); @@ -470,6 +565,14 @@ sfud_err sfud_chip_erase(const sfud_flash *flash) { } cmd_data[0] = SFUD_CMD_ERASE_CHIP; +#ifdef SFUD_USING_OSPI + if (spi->ospi_write_read && spi->get_ospi_mode && (spi->get_ospi_mode(spi) != SFUD_OSPI_MODE_OFF)) { + sfud_flash *f = (sfud_flash *)flash; + ospi_set_cmd_format(f, SFUD_CMD_ERASE_CHIP, 0); + result = spi->ospi_write_read(&flash->spi, 0, &f->ospi_cmd_format, NULL, 0, NULL, 0); + } + else +#endif /* dual-buffer write, like AT45DB series flash chip erase operate is different for other flash */ if (flash->chip.write_mode & SFUD_WM_DUAL_BUFFER) { cmd_data[1] = 0x94; @@ -479,6 +582,13 @@ sfud_err sfud_chip_erase(const sfud_flash *flash) { } else { result = spi->wr(spi, cmd_data, 1, NULL, 0); } +#ifdef SFUD_USING_OSPI + if (result != SFUD_SUCCESS) { + SFUD_INFO("Error: Flash chip erase OSPI communicate error."); + goto __exit; + } + else +#endif if (result != SFUD_SUCCESS) { SFUD_INFO("Error: Flash chip erase SPI communicate error."); goto __exit; @@ -556,13 +666,27 @@ sfud_err sfud_erase(const sfud_flash *flash, uint32_t addr, size_t size) { goto __exit; } - cmd_data[0] = cur_erase_cmd; - make_address_byte_array(flash, addr, &cmd_data[1]); - cmd_size = flash->addr_in_4_byte ? 5 : 4; - result = spi->wr(spi, cmd_data, cmd_size, NULL, 0); - if (result != SFUD_SUCCESS) { - SFUD_INFO("Error: Flash erase SPI communicate error."); - goto __exit; +#ifdef SFUD_USING_OSPI + if (spi->ospi_write_read && spi->get_ospi_mode && (spi->get_ospi_mode(spi) != SFUD_OSPI_MODE_OFF)) { + sfud_flash *f = (sfud_flash *)flash; + ospi_set_cmd_format(f, cur_erase_cmd, 0); + result = spi->ospi_write_read(&flash->spi, addr, &f->ospi_cmd_format, NULL, 0, NULL, 0); + if (result != SFUD_SUCCESS) { + SFUD_INFO("Error: Flash erase OSPI communicate error."); + goto __exit; + } + } + else +#endif + { + cmd_data[0] = cur_erase_cmd; + make_address_byte_array(flash, addr, &cmd_data[1]); + cmd_size = flash->addr_in_4_byte ? 5 : 4; + result = spi->wr(spi, cmd_data, cmd_size, NULL, 0); + if (result != SFUD_SUCCESS) { + SFUD_INFO("Error: Flash erase SPI communicate error."); + goto __exit; + } } result = wait_busy(flash); if (result != SFUD_SUCCESS) { @@ -659,12 +783,57 @@ static sfud_err page256_or_1_byte_write(const sfud_flash *flash, uint32_t addr, size -= data_size; addr += data_size; - rt_memcpy(&cmd_data[cmd_size], data, data_size); +#ifdef SFUD_USING_OSPI + if (spi->ospi_write_read && spi->get_ospi_mode && (spi->get_ospi_mode(spi) != SFUD_OSPI_MODE_OFF)) { + sfud_flash *f = (sfud_flash *)flash; + ospi_set_cmd_format(f, SFUD_CMD_PAGE_PROGRAM_4B, 0); + /* OPI-DTR requires an even transfer length */ + if ((size <= 0) && (spi->get_ospi_mode(spi) == SFUD_OSPI_MODE_DTR) && (data_size % 2)) { + uint8_t dtr_readbuf[2] = {0}; + uint8_t *dtr_databuf = NULL; + dtr_databuf = (uint8_t *)rt_malloc(data_size + 1); + /* Before the last write command, read data to write correct data to last byte of an odd-length sequence*/ + ospi_set_cmd_format(f, SFUD_CMD_READ_DATA_OSPI_DTR, SFUD_OSPI_6_DUMMY_CYCLES); + result = spi->ospi_write_read(&flash->spi, addr, &f->ospi_cmd_format, NULL, 0, dtr_readbuf, 2); + if (result != SFUD_SUCCESS) { + SFUD_INFO("Error: Flash read OSPI communicate error."); + if (dtr_databuf != RT_NULL) { + rt_free(dtr_databuf); + } + goto __exit; + } + rt_memcpy(dtr_databuf, data, data_size); + dtr_databuf[data_size] = dtr_readbuf[0]; + ospi_set_cmd_format(f, SFUD_CMD_PAGE_PROGRAM_4B, 0); + result = spi->ospi_write_read(&flash->spi, (uint32_t)(addr-(uint32_t)data_size), &f->ospi_cmd_format, dtr_databuf, data_size + 1, NULL, 0); + if (result != SFUD_SUCCESS) { + SFUD_INFO("Error: Flash DTR write OSPI communicate error."); + if (dtr_databuf != RT_NULL) { + rt_free(dtr_databuf); + } + goto __exit; + } + if (dtr_databuf != RT_NULL) { + rt_free(dtr_databuf); + } + } else { + result = spi->ospi_write_read(&flash->spi, (uint32_t)(addr-(uint32_t)data_size), &f->ospi_cmd_format, data, data_size, NULL, 0); + if (result != SFUD_SUCCESS) { + SFUD_INFO("Error: Flash write OSPI communicate error."); + goto __exit; + } + } + } + else +#endif + { + rt_memcpy(&cmd_data[cmd_size], data, data_size); - result = spi->wr(spi, cmd_data, cmd_size + data_size, NULL, 0); - if (result != SFUD_SUCCESS) { - SFUD_INFO("Error: Flash write SPI communicate error."); - goto __exit; + result = spi->wr(spi, cmd_data, cmd_size + data_size, NULL, 0); + if (result != SFUD_SUCCESS) { + SFUD_INFO("Error: Flash write SPI communicate error."); + goto __exit; + } } result = wait_busy(flash); if (result != SFUD_SUCCESS) { @@ -887,16 +1056,41 @@ static sfud_err read_jedec_id(sfud_flash *flash) { static sfud_err set_write_enabled(const sfud_flash *flash, bool enabled) { sfud_err result = SFUD_SUCCESS; uint8_t cmd, register_status; + const sfud_spi *spi = &flash->spi; SFUD_ASSERT(flash); +#ifdef SFUD_USING_OSPI + if (spi->ospi_write_read && spi->get_ospi_mode && (spi->get_ospi_mode(spi) != SFUD_OSPI_MODE_OFF)) { + cmd = enabled ? SFUD_CMD_WRITE_ENABLE : SFUD_CMD_WRITE_DISABLE; + sfud_flash *f = (sfud_flash *)flash; + ospi_set_cmd_format(f, cmd, 0); + result = spi->ospi_write_read(&flash->spi, 0, &f->ospi_cmd_format, NULL, 0, NULL, 0); + + if (result == SFUD_SUCCESS) { + result = sfud_read_status(flash, ®ister_status); + } + + if (result == SFUD_SUCCESS) { + if (enabled && (register_status & SFUD_STATUS_REGISTER_WEL) == 0) { + SFUD_INFO("Error: Can't enable write status."); + return SFUD_ERR_WRITE; + } else if (!enabled && (register_status & SFUD_STATUS_REGISTER_WEL) != 0) { + SFUD_INFO("Error: Can't disable write status."); + return SFUD_ERR_WRITE; + } + } + + return result; + } +#endif if (enabled) { cmd = SFUD_CMD_WRITE_ENABLE; } else { cmd = SFUD_CMD_WRITE_DISABLE; } - result = flash->spi.wr(&flash->spi, &cmd, 1, NULL, 0); + result = spi->wr(&flash->spi, &cmd, 1, NULL, 0); if (result == SFUD_SUCCESS) { result = sfud_read_status(flash, ®ister_status); @@ -965,11 +1159,29 @@ static sfud_err set_4_byte_address_mode(sfud_flash *flash, bool enabled) { */ sfud_err sfud_read_status(const sfud_flash *flash, uint8_t *status) { uint8_t cmd = SFUD_CMD_READ_STATUS_REGISTER; + const sfud_spi *spi = &flash->spi; SFUD_ASSERT(flash); SFUD_ASSERT(status); - return flash->spi.wr(&flash->spi, &cmd, 1, status, 1); +#ifdef SFUD_USING_OSPI + if (spi->ospi_write_read && spi->get_ospi_mode && (spi->get_ospi_mode(spi) != SFUD_OSPI_MODE_OFF)) { + sfud_flash *f = (sfud_flash *)flash; + ospi_set_cmd_format(f, cmd, SFUD_OSPI_6_DUMMY_CYCLES); + if (spi->get_ospi_mode(spi) == SFUD_OSPI_MODE_STR) { + return spi->ospi_write_read(&flash->spi, 0, &f->ospi_cmd_format, NULL, 0, status, 1); + } else { + sfud_err result = SFUD_SUCCESS; + uint8_t dtr_databuf[2] = {0}; + result = spi->ospi_write_read(&flash->spi, 0, &f->ospi_cmd_format, NULL, 0, dtr_databuf, sizeof(dtr_databuf)); + /* when read status register in 8-8-8 DTR mode, 1-Byte data will be read twice */ + *status = dtr_databuf[0]; + return result; + } + } +#endif + + return spi->wr(&flash->spi, &cmd, 1, status, 1); } static sfud_err wait_busy(const sfud_flash *flash) { @@ -1032,9 +1244,26 @@ sfud_err sfud_write_status(const sfud_flash *flash, bool is_volatile, uint8_t st } if (result == SFUD_SUCCESS) { - cmd_data[0] = SFUD_CMD_WRITE_STATUS_REGISTER; - cmd_data[1] = status; - result = spi->wr(spi, cmd_data, 2, NULL, 0); +#ifdef SFUD_USING_OSPI + if (spi->ospi_write_read && spi->get_ospi_mode && (spi->get_ospi_mode(spi) != SFUD_OSPI_MODE_OFF)) { + sfud_flash *f = (sfud_flash *)flash; + ospi_set_cmd_format(f, SFUD_CMD_WRITE_STATUS_REGISTER, 0); + if (spi->get_ospi_mode(spi) == SFUD_OSPI_MODE_STR) { + result = spi->ospi_write_read(&flash->spi, 0, &f->ospi_cmd_format, &status, 1, NULL, 0); + } else { + uint8_t dtr_databuf[2]; + dtr_databuf[0] = status; + dtr_databuf[1] = status; + result = spi->ospi_write_read(&flash->spi, 0, &f->ospi_cmd_format, dtr_databuf, sizeof(dtr_databuf), NULL, 0); + } + } + else +#endif + { + cmd_data[0] = SFUD_CMD_WRITE_STATUS_REGISTER; + cmd_data[1] = status; + result = spi->wr(spi, cmd_data, 2, NULL, 0); + } } if (result != SFUD_SUCCESS) { From 7f9ae87efa68e1cb5ab89dea04cbf5296efd95d1 Mon Sep 17 00:00:00 2001 From: clifflin Date: Mon, 28 Sep 2026 14:39:10 +0800 Subject: [PATCH 2/4] [bsp][stm32] Add generic OSPI low-level driver Purpose: Provide a generic OSPI low-level driver under STM32 HAL_Drivers to validate and enable the components-layer OSPI path on STM32 BSPs. Description: 1. bsp/stm32/libraries/HAL_Drivers/drivers/drv_ospi.c/.h: Implement generic OctoSPI init, support transfers in SPI/OSPI mode (1-1-1/8-8-8) and provide helpers for command sequences. 2. bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/ospi_config.h: Add default OCTOSPI mapping for stm32l4xx. 3. bsp/stm32/libraries/HAL_Drivers/drivers/SConscript, drv_config.h: Include the new driver when needed. Tested in stm32l4r9-st-eval BSP project. Signed-off-by: CliffLL --- .../libraries/HAL_Drivers/drivers/SConscript | 3 + .../drivers/config/l4/ospi_config.h | 68 +++ .../HAL_Drivers/drivers/drv_config.h | 2 + .../libraries/HAL_Drivers/drivers/drv_ospi.c | 504 ++++++++++++++++++ .../libraries/HAL_Drivers/drivers/drv_ospi.h | 27 + 5 files changed, 604 insertions(+) create mode 100644 bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/ospi_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/drivers/drv_ospi.c create mode 100644 bsp/stm32/libraries/HAL_Drivers/drivers/drv_ospi.h diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/SConscript b/bsp/stm32/libraries/HAL_Drivers/drivers/SConscript index 0a9ceb24da50..cdeae73b9bd5 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/SConscript +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/SConscript @@ -36,6 +36,9 @@ if GetDepend(['RT_USING_SPI']): if GetDepend(['RT_USING_QSPI']): src += ['drv_qspi.c'] +if GetDepend(['RT_USING_OSPI']): + src += ['drv_ospi.c'] + if GetDepend(['RT_USING_I2C']): if GetDepend('BSP_USING_HARD_I2C1') or GetDepend('BSP_USING_HARD_I2C2') or GetDepend('BSP_USING_HARD_I2C3') or GetDepend('BSP_USING_HARD_I2C4'): src += ['drv_hard_i2c.c'] diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/ospi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/ospi_config.h new file mode 100644 index 000000000000..501cdadb37c4 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/ospi_config.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-08-17 CliffLL first version + */ + +#ifndef __OSPI_CONFIG_H__ +#define __OSPI_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_OSPI +#ifndef OSPI_INSTANCE +#define OSPI_INSTANCE OCTOSPI1 +#endif + +#ifndef OSPI_MEMORY_TYPE +#define OSPI_MEMORY_TYPE HAL_OSPI_MEMTYPE_MACRONIX +#endif + +#ifndef OSPI_CLK_PORT +#define OSPI_CLK_PORT 1U +#endif + +#ifndef OSPI_DQS_PORT +#define OSPI_DQS_PORT 1U +#endif + +#ifndef OSPI_NCS_PORT +#define OSPI_NCS_PORT 1U +#endif + +#ifndef OSPI_IO_LOW_PORT +#define OSPI_IO_LOW_PORT HAL_OSPIM_IOPORT_1_LOW +#endif + +#ifndef OSPI_IO_HIGH_PORT +#define OSPI_IO_HIGH_PORT HAL_OSPIM_IOPORT_1_HIGH +#endif + +#ifndef OSPI_BUS_CONFIG +#define OSPI_BUS_CONFIG \ + { \ + .Instance = OSPI_INSTANCE, \ + .Init.FifoThreshold = 4, \ + .Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE, \ + .Init.ChipSelectHighTime = 2, \ + .Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE, \ + .Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE, \ + .Init.ChipSelectBoundary = 0, \ + .Init.MemoryType = OSPI_MEMORY_TYPE, \ + } +#endif /* OSPI_BUS_CONFIG */ +#endif /* BSP_USING_OSPI */ + +#ifdef __cplusplus +} +#endif + +#endif /* __OSPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h index 80a2897ecdfd..5e7b0e7a8d79 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-10-30 SummerGift first version * 2020-10-14 PeakRacing Porting for stm32wbxx + * 2026-08-18 CliffLL add l4/ospi_config.h */ #ifndef __DRV_CONFIG_H__ @@ -88,6 +89,7 @@ extern "C" { #include "l4/uart_config.h" #include "l4/spi_config.h" #include "l4/qspi_config.h" +#include "l4/ospi_config.h" #include "l4/adc_config.h" #include "l4/adc_config_v2.h" #include "l4/dac_config.h" diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_ospi.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_ospi.c new file mode 100644 index 000000000000..71d5c6012548 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_ospi.c @@ -0,0 +1,504 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-08-17 CliffLL first version + */ + +#include "board.h" +#include "drv_ospi.h" +#include "drv_dma.h" +#include "drv_config.h" + +#ifdef RT_USING_OSPI + +#define DRV_DEBUG +#define LOG_TAG "drv.ospi" +#include + +#if defined(BSP_USING_OSPI) + +struct stm32_ospi_bus +{ + OSPI_HandleTypeDef OSPI_Handler; + char *bus_name; +}; + +struct rt_spi_bus _ospi_bus1; +struct stm32_ospi_bus _stm32_ospi_bus; + +static int stm32_ospi_init(struct rt_ospi_device *device, struct rt_ospi_configuration *ospi_cfg) +{ + int result = RT_EOK; + unsigned int i = 1; + + OSPIM_CfgTypeDef OSPIM_Cfg_Struct = { 0 }; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(ospi_cfg != RT_NULL); + + struct rt_spi_configuration *cfg = &ospi_cfg->parent; + struct stm32_ospi_bus *ospi_bus = device->parent.bus->parent.user_data; + rt_memset(&ospi_bus->OSPI_Handler, 0, sizeof(ospi_bus->OSPI_Handler)); + + OSPI_HandleTypeDef OSPI_Handler_config = OSPI_BUS_CONFIG; + ospi_bus->OSPI_Handler = OSPI_Handler_config; + + while (cfg->max_hz < HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_OSPI) / (i + 1)) + { + i++; + if (i == 255) + { + LOG_E("OSPI init failed, OSPI frequency(%d) is too low.", cfg->max_hz); + return -RT_ERROR; + } + } + + ospi_bus->OSPI_Handler.Init.ClockPrescaler = i; + + if (!(cfg->mode & RT_SPI_CPOL)) + { + /* OSPI MODE0 */ + ospi_bus->OSPI_Handler.Init.ClockMode = HAL_OSPI_CLOCK_MODE_0; + } + else + { + /* OSPI MODE3 */ + ospi_bus->OSPI_Handler.Init.ClockMode = HAL_OSPI_CLOCK_MODE_3; + } + + /* flash size */ + ospi_bus->OSPI_Handler.Init.DeviceSize = POSITION_VAL(ospi_cfg->medium_size); + + /* dqs mode */ + if (ospi_cfg->dtr_mode) + { + /* OSPI DTR MODE */ + ospi_bus->OSPI_Handler.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE; + } + else + { + /* OSPI STR MODE */ + ospi_bus->OSPI_Handler.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_DISABLE; + } + + result = HAL_OSPI_Init(&ospi_bus->OSPI_Handler); + if (result == HAL_OK) + { + LOG_D("ospi init success!"); + } + else + { + LOG_E("ospi init failed (%d)!", result); + return -RT_EIO; + } + + OSPIM_Cfg_Struct.ClkPort = OSPI_CLK_PORT; + OSPIM_Cfg_Struct.DQSPort = OSPI_DQS_PORT; + OSPIM_Cfg_Struct.NCSPort = OSPI_NCS_PORT; + OSPIM_Cfg_Struct.IOLowPort = OSPI_IO_LOW_PORT; + OSPIM_Cfg_Struct.IOHighPort = OSPI_IO_HIGH_PORT; + + if (HAL_OSPIM_Config(&ospi_bus->OSPI_Handler, &OSPIM_Cfg_Struct, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + LOG_E("ospim init failed !"); + return -RT_EIO; + } + + return result; +} + +static rt_err_t stm32_ospi_recover(struct rt_spi_device *device) +{ + HAL_StatusTypeDef status; + struct rt_ospi_device *ospi_device; + struct stm32_ospi_bus *ospi_bus; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + + ospi_device = (struct rt_ospi_device *)device; + ospi_bus = device->bus->parent.user_data; + + RT_ASSERT(ospi_bus != RT_NULL); + + /* + * Abort may fail if the previous command did not enter a transferable + * state, but DeInit is still attempted for controller recovery. + */ + status = HAL_OSPI_Abort(&ospi_bus->OSPI_Handler); + if (status != HAL_OK) + { + LOG_W("HAL_OSPI_Abort failed, status=%d, error=0x%08X", (int)status, (unsigned int)ospi_bus->OSPI_Handler.ErrorCode); + } + + status = HAL_OSPI_DeInit(&ospi_bus->OSPI_Handler); + if (status != HAL_OK) + { + LOG_E("HAL_OSPI_DeInit failed, status=%d, error=0x%08X", (int)status, (unsigned int)ospi_bus->OSPI_Handler.ErrorCode); + return -RT_EIO; + } + + /* + * Rebuild OSPI Handle and configure OSPIM routing using the current + * OSPI device configuration. + */ + return stm32_ospi_init(ospi_device, &ospi_device->config); +} + +static rt_err_t ospi_send_cmd(struct stm32_ospi_bus *ospi_bus, struct rt_ospi_message *message) +{ + RT_ASSERT(ospi_bus != RT_NULL); + RT_ASSERT(message != RT_NULL); + + OSPI_RegularCmdTypeDef Cmdhandler = { 0 }; + HAL_StatusTypeDef status; + + /* set OSPI cmd struct */ + Cmdhandler.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; + Cmdhandler.FlashId = HAL_OSPI_FLASH_ID_1; + Cmdhandler.Instruction = message->instruction.content; + Cmdhandler.Address = message->address.content; + Cmdhandler.DummyCycles = message->dummy_cycles; + if (message->instruction.ospi_lines == 0) + { + Cmdhandler.InstructionMode = HAL_OSPI_INSTRUCTION_NONE; + } + else if (message->instruction.ospi_lines == 1) + { + Cmdhandler.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE; + } + else if (message->instruction.ospi_lines == 2) + { + Cmdhandler.InstructionMode = HAL_OSPI_INSTRUCTION_2_LINES; + } + else if (message->instruction.ospi_lines == 4) + { + Cmdhandler.InstructionMode = HAL_OSPI_INSTRUCTION_4_LINES; + } + else if (message->instruction.ospi_lines == 8) + { + Cmdhandler.InstructionMode = HAL_OSPI_INSTRUCTION_8_LINES; + } + else + { + return -RT_EINVAL; + } + + if (message->instruction.dtrmode == 0) + { + Cmdhandler.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE; + } + else if (message->instruction.dtrmode == 1) + { + Cmdhandler.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_ENABLE; + } + else + { + return -RT_EINVAL; + } + + if (message->instruction.size == 8) + { + Cmdhandler.InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS; + } + else if (message->instruction.size == 16) + { + Cmdhandler.InstructionSize = HAL_OSPI_INSTRUCTION_16_BITS; + } + else + { + return -RT_EINVAL; + } + + if (message->address.ospi_lines == 0) + { + Cmdhandler.AddressMode = HAL_OSPI_ADDRESS_NONE; + } + else + { + if (message->address.ospi_lines == 1) + { + Cmdhandler.AddressMode = HAL_OSPI_ADDRESS_1_LINE; + } + else if (message->address.ospi_lines == 2) + { + Cmdhandler.AddressMode = HAL_OSPI_ADDRESS_2_LINES; + } + else if (message->address.ospi_lines == 4) + { + Cmdhandler.AddressMode = HAL_OSPI_ADDRESS_4_LINES; + } + else if (message->address.ospi_lines == 8) + { + Cmdhandler.AddressMode = HAL_OSPI_ADDRESS_8_LINES; + } + else + { + return -RT_EINVAL; + } + + if (message->address.dtrmode == 0) + { + Cmdhandler.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE; + } + else if (message->address.dtrmode == 1) + { + Cmdhandler.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_ENABLE; + } + else + { + return -RT_EINVAL; + } + + if (message->address.size == 24) + { + Cmdhandler.AddressSize = HAL_OSPI_ADDRESS_24_BITS; + } + else if (message->address.size == 32) + { + Cmdhandler.AddressSize = HAL_OSPI_ADDRESS_32_BITS; + } + else + { + return -RT_EINVAL; + } + } + + if (message->ospi_data_lines == 0) + { + Cmdhandler.DataMode = HAL_OSPI_DATA_NONE; + } + else if (message->ospi_data_lines == 1) + { + Cmdhandler.DataMode = HAL_OSPI_DATA_1_LINE; + } + else if (message->ospi_data_lines == 2) + { + Cmdhandler.DataMode = HAL_OSPI_DATA_2_LINES; + } + else if (message->ospi_data_lines == 4) + { + Cmdhandler.DataMode = HAL_OSPI_DATA_4_LINES; + } + else if (message->ospi_data_lines == 8) + { + Cmdhandler.DataMode = HAL_OSPI_DATA_8_LINES; + } + else + { + return -RT_EINVAL; + } + + if (message->ospi_data_dtrmode == 0) + { + Cmdhandler.DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE; + } + else if (message->ospi_data_dtrmode == 1) + { + Cmdhandler.DataDtrMode = HAL_OSPI_DATA_DTR_ENABLE; + } + else + { + return -RT_EINVAL; + } + + if (message->dqs_mode == 0) + { + Cmdhandler.DQSMode = HAL_OSPI_DQS_DISABLE; + } + else if (message->dqs_mode == 1) + { + Cmdhandler.DQSMode = HAL_OSPI_DQS_ENABLE; + } + else + { + return -RT_EINVAL; + } + + Cmdhandler.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD; + + /* Alternate bytes are not required by currently supported */ + Cmdhandler.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; + Cmdhandler.NbData = message->parent.length; + + status = HAL_OSPI_Command(&ospi_bus->OSPI_Handler, &Cmdhandler, 5000); + if (status != HAL_OK) + { + LOG_E("HAL_OSPI_Command failed, status=%d, error=0x%08X", (int)status, (unsigned int)ospi_bus->OSPI_Handler.ErrorCode); + if (HAL_OSPI_Abort(&ospi_bus->OSPI_Handler) != HAL_OK) + { + LOG_E("HAL_OSPI_Abort failed, error=0x%08X", (unsigned int)ospi_bus->OSPI_Handler.ErrorCode); + } + return -RT_EIO; + } + + return RT_EOK; +} + +static rt_ssize_t ospixfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + rt_ssize_t result = 0; + rt_err_t cmd_result; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + + struct rt_ospi_message *ospi_message = (struct rt_ospi_message *)message; + struct stm32_ospi_bus *ospi_bus = device->bus->parent.user_data; + + const rt_uint8_t *sndb = message->send_buf; + rt_uint8_t *rcvb = message->recv_buf; + rt_int32_t length = message->length; + + /* Length < 0 is invalid */ + if (length < 0) + { + return -RT_EINVAL; + } + + /* Length > 0 but neither TX or RX buffer exists is invalid */ + if ((length > 0) && (sndb == RT_NULL) && (rcvb == RT_NULL)) + { + return -RT_EINVAL; + } + + /* TX and RX buffer exists at the same time is invalid */ + if ((sndb != RT_NULL) && (rcvb != RT_NULL)) + { + return -RT_EINVAL; + } + + /* Execute HAL_OSPI_Command */ + cmd_result = ospi_send_cmd(ospi_bus, ospi_message); + if (cmd_result != RT_EOK) + { + if (stm32_ospi_recover(device) != RT_EOK) + { + LOG_W("OSPI controller recovery failed after command error."); + } + return cmd_result; + } + + /* send only header */ + if (length == 0) + { + /* rt_ospi_transfer_message() treats zero as failure, return a positive value for a successful command-only transfer */ + return 1; + } + else if (sndb)/* send data */ + { + if (HAL_OSPI_Transmit(&ospi_bus->OSPI_Handler, (rt_uint8_t *)sndb, 5000) == HAL_OK) + { + return length; + } + else + { + LOG_E("OSPI send data failed(%d)!", ospi_bus->OSPI_Handler.ErrorCode); + if (stm32_ospi_recover(device) != RT_EOK) + { + LOG_W("OSPI controller recovery failed after transmit error."); + } + return -RT_EIO; + } + } + else if (rcvb)/* recv data */ + { + if (HAL_OSPI_Receive(&ospi_bus->OSPI_Handler, rcvb, 5000) == HAL_OK) + { + return length; + } + else + { + LOG_E("OSPI recv data failed(%d)!", ospi_bus->OSPI_Handler.ErrorCode); + if (stm32_ospi_recover(device) != RT_EOK) + { + LOG_W("OSPI controller recovery failed after transmit error."); + } + return -RT_EIO; + } + } + + return -RT_EINVAL; +} + +static rt_err_t ospi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + struct rt_ospi_device *ospi_device = (struct rt_ospi_device *)device; + return stm32_ospi_init(ospi_device, &ospi_device->config); +} + +static const struct rt_spi_ops stm32_ospi_ops = { + .configure = ospi_configure, + .xfer = ospixfer, +}; + +static int stm32_ospi_register_bus(struct stm32_ospi_bus *ospi_bus, const char *name) +{ + RT_ASSERT(ospi_bus != RT_NULL); + RT_ASSERT(name != RT_NULL); + + _ospi_bus1.parent.user_data = ospi_bus; + return rt_ospi_bus_register(&_ospi_bus1, name, &stm32_ospi_ops); +} + +/** + * @brief This function attach device to OSPI bus. + * @param device_name OSPI device name + * @param enter_ospi_str_mode Callback function that lets FLASH enter STR-OPI mode + * @param enter_ospi_dtr_mode Callback function that lets FLASH enter DTR-OPI mode + * @param exit_ospi_mode Callback function that lets FLASH exit OSPI mode + * @retval 0 : success + * -1 : failed + */ +rt_err_t rt_hw_ospi_device_attach(const char *bus_name, const char *device_name, rt_err_t (*enter_ospi_str_mode)(struct rt_ospi_device *device), rt_err_t (*enter_ospi_dtr_mode)(struct rt_ospi_device *device), rt_err_t (*exit_ospi_mode)(struct rt_ospi_device *device)) +{ + struct rt_ospi_device *ospi_device = RT_NULL; + rt_err_t result = RT_EOK; + + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + + ospi_device = (struct rt_ospi_device *)rt_malloc(sizeof(struct rt_ospi_device)); + if (ospi_device == RT_NULL) + { + LOG_E("no memory, ospi bus attach device failed!"); + result = -RT_ENOMEM; + goto __exit; + } + rt_memset(ospi_device, 0, sizeof(struct rt_ospi_device)); + ospi_device->config.dtr_mode = 0; + ospi_device->ospi_mode = RT_OSPI_MODE_OFF; + + ospi_device->enter_ospi_str_mode = enter_ospi_str_mode; + ospi_device->enter_ospi_dtr_mode = enter_ospi_dtr_mode; + ospi_device->exit_ospi_mode = exit_ospi_mode; + + result = rt_spi_bus_attach_device_cspin(&ospi_device->parent, device_name, bus_name, PIN_NONE, RT_NULL); + +__exit: + if (result != RT_EOK) + { + if (ospi_device) + { + rt_free(ospi_device); + } + } + + return result; +} + +static int rt_hw_ospi_bus_init(void) +{ + return stm32_ospi_register_bus(&_stm32_ospi_bus, "ospi1"); +} +INIT_BOARD_EXPORT(rt_hw_ospi_bus_init); + +#endif /* BSP_USING_OSPI */ +#endif /* RT_USING_OSPI */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_ospi.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_ospi.h new file mode 100644 index 000000000000..19a07a83c73e --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_ospi.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-08-17 CliffLL first version + */ + +#ifndef __DRV_OSPI_H__ +#define __DRV_OSPI_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct rt_ospi_device; +rt_err_t rt_hw_ospi_device_attach(const char *bus_name, const char *device_name, rt_err_t (*enter_ospi_str_mode)(struct rt_ospi_device *device), rt_err_t (*enter_ospi_dtr_mode)(struct rt_ospi_device *device), rt_err_t (*exit_ospi_mode)(struct rt_ospi_device *device)); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_OSPI_H__ */ From 8eb72ec5f09a3b6190b7a506b329016cba7cc7bf Mon Sep 17 00:00:00 2001 From: clifflin Date: Mon, 28 Sep 2026 14:45:08 +0800 Subject: [PATCH 3/4] [bsp][stm32l4r9-eval] Add OctaFlash support and fix linker/heap config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Purpose: 1. Validate the components‑layer OSPI path on a real board by adding board‑level OctaFlash support (1‑1‑1 and OPI STR/DTR). 2. Provide a working BSP setup (clocks/pins/MSP/OSPIM and heap/linker fixes) for out-of-the-box SFUD testing. Description: 1. Provide the OSPI flash driver to attach OSPI device on stm32l4r9‑eval, init bus and provide helpers to enter OPI STR/DTR for upper‑layer tests. 2. Modify the .ioc file and regenerate code to enable OCTOSPI1 and update pin/clock/MSP. 3. Add using OSPI options and include the new driver. 4. Fix heap/linker mismatches observed in GCC run: Align BSP with RT‑Thread heap/layout template to avoid .bss overlap. 5. Document OctaFlash support and usage notes for this board. 6. Regenerate the MDK5 and IAR projects for the BSP. Notes: 1. Default to BSP minimal config per guideline: Only UART (console) and GPIO enabled; DMA off; FinSH MSH‑only; User main with 1Hz LED blink. 2. Dist packaging: created offline dist for testing; GCC build from dist is OK; MDK5 and IAR projects generated by dist are OK. 3. Due to environment limits, MDK5/IAR flashing was not performed. (Build and run were fully verified on GCC; MDK5/IAR projects were generated.) Signed-off-by: CliffLL --- bsp/stm32/stm32l4r9-st-eval/.config | 68 ++- bsp/stm32/stm32l4r9-st-eval/README.md | 2 + .../board/CubeMX_Config/.mxproject | 11 +- .../board/CubeMX_Config/CubeMX_Config.ioc | 205 +++++--- .../CubeMX_Config/Inc/stm32l4xx_hal_conf.h | 10 +- .../CubeMX_Config/Src/stm32l4xx_hal_msp.c | 204 ++++++-- .../board/CubeMX_Config/Src/stm32l4xx_it.c | 1 + bsp/stm32/stm32l4r9-st-eval/board/Kconfig | 13 + bsp/stm32/stm32l4r9-st-eval/board/SConscript | 3 + bsp/stm32/stm32l4r9-st-eval/board/board.c | 103 ++-- bsp/stm32/stm32l4r9-st-eval/board/board.h | 19 +- .../board/linker_scripts/link.icf | 3 +- .../board/linker_scripts/link.sct | 2 +- .../board/ports/drv_ospi_flash.c | 439 ++++++++++++++++ bsp/stm32/stm32l4r9-st-eval/project.ewp | 300 ++++++----- bsp/stm32/stm32l4r9-st-eval/project.uvprojx | 478 +++++++++++++----- bsp/stm32/stm32l4r9-st-eval/rtconfig.h | 20 +- 17 files changed, 1448 insertions(+), 433 deletions(-) create mode 100644 bsp/stm32/stm32l4r9-st-eval/board/ports/drv_ospi_flash.c diff --git a/bsp/stm32/stm32l4r9-st-eval/.config b/bsp/stm32/stm32l4r9-st-eval/.config index 36d50770b621..42c2fb5019e7 100644 --- a/bsp/stm32/stm32l4r9-st-eval/.config +++ b/bsp/stm32/stm32l4r9-st-eval/.config @@ -242,10 +242,11 @@ CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set -CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set @@ -254,7 +255,6 @@ CONFIG_RT_USING_I2C_BITOPS=y # CONFIG_RT_USING_SOFT_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -267,7 +267,22 @@ CONFIG_RT_USING_I2C_BITOPS=y # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set +CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set +# CONFIG_RT_USING_SOFT_SPI is not set +# CONFIG_RT_USING_QSPI is not set +CONFIG_RT_USING_OSPI=y +# CONFIG_RT_USING_SPI_MSD is not set +CONFIG_RT_USING_SFUD=y +# CONFIG_RT_SFUD_USING_SFDP is not set +CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y +# CONFIG_RT_SFUD_USING_QSPI is not set +CONFIG_RT_SFUD_USING_OSPI=y +CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 +# CONFIG_RT_DEBUG_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set @@ -275,10 +290,10 @@ CONFIG_RT_USING_I2C_BITOPS=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -471,6 +486,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -647,6 +663,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set # end of tools packages # @@ -836,7 +853,21 @@ CONFIG_PKG_STM32L4_CMSIS_DRIVER_VER="latest" # CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -924,6 +955,23 @@ CONFIG_PKG_STM32L4_CMSIS_DRIVER_VER="latest" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -1057,6 +1105,7 @@ CONFIG_PKG_STM32L4_CMSIS_DRIVER_VER="latest" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1107,6 +1156,7 @@ CONFIG_PKG_STM32L4_CMSIS_DRIVER_VER="latest" # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1209,6 +1259,7 @@ CONFIG_PKG_STM32L4_CMSIS_DRIVER_VER="latest" # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_GET_IRQ_PRIORITY is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1460,6 +1511,7 @@ CONFIG_SOC_SERIES_STM32L4=y # CONFIG_BSP_USING_STLINK_TO_USART=y # CONFIG_BSP_USING_DSI is not set +# CONFIG_BSP_USING_OSPI_FLASH is not set # # Enable Touch @@ -1475,10 +1527,10 @@ CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART=y CONFIG_BSP_STM32_UART_V1_TX_TIMEOUT=2000 CONFIG_BSP_USING_UART3=y -# CONFIG_BSP_UART3_RX_USING_DMA is not set -# CONFIG_BSP_UART3_TX_USING_DMA is not set +# CONFIG_BSP_USING_OSPI is not set # CONFIG_BSP_USING_SRAM is not set -# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_ADC_V2 is not set # CONFIG_BSP_USING_CRC is not set # CONFIG_BSP_USING_RNG is not set # CONFIG_BSP_USING_UDID is not set diff --git a/bsp/stm32/stm32l4r9-st-eval/README.md b/bsp/stm32/stm32l4r9-st-eval/README.md index e91aced25cf0..5734ad921d05 100644 --- a/bsp/stm32/stm32l4r9-st-eval/README.md +++ b/bsp/stm32/stm32l4r9-st-eval/README.md @@ -40,9 +40,11 @@ | LCD | 支持 | DSI mode round lcd | | TOUCH | 支持 | touch for round lcd | | SRAM | 支持 | | +| OSPI Flash | 支持 | | | **片上外设** | **支持情况** | **备注** | | GPIO | 支持 | | | UART | 支持 | USART3 | +| OCTOSPI | 支持 | OCTOSPI1 | diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/.mxproject index c20f8463309d..c358cca04d30 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/.mxproject @@ -1,13 +1,14 @@ [PreviousGenFiles] -HeaderPath=E:/0423/rt-thread/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc +HeaderPath=D:/rt-thread/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc HeaderFiles=stm32l4xx_it.h;stm32l4xx_hal_conf.h;main.h;gfxmmu_lut.h; -SourcePath=E:/0423/rt-thread/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src +SourcePath=D:/rt-thread/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src SourceFiles=stm32l4xx_it.c;stm32l4xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dsi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gfxmmu.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gfxmmu.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dsi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gfxmmu.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; +LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dsi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gfxmmu.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ospi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gfxmmu.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dsi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gfxmmu.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ospi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/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[PreviousUsedKeilFiles] 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4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;../\Src/system_stm32l4xx.c;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;null; +HeaderPath=C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers\STM32L4xx_HAL_Driver\Inc;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers\CMSIS\Device\ST\STM32L4xx\Include;C:\Users\clifflin\STM32Cube\Repository\STM32Cube_FW_L4_V1.14.0\Drivers\CMSIS\Include;..\Inc; +CDefines=USE_HAL_DRIVER;STM32L4R9xx;USE_HAL_DRIVER;STM32L4R9xx; diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/CubeMX_Config.ioc index b5a954c18e0e..b839ca7ed9f0 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/CubeMX_Config.ioc @@ -20,87 +20,123 @@ Mcu.IP2=FMC Mcu.IP3=GFXMMU Mcu.IP4=LTDC Mcu.IP5=NVIC -Mcu.IP6=RCC -Mcu.IP7=SYS -Mcu.IP8=USART3 -Mcu.IPNb=9 +Mcu.IP6=OCTOSPI1 +Mcu.IP7=RCC +Mcu.IP8=SYS +Mcu.IP9=USART3 +Mcu.IPNb=10 Mcu.Name=STM32L4R9A(G-I)Ix Mcu.Package=UFBGA169 -Mcu.Pin0=PE0 -Mcu.Pin1=PE1 -Mcu.Pin10=PF2 -Mcu.Pin11=PF1 -Mcu.Pin12=PF0 -Mcu.Pin13=PD7 -Mcu.Pin14=PC15-OSC32_OUT (PC15) -Mcu.Pin15=PF3 -Mcu.Pin16=PF4 -Mcu.Pin17=PF5 -Mcu.Pin18=PG4 -Mcu.Pin19=PG3 -Mcu.Pin2=PD0 -Mcu.Pin20=PG5 -Mcu.Pin21=PH0-OSC_IN (PH0) -Mcu.Pin22=PG1 -Mcu.Pin23=PE10 -Mcu.Pin24=PB11 -Mcu.Pin25=PD13 -Mcu.Pin26=PG2 -Mcu.Pin27=PD15 -Mcu.Pin28=PD14 -Mcu.Pin29=PH1-OSC_OUT (PH1) -Mcu.Pin3=PD4 -Mcu.Pin30=PG0 -Mcu.Pin31=PE9 -Mcu.Pin32=PE15 -Mcu.Pin33=PD12 -Mcu.Pin34=PD11 -Mcu.Pin35=PD10 -Mcu.Pin36=DSIHOST_D1P -Mcu.Pin37=DSIHOST_D1N -Mcu.Pin38=PF15 -Mcu.Pin39=PE8 -Mcu.Pin4=PD1 -Mcu.Pin40=PE14 -Mcu.Pin41=PD9 -Mcu.Pin42=PD8 -Mcu.Pin43=DSIHOST_CKP -Mcu.Pin44=DSIHOST_CKN -Mcu.Pin45=PF14 -Mcu.Pin46=PE7 -Mcu.Pin47=PE13 -Mcu.Pin48=DSIHOST_D0P -Mcu.Pin49=DSIHOST_D0N -Mcu.Pin5=PE4 -Mcu.Pin50=PF13 -Mcu.Pin51=PE12 -Mcu.Pin52=PF12 -Mcu.Pin53=PE11 -Mcu.Pin54=PB10 -Mcu.Pin55=VP_DMA2D_VS_DMA2D -Mcu.Pin56=VP_GFXMMU_VS_GFXMMU -Mcu.Pin57=VP_LTDC_DSIMode -Mcu.Pin58=VP_SYS_VS_Systick -Mcu.Pin6=PE3 -Mcu.Pin7=PD5 -Mcu.Pin8=PE5 -Mcu.Pin9=PC14-OSC32_IN (PC14) -Mcu.PinsNb=59 +Mcu.Pin0=PH2 +Mcu.Pin1=PE0 +Mcu.Pin10=PG11 +Mcu.Pin11=PC14-OSC32_IN (PC14) +Mcu.Pin12=PF2 +Mcu.Pin13=PF1 +Mcu.Pin14=PF0 +Mcu.Pin15=PD7 +Mcu.Pin16=PC15-OSC32_OUT (PC15) +Mcu.Pin17=PF3 +Mcu.Pin18=PF4 +Mcu.Pin19=PF5 +Mcu.Pin2=PE1 +Mcu.Pin20=PG4 +Mcu.Pin21=PG3 +Mcu.Pin22=PG5 +Mcu.Pin23=PH0-OSC_IN (PH0) +Mcu.Pin24=PG1 +Mcu.Pin25=PE10 +Mcu.Pin26=PB11 +Mcu.Pin27=PD13 +Mcu.Pin28=PG2 +Mcu.Pin29=PD15 +Mcu.Pin3=PD0 +Mcu.Pin30=PD14 +Mcu.Pin31=PH1-OSC_OUT (PH1) +Mcu.Pin32=PG0 +Mcu.Pin33=PE9 +Mcu.Pin34=PE15 +Mcu.Pin35=PD12 +Mcu.Pin36=PD11 +Mcu.Pin37=PD10 +Mcu.Pin38=DSIHOST_D1P +Mcu.Pin39=DSIHOST_D1N +Mcu.Pin4=PD4 +Mcu.Pin40=PC3 +Mcu.Pin41=PC4 +Mcu.Pin42=PF15 +Mcu.Pin43=PE8 +Mcu.Pin44=PE14 +Mcu.Pin45=PD9 +Mcu.Pin46=PD8 +Mcu.Pin47=DSIHOST_CKP +Mcu.Pin48=DSIHOST_CKN +Mcu.Pin49=PA6 +Mcu.Pin5=PD1 +Mcu.Pin50=PB1 +Mcu.Pin51=PF14 +Mcu.Pin52=PE7 +Mcu.Pin53=PE13 +Mcu.Pin54=DSIHOST_D0P +Mcu.Pin55=DSIHOST_D0N +Mcu.Pin56=PA3 +Mcu.Pin57=PA7 +Mcu.Pin58=PF13 +Mcu.Pin59=PE12 +Mcu.Pin6=PE4 +Mcu.Pin60=PA2 +Mcu.Pin61=PB0 +Mcu.Pin62=PB2 +Mcu.Pin63=PF12 +Mcu.Pin64=PE11 +Mcu.Pin65=PB10 +Mcu.Pin66=VP_DMA2D_VS_DMA2D +Mcu.Pin67=VP_GFXMMU_VS_GFXMMU +Mcu.Pin68=VP_LTDC_DSIMode +Mcu.Pin69=VP_OCTOSPI1_VS_octo +Mcu.Pin7=PE3 +Mcu.Pin70=VP_SYS_VS_Systick +Mcu.Pin8=PD5 +Mcu.Pin9=PE5 +Mcu.PinsNb=71 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32L4R9AIIx -MxCube.Version=5.0.1 -MxDb.Version=DB.5.0.1 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false +MxCube.Version=5.3.0 +MxDb.Version=DB.5.0.30 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +OCTOSPI1.ChipSelectBoundary=0 +OCTOSPI1.ChipSelectHighTime=2 +OCTOSPI1.ClockPrescaler=3 +OCTOSPI1.DeviceSize=26 +OCTOSPI1.FifoThreshold=4 +OCTOSPI1.IPParameters=FifoThreshold,DeviceSize,ChipSelectHighTime,ClockPrescaler,OperationType,ChipSelectBoundary +OCTOSPI1.OperationType=HAL_OSPI_OPTYPE_COMMON_CFG +PA2.GPIOParameters=GPIO_PuPd +PA2.GPIO_PuPd=GPIO_PULLUP +PA2.Locked=true +PA2.Mode=OCTOSPI1_Port1_NCS +PA2.Signal=OCTOSPIM_P1_NCS +PA3.Locked=true +PA3.Mode=OCTOSPI1_Port1_CLK +PA3.Signal=OCTOSPIM_P1_CLK +PA6.Locked=true +PA6.Signal=OCTOSPIM_P1_IO3 +PA7.Locked=true +PA7.Signal=OCTOSPIM_P1_IO2 +PB0.Locked=true +PB0.Signal=OCTOSPIM_P1_IO1 +PB1.Locked=true +PB1.Signal=OCTOSPIM_P1_IO0 PB10.GPIOParameters=GPIO_PuPd PB10.GPIO_PuPd=GPIO_PULLUP PB10.Mode=Asynchronous @@ -109,10 +145,17 @@ PB11.GPIOParameters=GPIO_PuPd PB11.GPIO_PuPd=GPIO_PULLUP PB11.Mode=Asynchronous PB11.Signal=USART3_RX +PB2.Locked=true +PB2.Mode=OCTOSPI1_Port1_DQS +PB2.Signal=OCTOSPIM_P1_DQS PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT +PC3.Locked=true +PC3.Signal=OCTOSPIM_P1_IO6 +PC4.Locked=true +PC4.Signal=OCTOSPIM_P1_IO7 PCC.Checker=true PCC.Line=STM32L4R9/S9 PCC.MCU=STM32L4R9A(G-I)Ix @@ -120,7 +163,7 @@ PCC.PartNumber=STM32L4R9AIIx PCC.Seq0=0 PCC.Series=STM32L4 PCC.Temperature=25 -PCC.Vdd=null +PCC.Vdd=3.0 PD0.Signal=FMC_D2_DA2 PD1.Signal=FMC_D3_DA3 PD10.Signal=FMC_D15_DA15 @@ -163,6 +206,8 @@ PF4.Signal=FMC_A4 PF5.Signal=FMC_A5 PG0.Signal=FMC_A10 PG1.Signal=FMC_A11 +PG11.Locked=true +PG11.Signal=OCTOSPIM_P1_IO5 PG2.Signal=FMC_A12 PG3.Signal=FMC_A13 PG4.Signal=FMC_A14 @@ -171,6 +216,8 @@ PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT +PH2.Locked=true +PH2.Signal=OCTOSPIM_P1_IO4 PinOutPanel.CurrentBGAView=Top PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true @@ -182,7 +229,7 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32L4R9AIIx -ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.13.0 +ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.14.0 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 @@ -199,7 +246,7 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=MDK-ARM V5 ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_LTDC_Init-LTDC-false-HAL-true,5-MX_FMC_Init-FMC-false-HAL-true,6-MX_DMA2D_Init-DMA2D-false-HAL-true,7-MX_DSIHOST_DSI_Init-DSIHOST-false-HAL-true,8-MX_GFXMMU_Init-GFXMMU-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_LTDC_Init-LTDC-false-HAL-true,5-MX_FMC_Init-FMC-false-HAL-true,6-MX_DMA2D_Init-DMA2D-false-HAL-true,7-MX_DSIHOST_DSI_Init-DSIHOST-false-HAL-true,8-MX_GFXMMU_Init-GFXMMU-false-HAL-true,9-MX_OCTOSPI1_Init-OCTOSPI1-false-HAL-true RCC.ADCFreq_Value=64000000 RCC.AHBFreq_Value=120000000 RCC.APB1Freq_Value=120000000 @@ -359,6 +406,8 @@ VP_GFXMMU_VS_GFXMMU.Mode=GFXMMU_Activate VP_GFXMMU_VS_GFXMMU.Signal=GFXMMU_VS_GFXMMU VP_LTDC_DSIMode.Mode=RGB888 VP_LTDC_DSIMode.Signal=LTDC_DSIMode +VP_OCTOSPI1_VS_octo.Mode=octo_mode +VP_OCTOSPI1_VS_octo.Signal=OCTOSPI1_VS_octo VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick board=custom diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h index 9a78d0cd72b3..6d52029a9c59 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h @@ -5,7 +5,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2019 STMicroelectronics

+ *

© COPYRIGHT(c) 2026 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -70,11 +70,12 @@ #define HAL_LTDC_MODULE_ENABLED /*#define HAL_LCD_MODULE_ENABLED */ /*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ /*#define HAL_NAND_MODULE_ENABLED */ /*#define HAL_NOR_MODULE_ENABLED */ /*#define HAL_OPAMP_MODULE_ENABLED */ /*#define HAL_OSPI_MODULE_ENABLED */ -/*#define HAL_OSPI_MODULE_ENABLED */ +#define HAL_OSPI_MODULE_ENABLED /*#define HAL_PCD_MODULE_ENABLED */ /*#define HAL_QSPI_MODULE_ENABLED */ /*#define HAL_QSPI_MODULE_ENABLED */ @@ -94,6 +95,7 @@ /*#define HAL_WWDG_MODULE_ENABLED */ /*#define HAL_EXTI_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED @@ -296,6 +298,10 @@ #include "stm32l4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32l4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + #ifdef HAL_NOR_MODULE_ENABLED #include "stm32l4xx_hal_nor.h" #endif /* HAL_NOR_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index e8da0f73bc79..46a442eaf7b4 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -105,7 +105,6 @@ void HAL_MspInit(void) */ void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) { - if(hdma2d->Instance==DMA2D) { /* USER CODE BEGIN DMA2D_MspInit 0 */ @@ -126,10 +125,8 @@ void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) * @param hdma2d: DMA2D handle pointer * @retval None */ - void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) { - if(hdma2d->Instance==DMA2D) { /* USER CODE BEGIN DMA2D_MspDeInit 0 */ @@ -152,7 +149,6 @@ void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) */ void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) { - if(hdsi->Instance==DSI) { /* USER CODE BEGIN DSI_MspInit 0 */ @@ -173,10 +169,8 @@ void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) * @param hdsi: DSI handle pointer * @retval None */ - void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) { - if(hdsi->Instance==DSI) { /* USER CODE BEGIN DSI_MspDeInit 0 */ @@ -199,7 +193,6 @@ void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) */ void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef* hgfxmmu) { - if(hgfxmmu->Instance==GFXMMU) { /* USER CODE BEGIN GFXMMU_MspInit 0 */ @@ -220,10 +213,8 @@ void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef* hgfxmmu) * @param hgfxmmu: GFXMMU handle pointer * @retval None */ - void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef* hgfxmmu) { - if(hgfxmmu->Instance==GFXMMU) { /* USER CODE BEGIN GFXMMU_MspDeInit 0 */ @@ -246,7 +237,6 @@ void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef* hgfxmmu) */ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) { - if(hltdc->Instance==LTDC) { /* USER CODE BEGIN LTDC_MspInit 0 */ @@ -267,10 +257,8 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) * @param hltdc: LTDC handle pointer * @retval None */ - void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) { - if(hltdc->Instance==LTDC) { /* USER CODE BEGIN LTDC_MspDeInit 0 */ @@ -285,6 +273,137 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) } +/** +* @brief OSPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hospi: OSPI handle pointer +* @retval None +*/ +void HAL_OSPI_MspInit(OSPI_HandleTypeDef* hospi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hospi->Instance==OCTOSPI1) + { + /* USER CODE BEGIN OCTOSPI1_MspInit 0 */ + + /* USER CODE END OCTOSPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_OSPI1_CLK_ENABLE(); + + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + HAL_PWREx_EnableVddIO2(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**OCTOSPI1 GPIO Configuration + PH2 ------> OCTOSPIM_P1_IO4 + PG11 ------> OCTOSPIM_P1_IO5 + PC3 ------> OCTOSPIM_P1_IO6 + PC4 ------> OCTOSPIM_P1_IO7 + PA6 ------> OCTOSPIM_P1_IO3 + PB1 ------> OCTOSPIM_P1_IO0 + PA3 ------> OCTOSPIM_P1_CLK + PA7 ------> OCTOSPIM_P1_IO2 + PA2 ------> OCTOSPIM_P1_NCS + PB0 ------> OCTOSPIM_P1_IO1 + PB2 ------> OCTOSPIM_P1_DQS + */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF3_OCTOSPIM_P1; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF3_OCTOSPIM_P1; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPIM_P1; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_3|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPIM_P1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPIM_P1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPIM_P1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN OCTOSPI1_MspInit 1 */ + + /* USER CODE END OCTOSPI1_MspInit 1 */ + } + +} + +/** +* @brief OSPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hospi: OSPI handle pointer +* @retval None +*/ +void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef* hospi) +{ + if(hospi->Instance==OCTOSPI1) + { + /* USER CODE BEGIN OCTOSPI1_MspDeInit 0 */ + + /* USER CODE END OCTOSPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_OSPI1_CLK_DISABLE(); + + /**OCTOSPI1 GPIO Configuration + PH2 ------> OCTOSPIM_P1_IO4 + PG11 ------> OCTOSPIM_P1_IO5 + PC3 ------> OCTOSPIM_P1_IO6 + PC4 ------> OCTOSPIM_P1_IO7 + PA6 ------> OCTOSPIM_P1_IO3 + PB1 ------> OCTOSPIM_P1_IO0 + PA3 ------> OCTOSPIM_P1_CLK + PA7 ------> OCTOSPIM_P1_IO2 + PA2 ------> OCTOSPIM_P1_NCS + PB0 ------> OCTOSPIM_P1_IO1 + PB2 ------> OCTOSPIM_P1_DQS + */ + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_2); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11); + + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_3|GPIO_PIN_4); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_6|GPIO_PIN_3|GPIO_PIN_7|GPIO_PIN_2); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_2); + + /* USER CODE BEGIN OCTOSPI1_MspDeInit 1 */ + + /* USER CODE END OCTOSPI1_MspDeInit 1 */ + } + +} + /** * @brief UART MSP Initialization * This function configures the hardware resources used in this example @@ -293,7 +412,6 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; if(huart->Instance==USART3) { @@ -302,11 +420,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration + /**USART3 GPIO Configuration PB11 ------> USART3_RX - PB10 ------> USART3_TX + PB10 ------> USART3_TX */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -328,10 +446,8 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) * @param huart: UART handle pointer * @retval None */ - void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) { - if(huart->Instance==USART3) { /* USER CODE BEGIN USART3_MspDeInit 0 */ @@ -339,10 +455,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration + + /**USART3 GPIO Configuration PB11 ------> USART3_RX - PB10 ------> USART3_TX + PB10 ------> USART3_TX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_11|GPIO_PIN_10); @@ -359,15 +475,15 @@ static void HAL_FMC_MspInit(void){ /* USER CODE BEGIN FMC_MspInit 0 */ /* USER CODE END FMC_MspInit 0 */ - GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitTypeDef GPIO_InitStruct ={0}; if (FMC_Initialized) { return; } FMC_Initialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_ENABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 PD0 ------> FMC_D2 @@ -412,9 +528,9 @@ static void HAL_FMC_MspInit(void){ PF12 ------> FMC_A6 PE11 ------> FMC_D8 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_3 - |GPIO_PIN_5|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_15 - |GPIO_PIN_8|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_13 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_3 + |GPIO_PIN_5|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_15 + |GPIO_PIN_8|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_13 |GPIO_PIN_12|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -422,9 +538,9 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_4|GPIO_PIN_1|GPIO_PIN_5 - |GPIO_PIN_7|GPIO_PIN_13|GPIO_PIN_15|GPIO_PIN_14 - |GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_4|GPIO_PIN_1|GPIO_PIN_5 + |GPIO_PIN_7|GPIO_PIN_13|GPIO_PIN_15|GPIO_PIN_14 + |GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 |GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -432,8 +548,8 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_15|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_15|GPIO_PIN_14 |GPIO_PIN_13|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -441,7 +557,7 @@ static void HAL_FMC_MspInit(void){ GPIO_InitStruct.Alternate = GPIO_AF12_FMC; HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_1 + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_1 |GPIO_PIN_2|GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -476,8 +592,8 @@ static void HAL_FMC_MspDeInit(void){ FMC_DeInitialized = 1; /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_DISABLE(); - - /** FMC GPIO Configuration + + /** FMC GPIO Configuration PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 PD0 ------> FMC_D2 @@ -522,21 +638,21 @@ static void HAL_FMC_MspDeInit(void){ PF12 ------> FMC_A6 PE11 ------> FMC_D8 */ - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_3 - |GPIO_PIN_5|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_15 - |GPIO_PIN_8|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_13 + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_3 + |GPIO_PIN_5|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_15 + |GPIO_PIN_8|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_13 |GPIO_PIN_12|GPIO_PIN_11); - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_4|GPIO_PIN_1|GPIO_PIN_5 - |GPIO_PIN_7|GPIO_PIN_13|GPIO_PIN_15|GPIO_PIN_14 - |GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_4|GPIO_PIN_1|GPIO_PIN_5 + |GPIO_PIN_7|GPIO_PIN_13|GPIO_PIN_15|GPIO_PIN_14 + |GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 |GPIO_PIN_8); - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_15|GPIO_PIN_14 + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_15|GPIO_PIN_14 |GPIO_PIN_13|GPIO_PIN_12); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_1 + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_1 |GPIO_PIN_2|GPIO_PIN_0); /* USER CODE BEGIN FMC_MspDeInit 1 */ diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_it.c b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_it.c index d8515c43de70..8c102e725a56 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_it.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_it.c @@ -71,6 +71,7 @@ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ + /* USER CODE BEGIN EV */ /* USER CODE END EV */ diff --git a/bsp/stm32/stm32l4r9-st-eval/board/Kconfig b/bsp/stm32/stm32l4r9-st-eval/board/Kconfig index e29ec26b817c..adc0cc3b8b9a 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/Kconfig +++ b/bsp/stm32/stm32l4r9-st-eval/board/Kconfig @@ -14,6 +14,13 @@ menu "Onboard Peripheral Drivers" select BSP_USING_GFXMMU default n + config BSP_USING_OSPI_FLASH + bool "Enable OctoSPI Flash (MX25LM51245GXDI00)" + select BSP_USING_OSPI + select RT_USING_SFUD + select RT_SFUD_USING_OSPI + default n + menu "Enable Touch" config BSP_USING_TOUCH @@ -102,6 +109,12 @@ menu "On-chip Peripheral Drivers" endif endif + config BSP_USING_OSPI + bool "Enable OSPI BUS" + select RT_USING_OSPI + select RT_USING_SPI + default n + config BSP_USING_SRAM bool "Enable SRAM" select BSP_USING_FMC diff --git a/bsp/stm32/stm32l4r9-st-eval/board/SConscript b/bsp/stm32/stm32l4r9-st-eval/board/SConscript index d67ba57356aa..bfb21f8784b4 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/SConscript +++ b/bsp/stm32/stm32l4r9-st-eval/board/SConscript @@ -18,6 +18,9 @@ if GetDepend(['BSP_USING_TOUCH']): src += Glob('ports/drv_touch.c') src += Glob('ports/drv_touch_ft.c') +if GetDepend(['BSP_USING_OSPI_FLASH']): + src += Glob('ports/drv_ospi_flash.c') + path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] path += [cwd + '/ports/include'] diff --git a/bsp/stm32/stm32l4r9-st-eval/board/board.c b/bsp/stm32/stm32l4r9-st-eval/board/board.c index 179ccf08ae3d..eb878c95eca3 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/board.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/board.c @@ -13,56 +13,59 @@ void SystemClock_Config(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Configure the main internal regulator output voltage - */ - if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) - { - Error_Handler(); - } - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 2; - RCC_OscInitStruct.PLL.PLLN = 30; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; - RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + /** Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 30; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) - { - Error_Handler(); - } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_DSI|RCC_PERIPHCLK_LTDC; - PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; - PeriphClkInit.DsiClockSelection = RCC_DSICLKSOURCE_DSIPHY; - PeriphClkInit.LtdcClockSelection = RCC_LTDCCLKSOURCE_PLLSAI2_DIV2; - PeriphClkInit.PLLSAI2.PLLSAI2Source = RCC_PLLSOURCE_HSE; - PeriphClkInit.PLLSAI2.PLLSAI2M = 2; - PeriphClkInit.PLLSAI2.PLLSAI2N = 8; - PeriphClkInit.PLLSAI2.PLLSAI2P = RCC_PLLP_DIV2; - PeriphClkInit.PLLSAI2.PLLSAI2R = RCC_PLLR_DIV2; - PeriphClkInit.PLLSAI2.PLLSAI2Q = RCC_PLLQ_DIV2; - PeriphClkInit.PLLSAI2.PLLSAI2ClockOut = RCC_PLLSAI2_LTDCCLK; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_OSPI + |RCC_PERIPHCLK_DSI|RCC_PERIPHCLK_LTDC; + PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; + PeriphClkInit.DsiClockSelection = RCC_DSICLKSOURCE_DSIPHY; + PeriphClkInit.OspiClockSelection = RCC_OSPICLKSOURCE_SYSCLK; + PeriphClkInit.LtdcClockSelection = RCC_LTDCCLKSOURCE_PLLSAI2_DIV2; + PeriphClkInit.PLLSAI2.PLLSAI2Source = RCC_PLLSOURCE_HSE; + PeriphClkInit.PLLSAI2.PLLSAI2M = 2; + PeriphClkInit.PLLSAI2.PLLSAI2N = 8; + PeriphClkInit.PLLSAI2.PLLSAI2P = RCC_PLLP_DIV2; + PeriphClkInit.PLLSAI2.PLLSAI2R = RCC_PLLR_DIV2; + PeriphClkInit.PLLSAI2.PLLSAI2Q = RCC_PLLQ_DIV2; + PeriphClkInit.PLLSAI2.PLLSAI2ClockOut = RCC_PLLSAI2_LTDCCLK; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } } diff --git a/bsp/stm32/stm32l4r9-st-eval/board/board.h b/bsp/stm32/stm32l4r9-st-eval/board/board.h index 4552dd794c38..3ff17195940a 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/board.h +++ b/bsp/stm32/stm32l4r9-st-eval/board/board.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-11-5 SummerGift first version * 2019-04-09 jhb + * 2026-09-03 CliffLL modify HEAP_BEGIN for GCC */ #ifndef __BOARD_H__ @@ -26,8 +27,24 @@ extern "C" { #define STM32_SRAM3_START (0x20040000) #define STM32_SRAM3_END (STM32_SRAM3_START + STM32_SRAM3_SIZE * 1024) -#define HEAP_BEGIN STM32_SRAM3_START +#define STM32_SRAM1_SIZE (192) +#define STM32_SRAM1_START (0x20000000U) +#define STM32_SRAM1_END (STM32_SRAM1_START + STM32_SRAM1_SIZE * 1024U) + +#if defined(__ARMCC_VERSION) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#define HEAP_END ((void *)STM32_SRAM1_END) +#elif __ICCARM__ +#pragma section="HEAP" +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_begin("HEAP")) +#define HEAP_END (__segment_begin("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) #define HEAP_END STM32_SRAM3_END +#endif void SystemClock_Config(void); diff --git a/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.icf b/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.icf index f94036f50406..a18dfc5fb3aa 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.icf @@ -22,6 +22,7 @@ define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __I define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; initialize by copy { readwrite }; do not initialize { section .noinit }; @@ -30,4 +31,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM1_region { section .sram }; -place in RAM2_region { readwrite, last block CSTACK}; +place in RAM2_region { readwrite, block HEAP, last block CSTACK}; diff --git a/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct b/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct index 75aad352202c..fabfaff8bfb4 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct @@ -9,7 +9,7 @@ LR_IROM1 0x08000000 0x00200000 { ; load region size_region .ANY (+RO) } - RW_IRAM1 0x20000000 0x00040000 { ; RW data + RW_IRAM1 0x20000000 0x00030000 { ; RW data .ANY (+RW +ZI) } diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_ospi_flash.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_ospi_flash.c new file mode 100644 index 000000000000..90055828a9c7 --- /dev/null +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_ospi_flash.c @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-08-20 CliffLL first version + */ + +#include +#include +#include +#include +#include + +#ifdef BSP_USING_OSPI_FLASH + +#include "dev_spi_flash.h" +#include "dev_spi_flash_sfud.h" + +static rt_err_t mx25lm51245g_read_configuration_register2_reg1(struct rt_ospi_device *device, rt_uint8_t *reg) +{ + rt_ssize_t ret; + + /* 0x718E read configuration register2 reg1 (address 00000000h) */ + rt_uint8_t instruction = 0x71; + struct rt_ospi_message message = { 0 }; + rt_uint16_t ospi_instruction = 0x718E; + uint8_t cr2_reg1[2] = { 0 }; + rt_uint8_t send_buf[5] = { 0 }; + send_buf[0] = instruction; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(reg != RT_NULL); + + if (device->ospi_mode != RT_OSPI_MODE_OFF) + { + /* set message struct */ + message.instruction.content = ospi_instruction; + message.instruction.size = 16; + message.instruction.ospi_lines = 8; + message.instruction.dtrmode = (device->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + + message.address.content = 0; + message.address.size = 32; + message.address.ospi_lines = 8; + message.address.dtrmode = (device->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + + message.alternate_bytes.content = 0; + message.alternate_bytes.size = 0; + message.alternate_bytes.ospi_lines = 0; + message.alternate_bytes.dtrmode = 0; + + message.dummy_cycles = 6; + + message.parent.send_buf = RT_NULL; + message.parent.recv_buf = cr2_reg1; + message.parent.length = (device->ospi_mode == RT_OSPI_MODE_DTR) ? 2 : 1; + message.parent.cs_release = 1; + message.parent.cs_take = 1; + message.ospi_data_lines = 8; + message.ospi_data_dtrmode = (device->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + message.dqs_mode = (device->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + message.parent.next = RT_NULL; + + ret = rt_ospi_transfer_message(device, &message); + if (ret != (rt_ssize_t)message.parent.length) + { + return -RT_EIO; + } + + /* MX25LM51245G returns duplicated register data in OPI-DTR mode */ + if ((device->ospi_mode == RT_OSPI_MODE_DTR) && (cr2_reg1[0] != cr2_reg1[1])) + { + return -RT_EIO; + } + } + else + { + ret = rt_ospi_send_then_recv(device, send_buf, 5, cr2_reg1, 1); + if (ret != 1) + { + return -RT_EIO; + } + } + *reg = cr2_reg1[0]; + + return RT_EOK; +} + +static rt_err_t mx25lm51245g_write_enable(struct rt_ospi_device *device) +{ + rt_ssize_t ret; + struct rt_ospi_message message = { 0 }; + + /* 0x06F9 write enable */ + rt_uint8_t instruction = 0x06; + rt_uint16_t ospi_instruction = 0x06F9; + + if (device->ospi_mode != RT_OSPI_MODE_OFF) + { + /* set message struct */ + message.instruction.content = ospi_instruction; + message.instruction.size = 16; + message.instruction.ospi_lines = 8; + message.instruction.dtrmode = (device->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + + message.address.content = 0; + message.address.size = 0; + message.address.ospi_lines = 0; + message.address.dtrmode = (device->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + + message.alternate_bytes.content = 0; + message.alternate_bytes.size = 0; + message.alternate_bytes.ospi_lines = 0; + message.alternate_bytes.dtrmode = 0; + + message.dummy_cycles = 0; + + message.parent.send_buf = RT_NULL; + message.parent.recv_buf = RT_NULL; + message.parent.length = 0; + message.parent.cs_release = 1; + message.parent.cs_take = 1; + message.ospi_data_lines = 0; + message.ospi_data_dtrmode = (device->ospi_mode == RT_OSPI_MODE_DTR) ? 1 : 0; + message.dqs_mode = 0; + message.parent.next = RT_NULL; + + ret = rt_ospi_transfer_message(device, &message); + } + else + { + ret = rt_ospi_send(device, &instruction, 1); + } + + if (ret <= 0) + { + return -RT_EIO; + } + + return RT_EOK; +} + +static rt_err_t mx25lm51245g_enter_ospi_str_mode(struct rt_ospi_device *device) +{ + rt_uint8_t reg; + rt_err_t result; + rt_ssize_t ret; + struct rt_ospi_message message = { 0 }; + + /* 0x728D write configuration register2 */ + rt_uint8_t instruction = 0x72; + rt_uint16_t ospi_instruction = 0x728D; + + /* write SOPI mode dummy cycles (0x07 set DC 6 cycles) */ + char write_cr2_reg3_buf[6] = { 0 }; + char dtr_cr2_reg3_buf[2] = { 0 }; + write_cr2_reg3_buf[0] = instruction; + write_cr2_reg3_buf[3] = 0x03; + write_cr2_reg3_buf[5] = 0x07; + dtr_cr2_reg3_buf[0] = 0x07; + dtr_cr2_reg3_buf[1] = 0x07; + + /* write configuration register2 reg1 enter ospi-str mode*/ + char write_cr2_reg1_buf[6] = { 0 }; + char dtr_cr2_reg1_buf[2] = { 0 }; + write_cr2_reg1_buf[0] = instruction; + write_cr2_reg1_buf[5] = 0x01; + dtr_cr2_reg1_buf[0] = 0x01; + dtr_cr2_reg1_buf[1] = 0x01; + + result = mx25lm51245g_read_configuration_register2_reg1(device, ®); + if (result != RT_EOK) + { + return result; + } + + if (reg == 0x02) + { + /* ospi-dtr to ospi-str */ + result = mx25lm51245g_write_enable(device); + if (result != RT_EOK) + { + return result; + } + + /* set message struct */ + message.instruction.content = ospi_instruction; + message.instruction.size = 16; + message.instruction.ospi_lines = 8; + message.instruction.dtrmode = 1; + + message.address.content = 0x00000300; + message.address.size = 32; + message.address.ospi_lines = 8; + message.address.dtrmode = 1; + + message.alternate_bytes.content = 0; + message.alternate_bytes.size = 0; + message.alternate_bytes.ospi_lines = 0; + message.alternate_bytes.dtrmode = 0; + + message.dummy_cycles = 0; + + message.parent.send_buf = dtr_cr2_reg3_buf; + message.parent.recv_buf = RT_NULL; + message.parent.length = 2; + message.parent.cs_release = 1; + message.parent.cs_take = 1; + message.ospi_data_lines = 8; + message.ospi_data_dtrmode = 1; + message.dqs_mode = 0; + message.parent.next = RT_NULL; + + ret = rt_ospi_transfer_message(device, &message); + if (ret != message.parent.length) + { + return -RT_EIO; + } + + result = mx25lm51245g_write_enable(device); + if (result != RT_EOK) + { + return result; + } + + message.address.content = 0x00000000; + message.parent.send_buf = dtr_cr2_reg1_buf; + ret = rt_ospi_transfer_message(device, &message); + if (ret != message.parent.length) + { + return -RT_EIO; + } + + rt_thread_mdelay(10); + } + else if (reg == 0x00) + { + /* spi to ospi-str */ + result = mx25lm51245g_write_enable(device); + if (result != RT_EOK) + { + return result; + } + + ret = rt_ospi_send(device, write_cr2_reg3_buf, 6); + if (ret != 6) + { + return -RT_EIO; + } + + result = mx25lm51245g_write_enable(device); + if (result != RT_EOK) + { + return result; + } + + ret = rt_ospi_send(device, write_cr2_reg1_buf, 6); + if (ret != 6) + { + return -RT_EIO; + } + + rt_thread_mdelay(10); + } + + + device->config.dtr_mode = 0; + result = rt_ospi_configure(device, &device->config); + if (result != RT_EOK) + { + return result; + } + device->ospi_mode = RT_OSPI_MODE_STR; + + /* check if flash enter OPI-STR mode */ + result = mx25lm51245g_read_configuration_register2_reg1(device, ®); + if (result != RT_EOK) + { + return result; + } + if (reg != 0x01) + { + return -RT_EIO; + } + + rt_kprintf("flash already enter ospi str mode\n"); + return RT_EOK; +} + +static rt_err_t mx25lm51245g_enter_ospi_dtr_mode(struct rt_ospi_device *device) +{ + rt_uint8_t reg; + rt_err_t result; + rt_ssize_t ret; + struct rt_ospi_message message = { 0 }; + /* 0x728D write configuration register2 */ + rt_uint8_t instruction = 0x72; + rt_uint16_t ospi_instruction = 0x728D; + + /* write SOPI mode dummy cycles (0x07 set DC 6 cycles) */ + char write_cr2_reg3_buf[6] = { 0 }; + write_cr2_reg3_buf[0] = instruction; + write_cr2_reg3_buf[3] = 0x03; + write_cr2_reg3_buf[5] = 0x07; + + /* write configuration register2 reg1 enter ospi-str mode*/ + char write_cr2_reg1_buf[6] = { 0 }; + write_cr2_reg1_buf[0] = instruction; + write_cr2_reg1_buf[5] = 0x02; + + result = mx25lm51245g_read_configuration_register2_reg1(device, ®); + if (result != RT_EOK) + { + return result; + } + + if (reg == 0x01) + { + /* ospi-str to ospi-dtr */ + result = mx25lm51245g_write_enable(device); + if (result != RT_EOK) + { + return result; + } + + /* set message struct */ + message.instruction.content = ospi_instruction; + message.instruction.size = 16; + message.instruction.ospi_lines = 8; + message.instruction.dtrmode = 0; + + message.address.content = 0x00000300; + message.address.size = 32; + message.address.ospi_lines = 8; + message.address.dtrmode = 0; + + message.alternate_bytes.content = 0; + message.alternate_bytes.size = 0; + message.alternate_bytes.ospi_lines = 0; + message.alternate_bytes.dtrmode = 0; + + message.dummy_cycles = 0; + + message.parent.send_buf = write_cr2_reg3_buf + 5; + message.parent.recv_buf = RT_NULL; + message.parent.length = 1; + message.parent.cs_release = 1; + message.parent.cs_take = 1; + message.ospi_data_lines = 8; + message.ospi_data_dtrmode = 0; + message.dqs_mode = 0; + message.parent.next = RT_NULL; + + ret = rt_ospi_transfer_message(device, &message); + if (ret != message.parent.length) + { + return -RT_EIO; + } + + result = mx25lm51245g_write_enable(device); + if (result != RT_EOK) + { + return result; + } + + message.address.content = 0x00000000; + message.parent.send_buf = write_cr2_reg1_buf + 5; + ret = rt_ospi_transfer_message(device, &message); + if (ret != message.parent.length) + { + return -RT_EIO; + } + + rt_thread_mdelay(10); + } + else if (reg == 0x00) + { + /* spi to ospi-dtr */ + result = mx25lm51245g_write_enable(device); + if (result != RT_EOK) + { + return result; + } + + ret = rt_ospi_send(device, write_cr2_reg3_buf, 6); + if (ret != 6) + { + return -RT_EIO; + } + + result = mx25lm51245g_write_enable(device); + if (result != RT_EOK) + { + return result; + } + + ret = rt_ospi_send(device, write_cr2_reg1_buf, 6); + if (ret != 6) + { + return -RT_EIO; + } + + rt_thread_mdelay(10); + } + + + device->config.dtr_mode = 1; + result = rt_ospi_configure(device, &device->config); + if (result != RT_EOK) + { + return result; + } + device->ospi_mode = RT_OSPI_MODE_DTR; + + /* check if flash enter OPI-DTR mode */ + result = mx25lm51245g_read_configuration_register2_reg1(device, ®); + if (result != RT_EOK) + { + return result; + } + if (reg != 0x02) + { + return -RT_EIO; + } + + rt_kprintf("flash already enter ospi dtr mode\n"); + return RT_EOK; +} + +static int rt_hw_ospi_flash_with_sfud_init(void) +{ + return rt_hw_ospi_device_attach("ospi1", "ospi10", mx25lm51245g_enter_ospi_str_mode, mx25lm51245g_enter_ospi_dtr_mode, RT_NULL); +} +INIT_DEVICE_EXPORT(rt_hw_ospi_flash_with_sfud_init); + +#endif/* BSP_USING_OSPI_FLASH */ diff --git a/bsp/stm32/stm32l4r9-st-eval/project.ewp b/bsp/stm32/stm32l4r9-st-eval/project.ewp index be1b40f1ded4..1ea534a78e8b 100644 --- a/bsp/stm32/stm32l4r9-st-eval/project.ewp +++ b/bsp/stm32/stm32l4r9-st-eval/project.ewp @@ -224,13 +224,13 @@ @@ -358,29 +358,33 @@ @@ -1425,29 +1429,33 @@