[FEATURE] Layout: keep ILM pin parasitic capacitance below 50 pF

[RodrigoCAndrade]

[FEATURE] Layout: keep ILM pin parasitic capacitance below 50 pF

1. Technical Objective

The TPS25947 datasheet explicitly requires parasitic capacitance on the ILM pin (U11 pin 9, R21) to stay below 50 pF for stable operation, and requires the trace to be kept away from switching signals. Because the ILM bias current directly controls overcurrent behaviour, this is easy to violate without noticing.

2. Proposed Solution

Layout constraints for U11:

• Place R21 immediately adjacent to pin 9, with the shortest possible return to the device GND pin.
• Same treatment for C18 (ITIMER) and C19 (DVDT).

3. Alternatives Considered

• None. This is a datasheet requirement.

References:

• [1] TPS25947 datasheet, §7.3.6 Analog Load Current Monitor and §8.4.1 Layout Guidelines: https://www.ti.com/lit/ds/symlink/tps25947.pdf