Skip to content

[BUG] TLV76733DRVR thermal margin is insufficient at the annotated 800 mA #7

Description

@RodrigoCAndrade

1. Technical Objective

U20 is a TLV767 in the DRV package (6-pin WSON, 2 × 2 mm). At the load annotated on sheet 3/3 (3.3 V @ 800 mA):

  • V_IN after D3 ≈ 4.6 V under load
  • P_D = (4.6 − 3.3) × 0.8 ≈ 1.04 W

For a 2 × 2 mm WSON with moderate copper (RθJA in the 70–80 °C/W range) that is roughly 80 °C of rise: Tj ≈ 105 °C at 25 °C ambient, and close to thermal shutdown at 50–60 °C ambient.

2. Proposed Solution

  1. Bench-measure worst-case current (LoRa TX at 22 dBm plus Wi-Fi active) before freezing the topology.
  2. If sustained current stays below ~500 mA, keep the LDO but allocate generous copper pour and thermal vias under the pad during layout.
  3. If not, replace the LDO with a buck converter, which removes the 1.3 V linear drop entirely.

3. Alternatives Considered

  • Larger LDO package (HVSSOP DGN, 3 × 3 mm): better RθJA, but the dissipated power is unchanged.

References:

Activity

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Metadata

Metadata

Labels

component: hardwareIssues related to PCB design, BOM, 3D modeling, or circuitry.priority: highSignificant impact on functionality, requiring immediate attention.status: blockedDevelopment halted pending external dependencies, parts arrival, or approvals.type: bugUnexpected behavior, runtime exception, or hardware malfunction.

Projects

No projects

    Milestone

    Relationships

    None yet

    Development

    No branches or pull requests

    Issue actions