ACPI PPTT table missing L1/L2/L3 cache node information on Sky1/CD8180 (CPU frequency reporting correct, cache topology absent)

[perlowja]

Title: ACPI PPTT table missing L1/L2/L3 cache node information on Sky1/CD8180 (CPU frequency reporting correct, cache topology absent)

Summary

Independently reproduced on a second Sky1/CD8180 board (O6N) after seeing the same issue reported by the community on Orange Pi 6 Plus (Sky1-Linux/linux-sky1#33, credit to the original reporter). Under ACPI boot, lscpu/hwloc/lstopo report correct CPU frequencies but show no L1d/L1i/L2/L3 cache information at all — the cache category headers appear but every field is empty. Reported separately on Device Tree boot, cache info is present but CPU frequencies are wrong instead — the two boot paths appear to expose complementary, incomplete subsets of topology info.

Hardware

• Board: O6N (CIX Sky1 dev board), CD8180
• CPU: 8x Cortex-A720 (CPU part 0xd81) + 4x Cortex-A520 (CPU part 0xd80)
• Firmware: ACPI (SystemReady), boot via rEFInd/systemd-boot, no DTB
• Kernel: mainline v7.2-rc5 + NCZ/cixtech 2026q2 driver patch set

Evidence

lscpu --caches:

NAME ONE-SIZE ALL-SIZE WAYS TYPE        LEVEL SETS PHY-LINE COHERENCY-SIZE
L1d                         Data            1
L1i                         Instruction     1
L2                          Unified         2
L3                          Unified         3

All size/ways/sets/line fields empty — the cache levels are recognized as existing but with no populated data.

lscpu -e (excerpt):

CPU NODE SOCKET CORE L1d:L1i:L2:L3 ONLINE    MAXMHZ   MINMHZ       MHZ
  0    0      0    0 0:0:0:0          yes 2600.0000 800.0000 2600.0000
  1    0      0    1 0:0:0:0          yes 2600.0000 800.0000 2600.0000
  2    0      0    0 0:0:0            yes 1800.0000 800.0000 1800.0000

Frequencies (2.6GHz A720 / 1.8GHz A520) match the board's published spec exactly and are reported correctly under ACPI. Cache index columns are all zero/placeholder.

The firmware does provide a PPTT table (/sys/firmware/acpi/tables/PPTT, signature confirmed, OEM ID CIXTEK), but it's only 396 bytes — small for a 12-core SoC with a proper multi-level, cluster-aware cache topology (processor hierarchy nodes + cache nodes for L1i/L1d per core plus shared L2/L3 typically runs substantially larger). This is consistent with the table describing processor topology but omitting cache node entries or cache references.

Question

Is this a firmware PPTT completeness gap (missing cache type structures / cache-reference links in the processor hierarchy nodes), or is the kernel-side ACPI PPTT parser not consuming something the table does provide? Given the DTB path reportedly has cache info but wrong frequencies (the inverse problem), this looks like two independent, boot-path-specific gaps rather than one shared root cause. Happy to pull the raw PPTT table dump if useful for review.

Cross-reference: github.com/Sky1-Linux/linux-sky1 issue #33 (Orange Pi 6 Plus, same symptom, unanswered)