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CUDA PTX inline asm listing for .func block fails internal exception for -e stmt_html #9397

Description

@antonysigma

Description

Related to #9196 : Sometimes, cos/sin functions are lowered to an internal .func NVPTX block having function name *trig_reduction* containing nested braces. The previous bugfix did not cover this corner case because it is .func, not .visible .entry.

Example .func nvptx code triggering the failure

const .align 8 .b8 __cudart_i2opi_d[144] = {...};
.const .align 8 .b8 __cudart_sin_cos_coeffs[128] = {...};
                                        // -- Begin function __internal_trig_reduction_slowpathd
                                        // @__internal_trig_reduction_slowpathd
.func  (.param .b64 func_retval0) __internal_trig_reduction_slowpathd(
    .param .b64 __internal_trig_reduction_slowpathd_param_0,
    .param .b64 __internal_trig_reduction_slowpathd_param_1
)
{

...

// begin inline asm
    {
    .reg .u32 r0, r1, r2, r3, alo, ahi, blo, bhi, clo, chi;
    mov.b64         {alo,ahi}, %rd51;    
    mov.b64         {blo,bhi}, %rd52;    
    mov.b64         {clo,chi}, %rd102;    
    mad.lo.cc.u32   r0, alo, blo, clo;
    madc.hi.cc.u32  r1, alo, blo, chi;
    madc.hi.u32     r2, alo, bhi,   0;
    mad.lo.cc.u32   r1, alo, bhi,  r1;
    madc.hi.cc.u32  r2, ahi, blo,  r2;
    madc.hi.u32     r3, ahi, bhi,   0;
    mad.lo.cc.u32   r1, ahi, blo,  r1;
    madc.lo.cc.u32  r2, ahi, bhi,  r2;
    addc.u32        r3,  r3,   0;     
    mov.b64         %rd49, {r0,r1};      
    mov.b64         %rd102, {r2,r3};      
    }
    // end inline asm
...
}

Reproducing case

const .align 8 .b8 __cudart_i2opi_d[144] = {...};
.const .align 8 .b8 __cudart_sin_cos_coeffs[128] = {...};
                                        // -- Begin function __internal_trig_reduction_slowpathd
                                        // @__internal_trig_reduction_slowpathd
.func  (.param .b64 func_retval0) __internal_trig_reduction_slowpathd(
    .param .b64 __internal_trig_reduction_slowpathd_param_0,
    .param .b64 __internal_trig_reduction_slowpathd_param_1
)
{

...

// begin inline asm
    {
    .reg .u32 r0, r1, r2, r3, alo, ahi, blo, bhi, clo, chi;
    mov.b64         {alo,ahi}, %rd51;    
    mov.b64         {blo,bhi}, %rd52;    
    mov.b64         {clo,chi}, %rd102;    
    mad.lo.cc.u32   r0, alo, blo, clo;
    madc.hi.cc.u32  r1, alo, blo, chi;
    madc.hi.u32     r2, alo, bhi,   0;
    mad.lo.cc.u32   r1, alo, bhi,  r1;
    madc.hi.cc.u32  r2, ahi, blo,  r2;
    madc.hi.u32     r3, ahi, bhi,   0;
    mad.lo.cc.u32   r1, ahi, blo,  r1;
    madc.lo.cc.u32  r2, ahi, bhi,  r2;
    addc.u32        r3,  r3,   0;     
    mov.b64         %rd49, {r0,r1};      
    mov.b64         %rd102, {r2,r3};      
    }
    // end inline asm
...
}

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x86_64-gnu-linux-cuda

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