From e4ceab372fae004b7a160bcda5a751991ed3f196 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:37 +0530 Subject: [PATCH 01/36] FROMLIST: ARM: dts: qcom: sdx55: Fix PCIe wake GPIO The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-1-2744251b1181@oss.qualcomm.com/ --- arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts index 082f7ed1a01fb..302c88c479604 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts @@ -251,7 +251,7 @@ &pcie_rc { perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie_default>; pinctrl-names = "default"; From e06d1a0bb3f8f18c3a24501aa5f8b0f04b98d7e8 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:38 +0530 Subject: [PATCH 02/36] FROMLIST: arm64: dts: qcom: msm8996: Fix PCIe wake GPIO The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-2-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index d55e4075040ff..5b42c266557ab 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -192,7 +192,7 @@ &pcie0 { perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&pm8994_l28>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 0386636a29f05..337db4db9895a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -280,7 +280,7 @@ vdda-supply = <&vreg_l28a_0p925>; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; }; &pcie_phy { From 9c0f24a1aa2bd8a18ad66ffd4a1101e62f43ca23 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:39 +0530 Subject: [PATCH 03/36] FROMLIST: arm64: dts: qcom: sdm845: Fix PCIe wake GPIO The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-3-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 5147d6d3cc26b..cd3c1cf047f9c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -582,7 +582,7 @@ &pcie0 { status = "okay"; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 134 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&pcie0_3p3v_dual>; From b2b3a73f5adf6e16d2b4865ab0e7a4ba246624f7 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:40 +0530 Subject: [PATCH 04/36] FROMLIST: arm64: dts: qcom: sc8180x: Fix PCIe wake GPIO The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-4-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 +- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 08d0784d0cbb8..acea9b1460391 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -464,7 +464,7 @@ &pcie3 { perst-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 180 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie3_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index 93de9fe918ebd..1b9f239931d9a 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -558,7 +558,7 @@ &pcie1 { perst-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 177 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 177 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; From 2ce17a6bd564091179d6a8bdf5bd4dfbd4639343 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:41 +0530 Subject: [PATCH 05/36] FROMLIST: arm64: dts: qcom: sm8150: Fix PCIe wake GPIO The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-5-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index acdba79612aa8..a9840c23b8c2a 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1896,7 +1896,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; - wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; From 14ed4c39b8cbc2b17ba1966c659cc1499ca93630 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:42 +0530 Subject: [PATCH 06/36] FROMLIST: arm64: dts: qcom: sm8250: Fix PCIe wake GPIO The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-6-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 50dd11432bb2e..defbe6608efdf 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2197,7 +2197,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 81 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; @@ -2324,7 +2324,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; @@ -2451,7 +2451,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; From d2a6c26a1263d74c90cb278de4d578acb0ed38dc Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:43 +0530 Subject: [PATCH 07/36] FROMLIST: arm64: dts: qcom: sm8350: Fix PCIe wake GPIO The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-7-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 24a8c91e9f70f..95733ccca9abe 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -494,7 +494,7 @@ pinctrl-0 = <&pcie0_default_state>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -508,7 +508,7 @@ &pcie1 { perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; From c94aab1048d0e4ca10217ef26f753569773d16df Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:44 +0530 Subject: [PATCH 08/36] FROMLIST: arm64: dts: qcom: sm8450: Fix PCIe wake GPIO The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-8-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index cdaff13325ccb..a8f2c412e687e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2035,7 +2035,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; @@ -2197,7 +2197,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; From b823b9187a38e7b2d736f40607bdce85e4030d03 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:45 +0530 Subject: [PATCH 09/36] FROMLIST: arm64: dts: qcom: sm8550: Fix PCIe wake GPIO The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-9-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 +- arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 2 +- arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 2 +- 6 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi index e6ac529e6b721..ca32e9eda5d44 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -336,7 +336,7 @@ &pcie0 { perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -349,7 +349,7 @@ &pcie1 { perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index b5d7f0cd443a1..d3b31f654a135 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1003,7 +1003,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -1037,7 +1037,7 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 38f2928f23cc3..5a35eb659aea7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -739,7 +739,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -756,7 +756,7 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index a3f4200a1145d..a050ad18123de 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -858,7 +858,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts index b4ef40ae2cd95..8b672939791a9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -510,7 +510,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index d90dc7b37c4a7..8a484489ad731 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -584,7 +584,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; From c97f9c06f72f76a9306ca60a838cbbb5f4fa3320 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:46 +0530 Subject: [PATCH 10/36] FROMLIST: arm64: dts: qcom: sm8650: Fix PCIe wake GPIO The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-10-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts index 0dc994f4e48d9..2123312d88f6b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts @@ -1074,7 +1074,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -1108,7 +1108,7 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 87d7190dc991b..92b10ba13710b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -942,7 +942,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -976,7 +976,7 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index c67bbace27439..8dc24db239bb5 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -642,7 +642,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -659,7 +659,7 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 9e790cf44804d..70b3f0c4b6e3e 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -893,7 +893,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; From b24210456935089e930e738be881298ce4593acb Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:47 +0530 Subject: [PATCH 11/36] FROMLIST: arm64: dts: qcom: sm8750: Fix PCIe wake GPIO The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-11-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index 9b8c453b6fe2b..dd939dc12bd51 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -974,7 +974,7 @@ }; &pcieport0 { - wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>; reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; wifi@0 { From ba1c950a33194d9ab658727081e399e3ab87c30a Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:49 +0530 Subject: [PATCH 12/36] FROMLIST: arm64: dts: qcom: sar2130p: Fix PCIe wake GPIO The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-13-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts index 74778a5b19ba6..71a09e76b3592 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts +++ b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts @@ -358,7 +358,7 @@ &pcie0 { perst-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; From 8d4bd19ecaa60b81940a15b8aa7e844bc69e996d Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:50 +0530 Subject: [PATCH 13/36] FROMLIST: arm64: dts: qcom: monaco: Fix PCIe wake GPIO The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-14-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi b/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi index 2434d1f9f58ba..92822ba5f48c5 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi @@ -734,12 +734,12 @@ &pcieport0 { reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; }; &pcieport1 { reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 21 GPIO_ACTIVE_LOW>; }; &pmm8620au_0_gpios { diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 4e2fb94a147c5..842aa6743ef75 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -597,7 +597,7 @@ &pcieport0 { reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; }; &pcie0_phy { @@ -617,7 +617,7 @@ &pcieport1 { reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 21 GPIO_ACTIVE_LOW>; }; &pcie1_phy { From ec9563cfabafd2a0182adf443ebf32714532cbbc Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:51 +0530 Subject: [PATCH 14/36] FROMLIST: arm64: dts: qcom: lemans: Fix PCIe wake GPIO The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-15-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 4 ++-- arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index eec8b8a1d9ae8..255718355fcaf 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -834,7 +834,7 @@ &pcie0 { perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -851,7 +851,7 @@ &pcie1 { perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index d66b33a1812ca..ca3031dc5cef8 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -969,7 +969,7 @@ &pcie0 { perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; @@ -979,7 +979,7 @@ &pcie1 { perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; From 2f009ea0a60e7d52f7233ca2b3be7afd35d400a5 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:52 +0530 Subject: [PATCH 15/36] FROMLIST: arm64: dts: qcom: sa8540p-ride: Fix PCIe wake The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-16-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 44177e9b64b52..702ae4cd3d0c1 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -367,7 +367,7 @@ <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>; perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie2a_default>; @@ -388,7 +388,7 @@ <0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>; perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie3a_default>; From a9d09df264434a81ade743d5c7fab8c51d29281c Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:53 +0530 Subject: [PATCH 16/36] FROMLIST: arm64: dts: qcom: kodiak: Fix PCIe wake GPIO The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-17-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts index c8494a9254fcd..ba01677f64cb3 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts @@ -550,7 +550,7 @@ &pcie0 { perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; pinctrl-names = "default"; From 36e725624ea0c84c4c8570bb8a25d5da86bc8e18 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:54 +0530 Subject: [PATCH 17/36] FROMLIST: arm64: dts: qcom: talos: Fix PCIe wake GPIO The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20260611-wake-v2-18-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 2 +- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 570ce3ddc4b0c..ddf94d6b39ca9 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -524,7 +524,7 @@ &pcie { perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index c5da6858b74b1..71095874d65e9 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -443,7 +443,7 @@ &pcie { perst-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie_default_state>; pinctrl-names = "default"; From 1b6f063664f5452900ec14bdfb2e1421e1c60479 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:55 +0530 Subject: [PATCH 18/36] FROMLIST: arm64: dts: qcom: lemans: Move PCIe phy and GPIOs The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys from the controller to pcieport0 and pcieport1. Add the missing pcieport1 label to the pcie1 root port node to allow board-level overrides. Move perst-gpios/wake-gpios from the &pcie0/&pcie1 controller overrides to the respective &pcieport0/ &pcieport1 nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-19-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 6 +++--- arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/lemans.dtsi | 8 ++++---- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 255718355fcaf..3a1c9431f4ebb 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause +&pcieport1 {&pcieport0 {// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved. */ @@ -833,7 +833,7 @@ }; &pcie0 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -850,7 +850,7 @@ }; &pcie1 { - perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index ca3031dc5cef8..170be40eebeb8 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause +};// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023, Linaro Limited */ @@ -968,7 +968,7 @@ }; &pcie0 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +&pcieport1 { wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -978,8 +978,8 @@ }; &pcie1 { - perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +&pcieport0 { pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 5cff6bb90f407..b49bf49b0d052 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause + phys = <&pcie1_phy>; phys = <&pcie0_phy>;// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023, Linaro Limited * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. @@ -8990,7 +8990,7 @@ power-domains = <&gcc PCIE_0_GDSC>; phys = <&pcie0_phy>; - phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; eq-presets-16gts = /bits/ 8 <0x55 0x55>; @@ -9048,7 +9048,7 @@ reset-names = "core"; power-domains = <&gcc PCIE_0_GDSC>; phys = <&pcie0_phy>; - phy-names = "pciephy"; + num-lanes = <2>; linux,pci-domain = <0>; @@ -9170,7 +9170,7 @@ status = "disabled"; - pcie@0 { + pcieport1: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; From 2694323e6d209543d1f528f8b847b054b2593dcb Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:56 +0530 Subject: [PATCH 19/36] FROMLIST: arm64: dts: qcom: msm8998: Move PCIe phy and The PCIe phy reference and the perst GPIO property are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys, phy-names, and perst-gpios from the controller to pcie0_port0, adding a label to this node to allow board-level overrides, and renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-20-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 5c75fba16ce2c..7322e7803d464 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -928,8 +928,8 @@ #address-cells = <3>; #size-cells = <2>; num-lanes = <1>; - phys = <&pcie_phy>; - phy-names = "pciephy"; + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + phys = <&pcie_phy>; status = "disabled"; ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>, @@ -969,9 +969,9 @@ power-domains = <&gcc PCIE_0_GDSC>; iommu-map = <0x100 &anoc1_smmu 0x1480 1>; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - pcie@0 { + + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; From 5c4ea2e5f77c36cc341aad243ac672d5dd40cf2d Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:57 +0530 Subject: [PATCH 20/36] FROMLIST: arm64: dts: qcom: qcs404: Move PCIe phy and GPIOs The PCIe phy reference and the perst GPIO property are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0, adding a label to this node to allow board-level overrides. Move perst-gpios from the &pcie controller override to &pcie0_port0 in the board file, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-21-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/qcs404.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index a22b4501ce1ef..b1c1b90b2b519 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +&pcie0_port0 {// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018, Linaro Limited */ @@ -101,7 +101,7 @@ &pcie { status = "okay"; - perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&perst_state>; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 4328c1dda898c..c491a8adfec88 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1518,11 +1518,11 @@ "ahb"; phys = <&pcie_phy>; - phy-names = "pciephy"; + phys = <&pcie_phy>; status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; From f9e767c3c62a2193a99af7e1e98b5997b94e0f42 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:58 +0530 Subject: [PATCH 21/36] FROMLIST: arm64: dts: qcom: qcs8550: Move PCIe GPIOs to The perst/wake GPIO properties are per root port and belong in the root port node, not in the RC controller node. Move perst-gpios/ wake-gpios from the &pcie0/&pcie1 controller overrides to the respective &pcieport0/&pcie1_port0 nodes, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-22-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi index ca32e9eda5d44..d70c35186ba26 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause +&pcie1_port0 {&pcieport0 {// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ @@ -335,7 +335,7 @@ }; &pcie0 { - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -348,7 +348,7 @@ }; &pcie1 { - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; From 3f956c8f549aabe3c3a7eda15fa4cfb68d45a544 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:59 +0530 Subject: [PATCH 22/36] FROMLIST: arm64: dts: qcom: sa8295p: Move PCIe GPIOs to The perst/wake GPIO properties are per root port and belong in the root port node, not in the RC controller node. Move perst-gpios/ wake-gpios from the &pcie2a, &pcie3a, &pcie3b, and &pcie4 controller overrides to the respective &pcie2a_port0, &pcie3a_port0, &pcie3b_port0, and &pcie4_port0 nodes, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-23-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index 64e59299672cb..d035de2819663 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause +&pcie4_port0 {&pcie3b_port0 {&pcie3a_port0 {&pcie2a_port0 {// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. * Copyright (c) 2022, Linaro Limited @@ -461,7 +461,7 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -480,7 +480,7 @@ &pcie3a { num-lanes = <2>; - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -497,7 +497,7 @@ }; &pcie3b { - perst-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -514,7 +514,7 @@ }; &pcie4 { - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; From 245a520ad9cec8c51bbeea01a04ddc2840cf9782 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:00 +0530 Subject: [PATCH 23/36] FROMLIST: arm64: dts: qcom: sa8540p: Move PCIe GPIOs to The perst/wake GPIO properties are per root port and belong in the root port node, not in the RC controller node. Move perst-gpios/ wake-gpios from the &pcie2a and &pcie3a controller overrides to the respective &pcie2a_port0 and &pcie3a_port0 nodes, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-24-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 702ae4cd3d0c1..97917da4961f9 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause +&pcie3a_port0 {&pcie2a_port0 {// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. * Copyright (c) 2022, Linaro Limited @@ -366,7 +366,7 @@ <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>, <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>; - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -387,7 +387,7 @@ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>, <0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>; - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; From 110330a859d6fc140ff0464fabcf5784747c7c1c Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:01 +0530 Subject: [PATCH 24/36] FROMLIST: arm64: dts: qcom: sar2130p: Move PCIe phy and The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcieport0 and newly labeled pcie1_port0, allowing board-level overrides. Move perst-gpios/wake-gpios from the &pcie0 controller override to &pcieport0 in the board file, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-25-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts | 4 ++-- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts index 71a09e76b3592..287c302782a63 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts +++ b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause + reset-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2024, Linaro Limited */ @@ -357,7 +357,7 @@ }; &pcie0 { - perst-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index d65ad0df68652..a604db93e1c48 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -1338,7 +1338,7 @@ power-domains = <&gcc PCIE_0_GDSC>; phys = <&pcie0_phy>; - phy-names = "pciephy"; + phys = <&pcie0_phy>; status = "disabled"; @@ -1465,11 +1465,11 @@ power-domains = <&gcc PCIE_1_GDSC>; phys = <&pcie1_phy>; - phy-names = "pciephy"; + phys = <&pcie1_phy>; status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; From 773449cf015e925b744da9b2e9975deddcfcb777 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:02 +0530 Subject: [PATCH 25/36] FROMLIST: arm64: dts: qcom: sc8180x: Move PCIe phy and The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0, pcie1_port0, pcie2_port0, and pcie3_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-26-2744251b1181@oss.qualcomm.com/ --- .../boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 4 ++-- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 4 ++-- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 24 +++++++++---------- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index acea9b1460391..0e64acc14ae86 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -463,8 +463,8 @@ }; &pcie3 { - perst-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; +&pcie3_port0 { pinctrl-0 = <&pcie3_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index 1b9f239931d9a..1b7577ecfa7f6 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -557,8 +557,8 @@ }; &pcie1 { - perst-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 177 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; +&pcie1_port0 { pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 85c2afcb417de..9296bda3a9c08 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1774,13 +1774,13 @@ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie0_phy>; - phy-names = "pciephy"; + phys = <&pcie0_phy>; + dma-coherent; status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1893,13 +1893,13 @@ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie3_phy>; - phy-names = "pciephy"; + phys = <&pcie3_phy>; + dma-coherent; status = "disabled"; - pcie@0 { + pcie3_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2013,13 +2013,13 @@ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie1_phy>; - phy-names = "pciephy"; + phys = <&pcie1_phy>; + dma-coherent; status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2133,13 +2133,13 @@ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie2_phy>; - phy-names = "pciephy"; + phys = <&pcie2_phy>; + dma-coherent; status = "disabled"; - pcie@0 { + pcie2_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; From 20361c45fd3f1060d90efe0c9de9babdcb244267 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:03 +0530 Subject: [PATCH 26/36] FROMLIST: arm64: dts: qcom: sc8280xp: Move PCIe phy and The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcie2a_port0, pcie2b_port0, pcie3a_port0, pcie3b_port0, and pcie4_port0 nodes. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-27-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts | 6 +++--- .../boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts | 8 ++++---- .../boot/dts/qcom/sc8280xp-microsoft-blackrock.dts | 6 +++--- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 +++++----- 6 files changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 490e970c54a24..008eec10b41cc 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause +&pcie4_port0 {&pcie3a_port0 {&pcie2a_port0 {// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. * Copyright (c) 2022, Linaro Limited @@ -634,7 +634,7 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&vreg_nvme>; @@ -653,7 +653,7 @@ }; &pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&vreg_wwan>; @@ -674,7 +674,7 @@ &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&vreg_wlan>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts index 0374251d33291..40016b3e54bd1 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;&pcie2a_port0 {// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. * Copyright (c) 2022, Linaro Limited @@ -745,7 +745,7 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&vreg_nvme>; @@ -766,7 +766,7 @@ &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&vreg_wlan>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 637430719e6d7..5fbd3cc74b54a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;&pcie3a_port0 {&pcie2a_port0 {// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. * Copyright (c) 2022, Linaro Limited @@ -939,7 +939,7 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&vreg_nvme>; @@ -958,7 +958,7 @@ }; &pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&vreg_wwan>; @@ -979,7 +979,7 @@ &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&vreg_wlan>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index aeed3ef152eba..0efc44262aeff 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;&pcie3a_port0 {&pcie2a_port0 {// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2024, Jérôme de Bretagne */ @@ -492,7 +492,7 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&vreg_nvme>; @@ -511,7 +511,7 @@ }; &pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&vreg_wwan>; @@ -532,7 +532,7 @@ &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&vreg_wlan>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index a40dccd70dfda..0eb751575d254 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;&pcie2a_port0 {// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. * Copyright (c) 2022, Linaro Limited @@ -630,7 +630,7 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&vreg_nvme>; @@ -651,7 +651,7 @@ &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&vreg_wlan>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index d89938e17e093..dcb655dabe8ab 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2215,7 +2215,7 @@ required-opps = <&rpmhpd_opp_nom>; phys = <&pcie4_phy>; - phy-names = "pciephy"; + phys = <&pcie4_phy>; status = "disabled"; @@ -2326,7 +2326,7 @@ required-opps = <&rpmhpd_opp_nom>; phys = <&pcie3b_phy>; - phy-names = "pciephy"; + phys = <&pcie3b_phy>; status = "disabled"; @@ -2437,7 +2437,7 @@ required-opps = <&rpmhpd_opp_nom>; phys = <&pcie3a_phy>; - phy-names = "pciephy"; + phys = <&pcie3a_phy>; status = "disabled"; @@ -2551,7 +2551,7 @@ required-opps = <&rpmhpd_opp_nom>; phys = <&pcie2b_phy>; - phy-names = "pciephy"; + phys = <&pcie2b_phy>; status = "disabled"; @@ -2662,7 +2662,7 @@ required-opps = <&rpmhpd_opp_nom>; phys = <&pcie2a_phy>; - phy-names = "pciephy"; + phys = <&pcie2a_phy>; status = "disabled"; From 57dc0b0ecc03b9db19c0f4b1d815fd76e84f6a1f Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:04 +0530 Subject: [PATCH 27/36] FROMLIST: arm64: dts: qcom: sdm845: Move PCIe phy and GPIOs The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0 and pcie1_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-28-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 6 +++--- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 6 +++--- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index cd3c1cf047f9c..78867e4bd9386 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +&pcie0_port0 {// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2019, Linaro Ltd. */ @@ -581,7 +581,7 @@ &pcie0 { status = "okay"; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 134 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&pcie0_3p3v_dual>; @@ -599,7 +599,7 @@ &pcie1 { status = "okay"; - perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; +&pcie1_port0 { pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 63d2993536ade..335b46e2fddb6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +&pcie1_port0 {&pcie0_port0 {// SPDX-License-Identifier: GPL-2.0 /* * SDM845 MTP board device tree source * @@ -511,7 +511,7 @@ }; &pcie0 { - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -527,7 +527,7 @@ }; &pcie1 { - perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 13c9515260ef1..6288bd403f987 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2390,11 +2390,11 @@ power-domains = <&gcc PCIE_0_GDSC>; phys = <&pcie0_phy>; - phy-names = "pciephy"; + phys = <&pcie0_phy>; status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2520,11 +2520,11 @@ power-domains = <&gcc PCIE_1_GDSC>; phys = <&pcie1_phy>; - phy-names = "pciephy"; + phys = <&pcie1_phy>; status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; From e5abb7daf3a532c08ce63296149cd3eb2a08033e Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:05 +0530 Subject: [PATCH 28/36] FROMLIST: arm64: dts: qcom: sm8150: Move PCIe phy and GPIOs The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios from the controller to pcie0_port0 and pcie1_port0, adding labels to these nodes to allow board-level overrides, and renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-29-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a9840c23b8c2a..5c86fd2bdaaf1 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause + phys = <&pcie1_phy>; phys = <&pcie0_phy>;// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2019, Linaro Limited @@ -1893,9 +1893,9 @@ power-domains = <&gcc PCIE_0_GDSC>; phys = <&pcie0_phy>; - phy-names = "pciephy"; + reset-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -1903,7 +1903,7 @@ status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2013,7 +2013,7 @@ phys = <&pcie1_phy>; phy-names = "pciephy"; - perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; + enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; @@ -2021,7 +2021,7 @@ status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; From c3f501db64d598011443ee8e91577bbe1d67310c Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:06 +0530 Subject: [PATCH 29/36] FROMLIST: arm64: dts: qcom: sm8250: Move PCIe phy and GPIOs The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios from the controller to the existing pcieport0 and newly labeled pcie1_port0 and pcie2_port0, allowing board-level overrides. Rename perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-30-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index defbe6608efdf..a57c7c2269e52 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause + phys = <&pcie2_phy>; phys = <&pcie1_phy>; phys = <&pcie0_phy>;// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. */ @@ -2196,7 +2196,7 @@ phys = <&pcie0_phy>; phy-names = "pciephy"; - perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 81 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -2323,7 +2323,7 @@ phys = <&pcie1_phy>; phy-names = "pciephy"; - perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -2332,7 +2332,7 @@ status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2450,7 +2450,7 @@ phys = <&pcie2_phy>; phy-names = "pciephy"; - perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -2459,7 +2459,7 @@ status = "disabled"; - pcie@0 { + pcie2_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; From 03b284d9b98f8686510fb4f88c90932c673a831d Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:07 +0530 Subject: [PATCH 30/36] FROMLIST: arm64: dts: qcom: sm8350: Move PCIe phy and GPIOs The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0 and pcie1_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board file, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-31-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 95733ccca9abe..a030f54f4fc60 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause +&pcie1_port0 {&pcie0_port0 {// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2020-2021, Linaro Limited */ @@ -493,7 +493,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; status = "okay"; @@ -507,7 +507,7 @@ }; &pcie1 { - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index fc4ce9d4977e8..09a97fd8d20fb 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1584,11 +1584,11 @@ power-domains = <&gcc PCIE_0_GDSC>; phys = <&pcie0_phy>; - phy-names = "pciephy"; + phys = <&pcie0_phy>; status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1693,11 +1693,11 @@ power-domains = <&gcc PCIE_1_GDSC>; phys = <&pcie1_phy>; - phy-names = "pciephy"; + phys = <&pcie1_phy>; status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; From eeab860877a022b9238fe2831e275ea8c4b7e103 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:08 +0530 Subject: [PATCH 31/36] FROMLIST: arm64: dts: qcom: sm8450: Move PCIe phy and GPIOs The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios from the controller to the existing pcieport0 and newly labeled pcie1_port0, allowing board-level overrides. Rename perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-32-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index a8f2c412e687e..b2f17fb3184fb 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause + phys = <&pcie1_phy>; phys = <&pcie0_phy>;// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2021, Linaro Limited */ @@ -2034,7 +2034,7 @@ phys = <&pcie0_phy>; phy-names = "pciephy"; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -2196,7 +2196,7 @@ phys = <&pcie1_phy>; phy-names = "pciephy"; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -2252,7 +2252,7 @@ }; }; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; From f2de454c6643349b70ebbd9d152f558efd7b1684 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:09 +0530 Subject: [PATCH 32/36] FROMLIST: arm64: dts: qcom: sm8550: Move PCIe phy and GPIOs The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcieport0 and newly labeled pcie1_port0, allowing board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-33-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +++--- 6 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index d3b31f654a135..1652814512bf0 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause +&pcie1_port0 { reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2024 Linaro Limited */ @@ -1003,8 +1003,8 @@ }; &pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -1038,7 +1038,7 @@ &pcie1 { wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 5a35eb659aea7..0c75e4140c436 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause +&pcie1_port0 {&pcieport0 {// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2022, Linaro Limited */ @@ -740,7 +740,7 @@ &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; @@ -757,7 +757,7 @@ &pcie1 { wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index a050ad18123de..59aac4be5f108 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023 Linaro Limited */ @@ -858,8 +858,8 @@ }; &pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts index 8b672939791a9..9020d47dc9a70 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -510,8 +510,8 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; +&pcieport0 { pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index 8a484489ad731..a9a56e69787e6 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause +&pcieport0 {// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023, Linaro Limited */ @@ -585,7 +585,7 @@ &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 7a56d2625014c..f7d403306558b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2018,7 +2018,7 @@ power-domains = <&gcc PCIE_0_GDSC>; phys = <&pcie0_phy>; - phy-names = "pciephy"; + phys = <&pcie0_phy>; operating-points-v2 = <&pcie0_opp_table>; @@ -2185,7 +2185,7 @@ power-domains = <&gcc PCIE_1_GDSC>; phys = <&pcie1_phy>; - phy-names = "pciephy"; + phys = <&pcie1_phy>; operating-points-v2 = <&pcie1_opp_table>; @@ -2237,7 +2237,7 @@ }; }; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; From 08aa641767033e53b8687575217daae4a4293091 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:10 +0530 Subject: [PATCH 33/36] FROMLIST: arm64: dts: qcom: talos: Move PCIe phy and GPIOs The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys from the controller to pcie_port0, and move perst-gpios/wake-gpios from the &pcie controller overrides to the &pcie_port0 node in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-34-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 4 ++-- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/talos.dtsi | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index ddf94d6b39ca9..d73418f1c63c7 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause +&pcie_port0 {// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ @@ -523,7 +523,7 @@ }; &pcie { - perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie_default_state>; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index 71095874d65e9..4a3fb1801b413 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause +&pcie_port0 {// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ @@ -442,7 +442,7 @@ }; &pcie { - perst-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie_default_state>; diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 3dd9fb230fee9..01d88c1b2efae 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -1395,7 +1395,7 @@ power-domains = <&gcc PCIE_0_GDSC>; phys = <&pcie_phy>; - phy-names = "pciephy"; + phys = <&pcie_phy>; max-link-speed = <2>; From e51a717fba54f576fe3203590213c2c96930f303 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:11 +0530 Subject: [PATCH 34/36] FROMLIST: arm64: dts: qcom: sm8650: Move PCIe phy and GPIOs The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcieport0 and pcie1_port0, allowing board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-35-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650.dtsi | 4 ++-- 5 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts index 2123312d88f6b..bc1cb5e97ddfc 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause +&pcie1_port0 { reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023, Linaro Limited * Copyright (c) 2025, Kancy Joe @@ -1074,8 +1074,8 @@ }; &pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -1109,7 +1109,7 @@ &pcie1 { wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 92b10ba13710b..387fe446b9a56 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause +&pcie1_port0 { reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2024, Linaro Limited */ @@ -942,8 +942,8 @@ }; &pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -977,7 +977,7 @@ &pcie1 { wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 8dc24db239bb5..c1604cf9dd172 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause +&pcie1_port0 {&pcieport0 {// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023, Linaro Limited */ @@ -643,7 +643,7 @@ &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -660,7 +660,7 @@ &pcie1 { wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 70b3f0c4b6e3e..e657e456bc220 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023, Linaro Limited */ @@ -893,8 +893,8 @@ }; &pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 842396cf75d95..072182e6b842d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3645,7 +3645,7 @@ bus-range = <0 0xff>; phys = <&pcie0_phy>; - phy-names = "pciephy"; + phys = <&pcie0_phy>; #address-cells = <3>; #size-cells = <2>; @@ -3825,7 +3825,7 @@ bus-range = <0 0xff>; phys = <&pcie1_phy>; - phy-names = "pciephy"; + phys = <&pcie1_phy>; dma-coherent; From d7d9017c1374f0ef41d8b22b51edd7060e85502f Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:12 +0530 Subject: [PATCH 35/36] FROMLIST: arm64: dts: qcom: kodiak: Move PCIe phy and GPIOs The PCIe phy reference and the perst/wake GPIO properties are per-root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys from the controller to pcie0_port and pcie1_port0, and move perst-gpios/wake-gpios from the &pcie0/&pcie1 controller overrides to the respective &pcie0_port/&pcie1_port0 nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-36-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts | 6 +++--- .../boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 4 ++-- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++-- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts index ba01677f64cb3..71ac4c0938d07 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause +&pcie1_port0 {&pcie0_port {// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * Copyright (c) 2023, Luca Weiss @@ -549,7 +549,7 @@ }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; @@ -566,7 +566,7 @@ }; &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 7a623062bb388..8d3f38fe7c26d 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. */ @@ -81,7 +81,7 @@ }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index ef4055f3b364a..b81085215f48f 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: BSD-3-Clause + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ @@ -976,7 +976,7 @@ }; &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 5c5e4f1dd2217..fb260876e0841 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -472,7 +472,7 @@ ap_i2c_tpm: &i2c14 { pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>; - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +&pcie1_port0 { vddpe-3v3-supply = <&pp3300_ssd>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index ccd39a1baeda5..70de3de13360b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -418,7 +418,7 @@ &pcie1 { status = "okay"; - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +&pcie1_port0 { vddpe-3v3-supply = <&nvme_3v3_regulator>; From dd4159942f0dd5a3a546c893ddcac8987fa60417 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:13 +0530 Subject: [PATCH 36/36] FROMLIST: arm64: dts: qcom: msm8996: Move PCIe phy and The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0, pcie1_port0, and pcie2_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/all/20260611-wake-v2-37-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi | 2 +- .../boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8996.dtsi | 12 ++++++------ 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi index 63ab564655bc8..2726747a259a3 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi @@ -210,7 +210,7 @@ }; &pcie0 { - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; +&pcie0_port0 { vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&vreg_l28a_0p925>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index 5b42c266557ab..6e72c22c3aaec 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -191,8 +191,8 @@ }; &pcie0 { - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; +&pcie0_port0 { vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&pm8994_l28>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 337db4db9895a..34ce3b61696d0 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -279,7 +279,7 @@ vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&vreg_l28a_0p925>; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; +&pcie0_port0 { wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 33608b1d7d060..e725790a25b6d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1901,7 +1901,7 @@ reg-names = "parf", "dbi", "elbi","config"; phys = <&pciephy_0>; - phy-names = "pciephy"; + phys = <&pciephy_0>; #address-cells = <3>; #size-cells = <2>; @@ -1951,7 +1951,7 @@ "bus_master", "bus_slave"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1978,7 +1978,7 @@ reg-names = "parf", "dbi", "elbi","config"; phys = <&pciephy_1>; - phy-names = "pciephy"; + phys = <&pciephy_1>; #address-cells = <3>; #size-cells = <2>; @@ -2028,7 +2028,7 @@ "bus_master", "bus_slave"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2053,7 +2053,7 @@ reg-names = "parf", "dbi", "elbi","config"; phys = <&pciephy_2>; - phy-names = "pciephy"; + phys = <&pciephy_2>; #address-cells = <3>; #size-cells = <2>; @@ -2102,7 +2102,7 @@ "bus_master", "bus_slave"; - pcie@0 { + pcie2_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>;