From a88ef64861c1e1fd3df89e5fc14d5178c3823327 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Jul 2026 09:31:37 +0200 Subject: [PATCH 1/3] system(h5) update STM32H5xx HAL Drivers to v1.7.0 Included in STM32CubeH5 FW v1.7.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 21 +- .../Inc/stm32h5xx_hal_ccb.h | 3 + .../Inc/stm32h5xx_hal_crc_ex.h | 80 +- .../Inc/stm32h5xx_hal_cryp.h | 3 + .../Inc/stm32h5xx_hal_dma2d.h | 60 +- .../Inc/stm32h5xx_hal_eth.h | 16 +- .../Inc/stm32h5xx_hal_flash.h | 6 + .../Inc/stm32h5xx_hal_flash_ex.h | 12 - .../Inc/stm32h5xx_hal_gpio_ex.h | 77 +- .../Inc/stm32h5xx_hal_i2s.h | 2 +- .../Inc/stm32h5xx_hal_i3c.h | 85 + .../Inc/stm32h5xx_hal_lptim.h | 6 + .../Inc/stm32h5xx_hal_mdf.h | 8 +- .../Inc/stm32h5xx_hal_nor.h | 7 + .../Inc/stm32h5xx_hal_pcd.h | 2 - .../Inc/stm32h5xx_hal_pka.h | 3 + .../Inc/stm32h5xx_hal_play.h | 174 +- .../Inc/stm32h5xx_hal_rcc_ex.h | 40 +- .../Inc/stm32h5xx_hal_rng_ex.h | 22 +- .../Inc/stm32h5xx_hal_rtc_ex.h | 53 + .../Inc/stm32h5xx_hal_uart_ex.h | 44 + .../Inc/stm32h5xx_hal_usart.h | 104 + .../Inc/stm32h5xx_ll_adc.h | 92 +- .../Inc/stm32h5xx_ll_bus.h | 72 +- .../Inc/stm32h5xx_ll_comp.h | 3 +- .../Inc/stm32h5xx_ll_crc.h | 175 ++ .../Inc/stm32h5xx_ll_dma2d.h | 2 +- .../Inc/stm32h5xx_ll_exti.h | 248 +- .../Inc/stm32h5xx_ll_i3c.h | 468 ++++ .../Inc/stm32h5xx_ll_lptim.h | 26 +- .../Inc/stm32h5xx_ll_pka.h | 13 +- .../Inc/stm32h5xx_ll_play.h | 521 +++-- .../Inc/stm32h5xx_ll_rcc.h | 27 +- .../Inc/stm32h5xx_ll_rng.h | 168 +- .../Inc/stm32h5xx_ll_rtc.h | 95 + .../Inc/stm32h5xx_ll_system.h | 32 +- .../Inc/stm32h5xx_ll_usb.h | 13 +- .../Drivers/STM32H5xx_HAL_Driver/LICENSE.md | 2 +- system/Drivers/STM32H5xx_HAL_Driver/README.md | 4 +- .../STM32H5xx_HAL_Driver/Release_Notes.html | 170 +- .../STM32H5xx_HAL_Driver/SW_Security_Level.md | 47 + .../STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c | 2 +- .../Src/stm32h5xx_hal_ccb.c | 1997 ++++++++++++----- .../Src/stm32h5xx_hal_crc.c | 8 + .../Src/stm32h5xx_hal_cryp.c | 389 +++- .../Src/stm32h5xx_hal_dma2d.c | 165 +- .../Src/stm32h5xx_hal_eth.c | 42 +- .../Src/stm32h5xx_hal_eth_ex.c | 6 +- .../Src/stm32h5xx_hal_flash.c | 100 + .../Src/stm32h5xx_hal_i3c.c | 366 +++ .../Src/stm32h5xx_hal_mmc.c | 11 +- .../Src/stm32h5xx_hal_nand.c | 256 ++- .../Src/stm32h5xx_hal_nor.c | 235 +- .../Src/stm32h5xx_hal_pcd.c | 13 +- .../Src/stm32h5xx_hal_pka.c | 218 +- .../Src/stm32h5xx_hal_play.c | 1563 ++++++------- .../Src/stm32h5xx_hal_rng.c | 30 +- .../Src/stm32h5xx_hal_rng_ex.c | 296 ++- .../Src/stm32h5xx_hal_sd.c | 11 +- .../Src/stm32h5xx_hal_sdio.c | 47 +- .../Src/stm32h5xx_hal_sdram.c | 26 +- .../Src/stm32h5xx_hal_smartcard.c | 16 +- .../Src/stm32h5xx_hal_sram.c | 22 +- .../Src/stm32h5xx_ll_exti.c | 2 +- .../Src/stm32h5xx_ll_play.c | 10 +- .../Src/stm32h5xx_ll_usb.c | 20 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 67 files changed, 6382 insertions(+), 2477 deletions(-) create mode 100644 system/Drivers/STM32H5xx_HAL_Driver/SW_Security_Level.md diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 17947e408f..35650fcc17 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -1917,7 +1917,11 @@ extern "C" { #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +#define PWR_PVM_USB PWR_PVM_ENABLE +#define PWR_FLAG_PVMOUSB PWR_FLAG_PVMOVDDIO2 +#define PWR_FLAG_PVMO_USB PWR_FLAG_PVMO_VDDIO2 +#endif /* STM32G0C1xx || STM32G0B1xx */ #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING @@ -2161,6 +2165,13 @@ extern "C" { #define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig #endif /* STM32H7RS || STM32N6 */ +#if defined(STM32N6) +/* alias CMSIS */ +#define CSI_PCR_PWRDOWN_Pos CSI_PCR_NPWRDOWN_Pos +#define CSI_PCR_PWRDOWN_Msk CSI_PCR_NPWRDOWN_Msk +#define CSI_PCR_PWRDOWN CSI_PCR_NPWRDOWN +#endif /* STM32N6 */ + /** * @} */ @@ -3713,8 +3724,7 @@ extern "C" { #define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK #endif -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3963,10 +3973,7 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ - defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32U3) || defined (STM32WBA) || defined (STM32H5) || defined (STM32U0) || \ - defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_ccb.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_ccb.h index 8f8a4ae02e..3535123750 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_ccb.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_ccb.h @@ -22,6 +22,9 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_hal_def.h" +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +#include "stm32h5xx_ll_rng.h" +#endif /* RNG_HTSR0_RPERRX) || RNG_HTSR1_ADERRX */ /** @addtogroup STM32H5xx_HAL_Driver * @{ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_crc_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_crc_ex.h index e8eea09bf5..b4bd22cd5a 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_crc_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_crc_ex.h @@ -44,10 +44,23 @@ extern "C" { /** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes * @{ */ +#if defined(CRC_CR_RTYPE_IN) +#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */ +#define CRC_INPUTDATA_INVERSION_HALFWORD_BYWORD (CRC_CR_RTYPE_IN | CRC_CR_REV_IN_0) /*!< Input data half-word-reversal done by word */ +#define CRC_INPUTDATA_INVERSION_BYTE_BYWORD (CRC_CR_RTYPE_IN | CRC_CR_REV_IN_1) /*!< Input data byte-reversal done by word */ +#define CRC_INPUTDATA_INVERSION_BIT_BYBYTE CRC_CR_REV_IN_0 /*!< Input data bit-reversal done by byte */ +#define CRC_INPUTDATA_INVERSION_BIT_BYHALFWORD CRC_CR_REV_IN_1 /*!< Input data bit-reversal done by half-word */ +#define CRC_INPUTDATA_INVERSION_BIT_BYWORD CRC_CR_REV_IN /*!< Input data bit-reversal done by word */ + +#define CRC_INPUTDATA_INVERSION_BYTE CRC_INPUTDATA_INVERSION_BIT_BYBYTE /*!< Definition for compatibility with legacy code */ +#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_INPUTDATA_INVERSION_BIT_BYHALFWORD /*!< Definition for compatibility with legacy code */ +#define CRC_INPUTDATA_INVERSION_WORD CRC_INPUTDATA_INVERSION_BIT_BYWORD /*!< Definition for compatibility with legacy code */ +#else #define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */ #define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */ #define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */ #define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */ +#endif /* CRC_CR_RTYPE_IN */ /** * @} */ @@ -55,8 +68,17 @@ extern "C" { /** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes * @{ */ +#if defined(CRC_CR_RTYPE_OUT) +#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */ +#define CRC_OUTPUTDATA_INVERSION_BIT CRC_CR_REV_OUT_0 /*!< Output data bit-reversal */ +#define CRC_OUTPUTDATA_INVERSION_HALFWORD (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT_0) /*!< Output data half-word-reversal done by word */ +#define CRC_OUTPUTDATA_INVERSION_BYTE (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT_1) /*!< Output data byte-reversal done by word */ + +#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_OUTPUTDATA_INVERSION_BIT /*!< Definition for compatibility with legacy code */ +#else #define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */ #define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */ +#endif /* CRC_CR_RTYPE_OUT */ /** * @} */ @@ -70,6 +92,45 @@ extern "C" { * @{ */ +#if defined(CRC_CR_RTYPE_OUT) +/** + * @brief Set CRC output bit-reversal + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_OUTPUTREVERSAL_BIT_ENABLE(__HANDLE__) MODIFY_REG(((__HANDLE__)->Instance->CR),\ + (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT),\ + CRC_CR_REV_OUT_0); + +/** + * @brief Set CRC output halfword-reversal + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_OUTPUTREVERSAL_HALFWORD_ENABLE(__HANDLE__) MODIFY_REG(((__HANDLE__)->Instance->CR),\ + (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT),\ + (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT_0)); + +/** + * @brief Set CRC output byte-reversal + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_OUTPUTREVERSAL_BYTE_ENABLE(__HANDLE__) MODIFY_REG(((__HANDLE__)->Instance->CR), \ + (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT), \ + (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT_1)); + +/* Definition for compatibility with legacy code */ +#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) __HAL_CRC_OUTPUTREVERSAL_BIT_ENABLE(__HANDLE__) + +/** + * @brief Unset CRC output reversal + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_RTYPE_OUT |\ + CRC_CR_REV_OUT)) +#else /** * @brief Set CRC output reversal * @param __HANDLE__ CRC handle @@ -83,6 +144,7 @@ extern "C" { * @retval None */ #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) +#endif /* CRC_CR_RTYPE_OUT */ /** * @brief Set CRC non-default polynomial @@ -101,13 +163,29 @@ extern "C" { * @{ */ +#if defined(CRC_CR_RTYPE_IN) +#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD_BYWORD) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_BYTE_BYWORD) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_BIT_BYBYTE) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_BIT_BYHALFWORD) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_BIT_BYWORD)) +#else #define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \ ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \ ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \ ((MODE) == CRC_INPUTDATA_INVERSION_WORD)) - +#endif /* CRC_CR_RTYPE_IN */ + +#if defined(CRC_CR_RTYPE_OUT) +#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \ + ((MODE) == CRC_OUTPUTDATA_INVERSION_BIT) || \ + ((MODE) == CRC_OUTPUTDATA_INVERSION_HALFWORD) || \ + ((MODE) == CRC_OUTPUTDATA_INVERSION_BYTE)) +#else #define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \ ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE)) +#endif /* CRC_CR_RTYPE_OUT */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cryp.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cryp.h index 672310e837..c3e32f5b77 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cryp.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cryp.h @@ -26,6 +26,9 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_hal_def.h" +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +#include "stm32h5xx_ll_rng.h" +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ /** @addtogroup STM32H5xx_HAL_Driver * @{ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma2d.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma2d.h index c375d951c1..85f78f6d8f 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma2d.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma2d.h @@ -79,10 +79,14 @@ typedef struct */ typedef struct { - uint32_t PixelPerLines; /*!< The number of pixel per lines of the Scaler */ - uint32_t NumberOfLines; /*!< The number of lines of the Scaler */ + uint32_t PixelPerLines; /*!< Source width, in pixels, to be processed by the scaler */ + uint32_t NumberOfLines; /*!< Source height, in lines, to be processed by the scaler */ uint16_t VRatio; /*!< The Vertical scaling Ratio */ + uint16_t VRatioDiv; /*!< The Vertical scaling Ratio divider: The output height is computed + from NumberOfLines * VRatio / VRatioDiv */ uint16_t HRatio; /*!< Horizontal scaling Ratio */ + uint16_t HRatioDiv; /*!< Horizontal scaling Ratio divider: The output width is computed + from PixelPerLines * HRatio / HRatioDiv */ uint32_t VPhase; /*!< Vertical Phase (This allows partial redrawing of scaled images) */ uint32_t HPhase; /*!< Horizontal Phase (This allows partial redrawing of scaled images) */ } DMA2D_DownscalingCfgTypeDef; @@ -344,8 +348,8 @@ typedef void (*pDMA2D_CL_GeneralPurposeEventCallbackTypeDef)(DMA2D_CL_HandleType #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ -#define DMA2D_OUTPUT_ARGB2222 (DMA2D_OPFCCR_CM_1 | DMA2D_OPFCCR_CM_2 | DMA2D_OPFCCR_CM_3) - /*!< ARGB2222 DMA2D color mode */ +#define DMA2D_OUTPUT_ARGB2222 (DMA2D_OPFCCR_CM_1 | DMA2D_OPFCCR_CM_2 | DMA2D_OPFCCR_CM_3) /*!< ARGB2222 + DMA2D color mode */ /** * @} */ @@ -899,7 +903,30 @@ HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d); uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d); #endif /* USE_DMA2D_COMMAND_LIST_MODE == 0 */ #if (USE_DMA2D_COMMAND_LIST_MODE == 1) -/** @addtogroup DMA2D_Exported_Functions_Group5 IO operation functions +/** @addtogroup DMA2D_Exported_Functions_Group5 DMA2D Command List (CL) functions + * @brief DMA2D Command List mode exported functions + * +@verbatim + =============================================================================== + ##### Command List (CL) mode functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and de-initialize the DMA2D in Command List mode + using HAL_DMA2D_CL_Init() and HAL_DMA2D_CL_DeInit(). + (+) Build command lists using APIs such as + HAL_DMA2D_CL_Init_CommandList(), HAL_DMA2D_CL_AddConfigLayerCMD(), + HAL_DMA2D_CL_AddConfigRotationCMD(), HAL_DMA2D_CL_AddConfigStencilCMD(), + HAL_DMA2D_CL_AddConfigDownscalingCMD(), + HAL_DMA2D_CL_AddProgramLineEventCMD(), HAL_DMA2D_CL_AddCopyCMD(), + HAL_DMA2D_CL_AddBlendingCMD(), HAL_DMA2D_CL_AddCLUTStartLoadCMD(). + (+) Insert prepared command lists into the ring buffer and start + execution using HAL_DMA2D_CL_InsertCommandList(), HAL_DMA2D_CL_Start() + and HAL_DMA2D_CL_StartOpt(). + (+) Handle DMA2D CL interrupts through HAL_DMA2D_CL_IRQHandler() and + related callbacks, and control execution using + HAL_DMA2D_CL_Suspend(), HAL_DMA2D_CL_Resume() and HAL_DMA2D_CL_Abort(). + +@endverbatim * @{ */ HAL_StatusTypeDef HAL_DMA2D_CL_Init(DMA2D_CL_HandleTypeDef *hdma2d); @@ -914,9 +941,13 @@ HAL_StatusTypeDef HAL_DMA2D_CL_RegisterCallback(DMA2D_CL_HandleTypeDef *hdma2d, pDMA2D_CL_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_DMA2D_CL_UnRegisterCallback(DMA2D_CL_HandleTypeDef *hdma2d, HAL_DMA2D_CL_CallbackIDTypeDef CallbackID); -HAL_StatusTypeDef HAL_DMA2D_CL_Register_GeneralPurposeEvent_Callback(DMA2D_CL_HandleTypeDef *hdma2d, HAL_DMA2D_CL_CallbackIDTypeDef CallbackID, - pDMA2D_CL_GeneralPurposeEventCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_DMA2D_CL_UnRegister_GeneralPurposeEvent_Callback(DMA2D_CL_HandleTypeDef *hdma2d, HAL_DMA2D_CL_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_DMA2D_CL_Register_GeneralPurposeEvent_Callback(DMA2D_CL_HandleTypeDef *hdma2d, + HAL_DMA2D_CL_CallbackIDTypeDef + CallbackID, + pDMA2D_CL_GeneralPurposeEventCallbackTypeDef + pCallback); +HAL_StatusTypeDef HAL_DMA2D_CL_UnRegister_GeneralPurposeEvent_Callback(DMA2D_CL_HandleTypeDef *hdma2d, + HAL_DMA2D_CL_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ @@ -936,18 +967,19 @@ HAL_StatusTypeDef HAL_DMA2D_CL_AddConfigLayerCMD(DMA2D_CL_HandleTypeDef *hdma2d, HAL_StatusTypeDef HAL_DMA2D_CL_AddConfigRotationCMD(DMA2D_CL_HandleTypeDef *hdma2d, uint32_t Source, uint32_t Mirroring_Type); HAL_StatusTypeDef HAL_DMA2D_CL_AddConfigStencilCMD(DMA2D_CL_HandleTypeDef *hdma2d, uint32_t Source, - DMA2D_StencilCfgTypeDef *pStencilCfg); + DMA2D_StencilCfgTypeDef *pStencilCfg); HAL_StatusTypeDef HAL_DMA2D_CL_AddConfigDownscalingCMD(DMA2D_CL_HandleTypeDef *hdma2d, uint32_t Source, DMA2D_DownscalingCfgTypeDef *pDownscalingCfg); HAL_StatusTypeDef HAL_DMA2D_CL_AddProgramLineEventCMD(DMA2D_CL_HandleTypeDef *hdma2d, uint32_t Line); -HAL_StatusTypeDef HAL_DMA2D_CL_AddCLUTStartLoadCMD(DMA2D_CL_HandleTypeDef *hdma2d,uint32_t LayerIdx, - const DMA2D_CLUTCfgTypeDef *CLUTCfg, - DMA2D_CL_CommandListTypeDef *pCommandList); +HAL_StatusTypeDef HAL_DMA2D_CL_AddCLUTStartLoadCMD(DMA2D_CL_HandleTypeDef *hdma2d, uint32_t LayerIdx, + const DMA2D_CLUTCfgTypeDef *CLUTCfg, + DMA2D_CL_CommandListTypeDef *pCommandList); HAL_StatusTypeDef HAL_DMA2D_CL_AddCopyCMD(DMA2D_CL_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, - uint32_t Width, uint32_t Height, DMA2D_CL_CommandListTypeDef *pCommandList); + uint32_t Width, uint32_t Height, + DMA2D_CL_CommandListTypeDef *pCommandList); HAL_StatusTypeDef HAL_DMA2D_CL_AddBlendingCMD(DMA2D_CL_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, - uint32_t Height,DMA2D_CL_CommandListTypeDef *pCommandList); + uint32_t Height ,DMA2D_CL_CommandListTypeDef *pCommandList); HAL_StatusTypeDef HAL_DMA2D_CL_Init_CommandList(uint32_t *Address, uint32_t Size, DMA2D_CL_CommandListTypeDef *pCommandList); HAL_StatusTypeDef HAL_DMA2D_CL_ResetIndex(DMA2D_CL_CommandListTypeDef *pCommandList); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h index 81fd5cc623..d739cd9dcf 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h @@ -472,19 +472,21 @@ typedef struct uint32_t TimestampMaster; /*!< Enable Timestamp Snapshot for Event Messages */ uint32_t TimestampSnapshots; /*!< Select PTP packets for Taking Snapshots */ uint32_t TimestampFilter; /*!< Enable MAC Address for PTP Packet Filtering */ -#if !defined(STM32H5E5xx) && !defined(STM32H5E4xx) && !defined(STM32H5F5xx) && !defined(STM32H5F4xx) +#if defined(STM32H563xx) || defined(STM32H573xx) uint32_t TimestampChecksumCorrection; /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ -#endif /* !defined(STM32H5E5xx) && !defined(STM32H5E4xx) && !defined(STM32H5F5xx) && !defined(STM32H5F4xx) */ +#endif /* defined(STM32H563xx) || defined(STM32H573xx) */ uint32_t TimestampStatusMode; /*!< Transmit Timestamp Status Mode */ uint32_t TimestampAddend; /*!< Timestamp addend value */ uint32_t TimestampSubsecondInc; /*!< Subsecond Increment */ -#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) +#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) \ + || defined(STM32H553xx) || defined(STM32H543xx) uint32_t TimestampPCS; /*!< Enable PCS latencies */ uint32_t TimestampCapturing; /*!< Enable Timestamp Capturing in PTP Clock Domain */ uint32_t TimestampLatencyAccuracy; /*!< Latency Input Based Timestamp Accuracy Disable */ uint32_t AV8021ASMEN; /*!< Enable AV 802.1AS Mode */ -#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) */ +#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) || + defined(STM32H553xx) || defined(STM32H543xx) */ } ETH_PTP_ConfigTypeDef; /** @@ -1334,7 +1336,8 @@ typedef struct * @} */ -#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) +#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) \ + || defined(STM32H553xx) || defined(STM32H543xx) /** @defgroup ETH_Watchdog_Jabber_Timeout ETH Watchdog Jabber Timeout * @{ */ @@ -1393,7 +1396,8 @@ typedef struct /** * @} */ -#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) */ +#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) || + defined(STM32H553xx) || defined(STM32H543xx) */ /** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap * @{ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h index 929d61d97c..cf3a801890 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h @@ -778,6 +778,12 @@ void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); /* Peripheral Control functions */ HAL_StatusTypeDef HAL_FLASH_Unlock(void); HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_Unlock_NS(void); +HAL_StatusTypeDef HAL_FLASH_Lock_NS(void); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +HAL_StatusTypeDef HAL_FLASH_Unlock_S(void); +HAL_StatusTypeDef HAL_FLASH_Lock_S(void); +#endif /* __ARM_FEATURE_CMSE && __ARM_FEATURE_CMSE == 3U */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); /* Option bytes control */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h index fe46174ffa..53f9571414 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h @@ -904,18 +904,6 @@ byte configuration */ */ #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) -/** - * @brief Enable the FLASH smart prefetch buffer. - * @retval None - */ -#define __HAL_FLASH_SMART_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_S_PRFTEN) - -/** - * @brief Disable the FLASH smart prefetch buffer. - * @retval None - */ -#define __HAL_FLASH_SMART_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_S_PRFTEN) - /** * @brief Set the FLASH Programming Delay. * @param __DELAY__ FLASH Programming Delay diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h index a745de1f47..b65ec19efc 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h @@ -100,9 +100,9 @@ extern "C" { #if defined(TIM5) #define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ #endif /* TIM5 */ -#if (defined(STM32H533xx) || defined(STM32H523xx)) +#if (defined(STM32H533xx) || defined(STM32H523xx) || defined(STM32H553xx) || defined(STM32H543xx)) #define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */ -#endif /* STM32H533xx || STM32H523xx */ +#endif /* STM32H533xx || STM32H523xx || STM32H553xx || STM32H543xx */ #if defined(TIM12) #define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */ #endif /* TIM12 */ @@ -172,9 +172,9 @@ extern "C" { #define GPIO_AF4_LPTIM1 ((uint8_t)0x04) /* LPTIM1 Alternate Function mapping */ #define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */ #define GPIO_AF4_SPI1 ((uint8_t)0x04) /* SPI1 Alternate Function mapping */ -#if (defined(STM32H533xx) || defined(STM32H523xx)) +#if (defined(STM32H533xx) || defined(STM32H523xx) || defined(STM32H553xx) || defined(STM32H543xx)) #define GPIO_AF4_SPI3 ((uint8_t)0x04) /* SPI3 Alternate Function mapping */ -#endif /* STM32H533xx || STM32H523xx */ +#endif /* STM32H533xx || STM32H523xx || STM32H553xx || STM32H543xx */ #if defined(TIM15) #define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */ #endif /* TIM15 */ @@ -198,8 +198,10 @@ extern "C" { #if defined(CEC) #define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */ #endif /* CEC */ -#if !defined(STM32H503xx) +#if !defined(STM32H553xx) || defined(STM32H543xx) || !defined(STM32H503xx) #define GPIO_AF5_I3C1 ((uint8_t)0x05) /* I3C1 Alternate Function mapping */ +#endif /* STM32H553xx || STM32H543xx || STM32H503xx */ +#if !defined(STM32H503xx) #define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ #endif /* STM32H503xx */ #define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /* LPTIM1 Alternate Function mapping */ @@ -235,10 +237,10 @@ extern "C" { #if defined(SAI1) #define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ #endif /* SAI1 */ -#if (defined(STM32H503xx) || defined(STM32H533xx) || defined(STM32H523xx)) +#if (defined(STM32H503xx) || defined(STM32H533xx) || defined(STM32H523xx) || defined(STM32H553xx) || defined(STM32H543xx)) #define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */ #define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */ -#endif /* STM32H503xx || STM32H533xx || STM32H523xx */ +#endif /* STM32H503xx || STM32H533xx || STM32H523xx || STM32H553xx || STM32H543xx */ #define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ #if defined(SPI4) #define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping */ @@ -246,9 +248,9 @@ extern "C" { #if defined(UART4) #define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */ #endif /* UART4 */ -#if (defined(STM32H533xx) || defined(STM32H523xx)) +#if (defined(STM32H533xx) || defined(STM32H523xx) || defined(STM32H553xx) || defined(STM32H543xx)) #define GPIO_AF6_USART6 ((uint8_t)0x06) /* USART6 Alternate Function mapping */ -#endif /* STM32H533xx || STM32H523xx */ +#endif /* STM32H533xx || STM32H523xx || STM32H553xx || STM32H543xx */ #if defined(UART12) #define GPIO_AF6_UART12 ((uint8_t)0x06) /* UART12 Alternate Function mapping */ #endif /* UART12 */ @@ -260,11 +262,15 @@ extern "C" { #endif /* UCPD1 */ #if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) #define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ -#define GPIO_AF6_ETH ((uint8_t)0x06) /* ETH Alternate Function mapping */ #define GPIO_AF6_I2C1 ((uint8_t)0x06) /* I2C1 Alternate Function mapping */ #define GPIO_AF6_USART12 ((uint8_t)0x06) /* USART12 Alternate Function mapping */ #endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ - +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H553xx) || defined(STM32H543xx) +#define GPIO_AF6_ETH ((uint8_t)0x06) /* ETH Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx || STM32H553xx || STM32H543xx */ +#if defined(STM32H553xx) || defined(STM32H543xx) +#define GPIO_AF6_I3C1 ((uint8_t)0x06) /* I3C1 Alternate Function mapping */ +#endif /* STM32H553xx || STM32H543xx */ /** * @brief AF 7 selection */ @@ -279,9 +285,11 @@ extern "C" { #if defined(UART7) #define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */ #endif /* UART7 */ +#if !defined(STM32H553xx) || !defined(STM32H543xx) #if defined(UART8) #define GPIO_AF7_UART8 ((uint8_t)0x07) /* UART8 Alternate Function mapping */ #endif /* UART8 */ +#endif /* STM32H553xx || STM32H543xx */ #if !defined(STM32H5F5xx) || !defined(STM32H5F4xx) || !defined(STM32H5E5xx) || !defined(STM32H5E4xx) #if defined(UART12) #define GPIO_AF7_UART12 ((uint8_t)0x07) /* UART12 Alternate Function mapping */ @@ -299,9 +307,9 @@ extern "C" { #if defined(USART11) #define GPIO_AF7_USART11 ((uint8_t)0x07) /* USART11 Alternate Function mapping */ #endif /* USART11 */ -#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H553xx) || defined(STM32H543xx) #define GPIO_AF7_ETH ((uint8_t)0x07) /* ETH Alternate Function mapping */ -#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx || STM32H553xx || || STM32H543xx */ /** * @brief AF 8 selection */ @@ -329,10 +337,12 @@ extern "C" { #if defined(UART8) #define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ #endif /* UART8 */ -#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H553xx) || defined(STM32H543xx) #define GPIO_AF8_ETH ((uint8_t)0x08) /* ETH Alternate Function mapping */ -#define GPIO_AF8_FMC ((uint8_t)0x08) /* FMC Alternate Function mapping */ #define GPIO_AF8_I3C2 ((uint8_t)0x08) /* I3C2 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx || STM32H553xx || STM32H543xx */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF8_FMC ((uint8_t)0x08) /* FMC Alternate Function mapping */ #define GPIO_AF8_OCTOSPI1 ((uint8_t)0x08) /* OCTOSPI1 Alternate Function mapping */ #endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ #if defined(OCTOSPI2) @@ -368,10 +378,10 @@ extern "C" { #define GPIO_AF9_USART2 ((uint8_t)0x09) /* USART2 Alternate Function mapping */ #define GPIO_AF9_USART3 ((uint8_t)0x09) /* USART3 Alternate Function mapping */ #endif /* STM32H503xx */ -#if (defined(STM32H533xx) || defined(STM32H523xx)) +#if (defined(STM32H533xx) || defined(STM32H523xx) || defined(STM32H553xx) || defined(STM32H543xx)) #define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ #define GPIO_AF9_I3C2 ((uint8_t)0x09) /* I3C2 Alternate Function mapping */ -#endif /* STM32H533xx || STM32H523xx */ +#endif /* STM32H533xx || STM32H523xx || STM32H553xx || STM32H543xx */ #if defined(OCTOSPI2) #define GPIO_AF9_OCTOSPI2 ((uint8_t)0x09) /* OCTOSPI2 Alternate Function mapping */ #endif /* OCTOSPI2 */ @@ -390,9 +400,9 @@ extern "C" { #define GPIO_AF10_I3C1 ((uint8_t)0x0A) /* I3C1 Alternate Function mapping */ #define GPIO_AF10_SPI3 ((uint8_t)0x0A) /* SPI3 Alternate Function mapping */ #endif /* STM32H503xx */ -#if (defined(STM32H503xx) || defined(STM32H533xx) || defined(STM32H523xx)) +#if (defined(STM32H503xx) || defined(STM32H533xx) || defined(STM32H523xx) || defined(STM32H553xx) || defined(STM32H543xx)) #define GPIO_AF10_I3C2 ((uint8_t)0x0A) /* I3C2 Alternate Function mapping */ -#endif /* STM32H503xx || STM32H533xx || STM32H523xx */ +#endif /* STM32H503xx || STM32H533xx || STM32H523xx || STM32H553xx || STM32H543xx */ #if defined(FMC_BANK1) #define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping */ #endif /* FMC_BANK1 */ @@ -402,9 +412,9 @@ extern "C" { #if defined(SAI2) #define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */ #endif /* SAI2 */ -#if (defined(STM32H533xx) || defined(STM32H523xx)) +#if (defined(STM32H533xx) || defined(STM32H523xx) || defined(STM32H553xx) || defined(STM32H543xx)) #define GPIO_AF10_SDMMC1 ((uint8_t)0x0A) /* SDMMC1 Alternate Function mapping */ -#endif /* STM32H533xx || STM32H523xx */ +#endif /* STM32H533xx || STM32H523xx || STM32H553xx || STM32H543xx */ #if defined(SDMMC2) #define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */ #endif /* SDMMC2 */ @@ -442,9 +452,9 @@ extern "C" { #if defined(OCTOSPI1) #define GPIO_AF11_OCTOSPI1 ((uint8_t)0x0B) /* OCTOSPI1 Alternate Function mapping */ #endif /* OCTOSPI1 */ -#if (defined(STM32H533xx) || defined(STM32H523xx)) +#if (defined(STM32H533xx) || defined(STM32H523xx) || defined(STM32H553xx) || defined(STM32H543xx)) #define GPIO_AF11_SDMMC1 ((uint8_t)0x0B) /* SDMMC1 Alternate Function mapping */ -#endif /* STM32H533xx || STM32H523xx */ +#endif /* STM32H533xx || STM32H523xx || STM32H553xx || STM32H543xx */ #if defined(SDMMC2) #define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */ #endif /* SDMMC2 */ @@ -480,9 +490,9 @@ extern "C" { #define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ #define GPIO_AF12_SPI1 ((uint8_t)0x0C) /* SPI1 Alternate Function mapping */ #endif /* STM32H503xx */ -#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H553xx) || defined(STM32H543xx) #define GPIO_AF12_ETH ((uint8_t)0x0C) /* ETH Alternate Function mapping */ -#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx || STM32H553xx || STM32H543xx */ #if defined(LTDC) #define GPIO_AF12_LTDC ((uint8_t)0x0C) /* LTDC Alternate Function mapping */ #endif /* LTDC */ @@ -510,7 +520,10 @@ extern "C" { #if defined(LTDC) #define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */ #endif /* LTDC */ - +#if defined(STM32H553xx) || defined(STM32H543xx) +#define GPIO_AF13_UART8 ((uint8_t)0x0D) /* UART8 Alternate Function mapping */ +#define GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */ +#endif /* STM32H553xx || STM32H543xx */ /** * @brief AF 14 selection */ @@ -533,15 +546,15 @@ extern "C" { #if defined(LPTIM6) #define GPIO_AF14_LPTIM6 ((uint8_t)0x0E) /* LPTIM6 Alternate Function mapping */ #endif /* LPTIM6 */ -#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || defined(STM32H523xx) +#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || defined(STM32H523xx) || defined(STM32H553xx) || defined(STM32H543xx) #define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ -#endif /* STM32H573xx || STM32H563xx || STM32H562xx || STM32H533xx || STM32H523xx */ +#endif /* STM32H573xx || STM32H563xx || STM32H562xx || STM32H533xx || STM32H523xx || STM32H553xx || STM32H543xx */ #if defined(UART5) #define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */ #endif /* UART5 */ -#if (defined(STM32H533xx) || defined(STM32H523xx)) +#if (defined(STM32H533xx) || defined(STM32H523xx) || defined(STM32H553xx) || defined(STM32H543xx)) #define GPIO_AF14_USART6 ((uint8_t)0x0E) /* USART6 Alternate Function mapping */ -#endif /* STM32H533xx || STM32H523xx */ +#endif /* STM32H533xx || STM32H523xx || STM32H553xx || STM32H543xx */ #if defined(LTDC) #define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */ #endif /* LTDC */ @@ -549,7 +562,9 @@ extern "C" { #define GPIO_AF14_PLAY1_IN ((uint8_t)0x0E) /* PLAY1_IN Alternate Function mapping */ #define GPIO_AF14_PLAY1_OUT ((uint8_t)0x0E) /* PLAY1_OUT Alternate Function mapping */ #endif /* PLAY1 */ - +#if defined(STM32H553xx) || defined(STM32H543xx) +#define GPIO_AF14_COMP2 ((uint8_t)0x0E) /* COMP2 Alternate Function mapping */ +#endif /* STM32H553xx || STM32H543xx */ /** * @brief AF 15 selection */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2s.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2s.h index a9030e38d7..cf4f2da288 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2s.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2s.h @@ -551,7 +551,7 @@ uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s); /** @defgroup I2S_Private_Functions I2S Private Functions * @{ */ -/* Private functions are defined in stm32h7xx_hal_i2S.c file */ +/* Private functions are defined in stm32xxxx_hal_i2S.c file */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i3c.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i3c.h index cf2b9f0863..ab90b16ba7 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i3c.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i3c.h @@ -98,6 +98,20 @@ typedef struct when receiving a hot join request from target. This parameter can be set to ENABLE or DISABLE */ +#if defined(I3C_TIMINGR2_STALLL) + FunctionalState ACKI2CAddrState; /*!< Specifies the Enable/Disable state of the controller clock stall + on data ACK/NACK bit of legacy I2C address phase. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ACKI2CWriteState; /*!< Specifies the Enable/Disable state of the controller clock stall + on ACK/NACK bit of legacy I2C write message phase. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ACKI2CReadState; /*!< Specifies the Enable/Disable state of the controller clock stall + on ACK/NACK bit of legacy I2C read message phase. + This parameter can be set to ENABLE or DISABLE */ + +#endif /* I3C_TIMINGR2_STALLL */ FunctionalState ACKStallState; /*!< Specifies the Enable/Disable state of the controller clock stall on the ACK phase. This parameter can be set to ENABLE or DISABLE */ @@ -761,6 +775,10 @@ typedef void (*pI3C_TgtReqDynamicAddrCallbackTypeDef)(I3C_HandleTypeDef *hi3c, */ #define HAL_I3C_SDA_HOLD_TIME_0_5 LL_I3C_SDA_HOLD_TIME_0_5 /*!< SDA hold time equal to 0.5 x ti3cclk */ #define HAL_I3C_SDA_HOLD_TIME_1_5 LL_I3C_SDA_HOLD_TIME_1_5 /*!< SDA hold time equal to 1.5 x ti3cclk */ +#if defined(I3C_TIMINGR1_SDA_HD_1) +#define HAL_I3C_SDA_HOLD_TIME_2_5 LL_I3C_SDA_HOLD_TIME_2_5 /*!< SDA hold time equal to 2.5 x ti3cclk */ +#define HAL_I3C_SDA_HOLD_TIME_3_5 LL_I3C_SDA_HOLD_TIME_3_5 /*!< SDA hold time equal to 3.5 x ti3cclk */ +#endif /* I3C_TIMINGR1_SDA_HD_1 */ /** * @} */ @@ -959,6 +977,61 @@ typedef void (*pI3C_TgtReqDynamicAddrCallbackTypeDef)(I3C_HandleTypeDef *hi3c, /** * @} */ +#if defined(I3C_MISR_CFNFMIS) + +/** @defgroup I3C_COMMON_INTERRUPT_MASKS I3C COMMON INTERRUPT MASKS + * @{ + */ +#define HAL_I3C_IT_MASKS_TXFNFMIS LL_I3C_MISR_TXFNFMIS /*!< Tx FIFO not full interrupt mask */ +#define HAL_I3C_IT_MASKS_RXFNEMIS LL_I3C_MISR_RXFNEMIS /*!< Rx FIFO not empty interrupt mask */ +#define HAL_I3C_IT_MASKS_FCMIS LL_I3C_MISR_FCMIS /*!< Frame complete interrupt mask */ +#define HAL_I3C_IT_MASKS_ERRMIS LL_I3C_MISR_ERRMIS /*!< Error interrupt mask */ +#define HAL_I3C_ALL_COMMON_ITS_MASK (uint32_t)(LL_I3C_MISR_TXFNFMIS | LL_I3C_MISR_RXFNEMIS | \ + LL_I3C_MISR_FCMIS | LL_I3C_MISR_ERRMIS) +/** + * @} + */ + +/** @defgroup I3C_TARGET_INTERRUPT_MASKS I3C TARGET INTERRUPT MASKS + * @{ + */ +#define HAL_I3C_IT_MASKS_IBIENDMIS LL_I3C_MISR_IBIENDMIS /*!< IBI end interrupt mask */ +#define HAL_I3C_IT_MASKS_CRUPDMIS LL_I3C_MISR_CRUPDMIS /*!< controller-role update interrupt mask */ +#define HAL_I3C_IT_MASKS_WKPMIS LL_I3C_MISR_WKPMIS /*!< wakeup interrupt mask */ +#define HAL_I3C_IT_MASKS_GETMIS LL_I3C_MISR_GETMIS /*!< GETxxx CCC interrupt mask */ +#define HAL_I3C_IT_MASKS_STAMIS LL_I3C_MISR_STAMIS /*!< GETSTATUS CCC interrupt mask */ +#define HAL_I3C_IT_MASKS_DAUPDMIS LL_I3C_MISR_DAUPDMIS /*!< ENTDAA/RSTDAA/SETNEWDA CCC interrupt mask */ +#define HAL_I3C_IT_MASKS_MWLUPDMIS LL_I3C_MISR_MWLUPDMIS /*!< SETMWL CCC interrupt mask */ +#define HAL_I3C_IT_MASKS_MRLUPDMIS LL_I3C_MISR_MRLUPDMIS /*!< SETMRL CCC interrupt mask */ +#define HAL_I3C_IT_MASKS_RSTMIS LL_I3C_MISR_RSTMIS /*!< reset pattern interrupt mask */ +#define HAL_I3C_IT_MASKS_ASUPDMIS LL_I3C_MISR_ASUPDMIS /*!< ENTASx CCC interrupt mask */ +#define HAL_I3C_IT_MASKS_INTUPDMIS LL_I3C_MISR_INTUPDMIS /*!< ENEC/DISEC CCC interrupt mask */ +#define HAL_I3C_IT_MASKS_DEFMIS LL_I3C_MISR_DEFMIS /*!< DEFTGTS CCC interrupt mask */ +#define HAL_I3C_IT_GRPMIS LL_I3C_MISR_GRPMIS /*!< DEFGRPA CCC interrupt mask */ +#define HAL_I3C_ALL_TGT_ITS_MASK (uint32_t)(LL_I3C_MISR_IBIENDMIS | LL_I3C_MISR_CRUPDMIS | LL_I3C_MISR_WKPMIS | \ + LL_I3C_MISR_GETMIS | LL_I3C_MISR_STAMIS | LL_I3C_MISR_DAUPDMIS | \ + LL_I3C_MISR_MWLUPDMIS | LL_I3C_MISR_MRLUPDMIS | LL_I3C_MISR_RSTMIS | \ + LL_I3C_MISR_ASUPDMIS | LL_I3C_MISR_INTUPDMIS | LL_I3C_MISR_DEFMIS | \ + LL_I3C_MISR_GRPMIS) +/** + * @} + */ + +/** @defgroup I3C_CONTROLLER_INTERRUPT I3C CONTROLLER INTERRUPT + * @{ + */ +#define HAL_I3C_IT_CFNFMIS LL_I3C_MISR_CFNFMIS /*!< Control FIFO not full interrupt mask */ +#define HAL_I3C_IT_SFNEMIS LL_I3C_MISR_SFNEMIS /*!< Status FIFO not empty interrupt mask */ +#define HAL_I3C_IT_HJMIS LL_I3C_MISR_HJMIS /*!< Hot-join interrupt mask */ +#define HAL_I3C_IT_CRMIS LL_I3C_MISR_CRMIS /*!< Controller-role request interrupt mask */ +#define HAL_I3C_IT_IBIMIS LL_I3C_MISR_IBIMIS /*!< IBI request interrupt mask */ +#define HAL_I3C_IT_RXTGTENDMIS LL_I3C_MISR_RXTGTENDMIS /*!< Target-initiated read end interrupt mask */ +#define HAL_I3C_ALL_CTRL_ITS_MASK (uint32_t)(LL_I3C_MISR_CFNFMIS | LL_I3C_MISR_SFNEMIS | LL_I3C_MISR_HJMIS | \ + LL_I3C_MISR_CRMIS | LL_I3C_MISR_IBIMIS | LL_I3C_MISR_RXTGTENDMIS) +/** + * @} + */ +#endif /* I3C_MISR_CFNFMIS */ /** @defgroup I3C_BCR_IN_PAYLOAD I3C BCR IN PAYLOAD * @{ @@ -1230,6 +1303,8 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI2C_Ready(I3C_HandleTypeDef *hi3c, uint8_t devAddress, uint32_t trials, uint32_t timeout); +/* Controller patterns APIs */ +HAL_StatusTypeDef HAL_I3C_Ctrl_GeneratePatterns(I3C_HandleTypeDef *hi3c, uint32_t pattern, uint32_t timeout); /* Controller arbitration APIs */ HAL_StatusTypeDef HAL_I3C_Ctrl_GenerateArbitration(I3C_HandleTypeDef *hi3c, uint32_t timeout); @@ -1304,8 +1379,15 @@ HAL_StatusTypeDef HAL_I3C_Get_ENTDAA_Payload_Info(I3C_HandleTypeDef *hi3c, #define IS_I3C_ENTDAA_OPTION(__OPTION__) (((__OPTION__) == I3C_RSTDAA_THEN_ENTDAA) || \ ((__OPTION__) == I3C_ONLY_ENTDAA)) +#if defined(I3C_TIMINGR1_SDA_HD_1) +#define IS_I3C_SDAHOLDTIME_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_SDA_HOLD_TIME_0_5) || \ + ((__VALUE__) == HAL_I3C_SDA_HOLD_TIME_1_5) || \ + ((__VALUE__) == HAL_I3C_SDA_HOLD_TIME_2_5) || \ + ((__VALUE__) == HAL_I3C_SDA_HOLD_TIME_3_5)) +#else #define IS_I3C_SDAHOLDTIME_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_SDA_HOLD_TIME_0_5) || \ ((__VALUE__) == HAL_I3C_SDA_HOLD_TIME_1_5)) +#endif /* I3C_TIMINGR1_SDA_HD_1 */ #define IS_I3C_WAITTIME_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_0) || \ ((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_1) || \ @@ -1367,6 +1449,9 @@ HAL_StatusTypeDef HAL_I3C_Get_ENTDAA_Payload_Info(I3C_HandleTypeDef *hi3c, #define IS_I3C_DMADESTINATIONWORD_VALUE(__VALUE__) ((__VALUE__) == DMA_DEST_DATAWIDTH_WORD) #define I3C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__)) +#define IS_I3C_PATTERN(__PATTERN__) (((__PATTERN__) == HAL_I3C_TARGET_RESET_PATTERN) || \ + ((__PATTERN__) == HAL_I3C_HDR_EXIT_PATTERN)) + #define IS_I3C_RESET_PATTERN(__RSTPTRN__) (((__RSTPTRN__) == HAL_I3C_RESET_PATTERN_ENABLE) || \ ((__RSTPTRN__) == HAL_I3C_RESET_PATTERN_DISABLE)) /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_lptim.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_lptim.h index ab19e6f2f5..c3018f6b15 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_lptim.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_lptim.h @@ -386,12 +386,14 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ #define LPTIM_INPUT1SOURCE_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2, LPTIM3, LPTIM4, LPTIM5 and LPTIM6 when supported */ +#if !defined(STM32H553xx) && !defined(STM32H543xx) #if defined(COMP1) #define LPTIM_INPUT1SOURCE_COMP1 LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM1 and LPTIM2, LPTIM3, LPTIM4, LPTIM5 and LPTIM6 when supported */ #endif /* COMP1 */ #if defined(PLAY1) #define LPTIM_INPUT1SOURCE_PLAY1_OUT3 LPTIM_CFGR2_IN1SEL_1 /*!Instance->ISTR)\ &= (uint16_t)(~(__INTERRUPT__))) #endif /* defined (USB_DRD_FS) */ - /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pka.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pka.h index cadb56f2ea..4088776bf2 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pka.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pka.h @@ -26,6 +26,9 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_hal_def.h" +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +#include "stm32h5xx_ll_rng.h" +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ /** @addtogroup STM32H5xx_HAL_Driver * @{ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_play.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_play.h index fa5b2d027e..f57a91cedd 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_play.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_play.h @@ -47,8 +47,8 @@ extern "C" { */ #define HAL_PLAY_LUT_INPUT_SOURCE_NBR LL_PLAY_LUT_INPUT_SOURCE_NBR /*!< Number of input sources per lookup table */ -#define HAL_PLAY_LUT_TRUTH_TABLE_VALUE_MAX (LL_PLAY_LUT_TRUTH_TABLE_VALUE_MAX) /*!< Maximal Lookup table value */ -#define HAL_PLAY_INPUT_FILTER_WIDTH_VALUE_MAX (LL_PLAY_INPUT_FILTER_WIDTH_VALUE_MAX) /*!< Maximal pulse width value */ +#define HAL_PLAY_LUT_TRUTH_TABLE_VALUE_MAX (LL_PLAY_LUT_TRUTH_TABLE_VALUE_MAX) /*!< Maximum Lookup table value */ +#define HAL_PLAY_INPUT_FILTER_WIDTH_VALUE_MAX (LL_PLAY_INPUT_FILTER_WIDTH_VALUE_MAX) /*!< Maximum pulse width value */ /** * @} @@ -61,6 +61,10 @@ extern "C" { #define HAL_PLAY_ERROR_NONE (0U) /*!< No error */ #define HAL_PLAY_ERROR_INVALID_PARAM (1UL << 1U) /*!< Invalid parameter */ #define HAL_PLAY_ERROR_INVALID_CALLBACK (1UL << 2U) /*!< Invalid Callback ID */ +#if defined(GENERATOR_SECURITY_RIF_SUPPORTED) +#define HAL_PLAY_ERROR_MUTEX_LOCKED (1UL << 5U) /*!< PLAY Mutex taken by another instance */ +#define HAL_PLAY_ERROR_MUTEX_NOT_LOCKED (1UL << 6U) /*!< PLAY Mutex not taken */ +#endif /* GENERATOR_SECURITY_RIF_SUPPORTED */ /** * @} @@ -112,7 +116,7 @@ extern "C" { #define HAL_PLAY_LUT13_OUT_DIRECT LL_PLAY_LUT13_OUT_DIRECT /*!< PLAY direct output of LUT 13 */ #define HAL_PLAY_LUT14_OUT_DIRECT LL_PLAY_LUT14_OUT_DIRECT /*!< PLAY direct output of LUT 14 */ #define HAL_PLAY_LUT15_OUT_DIRECT LL_PLAY_LUT15_OUT_DIRECT /*!< PLAY direct output of LUT 15 */ -#define HAL_PLAY_LUT_ALL_OUT_DIRECT LL_PLAY_LUT_ALL_OUT_DIRECT /*!< PLAY direct output of LUTs 0 to 15 */ +#define HAL_PLAY_LUT_ALL_OUT_DIRECT LL_PLAY_LUT_ALL_OUT_DIRECT /*!< PLAY direct outputs of LUTs 0 to 15 */ #define HAL_PLAY_LUT0_OUT_REGISTERED LL_PLAY_LUT0_OUT_REGISTERED /*!< PLAY registered output of LUT 0 */ #define HAL_PLAY_LUT1_OUT_REGISTERED LL_PLAY_LUT1_OUT_REGISTERED /*!< PLAY registered output of LUT 1 */ @@ -154,7 +158,10 @@ extern "C" { * @} */ -/* Exported macros -----------------------------------------------------------*/ +/** + * @} + */ + /* Exported types ------------------------------------------------------------*/ /** @defgroup PLAY_Exported_Types PLAY Exported Types * @{ @@ -164,11 +171,6 @@ extern "C" { * @{ */ -/** - * @brief HAL PLAY instance - */ - - /** * @brief PLAY Polling Mode on Lookup Table Output Edge Trigger enumeration */ @@ -491,24 +493,24 @@ typedef enum HAL_PLAY_LUT_INPUT_FILTER14 = LL_PLAY_LUT_SOURCE_FILTER14, /*!< PLAY input signal IN14 selected as input source */ HAL_PLAY_LUT_INPUT_FILTER15 = LL_PLAY_LUT_SOURCE_FILTER15, /*!< PLAY input signal IN15 selected as input source */ - HAL_PLAY_LUT_INPUT_SWTRIG0 = LL_PLAY_LUT_SOURCE_SWTRIG0, /*!< PLAY software trigger input 0 selected as input source */ - HAL_PLAY_LUT_INPUT_SWTRIG1 = LL_PLAY_LUT_SOURCE_SWTRIG1, /*!< PLAY software trigger input 1 selected as input source */ - HAL_PLAY_LUT_INPUT_SWTRIG2 = LL_PLAY_LUT_SOURCE_SWTRIG2, /*!< PLAY software trigger input 2 selected as input source */ - HAL_PLAY_LUT_INPUT_SWTRIG3 = LL_PLAY_LUT_SOURCE_SWTRIG3, /*!< PLAY software trigger input 3 selected as input source */ - HAL_PLAY_LUT_INPUT_SWTRIG4 = LL_PLAY_LUT_SOURCE_SWTRIG4, /*!< PLAY software trigger input 4 selected as input source */ - HAL_PLAY_LUT_INPUT_SWTRIG5 = LL_PLAY_LUT_SOURCE_SWTRIG5, /*!< PLAY software trigger input 5 selected as input source */ - HAL_PLAY_LUT_INPUT_SWTRIG6 = LL_PLAY_LUT_SOURCE_SWTRIG6, /*!< PLAY software trigger input 6 selected as input source */ - HAL_PLAY_LUT_INPUT_SWTRIG7 = LL_PLAY_LUT_SOURCE_SWTRIG7, /*!< PLAY software trigger input 7 selected as input source */ - HAL_PLAY_LUT_INPUT_SWTRIG8 = LL_PLAY_LUT_SOURCE_SWTRIG8, /*!< PLAY software trigger input 8 selected as input source */ - HAL_PLAY_LUT_INPUT_SWTRIG9 = LL_PLAY_LUT_SOURCE_SWTRIG9, /*!< PLAY software trigger input 9 selected as input source */ - HAL_PLAY_LUT_INPUT_SWTRIG10 = LL_PLAY_LUT_SOURCE_SWTRIG10, /*!< PLAY software trigger input 10 selected as input source */ - HAL_PLAY_LUT_INPUT_SWTRIG11 = LL_PLAY_LUT_SOURCE_SWTRIG11, /*!< PLAY software trigger input 11 selected as input source */ - HAL_PLAY_LUT_INPUT_SWTRIG12 = LL_PLAY_LUT_SOURCE_SWTRIG12, /*!< PLAY software trigger input 12 selected as input source */ - HAL_PLAY_LUT_INPUT_SWTRIG13 = LL_PLAY_LUT_SOURCE_SWTRIG13, /*!< PLAY software trigger input 13 selected as input source */ - HAL_PLAY_LUT_INPUT_SWTRIG14 = LL_PLAY_LUT_SOURCE_SWTRIG14, /*!< PLAY software trigger input 14 selected as input source */ - HAL_PLAY_LUT_INPUT_SWTRIG15 = LL_PLAY_LUT_SOURCE_SWTRIG15, /*!< PLAY software trigger input 15 selected as input source */ - - HAL_PLAY_LUT_INPUT_DEFAULT = LL_PLAY_LUT_SOURCE_SWTRIG15, /*!< Default value */ + HAL_PLAY_LUT_INPUT_SWTRIG0 = LL_PLAY_LUT_SOURCE_SWTRIG0, /*!< PLAY software trigger input 0 selected as input source */ + HAL_PLAY_LUT_INPUT_SWTRIG1 = LL_PLAY_LUT_SOURCE_SWTRIG1, /*!< PLAY software trigger input 1 selected as input source */ + HAL_PLAY_LUT_INPUT_SWTRIG2 = LL_PLAY_LUT_SOURCE_SWTRIG2, /*!< PLAY software trigger input 2 selected as input source */ + HAL_PLAY_LUT_INPUT_SWTRIG3 = LL_PLAY_LUT_SOURCE_SWTRIG3, /*!< PLAY software trigger input 3 selected as input source */ + HAL_PLAY_LUT_INPUT_SWTRIG4 = LL_PLAY_LUT_SOURCE_SWTRIG4, /*!< PLAY software trigger input 4 selected as input source */ + HAL_PLAY_LUT_INPUT_SWTRIG5 = LL_PLAY_LUT_SOURCE_SWTRIG5, /*!< PLAY software trigger input 5 selected as input source */ + HAL_PLAY_LUT_INPUT_SWTRIG6 = LL_PLAY_LUT_SOURCE_SWTRIG6, /*!< PLAY software trigger input 6 selected as input source */ + HAL_PLAY_LUT_INPUT_SWTRIG7 = LL_PLAY_LUT_SOURCE_SWTRIG7, /*!< PLAY software trigger input 7 selected as input source */ + HAL_PLAY_LUT_INPUT_SWTRIG8 = LL_PLAY_LUT_SOURCE_SWTRIG8, /*!< PLAY software trigger input 8 selected as input source */ + HAL_PLAY_LUT_INPUT_SWTRIG9 = LL_PLAY_LUT_SOURCE_SWTRIG9, /*!< PLAY software trigger input 9 selected as input source */ + HAL_PLAY_LUT_INPUT_SWTRIG10 = LL_PLAY_LUT_SOURCE_SWTRIG10, /*!< PLAY software trigger input 10 selected as input source */ + HAL_PLAY_LUT_INPUT_SWTRIG11 = LL_PLAY_LUT_SOURCE_SWTRIG11, /*!< PLAY software trigger input 11 selected as input source */ + HAL_PLAY_LUT_INPUT_SWTRIG12 = LL_PLAY_LUT_SOURCE_SWTRIG12, /*!< PLAY software trigger input 12 selected as input source */ + HAL_PLAY_LUT_INPUT_SWTRIG13 = LL_PLAY_LUT_SOURCE_SWTRIG13, /*!< PLAY software trigger input 13 selected as input source */ + HAL_PLAY_LUT_INPUT_SWTRIG14 = LL_PLAY_LUT_SOURCE_SWTRIG14, /*!< PLAY software trigger input 14 selected as input source */ + HAL_PLAY_LUT_INPUT_SWTRIG15 = LL_PLAY_LUT_SOURCE_SWTRIG15, /*!< PLAY software trigger input 15 selected as input source */ + + HAL_PLAY_LUT_INPUT_DEFAULT = LL_PLAY_LUT_SOURCE_SWTRIG15, /*!< Default value */ } HAL_PLAY_LUT_InputSourceTypeDef; /** @@ -639,32 +641,6 @@ typedef struct * @} */ -/** - * @} - */ - -/** @defgroup PLAY_ACCESS_CONTROL PLAY Access Control - * @{ - */ - -/** - * @brief PLAY Access Control TrustZone enumeration - */ -typedef enum -{ - HAL_PLAY_TZ_REG_UNPROTECTED = 0U, /*!< All registers are unprotected */ - HAL_PLAY_TZ_CONFIG_REG_PROTECTED = 1U, /*!< Only config registers are protected */ - HAL_PLAY_TZ_ALL_REG_PROTECTED = 3U, /*!< All registers are protected */ -} HAL_PLAY_TrustZone_AccessControlTypeDef; - - -typedef struct -{ - HAL_PLAY_TrustZone_AccessControlTypeDef SecureAccess; /*!< PLAY Secure access configuration */ - HAL_PLAY_TrustZone_AccessControlTypeDef PrivilegeAccess; /*!< PLAY Privilege access configuration */ -} HAL_PLAY_AccessControlConfTypeDef; - - /** * @} */ @@ -693,12 +669,12 @@ typedef struct __HAL_PLAY_HandleTypeDef typedef struct #endif /* USE_HAL_PLAY_REGISTER_CALLBACKS */ { - PLAY_TypeDef *instance; /*!< Register base address */ + PLAY_TypeDef *instance; /*!< Register base address */ - __IO HAL_PLAY_StateTypeDef global_state; /*!< PLAY peripheral state */ + __IO HAL_PLAY_StateTypeDef State; /*!< PLAY peripheral state */ - __IO uint32_t last_error_codes; /*!< Errors limited to the last process. - This parameter can be a combination of @ref PLAY_Error_Codes */ + __IO uint32_t ErrorCode; /*!< Errors codes of the peripheral. + This parameter can be a combination of @ref PLAY_Error_Codes */ #if (USE_HAL_PLAY_REGISTER_CALLBACKS == 1) void (* SWTriggerWriteCpltCallback)(struct __HAL_PLAY_HandleTypeDef *hplay); @@ -737,6 +713,42 @@ typedef void (*pPLAY_LUTOutputCallbackTypeDef)(HAL_PLAY_HandleTypeDef *hplay, ui * @} */ +/** + * @} + */ + +/** @defgroup PLAY_Attributes PLAY security/privilege attributes + * @{ + */ + +/** + * @brief Security access level attribute + */ +typedef enum +{ + HAL_PLAY_NSEC = LL_PLAY_ATTR_NSEC, /*!< Non-secure access level attribute */ + HAL_PLAY_SEC = LL_PLAY_ATTR_SEC /*!< Secure access level attribute */ +} HAL_PLAY_SecAttrTypeDef; + +/** + * @brief Privileged access level attribute + */ +typedef enum +{ + HAL_PLAY_NPRIV = LL_PLAY_ATTR_NPRIV, /*!< Non-privileged access level attribute */ + HAL_PLAY_PRIV = LL_PLAY_ATTR_PRIV /*!< Privileged access level attribute */ +} HAL_PLAY_PrivAttrTypeDef; + +/** + * @brief PLAY attributes configuration items + */ + +#define HAL_PLAY_SEC_ITEM_CONFIG LL_PLAY_SEC_ITEM_CONFIG /*!< PLAY configuration registers items */ +#define HAL_PLAY_SEC_ITEM_ALL LL_PLAY_SEC_ITEM_ALL /*!< All PLAY registers items */ + +#define HAL_PLAY_PRIV_ITEM_CONFIG LL_PLAY_PRIV_ITEM_CONFIG /*!< PLAY configuration registers items */ +#define HAL_PLAY_PRIV_ITEM_ALL LL_PLAY_PRIV_ITEM_ALL /*!< All PLAY registers items */ + /** * @} */ @@ -753,12 +765,12 @@ typedef void (*pPLAY_LUTOutputCallbackTypeDef)(HAL_PLAY_HandleTypeDef *hplay, ui #if (USE_HAL_PLAY_REGISTER_CALLBACKS == 1) #define __HAL_PLAY_RESET_HANDLE_STATE(__HANDLE__) \ do { \ - (__HANDLE__)->global_state = HAL_PLAY_STATE_RESET; \ + (__HANDLE__)->State = HAL_PLAY_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ } while (0U) #else -#define __HAL_PLAY_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->global_state = HAL_PLAY_STATE_RESET) +#define __HAL_PLAY_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PLAY_STATE_RESET) #endif /* USE_HAL_PLAY_REGISTER_CALLBACKS */ /** @@ -776,6 +788,7 @@ typedef void (*pPLAY_LUTOutputCallbackTypeDef)(HAL_PLAY_HandleTypeDef *hplay, ui HAL_StatusTypeDef HAL_PLAY_Init(HAL_PLAY_HandleTypeDef *hplay); HAL_StatusTypeDef HAL_PLAY_DeInit(HAL_PLAY_HandleTypeDef *hplay); + void HAL_PLAY_MspInit(HAL_PLAY_HandleTypeDef *hplay); void HAL_PLAY_MspDeInit(HAL_PLAY_HandleTypeDef *hplay); @@ -804,32 +817,33 @@ HAL_StatusTypeDef HAL_PLAY_OUTPUT_GetConfig(HAL_PLAY_HandleTypeDef *hplay, HAL_P uint32_t size_array); /* PLAY Configuration unitary functions for Input *****************************/ -HAL_StatusTypeDef HAL_PLAY_INPUT_SetSource(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_IN_SourceTypeDef source); +HAL_StatusTypeDef HAL_PLAY_INPUT_SetSource(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_IN_SourceTypeDef source); HAL_PLAY_IN_SourceTypeDef HAL_PLAY_INPUT_GetSource(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_INTypeDef mux_id); -HAL_StatusTypeDef HAL_PLAY_INPUT_SetMinPulseWidth(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_INTypeDef mux_id, +HAL_StatusTypeDef HAL_PLAY_INPUT_SetMinPulseWidth(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_INTypeDef mux_id, uint32_t width); uint32_t HAL_PLAY_INPUT_GetMinPulseWidth(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_INTypeDef mux_id); -HAL_StatusTypeDef HAL_PLAY_INPUT_SetEdgeDetectionMode(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_INTypeDef mux_id, +HAL_StatusTypeDef HAL_PLAY_INPUT_SetEdgeDetectionMode(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_INTypeDef mux_id, HAL_PLAY_EdgeDetectionModeTypeDef mode); HAL_PLAY_EdgeDetectionModeTypeDef HAL_PLAY_INPUT_GetEdgeDetectionMode(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_INTypeDef mux_id); /* PLAY Configuration unitary functions for Lookup table *********************/ -HAL_StatusTypeDef HAL_PLAY_LUT_SetTruthTable(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut, +HAL_StatusTypeDef HAL_PLAY_LUT_SetTruthTable(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut, uint32_t truth_table_value); uint32_t HAL_PLAY_LUT_GetTruthTable(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut); -HAL_StatusTypeDef HAL_PLAY_LUT_SetSource(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut, +HAL_StatusTypeDef HAL_PLAY_LUT_SetSource(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut, HAL_PLAY_LUT_InputTypeDef lut_input, HAL_PLAY_LUT_InputSourceTypeDef source); HAL_PLAY_LUT_InputSourceTypeDef HAL_PLAY_LUT_GetSource(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut, HAL_PLAY_LUT_InputTypeDef lut_input); -HAL_StatusTypeDef HAL_PLAY_LUT_SetClockGateSource(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut, +HAL_StatusTypeDef HAL_PLAY_LUT_SetClockGateSource(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut, HAL_PLAY_LUT_ClkGateSourceTypeDef source); HAL_PLAY_LUT_ClkGateSourceTypeDef HAL_PLAY_LUT_GetClockGateSource(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut_id); /* PLAY Configuration unitary functions for Output ****************************/ -HAL_StatusTypeDef HAL_PLAY_OUTPUT_SetSource(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_OUTTypeDef mux_id, uint32_t source); +HAL_StatusTypeDef HAL_PLAY_OUTPUT_SetSource(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_OUTTypeDef mux_id, + uint32_t source); uint32_t HAL_PLAY_OUTPUT_GetSource(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_OUTTypeDef mux_id); /** @@ -865,8 +879,8 @@ HAL_StatusTypeDef HAL_PLAY_LUT_PollForEdgeTrigger(HAL_PLAY_HandleTypeDef *hplay, uint32_t timeout_ms); /* PLAY APIs to manage interrupts on lookup table output */ -HAL_StatusTypeDef HAL_PLAY_LUT_EnableIT(HAL_PLAY_HandleTypeDef *hplay, uint32_t its_mask); -HAL_StatusTypeDef HAL_PLAY_LUT_DisableIT(HAL_PLAY_HandleTypeDef *hplay, uint32_t its_mask); +HAL_StatusTypeDef HAL_PLAY_LUT_EnableIT(const HAL_PLAY_HandleTypeDef *hplay, uint32_t its_mask); +HAL_StatusTypeDef HAL_PLAY_LUT_DisableIT(const HAL_PLAY_HandleTypeDef *hplay, uint32_t its_mask); uint32_t HAL_PLAY_LUT_GetIT(const HAL_PLAY_HandleTypeDef *hplay); /** @@ -877,12 +891,13 @@ uint32_t HAL_PLAY_LUT_GetIT(const HAL_PLAY_HandleTypeDef *hplay); * @{ */ -HAL_StatusTypeDef HAL_PLAY_WriteSWTrigger(HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_triggers, +HAL_StatusTypeDef HAL_PLAY_WriteSWTrigger(const HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_triggers, HAL_PLAY_SWTriggerStateTypeDef state, uint32_t timeout_ms); -HAL_StatusTypeDef HAL_PLAY_WriteSWTrigger_IT(HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_triggers, +HAL_StatusTypeDef HAL_PLAY_WriteSWTrigger_IT(const HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_triggers, HAL_PLAY_SWTriggerStateTypeDef state); -HAL_StatusTypeDef HAL_PLAY_ToggleSWTrigger(HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_triggers, uint32_t timeout_ms); -HAL_StatusTypeDef HAL_PLAY_ToggleSWTrigger_IT(HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_triggers); +HAL_StatusTypeDef HAL_PLAY_ToggleSWTrigger(const HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_triggers, + uint32_t timeout_ms); +HAL_StatusTypeDef HAL_PLAY_ToggleSWTrigger_IT(const HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_triggers); HAL_PLAY_SWTriggerStateTypeDef HAL_PLAY_ReadSWTrigger(const HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_trig); /** @@ -927,14 +942,19 @@ uint32_t HAL_PLAY_GetError(const HAL_PLAY_HandleTypeDef *hplay); * @} */ -/** @defgroup PLAY_Exported_Functions_Group8 Access control functions +/** @defgroup PLAY_Exported_Functions_Group8 Security and privileged access levels attributes management * @{ */ -HAL_StatusTypeDef HAL_PLAY_ConfigAttributes(HAL_PLAY_HandleTypeDef *hplay, - const HAL_PLAY_AccessControlConfTypeDef *p_config); -HAL_StatusTypeDef HAL_PLAY_GetConfigAttributes(HAL_PLAY_HandleTypeDef *hplay, - HAL_PLAY_AccessControlConfTypeDef *p_config); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +HAL_StatusTypeDef HAL_PLAY_SetSecAttr(const HAL_PLAY_HandleTypeDef *hplay, uint32_t item, + HAL_PLAY_SecAttrTypeDef sec_attr); +#endif /* __ARM_FEATURE_CMSE */ +HAL_PLAY_SecAttrTypeDef HAL_PLAY_GetSecAttr(const HAL_PLAY_HandleTypeDef *hplay, uint32_t item); + +HAL_StatusTypeDef HAL_PLAY_SetPrivAttr(const HAL_PLAY_HandleTypeDef *hplay, uint32_t item, + HAL_PLAY_PrivAttrTypeDef priv_attr); +HAL_PLAY_PrivAttrTypeDef HAL_PLAY_GetPrivAttr(const HAL_PLAY_HandleTypeDef *hplay, uint32_t item); /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h index 0f72572b76..27e86f2c38 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h @@ -2843,11 +2843,13 @@ typedef struct * This parameter can be one of the following values: * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_PLL2Q PLL2Q Clock selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_PLL3Q PLL3Q Clock selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_PLL3Q PLL3Q Clock selected as UART4 clock (*) * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_CSI CSI selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock * @retval None + * + * (*) : Not available for stm32h553xx and stm32h543xx family lines. */ #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) @@ -2856,10 +2858,12 @@ typedef struct * @retval The clock source can be one of the following values: * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_PLL2Q PLL2Q Clock selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_PLL3Q PLL3Q Clock selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_PLL3Q PLL3Q Clock selected as UART4 clock (*) * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_CSI CSI selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock + * + * (*) : Not available for stm32h553xx and stm32h543xx family lines. */ #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART4SEL))) #endif /* UART4 */ @@ -2871,11 +2875,13 @@ typedef struct * This parameter can be one of the following values: * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_PLL2Q PLL2Q Clock selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_PLL3Q PLL3Q Clock selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_PLL3Q PLL3Q Clock selected as UART5 clock (*) * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_CSI CSI selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock * @retval None + * + * (*) : Not available for stm32h553xx and stm32h543xx family lines. */ #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) @@ -2884,10 +2890,12 @@ typedef struct * @retval The clock source can be one of the following values: * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_PLL2Q PLL2Q Clock selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_PLL3Q PLL3Q Clock selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_PLL3Q PLL3Q Clock selected as UART5 clock (*) * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_CSI CSI selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock + * + * (*) : Not available for stm32h553xx and stm32h543xx family lines. */ #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART5SEL))) #endif /* UART5 */ @@ -2899,11 +2907,13 @@ typedef struct * This parameter can be one of the following values: * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK2 selected as USART6 clock * @arg @ref RCC_USART6CLKSOURCE_PLL2Q PLL2Q selected as USART6 clock - * @arg @ref RCC_USART6CLKSOURCE_PLL3Q PLL3Q selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_PLL3Q PLL3Q selected as USART6 clock (*) * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock * @arg @ref RCC_USART6CLKSOURCE_CSI CSI selected as USART6 clock * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock * @retval None + * + * (*) : Not available for stm32h553xx and stm32h543xx family lines. */ #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) @@ -2912,10 +2922,12 @@ typedef struct * @retval The clock source can be one of the following values: * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK1 selected as USART6 clock * @arg @ref RCC_USART6CLKSOURCE_PLL2Q PLL2Q selected as USART6 clock - * @arg @ref RCC_USART6CLKSOURCE_PLL3Q PLL3Q selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_PLL3Q PLL3Q selected as USART6 clock (*) * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock * @arg @ref RCC_USART6CLKSOURCE_CSI CSI selected as USART6 clock * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock + * + * (*) : Not available for stm32h553xx and stm32h543xx family lines. */ #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART6SEL))) #endif /* USART6 */ @@ -2927,11 +2939,13 @@ typedef struct * This parameter can be one of the following values: * @arg @ref RCC_UART7CLKSOURCE_PCLK1 PCLK1 selected as UART7 clock * @arg @ref RCC_UART7CLKSOURCE_PLL2Q PLL2Q selected as UART7 clock - * @arg @ref RCC_UART7CLKSOURCE_PLL3Q PLL3Q selected as UART7 clock + * @arg @ref RCC_UART7CLKSOURCE_PLL3Q PLL3Q selected as UART7 clock (*) * @arg @ref RCC_UART7CLKSOURCE_HSI HSI selected as UART7 clock * @arg @ref RCC_UART7CLKSOURCE_CSI CSI selected as UART7 clock * @arg @ref RCC_UART7CLKSOURCE_LSE LSE selected as UART7 clock * @retval None + * + * (*) : Not available for stm32h553xx and stm32h543xx family lines. */ #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) @@ -2940,10 +2954,12 @@ typedef struct * @retval The clock source can be one of the following values: * @arg @ref RCC_UART7CLKSOURCE_PCLK1 PCLK1 selected as UART7 clock * @arg @ref RCC_UART7CLKSOURCE_PLL2Q PLL2Q selected as UART7 clock - * @arg @ref RCC_UART7CLKSOURCE_PLL3Q PLL3Q selected as UART7 clock + * @arg @ref RCC_UART7CLKSOURCE_PLL3Q PLL3Q selected as UART7 clock (*) * @arg @ref RCC_UART7CLKSOURCE_HSI HSI selected as UART7 clock * @arg @ref RCC_UART7CLKSOURCE_CSI CSI selected as UART7 clock * @arg @ref RCC_UART7CLKSOURCE_LSE LSE selected as UART7 clock + * + * (*) : Not available for stm32h553xx and stm32h543xx family lines. */ #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART7SEL))) #endif /* UART5 */ @@ -2955,11 +2971,13 @@ typedef struct * This parameter can be one of the following values: * @arg @ref RCC_UART8CLKSOURCE_PCLK1 PCLK1 selected as UART8 clock * @arg @ref RCC_UART8CLKSOURCE_PLL2Q PLL2Q selected as UART8 clock - * @arg @ref RCC_UART8CLKSOURCE_PLL3Q PLL3Q selected as UART8 clock + * @arg @ref RCC_UART8CLKSOURCE_PLL3Q PLL3Q selected as UART8 clock (*) * @arg @ref RCC_UART8CLKSOURCE_HSI HSI selected as UART8 clock * @arg @ref RCC_UART8CLKSOURCE_CSI CSI selected as UART8 clock * @arg @ref RCC_UART8CLKSOURCE_LSE LSE selected as UART8 clock * @retval None + * + * (*) : Not available for stm32h553xx and stm32h543xx family lines. */ #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) @@ -2968,10 +2986,12 @@ typedef struct * @retval The clock source can be one of the following values: * @arg @ref RCC_UART8CLKSOURCE_PCLK1 PCLK1 selected as UART8 clock * @arg @ref RCC_UART8CLKSOURCE_PLL2Q PLL2Q selected as UART8 clock - * @arg @ref RCC_UART8CLKSOURCE_PLL3Q PLL3Q selected as UART8 clock + * @arg @ref RCC_UART8CLKSOURCE_PLL3Q PLL3Q selected as UART8 clock (*) * @arg @ref RCC_UART8CLKSOURCE_HSI HSI selected as UART8 clock * @arg @ref RCC_UART8CLKSOURCE_CSI CSI selected as UART8 clock * @arg @ref RCC_UART8CLKSOURCE_LSE LSE selected as UART8 clock + * + * (*) : Not available for stm32h553xx and stm32h543xx family lines. */ #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART8SEL))) #endif /* UART8 */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rng_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rng_ex.h index b5f275a480..f2bfe7adfa 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rng_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rng_ex.h @@ -26,6 +26,9 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_hal_def.h" +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +#include "stm32h5xx_ll_rng.h" +#endif /* RNG_HTSR0_RPERRX) || RNG_HTSR1_ADERRX */ /** @addtogroup STM32H5xx_HAL_Driver * @{ @@ -56,7 +59,7 @@ typedef struct uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can be a value of @ref RNGEx_Clock_Divider_Factor */ - uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a + uint32_t NistCompliance; /*!< NIST compliance configuration.This parameter can be a value of @ref RNGEx_NIST_Compliance */ uint32_t AutoReset; /*!< automatic reset When a noise source error occurs value of @ref RNGEx_Auto_Reset */ @@ -115,8 +118,8 @@ typedef struct /** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ -#define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ -#define RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */ +#define RNG_NIST_COMPLIANT (0x00000000UL) /*!< Default NIST compliant configuration*/ +#define RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST compliant configuration */ /** * @} @@ -188,13 +191,23 @@ typedef struct #define IS_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == RNG_NIST_COMPLIANT) || \ ((__NIST_COMPLIANCE__) == RNG_CUSTOM_NIST)) +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +#define IS_RNG_CONFIG1(__CONFIG1__) ((__CONFIG1__) <= 0xFFUL) +#else #define IS_RNG_CONFIG1(__CONFIG1__) ((__CONFIG1__) <= 0x3FUL) +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX) */ #define IS_RNG_CONFIG2(__CONFIG2__) ((__CONFIG2__) <= 0x07UL) #define IS_RNG_CONFIG3(__CONFIG3__) ((__CONFIG3__) <= 0xFUL) #define IS_RNG_ARDIS(__ARDIS__) (((__ARDIS__) == RNG_ARDIS_ENABLE) || \ ((__ARDIS__) == RNG_ARDIS_DISABLE)) +#if defined(RNG_HTCR3_HTCFG) +#define IS_RNG_HTCR_INDEX(__INDEX__) (((__INDEX__) == 0x01U) || \ + ((__INDEX__) == 0x02U) || \ + ((__INDEX__) == 0x03U)) +#define IS_RNG_HTCR_VALUE(__VALUE__) ((__VALUE__) <= 0x3FFFF) +#endif /* RNG_HTCR0_HTCFG || RNG_HTCR1_HTCFG || RNG_HTCR2_HTCFG || RNG_HTCR3_HTCFG */ /** @@ -230,6 +243,9 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); +#if defined(RNG_HTCR3_HTCFG) +HAL_StatusTypeDef HAL_RNGEx_SetHealthFactorConfig(RNG_HandleTypeDef *hrng, uint32_t htcr_idx, uint32_t htcr_value); +#endif /* RNG_HTCR0_HTCFG || RNG_HTCR1_HTCFG || RNG_HTCR2_HTCFG || RNG_HTCR3_HTCFG */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc_ex.h index 1a52499574..70156146c0 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc_ex.h @@ -505,6 +505,24 @@ typedef struct * @} */ +#if defined(TAMP_OR_IN2_RMP) || defined(TAMP_OR_IN3_RMP) || defined(TAMP_OR_IN4_RMP) || \ + defined(TAMP_OR_OUT3_RMP) || defined(TAMP_OR_OUT5_RMP) +/** @defgroup RTCEx_Tamper_Remap RTCEx Tamper Remap + * @{ + */ +#define RTC_TAMPER_RMP_TAMP_IN2_PA0_TO_PI8 TAMP_OR_IN2_RMP +#define RTC_TAMPER_RMP_TAMP_IN3_PC1_TO_PE6 TAMP_OR_IN3_RMP +#define RTC_TAMPER_RMP_TAMP_IN4_PA2_TO_PI11 TAMP_OR_IN4_RMP +#define RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PI8 TAMP_OR_OUT3_RMP_0 +#define RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PE3 TAMP_OR_OUT3_RMP_1 +#define RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PA2 TAMP_OR_OUT3_RMP +#define RTC_TAMPER_RMP_TAMP_OUT5_PI11_TO_PC1 TAMP_OR_OUT5_RMP +/** + * @} + */ +#endif /* defined(TAMP_OR_IN2_RMP) || defined(TAMP_OR_IN3_RMP) || defined(TAMP_OR_IN4_RMP) || \ + defined(TAMP_OR_OUT3_RMP) || defined(TAMP_OR_OUT5_RMP) */ + /** @defgroup RTCEx_Tamper_Interrupt RTCEx Tamper Interrupt * @{ @@ -1323,6 +1341,41 @@ typedef struct #define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 &= ~(__TAMPER__)) +#if defined(TAMP_OR_IN2_RMP) || defined(TAMP_OR_IN3_RMP) || defined(TAMP_OR_IN4_RMP) || \ + defined(TAMP_OR_OUT3_RMP) || defined(TAMP_OR_OUT5_RMP) +/** + * @brief Enable remap of TAMP INx on a different pin. + * @param __REMAP__ specifies the RTC Tamper remap to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_RMP_TAMP_IN2_PA0_TO_PI8 + * @arg RTC_TAMPER_RMP_TAMP_IN3_PC1_TO_PE6 + * @arg RTC_TAMPER_RMP_TAMP_IN4_PA2_TO_PI11 + * @arg RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PI8 + * @arg RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PE3 + * @arg RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PA2 + * @arg RTC_TAMPER_RMP_TAMP_OUT5_PI11_TO_PC1 + * @retval None + */ +#define __HAL_RTC_TAMPER_REMAP_ENABLE(__REMAP__) (TAMP->OR |= (__REMAP__)) + +/** + * @brief Disable remap of TAMP INx on a different pin. + * @param __REMAP__ specifies the RTC Tamper remap to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_RMP_TAMP_IN2_PA0_TO_PI8 + * @arg RTC_TAMPER_RMP_TAMP_IN3_PC1_TO_PE6 + * @arg RTC_TAMPER_RMP_TAMP_IN4_PA2_TO_PI11 + * @arg RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PI8 + * @arg RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PE3 + * @arg RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PA2 + * @arg RTC_TAMPER_RMP_TAMP_OUT5_PI11_TO_PC1 + * @retval None + */ +#define __HAL_RTC_TAMPER_REMAP_DISABLE(__REMAP__) (TAMP->OR &= ~(__REMAP__)) +#endif /* defined(TAMP_OR_IN2_RMP) || defined(TAMP_OR_IN3_RMP) || defined(TAMP_OR_IN4_RMP) || \ + defined(TAMP_OR_OUT3_RMP) || defined(TAMP_OR_OUT5_RMP) */ + + /**************************************************************************************************/ /** * @brief Enable the TAMP Tamper interrupt. diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h index 5f8468c285..79e3f1a913 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h @@ -298,6 +298,50 @@ HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef * (__CLOCKSOURCE__) = 0U; \ } \ } while(0U) +#elif (defined(STM32H553xx) || defined(STM32H543xx)) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART6; \ + } \ + else if((__HANDLE__)->Instance == UART7) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART7; \ + } \ + else if((__HANDLE__)->Instance == UART8) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART8; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) #else #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h index 3792270bec..35601c4387 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h @@ -1014,6 +1014,110 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) +#elif (defined(STM32H553xx) || defined(STM32H543xx)) +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART1CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART2CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART3CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ + case RCC_USART6CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART6CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART6CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART6CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART6CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) #else #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h index a29cc086e3..68cad4e61d 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h @@ -935,20 +935,26 @@ typedef struct | ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */ #define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP \ | ADC_CHANNEL_19_BITFIELD) /*!< ADC channel ADCx_IN19 */ -#if defined (ADC2) || defined(ADC3) +#if defined (ADC2) #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. - On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC1. */ + On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC1. + On STM32H553xx/H543xx/H5Exxx/H5Fxxx, ADC channel available only on ADC + instances: ADC1 and ADC3 */ #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to internal temperature sensor. - On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC1. */ + On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC1. + On STM32H553xx/H543xx/H5Exxx/H5Fxxx, ADC channel available only on ADC + instances: ADC1 and ADC3 */ #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have channel voltage always below Vdda. - On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC2. */ + On STM32H563xx/573xx/H553xx/H543xx/H5Exxx/H5Fxxx, ADC channel available only + on ADC instance: ADC2. */ #define LL_ADC_CHANNEL_VDDCORE (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to Vddcore. - On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC2. */ + On STM32H563xx/573xx/H553xx/H543xx/H5Exxx/H5Fxxx, ADC channel available only + on ADC instance: ADC2. */ #if defined(ADC3) #define LL_ADC_CHANNEL_VBAT_ADC3 (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 @@ -958,9 +964,11 @@ typedef struct connected to Vddcore. Channel specific to ADC3 */ #define LL_ADC_CHANNEL_DAC1_CH1 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel -connected to DAC1 channel 1, channel specific to ADC2 */ + connected to DAC1 channel 1. + channel specific to ADC3 */ #define LL_ADC_CHANNEL_DAC1_CH2 (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel -connected to DAC1 channel 1, channel specific to ADC2 */ + connected to DAC1 channel 2. + channel specific to ADC3 */ #endif /* ADC3 */ #else #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel @@ -2496,7 +2504,28 @@ connected to DAC1 channel 1, channel specific to ADC2 */ * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. * Value "1" if the internal channel selected is available on the ADC instance selected. */ -#if defined(ADC2) +#if defined(ADC3) +#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + ((((__ADC_INSTANCE__) == ADC1) \ + &&(((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR ) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)) \ + ) \ + || \ + (((__ADC_INSTANCE__) == ADC2) \ + &&(((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VDDCORE)) \ + ) \ + || \ + (((__ADC_INSTANCE__) == ADC3) \ + &&(((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VDDCORE_ADC3) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT_ADC3) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1_CH1) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1_CH2)) \ + ) \ + ) +#elif defined(ADC2) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ ((((__ADC_INSTANCE__) == ADC1) \ &&(((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR ) || \ @@ -2515,7 +2544,7 @@ connected to DAC1 channel 1, channel specific to ADC2 */ ((__CHANNEL__) == LL_ADC_CHANNEL_VDDCORE) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \ ) -#endif /* ADC2 */ +#endif /* ADC3 */ /** * @brief Helper macro to define ADC analog watchdog parameter: @@ -3415,11 +3444,52 @@ __STATIC_INLINE void LL_ADC_DisableChannelVDDcore(ADC_TypeDef *ADCx) } #endif /* ADC2 */ +#if defined (ADC2) +/** + * @brief Enable Channel 0 GPIO switch control. + * @note On this STM32 series, Channel 0 channel connection to GPIO is controlled via specific register. + * @note On this STM32 series, Channel 0 GPIO switch control must be enabled when INP0 is used. + * @rmtoll OR OP0 LL_ADC_EnableChannel0_GPIO + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableChannel0_GPIO(ADC_TypeDef *ADCx) +{ + if (ADCx == ADC2) + { + /* ADC2_INP0 switch is controlled by ADC1 */ + SET_BIT(ADC1->OR, ADC_OR_OP0); + } + else + { + SET_BIT(ADCx->OR, ADC_OR_OP0); + } +} + +/** + * @brief Disable Channel 0 GPIO switch control. + * @note On this STM32 series, Channel 0 connection to GPIO is controlled via specific register. + * @rmtoll OR OP0 LL_ADC_DisableChannel0_GPIO + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableChannel0_GPIO(ADC_TypeDef *ADCx) +{ + if (ADCx == ADC2) + { + /* ADC2_INP0 switch is controlled by ADC1 */ + CLEAR_BIT(ADC1->OR, ADC_OR_OP0); + } + else + { + CLEAR_BIT(ADCx->OR, ADC_OR_OP0); + } +} +#else /** * @brief Enable Channel 0 GPIO switch control. * @note On this STM32 series, Channel 0 channel connection to GPIO is controlled via specific register. * @note On this STM32 series, Channel 0 GPIO switch control must be enabled when INP0 is used. - * @note On this STM32 series, LL_ADC_EnableChannel0_GPIO available on all instances but ADC2. * @rmtoll OR OP0 LL_ADC_EnableChannel0_GPIO * @param ADCx ADC instance * @retval None @@ -3432,7 +3502,6 @@ __STATIC_INLINE void LL_ADC_EnableChannel0_GPIO(ADC_TypeDef *ADCx) /** * @brief Disable Channel 0 GPIO switch control. * @note On this STM32 series, Channel 0 connection to GPIO is controlled via specific register. - * @note On this STM32 series, LL_ADC_DisableChannel0_GPIO available on all instances but ADC2. * @rmtoll OR OP0 LL_ADC_DisableChannel0_GPIO * @param ADCx ADC instance * @retval None @@ -3441,6 +3510,7 @@ __STATIC_INLINE void LL_ADC_DisableChannel0_GPIO(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->OR, ADC_OR_OP0); } +#endif /* ADC2 */ /** * @brief Set ADC calibration factor in the mode single-ended diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h index 803586e15c..474e2bb7b4 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h @@ -624,7 +624,7 @@ __STATIC_INLINE uint32_t LL_APB_IsDisabledClock(uint32_t APBx) * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*) * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*) @@ -633,7 +633,7 @@ __STATIC_INLINE uint32_t LL_APB_IsDisabledClock(uint32_t APBx) * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 - * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 (*) * * (*) : Not available for all stm32h5xxxx family lines. * @retval None @@ -681,7 +681,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 - * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 (*) * * (*) : Not available for all stm32h5xxxx family lines. * @retval State of Periphs (1 or 0). @@ -725,7 +725,7 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 - * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 (*) * * (*) : Not available for all stm32h5xxxx family lines. * @retval None @@ -785,7 +785,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 - * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 (*) * * (*) : Not available for all stm32h5xxxx family lines. * @retval None @@ -877,7 +877,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 - * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 (*) * * (*) : Not available for all stm32h5xxxx family lines. * @retval State of Periphs (1 or 0). @@ -921,7 +921,7 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockSleep(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 - * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 (*) * * (*) : Not available for all stm32h5xxxx family lines. * @retval None @@ -1417,7 +1417,7 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 (*) * @arg @ref LL_AHB4_GRP1_PERIPH_FMC * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1 - * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 (*) * * (*) : Not available for all stm32h5xxxx family lines. * @retval None @@ -1443,11 +1443,13 @@ __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_AHB4_GRP1_PERIPH_ALL * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 (*) * @arg @ref LL_AHB4_GRP1_PERIPH_FMC * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1 - * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 (*) * @retval State of Periphs (1 or 0). + * + * (*) : Not available for all stm32h5xxxx family lines. */ __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) { @@ -1466,11 +1468,13 @@ __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_AHB4_GRP1_PERIPH_ALL * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 (*) * @arg @ref LL_AHB4_GRP1_PERIPH_FMC * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1 - * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 (*) * @retval None + * + * (*) : Not available for all stm32h5xxxx family lines. */ __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs) { @@ -1489,10 +1493,12 @@ __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_AHB4_GRP1_PERIPH_ALL * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 (*) * @arg @ref LL_AHB4_GRP1_PERIPH_FMC - * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 (*) * @retval None + * + * (*) : Not available for all stm32h5xxxx family lines. */ __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs) { @@ -1511,11 +1517,13 @@ __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_AHB4_GRP1_PERIPH_ALL * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 (*) * @arg @ref LL_AHB4_GRP1_PERIPH_FMC * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1 - * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 (*) * @retval None + * + * (*) : Not available for all stm32h5xxxx family lines. */ __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs) { @@ -1534,11 +1542,13 @@ __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_AHB4_GRP1_PERIPH_ALL * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 (*) * @arg @ref LL_AHB4_GRP1_PERIPH_FMC * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1 - * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 (*) * @retval None + * + * (*) : Not available for all stm32h5xxxx family lines. */ __STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) { @@ -1561,11 +1571,13 @@ __STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) * @arg @ref LL_AHB4_GRP1_PERIPH_ALL * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 (*) * @arg @ref LL_AHB4_GRP1_PERIPH_FMC * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1 - * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 (*) * @retval State of Periphs (1 or 0). + * + * (*) : Not available for all stm32h5xxxx family lines. */ __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClockSleep(uint32_t Periphs) { @@ -1584,11 +1596,13 @@ __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClockSleep(uint32_t Periphs) * @arg @ref LL_AHB4_GRP1_PERIPH_ALL * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 (*) * @arg @ref LL_AHB4_GRP1_PERIPH_FMC * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1 - * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 (*) * @retval None + * + * (*) : Not available for all stm32h5xxxx family lines. */ __STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) { @@ -2176,7 +2190,7 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_CRS * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART11 + * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*) * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) @@ -2372,7 +2386,7 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) * * (*) : Not available for all stm32h5xxxx family lines. * @retval None @@ -2454,7 +2468,7 @@ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) * * (*) : Not available for all stm32h5xxxx family lines. * @retval None @@ -2493,7 +2507,7 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) * * (*) : Not available for all stm32h5xxxx family lines. * @retval None @@ -2532,7 +2546,7 @@ __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) * * (*) : Not available for all stm32h5xxxx family lines. * @retval None @@ -2571,7 +2585,7 @@ __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) * * (*) : Not available for all stm32h5xxxx family lines. * @retval None @@ -2654,7 +2668,7 @@ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockSleep(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) * * (*) : Not available for all stm32h5xxxx family lines. * @retval None diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_comp.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_comp.h index 2d55e4ebae..9019e71c7b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_comp.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_comp.h @@ -676,7 +676,8 @@ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(const COMP_TypeDef *COMPx) * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 * @retval None * - * (*): Not available for stm32h5exxx and stm32h5fxxx family lines. + * (*): Not available for stm32h5exxx and stm32h5fxxx and + * stm32h553xx ans stm32h543xx family lines. */ __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus) { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crc.h index 3838cd3f56..329fdd0c25 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crc.h @@ -58,7 +58,46 @@ extern "C" { /** * @} */ +#if defined(CRC_CR_RTYPE_IN) +/** @defgroup CRC_LL_EC_INPUT_REVERSE_TYPE Input Reverse Type + * @{ + */ +#define LL_CRC_INDATA_REVERSETYPE_BIT 0x00000000U /*!< Input Data reverse type at bit level granularity */ +#define LL_CRC_INDATA_REVERSETYPE_BYTE_HALFWORD CRC_CR_RTYPE_IN /*!< Input Data reverse type at byte or half-word level granularity */ +/** + * @} + */ +#endif /* CRC_CR_RTYPE_IN */ +#if defined(CRC_CR_RTYPE_OUT) + +/** @defgroup CRC_LL_EC_OUTPUT_REVERSE_TYPE Output Reverse Type + * @{ + */ +#define LL_CRC_OUTDATA_REVERSETYPE_BIT 0x00000000U /*!< Output Data reverse type at bit level granularity */ +#define LL_CRC_OUTDATA_REVERSETYPE_BYTE_HALFWORD CRC_CR_RTYPE_OUT /*!< Output Data reverse type at byte or half-word level granularity */ +/** + * @} + */ +#endif /* CRC_CR_RTYPE_OUT */ + +#if defined(CRC_CR_RTYPE_IN) +/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse + * @{ + */ +#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */ +#define LL_CRC_INDATA_REVERSE_BIT_BYBYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */ +#define LL_CRC_INDATA_REVERSE_BYTE LL_CRC_INDATA_REVERSE_BIT_BYBYTE /*!< Definition for compatibility with legacy code */ +#define LL_CRC_INDATA_REVERSE_HALFWORD_BYWORD (CRC_CR_RTYPE_IN | CRC_CR_REV_IN_0) /*!< Input Data half-word reversal done by word */ +#define LL_CRC_INDATA_REVERSE_BIT_BYHALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */ +#define LL_CRC_INDATA_REVERSE_HALFWORD LL_CRC_INDATA_REVERSE_BIT_BYHALFWORD /*!< Definition for compatibility with legacy code */ +#define LL_CRC_INDATA_REVERSE_BYTE_BYWORD (CRC_CR_RTYPE_IN | CRC_CR_REV_IN_1) /*!< Input Data byte reversal done by word */ +#define LL_CRC_INDATA_REVERSE_BIT_BYWORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */ +#define LL_CRC_INDATA_REVERSE_WORD LL_CRC_INDATA_REVERSE_BIT_BYWORD /*!< Definition for compatibility with legacy code */ +/** + * @} + */ +#else /** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse * @{ */ @@ -69,7 +108,20 @@ extern "C" { /** * @} */ +#endif /* CRC_CR_RTYPE_IN */ +#if defined(CRC_CR_RTYPE_OUT) +/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse + * @{ + */ +#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */ +#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT_0 /*!< Output Data bit reversal done by bit */ +#define LL_CRC_OUTDATA_REVERSE_HALFWORD (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT_0) /*!< Output Data half-word reversal done by word */ +#define LL_CRC_OUTDATA_REVERSE_BYTE (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT_1) /*!< Output Data byte reversal done by word */ +/** + * @} + */ +#else /** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse * @{ */ @@ -78,6 +130,7 @@ extern "C" { /** * @} */ +#endif /* CRC_CR_RTYPE_OUT */ /** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value * @brief Normal representation of this polynomial value is @@ -189,6 +242,127 @@ __STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx) return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE)); } +#if defined(CRC_CR_RTYPE_OUT) +/** + * @brief Configure the reversal type of the input data + * @rmtoll CR RTYPE_IN LL_CRC_SetInputDataReverseType + * @param CRCx CRC Instance + * @param ReverseType This parameter can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSETYPE_BIT + * @arg @ref LL_CRC_INDATA_REVERSETYPE_BYTE_HALFWORD + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetInputDataReverseType(CRC_TypeDef *CRCx, uint32_t ReverseType) +{ + MODIFY_REG(CRCx->CR, CRC_CR_RTYPE_IN, ReverseType); +} + +/** + * @brief Return input data type of reversal + * @rmtoll CR RTYPE_IN LL_CRC_GetInputDataReverseType + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSETYPE_BIT + * @arg @ref LL_CRC_INDATA_REVERSETYPE_BYTE_HALFWORD + */ +__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseType(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_RTYPE_IN)); +} + +/** + * @brief Configure the reversal type of the output data + * @rmtoll CR RTYPE_OUT LL_CRC_SetOutputDataReverseType + * @param CRCx CRC Instance + * @param ReverseType This parameter can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSETYPE_BIT + * @arg @ref LL_CRC_OUTDATA_REVERSETYPE_BYTE_HALFWORD + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetOutputDataReverseType(CRC_TypeDef *CRCx, uint32_t ReverseType) +{ + MODIFY_REG(CRCx->CR, CRC_CR_RTYPE_OUT, ReverseType); +} + +/** + * @brief Return output data type of reversal + * @rmtoll CR RTYPE_OUT LL_CRC_GetOutputDataReverseType + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSETYPE_BIT + * @arg @ref LL_CRC_OUTDATA_REVERSETYPE_BYTE_HALFWORD + */ +__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseType(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_RTYPE_OUT)); +} + +/** + * @brief Configure the reversal of the bit order of the input data + * @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode + * @param CRCx CRC Instance + * @param ReverseMode This parameter can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSE_NONE + * @arg @ref LL_CRC_INDATA_REVERSE_BIT_BYBYTE + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD_BYWORD + * @arg @ref LL_CRC_INDATA_REVERSE_BIT_BYHALFWORD + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE_BYWORD + * @arg @ref LL_CRC_INDATA_REVERSE_BIT_BYWORD + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode) +{ + MODIFY_REG(CRCx->CR, (CRC_CR_RTYPE_IN | CRC_CR_REV_IN), ReverseMode); +} + +/** + * @brief Return mode of reversal for input data bit order + * @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSE_NONE + * @arg @ref LL_CRC_INDATA_REVERSE_BIT_BYBYTE + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD_BYWORD + * @arg @ref LL_CRC_INDATA_REVERSE_BIT_BYHALFWORD + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE_BYWORD + * @arg @ref LL_CRC_INDATA_REVERSE_BIT_BYWORD + */ +__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, (CRC_CR_RTYPE_IN | CRC_CR_REV_IN))); +} + +/** + * @brief Configure the reversal of the bit order of the Output data + * @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode + * @param CRCx CRC Instance + * @param ReverseMode This parameter can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE + * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT + * @arg @ref LL_CRC_OUTDATA_REVERSE_HALFWORD + * @arg @ref LL_CRC_OUTDATA_REVERSE_BYTE + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode) +{ + MODIFY_REG(CRCx->CR, (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT), ReverseMode); +} + +/** + * @brief Return mode of reversal of the bit order of the Output data + * @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE + * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT + * @arg @ref LL_CRC_OUTDATA_REVERSE_HALFWORD + * @arg @ref LL_CRC_OUTDATA_REVERSE_BYTE + */ +__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT))); +} +#else /** * @brief Configure the reversal of the bit order of the input data * @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode @@ -246,6 +420,7 @@ __STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx { return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT)); } +#endif /* CRC_CR_RTYPE_OUT */ /** * @brief Initialize the Programmable initial CRC value. diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma2d.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma2d.h index 160a47e25f..745713dbd6 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma2d.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma2d.h @@ -1415,7 +1415,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB1555 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB4444 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB2222 -*/ + */ __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM)); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h index b78b8c86de..67ffb6b566 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h @@ -414,10 +414,10 @@ __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 - * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 - * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_33 (*) + * @arg @ref LL_EXTI_LINE_34 (*) + * @arg @ref LL_EXTI_LINE_35 (*) + * @arg @ref LL_EXTI_LINE_36 (*) * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 @@ -425,20 +425,20 @@ __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 * @arg @ref LL_EXTI_LINE_43 - * @arg @ref LL_EXTI_LINE_44 - * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_45 (*) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_51 - * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_52 (*) * @arg @ref LL_EXTI_LINE_53 - * @arg @ref LL_EXTI_LINE_54 - * @arg @ref LL_EXTI_LINE_55 - * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_54 (*) + * @arg @ref LL_EXTI_LINE_55 (*) + * @arg @ref LL_EXTI_LINE_56 (*) + * @arg @ref LL_EXTI_LINE_57 (*) * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_59 (*) * @arg @ref LL_EXTI_LINE_60 (*) @@ -528,10 +528,10 @@ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 - * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 - * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_33 (*) + * @arg @ref LL_EXTI_LINE_34 (*) + * @arg @ref LL_EXTI_LINE_35 (*) + * @arg @ref LL_EXTI_LINE_36 (*) * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 @@ -539,20 +539,20 @@ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 * @arg @ref LL_EXTI_LINE_43 - * @arg @ref LL_EXTI_LINE_44 - * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_45 (*) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_51 - * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_52 (*) * @arg @ref LL_EXTI_LINE_53 - * @arg @ref LL_EXTI_LINE_54 - * @arg @ref LL_EXTI_LINE_55 - * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_54 (*) + * @arg @ref LL_EXTI_LINE_55 (*) + * @arg @ref LL_EXTI_LINE_56 (*) + * @arg @ref LL_EXTI_LINE_57 (*) * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_59 (*) * @arg @ref LL_EXTI_LINE_60 (*) @@ -642,10 +642,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 - * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 - * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_33 (*) + * @arg @ref LL_EXTI_LINE_34 (*) + * @arg @ref LL_EXTI_LINE_35 (*) + * @arg @ref LL_EXTI_LINE_36 (*) * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 @@ -653,20 +653,20 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 * @arg @ref LL_EXTI_LINE_43 - * @arg @ref LL_EXTI_LINE_44 - * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_45 (*) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_51 - * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_52 (*) * @arg @ref LL_EXTI_LINE_53 - * @arg @ref LL_EXTI_LINE_54 - * @arg @ref LL_EXTI_LINE_55 - * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_54 (*) + * @arg @ref LL_EXTI_LINE_55 (*) + * @arg @ref LL_EXTI_LINE_56 (*) + * @arg @ref LL_EXTI_LINE_57 (*) * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_59 (*) * @arg @ref LL_EXTI_LINE_60 (*) @@ -760,10 +760,10 @@ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_32 - * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 - * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_33 (*) + * @arg @ref LL_EXTI_LINE_34 (*) + * @arg @ref LL_EXTI_LINE_35 (*) + * @arg @ref LL_EXTI_LINE_36 (*) * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 @@ -771,20 +771,20 @@ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 * @arg @ref LL_EXTI_LINE_43 - * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_44 (*) * @arg @ref LL_EXTI_LINE_46 - * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_45 (*) * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_51 - * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_52 (*) * @arg @ref LL_EXTI_LINE_53 - * @arg @ref LL_EXTI_LINE_54 - * @arg @ref LL_EXTI_LINE_55 - * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_54 (*) + * @arg @ref LL_EXTI_LINE_55 (*) + * @arg @ref LL_EXTI_LINE_56 (*) + * @arg @ref LL_EXTI_LINE_57 (*) * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_59 (*) * @arg @ref LL_EXTI_LINE_60 (*) @@ -870,10 +870,10 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_32 - * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 - * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_33 (*) + * @arg @ref LL_EXTI_LINE_34 (*) + * @arg @ref LL_EXTI_LINE_35 (*) + * @arg @ref LL_EXTI_LINE_36 (*) * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 @@ -881,19 +881,19 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 * @arg @ref LL_EXTI_LINE_43 - * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_44 (*) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_51 - * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_52 (*) * @arg @ref LL_EXTI_LINE_53 - * @arg @ref LL_EXTI_LINE_54 - * @arg @ref LL_EXTI_LINE_55 - * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_54 (*) + * @arg @ref LL_EXTI_LINE_55 (*) + * @arg @ref LL_EXTI_LINE_56 (*) + * @arg @ref LL_EXTI_LINE_57 (*) * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_59 (*) * @arg @ref LL_EXTI_LINE_60 (*) @@ -980,10 +980,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_32 - * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 - * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_33 (*) + * @arg @ref LL_EXTI_LINE_34 (*) + * @arg @ref LL_EXTI_LINE_35 (*) + * @arg @ref LL_EXTI_LINE_36 (*) * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 @@ -991,19 +991,19 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 * @arg @ref LL_EXTI_LINE_43 - * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_44 (*) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_51 - * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_52 (*) * @arg @ref LL_EXTI_LINE_53 - * @arg @ref LL_EXTI_LINE_54 - * @arg @ref LL_EXTI_LINE_55 - * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_54 (*) + * @arg @ref LL_EXTI_LINE_55 (*) + * @arg @ref LL_EXTI_LINE_56 (*) + * @arg @ref LL_EXTI_LINE_57 (*) * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_59 (*) * @arg @ref LL_EXTI_LINE_60 (*) @@ -2227,10 +2227,10 @@ __STATIC_INLINE void LL_EXTI_EnableSecure_0_31(uint32_t ExtiLine) * @rmtoll SECCFGR2 SECx LL_EXTI_EnableSecure_32_63 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 - * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 - * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_33 (*) + * @arg @ref LL_EXTI_LINE_34 (*) + * @arg @ref LL_EXTI_LINE_35 (*) + * @arg @ref LL_EXTI_LINE_36 (*) * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 @@ -2238,19 +2238,19 @@ __STATIC_INLINE void LL_EXTI_EnableSecure_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 * @arg @ref LL_EXTI_LINE_43 - * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_44 (*) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_51 - * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_52 (*) * @arg @ref LL_EXTI_LINE_53 - * @arg @ref LL_EXTI_LINE_54 - * @arg @ref LL_EXTI_LINE_55 - * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_54 (*) + * @arg @ref LL_EXTI_LINE_55 (*) + * @arg @ref LL_EXTI_LINE_56 (*) + * @arg @ref LL_EXTI_LINE_57 (*) * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_59 * @arg @ref LL_EXTI_LINE_60 @@ -2334,10 +2334,10 @@ __STATIC_INLINE void LL_EXTI_DisableSecure_0_31(uint32_t ExtiLine) * @rmtoll SECCFGR2 SECx LL_EXTI_DisableSecure_32_63 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 - * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 - * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_33 (*) + * @arg @ref LL_EXTI_LINE_34 (*) + * @arg @ref LL_EXTI_LINE_35 (*) + * @arg @ref LL_EXTI_LINE_36 (*) * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 @@ -2345,19 +2345,19 @@ __STATIC_INLINE void LL_EXTI_DisableSecure_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 * @arg @ref LL_EXTI_LINE_43 - * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_44 (*) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_51 - * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_52 (*) * @arg @ref LL_EXTI_LINE_53 - * @arg @ref LL_EXTI_LINE_54 - * @arg @ref LL_EXTI_LINE_55 - * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_54 (*) + * @arg @ref LL_EXTI_LINE_55 (*) + * @arg @ref LL_EXTI_LINE_56 (*) + * @arg @ref LL_EXTI_LINE_57 (*) * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_59 * @arg @ref LL_EXTI_LINE_60 @@ -2444,10 +2444,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_0_31(uint32_t ExtiLine) * @rmtoll SECCFGR2 SECx LL_EXTI_IsEnabledSecure_32_63 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 - * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 - * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_33 (*) + * @arg @ref LL_EXTI_LINE_34 (*) + * @arg @ref LL_EXTI_LINE_35 (*) + * @arg @ref LL_EXTI_LINE_36 (*) * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 @@ -2455,19 +2455,19 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 * @arg @ref LL_EXTI_LINE_43 - * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_44 (*) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_51 - * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_52 (*) * @arg @ref LL_EXTI_LINE_53 - * @arg @ref LL_EXTI_LINE_54 - * @arg @ref LL_EXTI_LINE_55 - * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_54 (*) + * @arg @ref LL_EXTI_LINE_55 (*) + * @arg @ref LL_EXTI_LINE_56 (*) + * @arg @ref LL_EXTI_LINE_57 (*) * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_59 * @arg @ref LL_EXTI_LINE_60 @@ -2560,10 +2560,10 @@ __STATIC_INLINE void LL_EXTI_EnablePrivilege_0_31(uint32_t ExtiLine) * @rmtoll PRIVCFGR2 PRIVx LL_EXTI_EnablePrivilege_32_63 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 - * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 - * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_33 (*) + * @arg @ref LL_EXTI_LINE_34 (*) + * @arg @ref LL_EXTI_LINE_35 (*) + * @arg @ref LL_EXTI_LINE_36 (*) * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 @@ -2571,19 +2571,19 @@ __STATIC_INLINE void LL_EXTI_EnablePrivilege_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 * @arg @ref LL_EXTI_LINE_43 - * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_44 (*) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_51 - * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_52 (*) * @arg @ref LL_EXTI_LINE_53 - * @arg @ref LL_EXTI_LINE_54 - * @arg @ref LL_EXTI_LINE_55 - * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_54 (*) + * @arg @ref LL_EXTI_LINE_55 (*) + * @arg @ref LL_EXTI_LINE_56 (*) + * @arg @ref LL_EXTI_LINE_57 (*) * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_59 * @arg @ref LL_EXTI_LINE_60 @@ -2667,10 +2667,10 @@ __STATIC_INLINE void LL_EXTI_DisablePrivilege_0_31(uint32_t ExtiLine) * @rmtoll PRIVCFGR2 PRIVx LL_EXTI_DisablePrivilege_32_63 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 - * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 - * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_33 (*) + * @arg @ref LL_EXTI_LINE_34 (*) + * @arg @ref LL_EXTI_LINE_35 (*) + * @arg @ref LL_EXTI_LINE_36 (*) * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 @@ -2678,19 +2678,19 @@ __STATIC_INLINE void LL_EXTI_DisablePrivilege_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 * @arg @ref LL_EXTI_LINE_43 - * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_44 (*) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_51 - * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_52 (*) * @arg @ref LL_EXTI_LINE_53 - * @arg @ref LL_EXTI_LINE_54 - * @arg @ref LL_EXTI_LINE_55 - * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_54 (*) + * @arg @ref LL_EXTI_LINE_55 (*) + * @arg @ref LL_EXTI_LINE_56 (*) + * @arg @ref LL_EXTI_LINE_57 (*) * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_59 * @arg @ref LL_EXTI_LINE_60 @@ -2774,10 +2774,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_0_31(uint32_t ExtiLine) * @rmtoll PRIVCFGR2 PRIVx LL_EXTI_IsEnabledPrivilege_32_63 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 - * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 - * @arg @ref LL_EXTI_LINE_35 - * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_33 (*) + * @arg @ref LL_EXTI_LINE_34 (*) + * @arg @ref LL_EXTI_LINE_35 (*) + * @arg @ref LL_EXTI_LINE_36 (*) * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 @@ -2785,19 +2785,19 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 * @arg @ref LL_EXTI_LINE_43 - * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_44 (*) * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_51 - * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_52 (*) * @arg @ref LL_EXTI_LINE_53 - * @arg @ref LL_EXTI_LINE_54 - * @arg @ref LL_EXTI_LINE_55 - * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_54 (*) + * @arg @ref LL_EXTI_LINE_55 (*) + * @arg @ref LL_EXTI_LINE_56 (*) + * @arg @ref LL_EXTI_LINE_57 (*) * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_59 * @arg @ref LL_EXTI_LINE_60 diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i3c.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i3c.h index caac686d91..9f8ab5de8f 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i3c.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i3c.h @@ -203,6 +203,39 @@ typedef struct /** * @} */ +#if defined(I3C_MISR_CFNFMIS) + +/** @defgroup I3C_LL_EC_MASK_IT MASKS IT Defines + * @brief Masks Interrupt defines which can be used with LL_I3C_ReadReg and LL_I3C_WriteReg functions + * @{ + */ +#define LL_I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS +#define LL_I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS +#define LL_I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS +#define LL_I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS +#define LL_I3C_MISR_FCMIS I3C_MISR_FCMIS +#define LL_I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS +#define LL_I3C_MISR_ERRMIS I3C_MISR_ERRMIS +#define LL_I3C_MISR_IBIMIS I3C_MISR_IBIMIS +#define LL_I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS +#define LL_I3C_MISR_CRMIS I3C_MISR_CRMIS +#define LL_I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS +#define LL_I3C_MISR_HJMIS I3C_MISR_HJMIS +#define LL_I3C_MISR_WKPMIS I3C_MISR_WKPMIS +#define LL_I3C_MISR_GETMIS I3C_MISR_GETMIS +#define LL_I3C_MISR_STAMIS I3C_MISR_STAMIS +#define LL_I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS +#define LL_I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS +#define LL_I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS +#define LL_I3C_MISR_RSTMIS I3C_MISR_RSTMIS +#define LL_I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS +#define LL_I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS +#define LL_I3C_MISR_DEFMIS I3C_MISR_DEFMIS +#define LL_I3C_MISR_GRPMIS I3C_MISR_GRPMIS +/** + * @} + */ +#endif /* I3C_MISR_CFNFMIS */ /** @defgroup I3C_LL_EC_MODE MODE * @{ @@ -254,6 +287,22 @@ typedef struct * @} */ + +#if defined(I3C_CFGR_FCFDIS) + +/** @defgroup I3C_LL_EC_End_Of_FrameCompletion End of Frame completion + * @{ + */ +#define LL_I3C_END_OF_FRAME_CPLT_DISABLE I3C_CFGR_FCFDIS +/*!< Frame Completion Flag is autoclear by HW, no need SW action */ +#define LL_I3C_END_OF_FRAME_CPLT_ENABLE 0x00000000U +/*!< Frame Completion Flag need to be clear by SW action (default configuration) */ +/** + * @} + */ + +#endif /* I3C_CFGR_FCFDIS */ + /** @defgroup I3C_LL_EC_PAYLOAD PAYLOAD * @{ */ @@ -274,8 +323,19 @@ typedef struct /** @defgroup I3C_LL_EC_SDA_HOLD_TIME SDA HOLD TIME 0 * @{ */ +#if defined(I3C_TIMINGR1_SDA_HD_1) +#define LL_I3C_SDA_HOLD_TIME_0_5 0x00000000U +/*!< SDA hold time is 0.5 x ti3cclk */ +#define LL_I3C_SDA_HOLD_TIME_1_5 I3C_TIMINGR1_SDA_HD_0 +/*!< SDA hold time is 1.5 x ti3cclk */ +#define LL_I3C_SDA_HOLD_TIME_2_5 I3C_TIMINGR1_SDA_HD_1 +/*!< SDA hold time is 2.5 x ti3cclk */ +#define LL_I3C_SDA_HOLD_TIME_3_5 (I3C_TIMINGR1_SDA_HD_1 | I3C_TIMINGR1_SDA_HD_0) +/*!< SDA hold time is 3.5 x ti3cclk */ +#else #define LL_I3C_SDA_HOLD_TIME_0_5 0x00000000U /*!< SDA hold time is 0.5 x ti3cclk */ #define LL_I3C_SDA_HOLD_TIME_1_5 I3C_TIMINGR1_SDA_HD /*!< SDA hold time is 1.5 x ti3cclk */ +#endif /* I3C_TIMINGR1_SDA_HD_1 */ /** * @} */ @@ -1591,6 +1651,10 @@ __STATIC_INLINE uint32_t LL_I3C_GetPeriodClockHighI2C(const I3C_TypeDef *I3Cx) * @param DataHoldTime This parameter can be one of the following values: * @arg @ref LL_I3C_SDA_HOLD_TIME_0_5 * @arg @ref LL_I3C_SDA_HOLD_TIME_1_5 +#if defined(I3C_TIMINGR1_SDA_HD_1) + * @arg @ref LL_I3C_SDA_HOLD_TIME_2_5 + * @arg @ref LL_I3C_SDA_HOLD_TIME_3_5 +#endif * @retval None */ __STATIC_INLINE void LL_I3C_SetDataHoldTime(I3C_TypeDef *I3Cx, uint32_t DataHoldTime) @@ -1605,6 +1669,10 @@ __STATIC_INLINE void LL_I3C_SetDataHoldTime(I3C_TypeDef *I3Cx, uint32_t DataHold * @retval Returned value can be one of the following values: * @arg @ref LL_I3C_SDA_HOLD_TIME_0_5 * @arg @ref LL_I3C_SDA_HOLD_TIME_1_5 +#if defined(I3C_TIMINGR1_SDA_HD_1) + * @arg @ref LL_I3C_SDA_HOLD_TIME_2_5 + * @arg @ref LL_I3C_SDA_HOLD_TIME_3_5 +#endif */ __STATIC_INLINE uint32_t LL_I3C_GetDataHoldTime(const I3C_TypeDef *I3Cx) { @@ -1781,6 +1849,113 @@ __STATIC_INLINE uint32_t LL_I3C_GetStallTime(const I3C_TypeDef *I3Cx) { return (uint32_t)(READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALL)); } +#if defined(I3C_TIMINGR2_STALLL) + +/** + * @brief Set stall on data ACK/NACK bit of legacy I2C address (controller mode). + * @note This bit can be programmed when the I3C is disabled (EN = 0). + * @rmtoll TIMINGR2 STALLL LL_I3C_EnableStallACKI2CAddr + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableStallACKI2CAddr(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLL); +} + +/** + * @brief Disable stall on data ACK/NACK bit of legacy I2C address (controller mode). + * @note This bit can be programmed when the I3C is disabled (EN = 0). + * @rmtoll TIMINGR2 STALLA LL_I3C_DisableStallACKI2CAddr + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableStallACKI2CAddr(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLL); +} + +/** + * @brief Check if stall on data ACK/NACK bit of legacy I2C address is enabled or disabled (controller mode). + * @rmtoll TIMINGR2 STALLA LL_I3C_IsEnabledStallACKI2CAddr + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallACKI2CAddr(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLL) == (I3C_TIMINGR2_STALLL)) ? 1UL : 0UL); +} + +/** + * @brief Set stall on data ACK/NACK bit of legacy I2C write message (controller mode). + * @note This bit can be programmed when the I3C is disabled (EN = 0). + * @rmtoll TIMINGR2 STALLS LL_I3C_EnableStallACKI2CWrite + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableStallACKI2CWrite(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLS); +} + +/** + * @brief Disable stall on data ACK/NACK bit of legacy I2C write message (controller mode). + * @note This bit can be programmed when the I3C is disabled (EN = 0). + * @rmtoll TIMINGR2 STALLS LL_I3C_DisableStallACKI2CWrite + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableStallACKI2CWrite(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLS); +} + +/** + * @brief Check if stall on data ACK/NACK bit of legacy I2C write message is enabled or disabled (controller mode). + * @rmtoll TIMINGR2 STALLS LL_I3C_IsEnabledStallACKI2CWrite + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallACKI2CWrite(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLS) == (I3C_TIMINGR2_STALLS)) ? 1UL : 0UL); +} + +/** + * @brief Set stall on data ACK/NACK bit of legacy I2C read message (controller mode). + * @note This bit can be programmed when the I3C is disabled (EN = 0). + * @rmtoll TIMINGR2 STALLR LL_I3C_EnableStallACKI2CRead + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableStallACKI2CRead(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLR); +} + +/** + * @brief Disable stall on data ACK/NACK bit of legacy I2C read message (controller mode). + * @note This bit can be programmed when the I3C is disabled (EN = 0). + * @rmtoll TIMINGR2 STALLR LL_I3C_DisableStallACKI2CRead + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableStallACKI2CRead(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLR); +} + +/** + * @brief Check if stall on data ACK/NACK bit of legacy I2C read message is enabled or disabled (controller mode). + * @rmtoll TIMINGR2 STALLR LL_I3C_IsEnabledStallACKI2CRead + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallACKI2CRead(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLR) == (I3C_TIMINGR2_STALLR)) ? 1UL : 0UL); +} +#endif /* I3C_TIMINGR2_STALLL */ /** * @brief Set stall on ACK bit (controller mode). @@ -2319,6 +2494,36 @@ __STATIC_INLINE void LL_I3C_RequestStatusFIFOFlush(I3C_TypeDef *I3Cx) { SET_BIT(I3Cx->CFGR, I3C_CFGR_SFLUSH); } +#if defined(I3C_CFGR_FCFDIS) + +/** + * @brief Set End of Frame mode + * @note This bit can be modified only when there is no frame ongoing + * @rmtoll CFGR FCFDIS LL_I3C_SetEndOfFrameMode + * @param I3Cx I3C Instance. + * @param EOFrameConfig This parameter can be one of the following values: + * @arg @ref LL_I3C_END_OF_FRAME_CPLT_DISABLE + * @arg @ref LL_I3C_END_OF_FRAME_CPLT_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetEndOfFrameMode(I3C_TypeDef *I3Cx, uint32_t EOFrameConfig) +{ + MODIFY_REG(I3Cx->CFGR, I3C_CFGR_FCFDIS, EOFrameConfig); +} + +/** + * @brief Get End of Frame mode + * @rmtoll CFGR FCFDIS LL_I3C_GetEndOfFrameMode + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_END_OF_FRAME_CPLT_DISABLE + * @arg @ref LL_I3C_END_OF_FRAME_CPLT_ENABLE + */ +__STATIC_INLINE uint32_t LL_I3C_GetEndOfFrameMode(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->CFGR, I3C_CFGR_FCFDIS)); +} +#endif /* I3C_CFGR_FCFDIS */ /** * @brief Get Activity state of Controller on the I3C Bus (Target only). @@ -4368,6 +4573,269 @@ __STATIC_INLINE void LL_I3C_ClearFlag_GRP(I3C_TypeDef *I3Cx) /** * @} */ +#if defined(I3C_MISR_CFNFMIS) + +/** @defgroup I3C_LL_EF_MASK_IT_Management Mask_IT_Management + * @{ + */ + +/** + * @brief Indicates the status of masked interrupt Control FIFO Not Full flag. + * @rmtoll MISR CFNFMIS LL_I3C_IsActiveMaskFlag_CFNF + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_CFNF(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_CFNFMIS) == (I3C_MISR_CFNFMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Status FIFO Not Empty flag. + * @rmtoll MISR SFNEMIS LL_I3C_IsActiveMaskFlag_SFNE + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_SFNE(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_SFNEMIS) == (I3C_MISR_SFNEMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Transmit FIFO Not Full flag. + * @rmtoll MISR TXFNFMIS LL_I3C_IsActiveMaskFlag_TXFNF + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_TXFNF(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_TXFNFMIS) == (I3C_MISR_TXFNFMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Receive FIFO Not Empty flag. + * @rmtoll MISR RXFNEMIS LL_I3C_IsActiveMaskFlag_RXFNE + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_RXFNE(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_RXFNEMIS) == (I3C_MISR_RXFNEMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Frame Complete flag. + * @rmtoll MISR FCMIS LL_I3C_IsActiveMaskFlag_FC + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_FC(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_FCMIS) == (I3C_MISR_FCMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Reception Target End flag. + * @rmtoll MISR RXTGTENDMIS LL_I3C_IsActiveMaskFlag_RXTGTEND + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_RXTGTEND(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_RXTGTENDMIS) == (I3C_MISR_RXTGTENDMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Error flag. + * @rmtoll MISR ERRMIS LL_I3C_IsActiveMaskFlag_ERR + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_ERR(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_ERRMIS) == (I3C_MISR_ERRMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt IBI flag. + * @rmtoll MISR IBIMIS LL_I3C_IsActiveMaskFlag_IBI + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_IBI(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_IBIMIS) == (I3C_MISR_IBIMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt IBI End flag. + * @rmtoll MISR IBIENDMIS LL_I3C_IsActiveMaskFlag_IBIEND + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_IBIEND(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_IBIENDMIS) == (I3C_MISR_IBIENDMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Controller-role flag. + * @rmtoll MISR CRMIS LL_I3C_IsActiveMaskFlag_CR + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_CR(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_CRMIS) == (I3C_MISR_CRMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Controller-role Update flag. + * @rmtoll MISR CRUPDMIS LL_I3C_IsActiveMaskFlag_CRUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_CRUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_CRUPDMIS) == (I3C_MISR_CRUPDMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Hot Join flag. + * @rmtoll MISR HJMIS LL_I3C_IsActiveMaskFlag_HJ + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_HJ(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_HJMIS) == (I3C_MISR_HJMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Wake Up is enabled or disabled. + * @rmtoll MISR WKPMIS LL_I3C_IsActiveMaskFlag_WKP + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_WKP(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_WKPMIS) == (I3C_MISR_WKPMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Get Command is enabled or disabled. + * @rmtoll MISR GETMIS LL_I3C_IsActiveMaskFlag_GET + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_GET(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_GETMIS) == (I3C_MISR_GETMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Get Status flag. + * @rmtoll MISR STAMIS LL_I3C_IsActiveMaskFlag_STA + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_STA(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_STAMIS) == (I3C_MISR_STAMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Dynamic Address Update flag. + * @rmtoll MISR DAUPDMIS LL_I3C_IsActiveMaskFlag_DAUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_DAUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_DAUPDMIS) == (I3C_MISR_DAUPDMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Max Write Length Update flag. + * @rmtoll MISR MWLUPDMIS LL_I3C_IsActiveMaskFlag_MWLUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_MWLUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_MWLUPDMIS) == (I3C_MISR_MWLUPDMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Max Read Length Update flag. + * @rmtoll MISR MRLUPDMIS LL_I3C_IsActiveMaskFlag_MRLUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_MRLUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_MRLUPDMIS) == (I3C_MISR_MRLUPDMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Reset flag. + * @rmtoll MISR RSTMIS LL_I3C_IsActiveMaskFlag_RST + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_RST(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_RSTMIS) == (I3C_MISR_RSTMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Activity State Update flag. + * @rmtoll MISR ASUPDMIS LL_I3C_IsActiveMaskFlag_ASUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_ASUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_ASUPDMIS) == (I3C_MISR_ASUPDMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked Interrupt Update flag. + * @rmtoll MISR INTUPDMIS LL_I3C_IsActiveMaskFlag_INTUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_INTUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_INTUPDMIS) == (I3C_MISR_INTUPDMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Define List Target flag. + * @rmtoll MISR DEFMIS LL_I3C_IsActiveMaskFlag_DEF + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_DEF(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_DEFMIS) == (I3C_MISR_DEFMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Define List Group Addresses flag. + * @rmtoll MISR GRPMIS LL_I3C_IsActiveMaskFlag_GRP + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_GRP(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->MISR, I3C_MISR_GRPMIS) == (I3C_MISR_GRPMIS)) ? 1UL : 0UL); +} + +/** + * @} + */ +#endif /* I3C_MISR_CFNFMIS */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup I3C_LL_EF_Init Initialization and de-initialization functions diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_lptim.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_lptim.h index 70cf577aab..f830e08aa0 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_lptim.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_lptim.h @@ -397,6 +397,7 @@ typedef struct * @{ */ #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2 and possibly LPTIM3, LPTIM4, LPTIM5 and LPTIM6 when supported */ +#if !defined(STM32H553xx) && !defined(STM32H543xx) #if defined(COMP1) #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM1, LPTIM2 and possibly LPTIM3, LPTIM4, LPTIM5 and LPTIM6 when supported */ #endif /* COMP1 */ @@ -405,6 +406,7 @@ typedef struct #if defined(PLAY1) #define LL_LPTIM_INPUT1_SRC_PLAY1_OUT3 LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM1 and LPTIM2 */ #endif /* PLAY1 */ +#endif /* STM32H553xx && STM32H543xx */ /** * @} */ @@ -413,12 +415,14 @@ typedef struct * @{ */ #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2 and possibly LPTIM3, LPTIM4, LPTIM5 and LPTIM6 when supported */ +#if !defined(STM32H553xx) && !defined(STM32H543xx) #if defined(COMP2) #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0 /*!< For LPTIM1 and LPTIM2 and possibly LPTIM3, LPTIM5 and LPTIM6 when supported */ #endif /* COMP2 */ #if defined(PLAY1) #define LL_LPTIM_INPUT2_SRC_PLAY1_OUT4 LPTIM_CFGR2_IN2SEL_1 /*!< For LPTIM1 and LPTIM2 */ #endif /* PLAY1 */ +#endif /* STM32H553xx && STM32H543xx */ /** * @} */ @@ -427,6 +431,7 @@ typedef struct * @{ */ #define LL_LPTIM_LPTIM1_IC1_RMP_GPIO 0x00000000UL /*!< LPTIM1 IC1 connected to GPIO */ +#if !defined(STM32H553xx) && !defined(STM32H543xx) #if defined(COMP1) #define LL_LPTIM_LPTIM1_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< LPTIM1 IC1 connected to COMP1 */ #endif /* COMP1 */ @@ -438,6 +443,7 @@ typedef struct #if defined(PLAY1) #define LL_LPTIM_LPTIM1_IC1_RMP_PLAY1_OUT5 (LPTIM_CFGR2_IC1SEL_0 | LPTIM_CFGR2_IC1SEL_1) /*!< LPTIM1 IC1 connected to PLAY1 output 5 */ #endif /* PLAY1 */ +#endif /* STM32H553xx && STM32H543xx */ /** * @} */ @@ -448,7 +454,9 @@ typedef struct #define LL_LPTIM_LPTIM1_IC2_RMP_GPIO 0x00000000UL /*!< LPTIM1 IC2 connected to GPIO */ #define LL_LPTIM_LPTIM1_IC2_RMP_LSI LPTIM_CFGR2_IC2SEL_0 /*!< LPTIM1 IC2 connected to LSI */ #define LL_LPTIM_LPTIM1_IC2_RMP_LSE LPTIM_CFGR2_IC2SEL_1 /*!< LPTIM1 IC2 connected to LSE */ +#if defined(STM32H503xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) #define LL_LPTIM_LPTIM1_IC2_RMP_HSE_1M (LPTIM_CFGR2_IC2SEL_0 | LPTIM_CFGR2_IC2SEL_1) /*!< LPTIM1 IC2 connected to HSE_1M */ +#endif /* STM32H503xx || STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ /** * @} */ @@ -457,6 +465,7 @@ typedef struct * @{ */ #define LL_LPTIM_LPTIM2_IC1_RMP_GPIO 0x00000000UL /*!< LPTIM2 IC1 connected to GPIO */ +#if !defined(STM32H553xx) && !defined(STM32H543xx) #if defined(COMP1) #define LL_LPTIM_LPTIM2_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< LPTIM2 IC1 connected to COMP1 */ #endif /* COMP1 */ @@ -468,6 +477,7 @@ typedef struct #if defined(PLAY1) #define LL_LPTIM_LPTIM2_IC1_RMP_PLAY1_OUT5 (LPTIM_CFGR2_IC1SEL_0 | LPTIM_CFGR2_IC1SEL_1) /*!< LPTIM2 IC1 connected to PLAY1 output 5 */ #endif /* PLAY1 */ +#endif /* STM32H553xx && STM32H543xx */ /** * @} */ @@ -1209,26 +1219,26 @@ __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI_1024 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_CSI_128 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI_8 - * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_GPIO (*) * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_COMP1 (*) * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_COMP2 (*) - * @arg @ref LL_LPTIM_LPTIM3_IC2_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM3_IC2_RMP_GPIO (*) * @arg @ref LL_LPTIM_LPTIM3_IC2_RMP_COMP1 (*) * @arg @ref LL_LPTIM_LPTIM3_IC2_RMP_COMP2 (*) - * @arg @ref LL_LPTIM_LPTIM4_IC1_RMP_GPIO - * @arg @ref LL_LPTIM_LPTIM4_IC2_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM4_IC1_RMP_GPIO (*) + * @arg @ref LL_LPTIM_LPTIM4_IC2_RMP_GPIO (*) * @arg @ref LL_LPTIM_LPTIM4_IC2_RMP_COMP1 (*) * @arg @ref LL_LPTIM_LPTIM4_IC2_RMP_EVENTOUT (*) - * @arg @ref LL_LPTIM_LPTIM5_IC1_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM5_IC1_RMP_GPIO (*) * @arg @ref LL_LPTIM_LPTIM5_IC1_RMP_COMP1 (*) * @arg @ref LL_LPTIM_LPTIM5_IC1_RMP_COMP2 (*) * @arg @ref LL_LPTIM_LPTIM5_IC1_RMP_I3C1_IBIACK (*) - * @arg @ref LL_LPTIM_LPTIM5_IC2_RMP_GPIO - * @arg @ref LL_LPTIM_LPTIM6_IC1_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM5_IC2_RMP_GPIO (*) + * @arg @ref LL_LPTIM_LPTIM6_IC1_RMP_GPIO (*) * @arg @ref LL_LPTIM_LPTIM6_IC1_RMP_COMP1 (*) * @arg @ref LL_LPTIM_LPTIM6_IC1_RMP_COMP2 (*) * @arg @ref LL_LPTIM_LPTIM6_IC1_RMP_I3C2_IBIACK (*) - * @arg @ref LL_LPTIM_LPTIM6_IC2_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM6_IC2_RMP_GPIO (*) * * (*) Value not defined in all devices. \n * diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pka.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pka.h index 2dbd07ea2e..39fe6e1910 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pka.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pka.h @@ -516,7 +516,18 @@ __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->SR, PKA_SR_BUSY) == (PKA_SR_BUSY)) ? 1UL : 0UL); } - +#if defined(PKA_SR_INITOK) +/** + * @brief Get PKA init ok flag. + * @rmtoll SR INITOK LL_PKA_IsActiveFlag_INITOK + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_INITOK(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->SR, PKA_SR_INITOK) == (PKA_SR_INITOK)) ? 1UL : 0UL); +} +#endif /* PKA_SR_INITOK */ /** * @brief Clear PKA address error flag. * @rmtoll CLRFR ADDRERRFC LL_PKA_ClearFlag_ADDERR diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_play.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_play.h index bc57d4aa1a..7bd29551fd 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_play.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_play.h @@ -91,22 +91,22 @@ extern "C" { * @{ */ -#define LL_PLAY_LUT0 (0U) /*!< Lookup table 0 */ -#define LL_PLAY_LUT1 (1U) /*!< Lookup table 1 */ -#define LL_PLAY_LUT2 (2U) /*!< Lookup table 2 */ -#define LL_PLAY_LUT3 (3U) /*!< Lookup table 3 */ -#define LL_PLAY_LUT4 (4U) /*!< Lookup table 4 */ -#define LL_PLAY_LUT5 (5U) /*!< Lookup table 5 */ -#define LL_PLAY_LUT6 (6U) /*!< Lookup table 6 */ -#define LL_PLAY_LUT7 (7U) /*!< Lookup table 7 */ -#define LL_PLAY_LUT8 (8U) /*!< Lookup table 8 */ -#define LL_PLAY_LUT9 (9U) /*!< Lookup table 9 */ -#define LL_PLAY_LUT10 (10U) /*!< Lookup table 10 */ -#define LL_PLAY_LUT11 (11U) /*!< Lookup table 11 */ -#define LL_PLAY_LUT12 (12U) /*!< Lookup table 12 */ -#define LL_PLAY_LUT13 (13U) /*!< Lookup table 13 */ -#define LL_PLAY_LUT14 (14U) /*!< Lookup table 14 */ -#define LL_PLAY_LUT15 (15U) /*!< Lookup table 15 */ +#define LL_PLAY_LUT0 (0U) /*!< Lookup table 0 */ +#define LL_PLAY_LUT1 (1U) /*!< Lookup table 1 */ +#define LL_PLAY_LUT2 (2U) /*!< Lookup table 2 */ +#define LL_PLAY_LUT3 (3U) /*!< Lookup table 3 */ +#define LL_PLAY_LUT4 (4U) /*!< Lookup table 4 */ +#define LL_PLAY_LUT5 (5U) /*!< Lookup table 5 */ +#define LL_PLAY_LUT6 (6U) /*!< Lookup table 6 */ +#define LL_PLAY_LUT7 (7U) /*!< Lookup table 7 */ +#define LL_PLAY_LUT8 (8U) /*!< Lookup table 8 */ +#define LL_PLAY_LUT9 (9U) /*!< Lookup table 9 */ +#define LL_PLAY_LUT10 (10U) /*!< Lookup table 10 */ +#define LL_PLAY_LUT11 (11U) /*!< Lookup table 11 */ +#define LL_PLAY_LUT12 (12U) /*!< Lookup table 12 */ +#define LL_PLAY_LUT13 (13U) /*!< Lookup table 13 */ +#define LL_PLAY_LUT14 (14U) /*!< Lookup table 14 */ +#define LL_PLAY_LUT15 (15U) /*!< Lookup table 15 */ #define LL_PLAY_LUT_MAX (16U) /*!< Maximum LUT index */ /** @@ -128,7 +128,7 @@ extern "C" { /** @defgroup PLAY_LL_EC_LUT_INPUT_SOURCE Lookup table Input Source Definitions * @brief Lookup table Input Source definitions which can be used with LL_PLAY_WriteReg function. - * @note Depending of Lookup table, some LUT direct output sources can not be connected. + * @note Depending on the lookup table, some LUT direct output sources cannot be connected. * For example, configuring the LUT direct output 0 as input of LUT 4 will * have no effect and the input signal will stay always at 0. * @{ @@ -227,38 +227,38 @@ extern "C" { #define LL_PLAY_LUT_CLK_GATE_LUT13_OUT_REGISTERED (0x1DUL) /*!< LUT registered output 13 */ #define LL_PLAY_LUT_CLK_GATE_LUT14_OUT_REGISTERED (0x1EUL) /*!< LUT registered output 14 */ #define LL_PLAY_LUT_CLK_GATE_LUT15_OUT_REGISTERED (0x1FUL) /*!< LUT registered output 15 */ -#define LL_PLAY_LUT_CLK_GATE_FILTER0 (0x20UL) /*!< Signal from Input Multiplexer 0 */ -#define LL_PLAY_LUT_CLK_GATE_FILTER1 (0x21UL) /*!< Signal from Input Multiplexer 1 */ -#define LL_PLAY_LUT_CLK_GATE_FILTER2 (0x22UL) /*!< Signal from Input Multiplexer 2 */ -#define LL_PLAY_LUT_CLK_GATE_FILTER3 (0x23UL) /*!< Signal from Input Multiplexer 3 */ -#define LL_PLAY_LUT_CLK_GATE_FILTER4 (0x24UL) /*!< Signal from Input Multiplexer 4 */ -#define LL_PLAY_LUT_CLK_GATE_FILTER5 (0x25UL) /*!< Signal from Input Multiplexer 5 */ -#define LL_PLAY_LUT_CLK_GATE_FILTER6 (0x26UL) /*!< Signal from Input Multiplexer 6 */ -#define LL_PLAY_LUT_CLK_GATE_FILTER7 (0x27UL) /*!< Signal from Input Multiplexer 7 */ -#define LL_PLAY_LUT_CLK_GATE_FILTER8 (0x28UL) /*!< Signal from Input Multiplexer 8 */ -#define LL_PLAY_LUT_CLK_GATE_FILTER9 (0x29UL) /*!< Signal from Input Multiplexer 9 */ -#define LL_PLAY_LUT_CLK_GATE_FILTER10 (0x2AUL) /*!< Signal from Input Multiplexer 10 */ -#define LL_PLAY_LUT_CLK_GATE_FILTER11 (0x2BUL) /*!< Signal from Input Multiplexer 11 */ -#define LL_PLAY_LUT_CLK_GATE_FILTER12 (0x2CUL) /*!< Signal from Input Multiplexer 12 */ -#define LL_PLAY_LUT_CLK_GATE_FILTER13 (0x2DUL) /*!< Signal from Input Multiplexer 13 */ -#define LL_PLAY_LUT_CLK_GATE_FILTER14 (0x2EUL) /*!< Signal from Input Multiplexer 14 */ -#define LL_PLAY_LUT_CLK_GATE_FILTER15 (0x2FUL) /*!< Signal from Input Multiplexer 15 */ -#define LL_PLAY_LUT_CLK_GATE_SWTRIG0 (0x30UL) /*!< Software Trigger 0 */ -#define LL_PLAY_LUT_CLK_GATE_SWTRIG1 (0x31UL) /*!< Software Trigger 1 */ -#define LL_PLAY_LUT_CLK_GATE_SWTRIG2 (0x32UL) /*!< Software Trigger 2 */ -#define LL_PLAY_LUT_CLK_GATE_SWTRIG3 (0x33UL) /*!< Software Trigger 3 */ -#define LL_PLAY_LUT_CLK_GATE_SWTRIG4 (0x34UL) /*!< Software Trigger 4 */ -#define LL_PLAY_LUT_CLK_GATE_SWTRIG5 (0x35UL) /*!< Software Trigger 5 */ -#define LL_PLAY_LUT_CLK_GATE_SWTRIG6 (0x36UL) /*!< Software Trigger 6 */ -#define LL_PLAY_LUT_CLK_GATE_SWTRIG7 (0x37UL) /*!< Software Trigger 7 */ -#define LL_PLAY_LUT_CLK_GATE_SWTRIG8 (0x38UL) /*!< Software Trigger 8 */ -#define LL_PLAY_LUT_CLK_GATE_SWTRIG9 (0x39UL) /*!< Software Trigger 9 */ -#define LL_PLAY_LUT_CLK_GATE_SWTRIG10 (0x3AUL) /*!< Software Trigger 10 */ -#define LL_PLAY_LUT_CLK_GATE_SWTRIG11 (0x3BUL) /*!< Software Trigger 11 */ -#define LL_PLAY_LUT_CLK_GATE_SWTRIG12 (0x3CUL) /*!< Software Trigger 12 */ -#define LL_PLAY_LUT_CLK_GATE_SWTRIG13 (0x3DUL) /*!< Software Trigger 13 */ -#define LL_PLAY_LUT_CLK_GATE_SWTRIG14 (0x3EUL) /*!< Software Trigger 14 */ -#define LL_PLAY_LUT_CLK_GATE_SWTRIG15 (0x3FUL) /*!< Software Trigger 15 */ +#define LL_PLAY_LUT_CLK_GATE_FILTER0 (0x20UL) /*!< Signal from input multiplexer 0 */ +#define LL_PLAY_LUT_CLK_GATE_FILTER1 (0x21UL) /*!< Signal from input multiplexer 1 */ +#define LL_PLAY_LUT_CLK_GATE_FILTER2 (0x22UL) /*!< Signal from input multiplexer 2 */ +#define LL_PLAY_LUT_CLK_GATE_FILTER3 (0x23UL) /*!< Signal from input multiplexer 3 */ +#define LL_PLAY_LUT_CLK_GATE_FILTER4 (0x24UL) /*!< Signal from input multiplexer 4 */ +#define LL_PLAY_LUT_CLK_GATE_FILTER5 (0x25UL) /*!< Signal from input multiplexer 5 */ +#define LL_PLAY_LUT_CLK_GATE_FILTER6 (0x26UL) /*!< Signal from input multiplexer 6 */ +#define LL_PLAY_LUT_CLK_GATE_FILTER7 (0x27UL) /*!< Signal from input multiplexer 7 */ +#define LL_PLAY_LUT_CLK_GATE_FILTER8 (0x28UL) /*!< Signal from input multiplexer 8 */ +#define LL_PLAY_LUT_CLK_GATE_FILTER9 (0x29UL) /*!< Signal from input multiplexer 9 */ +#define LL_PLAY_LUT_CLK_GATE_FILTER10 (0x2AUL) /*!< Signal from input multiplexer 10 */ +#define LL_PLAY_LUT_CLK_GATE_FILTER11 (0x2BUL) /*!< Signal from input multiplexer 11 */ +#define LL_PLAY_LUT_CLK_GATE_FILTER12 (0x2CUL) /*!< Signal from input multiplexer 12 */ +#define LL_PLAY_LUT_CLK_GATE_FILTER13 (0x2DUL) /*!< Signal from input multiplexer 13 */ +#define LL_PLAY_LUT_CLK_GATE_FILTER14 (0x2EUL) /*!< Signal from input multiplexer 14 */ +#define LL_PLAY_LUT_CLK_GATE_FILTER15 (0x2FUL) /*!< Signal from input multiplexer 15 */ +#define LL_PLAY_LUT_CLK_GATE_SWTRIG0 (0x30UL) /*!< Software trigger 0 */ +#define LL_PLAY_LUT_CLK_GATE_SWTRIG1 (0x31UL) /*!< Software trigger 1 */ +#define LL_PLAY_LUT_CLK_GATE_SWTRIG2 (0x32UL) /*!< Software trigger 2 */ +#define LL_PLAY_LUT_CLK_GATE_SWTRIG3 (0x33UL) /*!< Software trigger 3 */ +#define LL_PLAY_LUT_CLK_GATE_SWTRIG4 (0x34UL) /*!< Software trigger 4 */ +#define LL_PLAY_LUT_CLK_GATE_SWTRIG5 (0x35UL) /*!< Software trigger 5 */ +#define LL_PLAY_LUT_CLK_GATE_SWTRIG6 (0x36UL) /*!< Software trigger 6 */ +#define LL_PLAY_LUT_CLK_GATE_SWTRIG7 (0x37UL) /*!< Software trigger 7 */ +#define LL_PLAY_LUT_CLK_GATE_SWTRIG8 (0x38UL) /*!< Software trigger 8 */ +#define LL_PLAY_LUT_CLK_GATE_SWTRIG9 (0x39UL) /*!< Software trigger 9 */ +#define LL_PLAY_LUT_CLK_GATE_SWTRIG10 (0x3AUL) /*!< Software trigger 10 */ +#define LL_PLAY_LUT_CLK_GATE_SWTRIG11 (0x3BUL) /*!< Software trigger 11 */ +#define LL_PLAY_LUT_CLK_GATE_SWTRIG12 (0x3CUL) /*!< Software trigger 12 */ +#define LL_PLAY_LUT_CLK_GATE_SWTRIG13 (0x3DUL) /*!< Software trigger 13 */ +#define LL_PLAY_LUT_CLK_GATE_SWTRIG14 (0x3EUL) /*!< Software trigger 14 */ +#define LL_PLAY_LUT_CLK_GATE_SWTRIG15 (0x3FUL) /*!< Software trigger 15 */ /** * @} @@ -404,7 +404,7 @@ extern "C" { #define LL_PLAY_SWTRIG14 PLAY_SWIN_SWIN14 /*!< Software Trigger 14 */ #define LL_PLAY_SWTRIG15 PLAY_SWIN_SWIN15 /*!< Software Trigger 15 */ -/*! All Software Triggers */ +/*! All software triggers */ #define LL_PLAY_SWTRIG_ALL \ (LL_PLAY_SWTRIG0 \ | LL_PLAY_SWTRIG1 \ @@ -432,11 +432,11 @@ extern "C" { * @{ */ -#define LL_PLAY_ISR_SWINWC PLAY_ISR_SWINWC /*!< Software Trigger write complete */ -#define LL_PLAY_ISR_FLCTLWC PLAY_ISR_FLCTLWC /*!< Edge Trigger write complete */ -#define LL_PLAY_ISR_FLAGS PLAY_ISR_FLAGS /*!< One or more bits in FLSTAT register is active */ -#define LL_PLAY_MSR_SWINWBFS PLAY_MSR_SWINWBFS /*!< Software Trigger write busy */ -#define LL_PLAY_MSR_FLCTLWBFS PLAY_MSR_FLCTLWBFS /*!< Edge Trigger write busy */ +#define LL_PLAY_ISR_SWINWC PLAY_ISR_SWINWC /*!< Software Trigger write complete */ +#define LL_PLAY_ISR_FLCTLWC PLAY_ISR_FLCTLWC /*!< Edge Trigger write complete */ +#define LL_PLAY_ISR_FLAGS PLAY_ISR_FLAGS /*!< One or more bits in FLSTAT register is active */ +#define LL_PLAY_MSR_SWINWBFS PLAY_MSR_SWINWBFS /*!< Software Trigger write busy */ +#define LL_PLAY_MSR_FLCTLWBFS PLAY_MSR_FLCTLWBFS /*!< Edge Trigger write busy */ /** * @} @@ -447,8 +447,8 @@ extern "C" { * @{ */ -#define LL_PLAY_IER_SWINWC_IEN PLAY_IER_SWINWC_IEN /*!< Software Trigger write complete */ -#define LL_PLAY_IER_FLCTLWC_IEN PLAY_IER_FLCTLWC_IEN /*!< Edge Trigger write complete */ +#define LL_PLAY_IER_SWINWC_IEN PLAY_IER_SWINWC_IEN /*!< Software Trigger write complete */ +#define LL_PLAY_IER_FLCTLWC_IEN PLAY_IER_FLCTLWC_IEN /*!< Edge Trigger write complete */ /** * @} @@ -458,8 +458,8 @@ extern "C" { * @{ */ -#define LL_PLAY_LUT_EDGE_TRIGGER_FALLING (0x00000000UL) /*!< Falling edge trigger */ -#define LL_PLAY_LUT_EDGE_TRIGGER_RISING (0xFFFFFFFFUL) /*!< Rising edge trigger */ +#define LL_PLAY_LUT_EDGE_TRIGGER_FALLING (0x00000000UL) /*!< Falling edge trigger */ +#define LL_PLAY_LUT_EDGE_TRIGGER_RISING (0xFFFFFFFFUL) /*!< Rising edge trigger */ /** * @} @@ -469,34 +469,41 @@ extern "C" { * @{ */ -#define LL_PLAY_EDGE_DETECTION_MODE_BYPASSED (0U) /*!< Bypassed mode: No edge detection */ -#define LL_PLAY_EDGE_DETECTION_MODE_RISING (PLAY_FILTxCFG_EDGEDET_0) /*!< Rising edge detection mode */ -#define LL_PLAY_EDGE_DETECTION_MODE_FALLING (PLAY_FILTxCFG_EDGEDET_1) /*!< Falling edge detection mode */ -#define LL_PLAY_EDGE_DETECTION_MODE_RISING_FALLING (PLAY_FILTxCFG_EDGEDET_0 \ - | PLAY_FILTxCFG_EDGEDET_1) /*!< Both rising and falling edge detection mode */ +#define LL_PLAY_EDGE_DETECTION_MODE_BYPASSED (0U) /*!< Bypassed mode: No edge detection */ +#define LL_PLAY_EDGE_DETECTION_MODE_RISING (PLAY_FILTxCFG_EDGEDET_0) /*!< Rising edge detection mode */ +#define LL_PLAY_EDGE_DETECTION_MODE_FALLING (PLAY_FILTxCFG_EDGEDET_1) /*!< Falling edge detection mode */ +#define LL_PLAY_EDGE_DETECTION_MODE_RISING_FALLING (PLAY_FILTxCFG_EDGEDET_0 \ + | PLAY_FILTxCFG_EDGEDET_1) /*!< Both rising and falling edge detection mode */ /** * @} */ -/** @defgroup PLAY_LL_EC_TRUSTZONE_ATTRIBUTES TrustZone Attributes Definitions +/** @defgroup PLAY_LL_EC_ATTRIBUTES PLAY Secure/Privilege attributes * @{ */ -#define LL_PLAY_NPRIV (0U) /*!< Non-Privileged mode */ -#define LL_PLAY_CONFIG_PRIV (PLAY_PRIVCFGR_PRIV_0) /*!< Configuration Privileged mode */ -#define LL_PLAY_FULL_PRIV (PLAY_PRIVCFGR_PRIV_0 | PLAY_PRIVCFGR_PRIV_1) /*!< Full Privileged mode */ +#define LL_PLAY_ATTR_NSEC (0U) /*!< Non-secure attribute */ +#define LL_PLAY_ATTR_SEC (1U) /*!< Secure attribute on configuration registers */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define LL_PLAY_NSEC (0U) /*!< Non-Secure mode */ -#define LL_PLAY_CONFIG_SEC (PLAY_SECCFGR_SEC_0) /*!< Configuration Secure mode */ -#define LL_PLAY_FULL_SEC (PLAY_SECCFGR_SEC_0 | PLAY_SECCFGR_SEC_1) /*!< Full Secure mode */ +#define LL_PLAY_ATTR_NPRIV (0U) /*!< Non-privileged attribute */ +#define LL_PLAY_ATTR_PRIV (1U) /*!< Privileged attribute on configuration registers */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @} */ +/** @defgroup PLAY_LL_EC_ITEMS PLAY Attributes Items + * @{ + */ + +#define LL_PLAY_SEC_ITEM_CONFIG (PLAY_SECCFGR_SEC_0) /*!< PLAY configuration registers items */ +#define LL_PLAY_SEC_ITEM_ALL (PLAY_SECCFGR_SEC_0 | PLAY_SECCFGR_SEC_1) /*!< All PLAY registers items */ + +#define LL_PLAY_PRIV_ITEM_CONFIG (PLAY_PRIVCFGR_PRIV_0) /*!< PLAY configuration registers items */ +#define LL_PLAY_PRIV_ITEM_ALL (PLAY_PRIVCFGR_PRIV_0 | PLAY_PRIVCFGR_PRIV_1) /*!< All PLAY registers items */ + + /** * @} */ @@ -519,6 +526,9 @@ extern "C" { */ /* Exported macro ------------------------------------------------------------*/ +/** @defgroup PLAY_LL_Exported_Macros LL PLAY Macros + * @{ + */ /** @defgroup PLAY_LL_EM_WRITE_READ Common Write and Read registers Macros * @{ */ @@ -558,9 +568,10 @@ extern "C" { /** * @brief Configure the filter of a Logic Array input. - * @rmtoll FILTxCFG PREMUXSEL LL_PLAY_INPUT_Config\n - * FILTxCFG EDGEDET LL_PLAY_INPUT_Config\n - * FILTxCFG WIDTH LL_PLAY_INPUT_Config + * @rmtoll + * FILTxCFG PREMUXSEL LL_PLAY_INPUT_Config \n + * FILTxCFG EDGEDET LL_PLAY_INPUT_Config \n + * FILTxCFG WIDTH LL_PLAY_INPUT_Config * @param playx PLAY Instance. * @param input_mux Value can be one of the following values: * @arg @ref LL_PLAY_IN0 @@ -586,7 +597,7 @@ extern "C" { * @arg @ref LL_PLAY_EDGE_DETECTION_MODE_FALLING * @arg @ref LL_PLAY_EDGE_DETECTION_MODE_RISING_FALLING * @param min_pulse_width Value in range 0x0000 to 0x00FF. - * @note This function set all parameters of a Logic Array input. + * @note This function sets all parameters of a Logic Array input. * These parameters can also be set individually using * dedicated functions: * - @ref LL_PLAY_INPUT_SetMinimumPulseWidth() @@ -597,7 +608,7 @@ __STATIC_INLINE void LL_PLAY_INPUT_Config(PLAY_TypeDef *playx, uint32_t input_mux, uint32_t premuxsel_value, uint32_t edge_detection_mode, uint32_t min_pulse_width) { - MODIFY_REG(playx->FILTCFG[input_mux & 0x0FU], + MODIFY_REG(playx->FILTCFG[input_mux & (LL_PLAY_IN_MAX - 1U)], (PLAY_FILTxCFG_WIDTH | PLAY_FILTxCFG_EDGEDET | PLAY_FILTxCFG_PREMUXSEL), ((min_pulse_width << PLAY_FILTxCFG_WIDTH_Pos) | edge_detection_mode | (premuxsel_value << PLAY_FILTxCFG_PREMUXSEL_Pos))); @@ -605,10 +616,12 @@ __STATIC_INLINE void LL_PLAY_INPUT_Config(PLAY_TypeDef *playx, /** * @brief Configure the inputs and the clock enable of a LUT. - * @rmtoll LExCFG2 IN_0_SEL LL_PLAY_LUT_ConfigInputs\n - * LExCFG2 IN_1_SEL LL_PLAY_LUT_ConfigInputs\n - * LExCFG2 IN_2_SEL LL_PLAY_LUT_ConfigInputs\n - * LExCFG2 IN_3_SEL LL_PLAY_LUT_ConfigInputs + * @rmtoll + * LExCFG2 IN_0_SEL LL_PLAY_LUT_ConfigInputs \n + * LExCFG2 IN_1_SEL LL_PLAY_LUT_ConfigInputs \n + * LExCFG2 IN_2_SEL LL_PLAY_LUT_ConfigInputs \n + * LExCFG2 IN_3_SEL LL_PLAY_LUT_ConfigInputs \n + * LExCFG2 CK_SEL LL_PLAY_LUT_ConfigInputs * @param playx PLAY Instance. * @param lut Value can be one of the following values: * @arg @ref LL_PLAY_LUT0 @@ -747,7 +760,7 @@ __STATIC_INLINE void LL_PLAY_INPUT_Config(PLAY_TypeDef *playx, * @arg @ref LL_PLAY_LUT_CLK_GATE_SWTRIG13 * @arg @ref LL_PLAY_LUT_CLK_GATE_SWTRIG14 * @arg @ref LL_PLAY_LUT_CLK_GATE_SWTRIG15 - * @note This function set some parameters of a LUT. + * @note This function sets some parameters of a LUT. * These parameters can also be set individually using * dedicated functions: * - @ref LL_PLAY_LUT_SetSource() @@ -758,7 +771,7 @@ __STATIC_INLINE void LL_PLAY_LUT_ConfigInputs(PLAY_TypeDef *playx, uint32_t lut, uint32_t source_sel2, uint32_t source_sel3, uint32_t clk_enable) { - MODIFY_REG(playx->LECFG2[lut], + MODIFY_REG(playx->LECFG2[lut & (LL_PLAY_LUT_MAX - 1U)], (PLAY_LExCFG2_IN0_SEL | PLAY_LExCFG2_IN1_SEL | PLAY_LExCFG2_IN2_SEL | PLAY_LExCFG2_IN3_SEL | PLAY_LExCFG2_CK_SEL), ((source_sel0 << PLAY_LExCFG2_IN0_SEL_Pos) | (source_sel1 << PLAY_LExCFG2_IN1_SEL_Pos) @@ -768,7 +781,8 @@ __STATIC_INLINE void LL_PLAY_LUT_ConfigInputs(PLAY_TypeDef *playx, uint32_t lut, /** * @brief Lock the Configuration registers. - * @rmtoll CFGCR UNLOCK LL_PLAY_Lock + * @rmtoll + * CFGCR UNLOCK LL_PLAY_Lock * @param playx PLAY Instance. */ __STATIC_INLINE void LL_PLAY_Lock(PLAY_TypeDef *playx) @@ -778,7 +792,8 @@ __STATIC_INLINE void LL_PLAY_Lock(PLAY_TypeDef *playx) /** * @brief Unlock the Configuration registers. - * @rmtoll CFGCR UNLOCK LL_PLAY_Unlock + * @rmtoll + * CFGCR UNLOCK LL_PLAY_Unlock * @param playx PLAY Instance. */ __STATIC_INLINE void LL_PLAY_Unlock(PLAY_TypeDef *playx) @@ -788,9 +803,10 @@ __STATIC_INLINE void LL_PLAY_Unlock(PLAY_TypeDef *playx) /** * @brief Indicates whether the PLAY Configuration registers are locked. - * @rmtoll CFGCR UNLOCK LL_PLAY_IsLocked + * @rmtoll + * CFGCR UNLOCK LL_PLAY_IsLocked * @param playx PLAY Instance. - * @return Status of bit (1 or 0). + * @return 1: locked, 0: unlocked. */ __STATIC_INLINE uint32_t LL_PLAY_IsLocked(const PLAY_TypeDef *playx) { @@ -799,7 +815,8 @@ __STATIC_INLINE uint32_t LL_PLAY_IsLocked(const PLAY_TypeDef *playx) /** * @brief Configure Minimum Pulse Width of an input filter. - * @rmtoll FILTxCFG WIDTH LL_PLAY_INPUT_SetMinimumPulseWidth + * @rmtoll + * FILTxCFG WIDTH LL_PLAY_INPUT_SetMinimumPulseWidth * @param playx PLAY Instance. * @param input_mux Value can be one of the following values: * @arg @ref LL_PLAY_IN0 @@ -823,12 +840,14 @@ __STATIC_INLINE uint32_t LL_PLAY_IsLocked(const PLAY_TypeDef *playx) __STATIC_INLINE void LL_PLAY_INPUT_SetMinimumPulseWidth(PLAY_TypeDef *playx, uint32_t input_mux, uint32_t min_pulse_width) { - MODIFY_REG(playx->FILTCFG[input_mux & 0x0FU], PLAY_FILTxCFG_WIDTH, (min_pulse_width << PLAY_FILTxCFG_WIDTH_Pos)); + MODIFY_REG(playx->FILTCFG[input_mux & (LL_PLAY_IN_MAX - 1U)], PLAY_FILTxCFG_WIDTH, + (min_pulse_width << PLAY_FILTxCFG_WIDTH_Pos)); } /** * @brief Get the Minimum Pulse Width. - * @rmtoll FILTxCFG WIDTH LL_PLAY_INPUT_GetMinimumPulseWidth + * @rmtoll + * FILTxCFG WIDTH LL_PLAY_INPUT_GetMinimumPulseWidth * @param playx PLAY Instance. * @param input_mux Value can be one of the following values: * @arg @ref LL_PLAY_IN0 @@ -851,12 +870,14 @@ __STATIC_INLINE void LL_PLAY_INPUT_SetMinimumPulseWidth(PLAY_TypeDef *playx, uin */ __STATIC_INLINE uint32_t LL_PLAY_INPUT_GetMinimumPulseWidth(const PLAY_TypeDef *playx, uint32_t input_mux) { - return (uint32_t)(READ_BIT(playx->FILTCFG[input_mux], PLAY_FILTxCFG_WIDTH)); + return (uint32_t)(READ_BIT(playx->FILTCFG[input_mux & (LL_PLAY_IN_MAX - 1U)], + PLAY_FILTxCFG_WIDTH) >> PLAY_FILTxCFG_WIDTH_Pos); } /** * @brief Configure Filtering Edge mode. - * @rmtoll FILTxCFG EDGEDET LL_PLAY_INPUT_SetEdgeDetectionMode + * @rmtoll + * FILTxCFG EDGEDET LL_PLAY_INPUT_SetEdgeDetectionMode * @param playx PLAY Instance. * @param input_mux Value can be one of the following values: * @arg @ref LL_PLAY_IN0 @@ -884,12 +905,13 @@ __STATIC_INLINE uint32_t LL_PLAY_INPUT_GetMinimumPulseWidth(const PLAY_TypeDef * __STATIC_INLINE void LL_PLAY_INPUT_SetEdgeDetectionMode(PLAY_TypeDef *playx, uint32_t input_mux, uint32_t edge_detection_mode) { - MODIFY_REG(playx->FILTCFG[input_mux], PLAY_FILTxCFG_EDGEDET, edge_detection_mode); + MODIFY_REG(playx->FILTCFG[input_mux & (LL_PLAY_IN_MAX - 1U)], PLAY_FILTxCFG_EDGEDET, edge_detection_mode); } /** * @brief Get the Filtering Edge Detection Mode configuration of a PLAY input. - * @rmtoll FILTxCFG EDGEDET LL_PLAY_INPUT_GetEdgeDetectionMode + * @rmtoll + * FILTxCFG EDGEDET LL_PLAY_INPUT_GetEdgeDetectionMode * @param playx PLAY Instance. * @param input_mux Value can be one of the following values: * @arg @ref LL_PLAY_IN0 @@ -916,12 +938,13 @@ __STATIC_INLINE void LL_PLAY_INPUT_SetEdgeDetectionMode(PLAY_TypeDef *playx, uin */ __STATIC_INLINE uint32_t LL_PLAY_INPUT_GetEdgeDetectionMode(const PLAY_TypeDef *playx, uint32_t input_mux) { - return (uint32_t)(READ_BIT(playx->FILTCFG[input_mux], PLAY_FILTxCFG_EDGEDET)); + return (uint32_t)(READ_BIT(playx->FILTCFG[input_mux & (LL_PLAY_IN_MAX - 1U)], PLAY_FILTxCFG_EDGEDET)); } /** * @brief Configure the signal source of a PLAY input. - * @rmtoll FILTxCFG PREMUXSEL LL_PLAY_INPUT_SetSource + * @rmtoll + * FILTxCFG PREMUXSEL LL_PLAY_INPUT_SetSource * @param playx PLAY Instance. * @param input_mux Value can be one of the following values: * @arg @ref LL_PLAY_IN0 @@ -950,7 +973,8 @@ __STATIC_INLINE void LL_PLAY_INPUT_SetSource(PLAY_TypeDef *playx, uint32_t input /** * @brief Return the signal source of a PLAY input. - * @rmtoll FILTxCFG PREMUXSEL LL_PLAY_INPUT_GetSource + * @rmtoll + * FILTxCFG PREMUXSEL LL_PLAY_INPUT_GetSource * @param playx PLAY Instance. * @param input_mux Value can be one of the following values: * @arg @ref LL_PLAY_IN0 @@ -979,7 +1003,8 @@ __STATIC_INLINE uint32_t LL_PLAY_INPUT_GetSource(const PLAY_TypeDef *playx, uint /** * @brief Configure the TruthTable value of a Lookup table. - * @rmtoll LExCFG1 LUT LL_PLAY_LUT_SetTruthTable + * @rmtoll + * LExCFG1 LUT LL_PLAY_LUT_SetTruthTable * @param playx PLAY Instance. * @param lut Value can be one of the following values: * @arg @ref LL_PLAY_LUT0 @@ -1007,7 +1032,8 @@ __STATIC_INLINE void LL_PLAY_LUT_SetTruthTable(PLAY_TypeDef *playx, uint32_t lut /** * @brief Get the LUT value of a Lookup table. - * @rmtoll LExCFG1 LUT LL_PLAY_LUT_GetTruthTable + * @rmtoll + * LExCFG1 LUT LL_PLAY_LUT_GetTruthTable * @param playx PLAY Instance. * @param lut Value can be one of the following values: * @arg @ref LL_PLAY_LUT0 @@ -1030,15 +1056,16 @@ __STATIC_INLINE void LL_PLAY_LUT_SetTruthTable(PLAY_TypeDef *playx, uint32_t lut */ __STATIC_INLINE uint32_t LL_PLAY_LUT_GetTruthTable(const PLAY_TypeDef *playx, uint32_t lut) { - return (uint32_t)(READ_BIT(playx->LECFG1[lut], PLAY_LExCFG1_LUT) >> PLAY_LExCFG1_LUT_Pos); + return (uint32_t)(READ_BIT(playx->LECFG1[lut & (LL_PLAY_LUT_MAX - 1U)], PLAY_LExCFG1_LUT) >> PLAY_LExCFG1_LUT_Pos); } /** * @brief Configure an Input of a Lookup table. - * @rmtoll LExCFG2 IN0_SEL LL_PLAY_LUT_SetSource\n - * LExCFG2 IN1_SEL LL_PLAY_LUT_SetSource\n - * LExCFG2 IN2_SEL LL_PLAY_LUT_SetSource\n - * LExCFG2 IN3_SEL LL_PLAY_LUT_SetSource + * @rmtoll + * LExCFG2 IN0_SEL LL_PLAY_LUT_SetSource \n + * LExCFG2 IN1_SEL LL_PLAY_LUT_SetSource \n + * LExCFG2 IN2_SEL LL_PLAY_LUT_SetSource \n + * LExCFG2 IN3_SEL LL_PLAY_LUT_SetSource * @param playx PLAY Instance. * @param lut Value can be one of the following values: * @arg @ref LL_PLAY_LUT0 @@ -1130,16 +1157,18 @@ __STATIC_INLINE uint32_t LL_PLAY_LUT_GetTruthTable(const PLAY_TypeDef *playx, ui */ __STATIC_INLINE void LL_PLAY_LUT_SetSource(PLAY_TypeDef *playx, uint32_t lut, uint32_t input_idx, uint32_t source_sel) { - MODIFY_REG(playx->LECFG2[lut], (PLAY_LExCFG2_IN0_SEL << (input_idx * PLAY_LExCFG2_IN1_SEL_Pos)), + MODIFY_REG(playx->LECFG2[lut & (LL_PLAY_LUT_MAX - 1U)], + (PLAY_LExCFG2_IN0_SEL << (input_idx * PLAY_LExCFG2_IN1_SEL_Pos)), (source_sel << (input_idx * PLAY_LExCFG2_IN1_SEL_Pos))); } /** * @brief Get the value of an input of a Lookup table. - * @rmtoll LExCFG2 IN0_SEL LL_PLAY_LUT_GetSource\n - * LExCFG2 IN1_SEL LL_PLAY_LUT_GetSource\n - * LExCFG2 IN2_SEL LL_PLAY_LUT_GetSource\n - * LExCFG2 IN3_SEL LL_PLAY_LUT_GetSource + * @rmtoll + * LExCFG2 IN0_SEL LL_PLAY_LUT_GetSource \n + * LExCFG2 IN1_SEL LL_PLAY_LUT_GetSource \n + * LExCFG2 IN2_SEL LL_PLAY_LUT_GetSource \n + * LExCFG2 IN3_SEL LL_PLAY_LUT_GetSource * @param playx PLAY Instance. * @param lut Value can be one of the following values: * @arg @ref LL_PLAY_LUT0 @@ -1231,14 +1260,15 @@ __STATIC_INLINE void LL_PLAY_LUT_SetSource(PLAY_TypeDef *playx, uint32_t lut, ui */ __STATIC_INLINE uint32_t LL_PLAY_LUT_GetSource(const PLAY_TypeDef *playx, uint32_t lut, uint32_t input_idx) { - return (uint32_t)((READ_BIT(playx->LECFG2[lut], + return (uint32_t)((READ_BIT(playx->LECFG2[lut & (LL_PLAY_LUT_MAX - 1U)], (PLAY_LExCFG2_IN0_SEL << (input_idx * PLAY_LExCFG2_IN1_SEL_Pos)))) >> (input_idx * PLAY_LExCFG2_IN1_SEL_Pos)); } /** * @brief Configure the Clock Gate of a Lookup table. - * @rmtoll LExCFG2 CK_SEL LL_PLAY_LUT_SetClockGate + * @rmtoll + * LExCFG2 CK_SEL LL_PLAY_LUT_SetClockGate * @param playx PLAY Instance. * @param lut Value can be one of the following values: * @arg @ref LL_PLAY_LUT0 @@ -1312,12 +1342,14 @@ __STATIC_INLINE uint32_t LL_PLAY_LUT_GetSource(const PLAY_TypeDef *playx, uint32 */ __STATIC_INLINE void LL_PLAY_LUT_SetClockGate(PLAY_TypeDef *playx, uint32_t lut, uint32_t clk_gate) { - MODIFY_REG(playx->LECFG2[lut], PLAY_LExCFG2_CK_SEL, clk_gate << PLAY_LExCFG2_CK_SEL_Pos); + MODIFY_REG(playx->LECFG2[lut & (LL_PLAY_LUT_MAX - 1U)], + PLAY_LExCFG2_CK_SEL, clk_gate << PLAY_LExCFG2_CK_SEL_Pos); } /** * @brief Get the Clock Gate of a Lookup table. - * @rmtoll LExCFG2 CK_SEL LL_PLAY_LUT_GetClockGate + * @rmtoll + * LExCFG2 CK_SEL LL_PLAY_LUT_GetClockGate * @param playx PLAY Instance. * @param lut Value can be one of the following values: * @arg @ref LL_PLAY_LUT0 @@ -1391,13 +1423,15 @@ __STATIC_INLINE void LL_PLAY_LUT_SetClockGate(PLAY_TypeDef *playx, uint32_t lut, */ __STATIC_INLINE uint32_t LL_PLAY_LUT_GetClockGate(const PLAY_TypeDef *playx, uint32_t lut) { - return (uint32_t)(READ_BIT(playx->LECFG2[lut], PLAY_LExCFG2_CK_SEL) >> PLAY_LExCFG2_CK_SEL_Pos); + return (uint32_t)(READ_BIT(playx->LECFG2[lut & (LL_PLAY_LUT_MAX - 1U)], + PLAY_LExCFG2_CK_SEL) >> PLAY_LExCFG2_CK_SEL_Pos); } /** * @brief Get LUT Output status. - * @rmtoll OSR LEOUTD LL_PLAY_LUT_GetStatus - * @rmtoll OSR LEOUTR LL_PLAY_LUT_GetStatus + * @rmtoll + * OSR LEOUTD LL_PLAY_LUT_GetStatus \n + * OSR LEOUTR LL_PLAY_LUT_GetStatus * @param playx PLAY Instance. * @param output Value can be a one of the following values: * @arg @ref LL_PLAY_LUT0_OUT_DIRECT @@ -1442,7 +1476,8 @@ __STATIC_INLINE uint32_t LL_PLAY_LUT_GetStatus(const PLAY_TypeDef *playx, uint32 /** * @brief Configure the source of an PLAY output. - * @rmtoll OUTxCFG SEL LL_PLAY_OUTPUT_SetSource + * @rmtoll + * OUTxCFG SEL LL_PLAY_OUTPUT_SetSource * @param playx PLAY Instance. * @param output_mux Value can be one of the following values: * @arg @ref LL_PLAY_OUT0 @@ -1497,12 +1532,14 @@ __STATIC_INLINE uint32_t LL_PLAY_LUT_GetStatus(const PLAY_TypeDef *playx, uint32 */ __STATIC_INLINE void LL_PLAY_OUTPUT_SetSource(PLAY_TypeDef *playx, uint32_t output_mux, uint32_t source) { - MODIFY_REG(playx->OUTCFG[output_mux], PLAY_OUTxCFG_SEL, (POSITION_VAL(source)) << PLAY_OUTxCFG_SEL_Pos); + MODIFY_REG(playx->OUTCFG[output_mux & (LL_PLAY_OUT_MAX - 1U)], PLAY_OUTxCFG_SEL, + (POSITION_VAL(source)) << PLAY_OUTxCFG_SEL_Pos); } /** * @brief Get the source of an PLAY output. - * @rmtoll OUTxCFG SEL LL_PLAY_OUTPUT_GetSource + * @rmtoll + * OUTxCFG SEL LL_PLAY_OUTPUT_GetSource * @param playx PLAY Instance. * @param output_mux Value can be one of the following values: * @arg @ref LL_PLAY_OUT0 @@ -1557,7 +1594,8 @@ __STATIC_INLINE void LL_PLAY_OUTPUT_SetSource(PLAY_TypeDef *playx, uint32_t outp */ __STATIC_INLINE uint32_t LL_PLAY_OUTPUT_GetSource(const PLAY_TypeDef *playx, uint32_t output_mux) { - return (uint32_t)(1UL << (READ_BIT(playx->OUTCFG[output_mux], PLAY_OUTxCFG_SEL) >> PLAY_OUTxCFG_SEL_Pos)); + return (uint32_t)(1UL << (READ_BIT(playx->OUTCFG[output_mux & (LL_PLAY_OUT_MAX - 1U)], + PLAY_OUTxCFG_SEL) >> PLAY_OUTxCFG_SEL_Pos)); } /** @@ -1570,7 +1608,8 @@ __STATIC_INLINE uint32_t LL_PLAY_OUTPUT_GetSource(const PLAY_TypeDef *playx, uin /** * @brief Set High level to a Software Trigger input. - * @rmtoll SWINSET SWIN LL_PLAY_SetSWTrigger + * @rmtoll + * SWINSET SWIN LL_PLAY_SetSWTrigger * @param playx PLAY Instance. * @param msk_swtriggers Value can be a combination of the following values: * @arg @ref LL_PLAY_SWTRIG0 @@ -1598,7 +1637,8 @@ __STATIC_INLINE void LL_PLAY_SetSWTrigger(PLAY_TypeDef *playx, uint32_t msk_swtr /** * @brief Set Low level to a Software Trigger input. - * @rmtoll SWINCLR SWIN LL_PLAY_ResetSWTrigger + * @rmtoll + * SWINCLR SWIN LL_PLAY_ResetSWTrigger * @param playx PLAY Instance. * @param msk_swtriggers Value can be a combination of the following values: * @arg @ref LL_PLAY_SWTRIG0 @@ -1626,7 +1666,8 @@ __STATIC_INLINE void LL_PLAY_ResetSWTrigger(PLAY_TypeDef *playx, uint32_t msk_sw /** * @brief Get the level of a Software Trigger input. - * @rmtoll SWIN SWIN LL_PLAY_IsSWTriggerSet + * @rmtoll + * SWIN SWIN LL_PLAY_IsSWTriggerSet * @param playx PLAY Instance. * @param swtrigger Value can be a one of the following values: * @arg @ref LL_PLAY_SWTRIG0 @@ -1654,7 +1695,8 @@ __STATIC_INLINE uint32_t LL_PLAY_IsSWTriggerSet(const PLAY_TypeDef *playx, uint3 /** * @brief Toggle the level of Software Trigger input. - * @rmtoll SWIN SWIN LL_PLAY_ToggleSWTrigger + * @rmtoll + * SWIN SWIN LL_PLAY_ToggleSWTrigger * @param playx PLAY Instance. * @param msk_swtriggers Value can be a combination of the following values: * @arg @ref LL_PLAY_SWTRIG0 @@ -1691,8 +1733,9 @@ __STATIC_INLINE void LL_PLAY_ToggleSWTrigger(PLAY_TypeDef *playx, uint32_t msk_s /** * @brief Enable lookup table output flag interrupt. - * @rmtoll FLIER FLAGD_IEN LL_PLAY_LUT_EnableIT - * @rmtoll FLIER FLAGR_IEN LL_PLAY_LUT_EnableIT + * @rmtoll + * FLIER FLAGD_IEN LL_PLAY_LUT_EnableIT \n + * FLIER FLAGR_IEN LL_PLAY_LUT_EnableIT * @param playx PLAY Instance. * @param msk_its Value can be a combination of the following values: * @arg @ref LL_PLAY_LUT0_OUT_DIRECT @@ -1737,8 +1780,9 @@ __STATIC_INLINE void LL_PLAY_LUT_EnableIT(PLAY_TypeDef *playx, uint32_t msk_its) /** * @brief Disable lookup table output flag interrupt. - * @rmtoll FLIER FLAGD_IEN LL_PLAY_LUT_DisableIT - * @rmtoll FLIER FLAGR_IEN LL_PLAY_LUT_DisableIT + * @rmtoll + * FLIER FLAGD_IEN LL_PLAY_LUT_DisableIT \n + * FLIER FLAGR_IEN LL_PLAY_LUT_DisableIT * @param playx PLAY Instance. * @param msk_its Value can be a combination of the following values: * @arg @ref LL_PLAY_LUT0_OUT_DIRECT @@ -1783,8 +1827,9 @@ __STATIC_INLINE void LL_PLAY_LUT_DisableIT(PLAY_TypeDef *playx, uint32_t msk_its /** * @brief Check lookup table output flag interrupt. - * @rmtoll FLIER FLAGD_IEN LL_PLAY_LUT_IsEnabledIT - * @rmtoll FLIER FLAGR_IEN LL_PLAY_LUT_IsEnabledIT + * @rmtoll + * FLIER FLAGD_IEN LL_PLAY_LUT_IsEnabledIT \n + * FLIER FLAGR_IEN LL_PLAY_LUT_IsEnabledIT * @param playx PLAY Instance. * @param flag Value can be a one of the following values: * @arg @ref LL_PLAY_LUT0_OUT_DIRECT @@ -1828,8 +1873,9 @@ __STATIC_INLINE uint32_t LL_PLAY_LUT_IsEnabledIT(const PLAY_TypeDef *playx, uint /** * @brief Get the lookup table output flag interrupt mask. - * @rmtoll FLIER FLAGD_IEN LL_PLAY_LUT_GetIT - * @rmtoll FLIER FLAGR_IEN LL_PLAY_LUT_GetIT + * @rmtoll + * FLIER FLAGD_IEN LL_PLAY_LUT_GetIT \n + * FLIER FLAGR_IEN LL_PLAY_LUT_GetIT * @param playx PLAY Instance. * @return Mask of enabled Lookup table output interrupts. */ @@ -1840,7 +1886,8 @@ __STATIC_INLINE uint32_t LL_PLAY_LUT_GetIT(const PLAY_TypeDef *playx) /** * @brief Enable Software Trigger write complete interrupt. - * @rmtoll IER SWINWC_IEN LL_PLAY_EnableIT_SWTriggerWriteComplete + * @rmtoll + * IER SWINWC_IEN LL_PLAY_EnableIT_SWTriggerWriteComplete * @param playx PLAY Instance. */ __STATIC_INLINE void LL_PLAY_EnableIT_SWTriggerWriteComplete(PLAY_TypeDef *playx) @@ -1850,7 +1897,8 @@ __STATIC_INLINE void LL_PLAY_EnableIT_SWTriggerWriteComplete(PLAY_TypeDef *playx /** * @brief Disable Software Trigger write complete interrupt. - * @rmtoll IER SWINWC_IEN LL_PLAY_DisableIT_SWTriggerWriteComplete + * @rmtoll + * IER SWINWC_IEN LL_PLAY_DisableIT_SWTriggerWriteComplete * @param playx PLAY Instance. */ __STATIC_INLINE void LL_PLAY_DisableIT_SWTriggerWriteComplete(PLAY_TypeDef *playx) @@ -1860,7 +1908,8 @@ __STATIC_INLINE void LL_PLAY_DisableIT_SWTriggerWriteComplete(PLAY_TypeDef *play /** * @brief Check Software Trigger write complete interrupt. - * @rmtoll IER SWINWC_IEN LL_PLAY_IsEnabledIT_SWTriggerWriteComplete + * @rmtoll + * IER SWINWC_IEN LL_PLAY_IsEnabledIT_SWTriggerWriteComplete * @param playx PLAY Instance. * @return State of bit (1 or 0). */ @@ -1871,7 +1920,8 @@ __STATIC_INLINE uint32_t LL_PLAY_IsEnabledIT_SWTriggerWriteComplete(const PLAY_T /** * @brief Enable Edge Trigger write complete interrupt. - * @rmtoll IER FLCTLWC_IEN LL_PLAY_LUT_EnableIT_EdgeTriggerWriteComplete + * @rmtoll + * IER FLCTLWC_IEN LL_PLAY_LUT_EnableIT_EdgeTriggerWriteComplete * @param playx PLAY Instance. */ __STATIC_INLINE void LL_PLAY_LUT_EnableIT_EdgeTriggerWriteComplete(PLAY_TypeDef *playx) @@ -1881,7 +1931,8 @@ __STATIC_INLINE void LL_PLAY_LUT_EnableIT_EdgeTriggerWriteComplete(PLAY_TypeDef /** * @brief Disable Edge Trigger write complete interrupt. - * @rmtoll IER FLCTLWC_IEN LL_PLAY_LUT_DisableIT_EdgeTriggerWriteComplete + * @rmtoll + * IER FLCTLWC_IEN LL_PLAY_LUT_DisableIT_EdgeTriggerWriteComplete * @param playx PLAY Instance. */ __STATIC_INLINE void LL_PLAY_LUT_DisableIT_EdgeTriggerWriteComplete(PLAY_TypeDef *playx) @@ -1891,7 +1942,8 @@ __STATIC_INLINE void LL_PLAY_LUT_DisableIT_EdgeTriggerWriteComplete(PLAY_TypeDef /** * @brief Check Edge Trigger write complete interrupt. - * @rmtoll IER FLCTLWC_IEN LL_PLAY_LUT_IsEnabledIT_EdgeTriggerWriteComplete + * @rmtoll + * IER FLCTLWC_IEN LL_PLAY_LUT_IsEnabledIT_EdgeTriggerWriteComplete * @param playx PLAY Instance. * @return State of bit (1 or 0). */ @@ -1910,8 +1962,9 @@ __STATIC_INLINE uint32_t LL_PLAY_LUT_IsEnabledIT_EdgeTriggerWriteComplete(const /** * @brief Set flag transition of all lookup table outputs. - * @rmtoll FLCTL FLAGD_EDGE LL_PLAY_LUT_ConfigEdgeTrigger - * @rmtoll FLCTL FLAGR_EDGE LL_PLAY_LUT_ConfigEdgeTrigger + * @rmtoll + * FLCTL FLAGD_EDGE LL_PLAY_LUT_ConfigEdgeTrigger \n + * FLCTL FLAGR_EDGE LL_PLAY_LUT_ConfigEdgeTrigger * @param playx PLAY Instance. * @param msk_rising_flags Mask of flags to configure on rising edge. * The others flag will be configured on falling edge. @@ -1960,8 +2013,9 @@ __STATIC_INLINE void LL_PLAY_LUT_ConfigEdgeTrigger(PLAY_TypeDef *playx, uint32_t /** * @brief Set flag transition for lookup table output. - * @rmtoll FLCTL FLAGD_EDGE LL_PLAY_LUT_SetEdgeTrigger - * @rmtoll FLCTL FLAGR_EDGE LL_PLAY_LUT_SetEdgeTrigger + * @rmtoll + * FLCTL FLAGD_EDGE LL_PLAY_LUT_SetEdgeTrigger \n + * FLCTL FLAGR_EDGE LL_PLAY_LUT_SetEdgeTrigger * @param playx PLAY Instance. * @param msk_out_falling Value can be a combination of the following values: * @arg @ref LL_PLAY_LUT0_OUT_DIRECT @@ -2045,8 +2099,9 @@ __STATIC_INLINE void LL_PLAY_LUT_SetEdgeTrigger(PLAY_TypeDef *playx, uint32_t ms /** * @brief Get flag transitions of all lookup table outputs. - * @rmtoll FLCTL FLAGD_EDGE LL_PLAY_LUT_GetEdgeTrigger - * @rmtoll FLCTL FLAGR_EDGE LL_PLAY_LUT_GetEdgeTrigger + * @rmtoll + * FLCTL FLAGD_EDGE LL_PLAY_LUT_GetEdgeTrigger \n + * FLCTL FLAGR_EDGE LL_PLAY_LUT_GetEdgeTrigger * @param playx PLAY Instance. */ __STATIC_INLINE uint32_t LL_PLAY_LUT_GetEdgeTrigger(const PLAY_TypeDef *playx) @@ -2056,8 +2111,9 @@ __STATIC_INLINE uint32_t LL_PLAY_LUT_GetEdgeTrigger(const PLAY_TypeDef *playx) /** * @brief Check lookup table output flag status. - * @rmtoll FLSTAT FLAGD LL_PLAY_LUT_IsActiveFlag - * @rmtoll FLSTAT FLAGR LL_PLAY_LUT_IsActiveFlag + * @rmtoll + * FLSTAT FLAGD LL_PLAY_LUT_IsActiveFlag \n + * FLSTAT FLAGR LL_PLAY_LUT_IsActiveFlag * @param playx PLAY Instance. * @param flag Value can be a one of the following values: * @arg @ref LL_PLAY_LUT0_OUT_DIRECT @@ -2101,8 +2157,9 @@ __STATIC_INLINE uint32_t LL_PLAY_LUT_IsActiveFlag(const PLAY_TypeDef *playx, uin /** * @brief Clear lookup table output flag. - * @rmtoll FLCLR FLAGD_CLR LL_PLAY_LUT_ClearFlag - * @rmtoll FLCLR FLAGR_CLR LL_PLAY_LUT_ClearFlag + * @rmtoll + * FLCLR FLAGD_CLR LL_PLAY_LUT_ClearFlag \n + * FLCLR FLAGR_CLR LL_PLAY_LUT_ClearFlag * @param playx PLAY Instance. * @param msk_flags Value can be a one of the following values: * @arg @ref LL_PLAY_LUT0_OUT_DIRECT @@ -2145,8 +2202,9 @@ __STATIC_INLINE void LL_PLAY_LUT_ClearFlag(PLAY_TypeDef *playx, uint32_t msk_fla /** * @brief Set lookup table output flag. - * @rmtoll FLSET FLAGD_SET LL_PLAY_LUT_SetFlag - * @rmtoll FLSET FLAGR_SET LL_PLAY_LUT_SetFlag + * @rmtoll + * FLSET FLAGD_SET LL_PLAY_LUT_SetFlag \n + * FLSET FLAGR_SET LL_PLAY_LUT_SetFlag * @param playx PLAY Instance. * @param msk_flags Value can be a one of the following values: * @arg @ref LL_PLAY_LUT0_OUT_DIRECT @@ -2191,8 +2249,9 @@ __STATIC_INLINE void LL_PLAY_LUT_SetFlag(PLAY_TypeDef *playx, uint32_t msk_flags /** * @brief Retrieve the status of all lookup table flags. - * @rmtoll FLSTAT FLAGD LL_PLAY_LUT_GetFlags - * @rmtoll FLSTAT FLAGR LL_PLAY_LUT_GetFlags + * @rmtoll + * FLSTAT FLAGD LL_PLAY_LUT_GetFlags \n + * FLSTAT FLAGR LL_PLAY_LUT_GetFlags * @param playx PLAY Instance. * @return Flags status (bit mask). * This value can be a combination of the following values: @@ -2236,7 +2295,8 @@ __STATIC_INLINE uint32_t LL_PLAY_LUT_GetFlags(const PLAY_TypeDef *playx) /** * @brief Check Software Trigger write busy flag status. - * @rmtoll MSR SWINWBFS LL_PLAY_IsSWTriggerWriteBusy + * @rmtoll + * MSR SWINWBFS LL_PLAY_IsSWTriggerWriteBusy * @param playx PLAY Instance. * @return State of bit (1 or 0). */ @@ -2247,7 +2307,8 @@ __STATIC_INLINE uint32_t LL_PLAY_IsSWTriggerWriteBusy(const PLAY_TypeDef *playx) /** * @brief Check Software Trigger write complete flag status. - * @rmtoll ISR SWINWC LL_PLAY_IsSWTriggerWriteComplete + * @rmtoll + * ISR SWINWC LL_PLAY_IsSWTriggerWriteComplete * @param playx PLAY Instance. * @return State of bit (1 or 0). */ @@ -2257,7 +2318,8 @@ __STATIC_INLINE uint32_t LL_PLAY_IsSWTriggerWriteComplete(const PLAY_TypeDef *pl } /** * @brief Clear Software Trigger write complete flag. - * @rmtoll ICR SWINWC_CLR LL_PLAY_ClearFlag_SWTriggerWriteComplete + * @rmtoll + * ICR SWINWC_CLR LL_PLAY_ClearFlag_SWTriggerWriteComplete * @param playx PLAY Instance. */ __STATIC_INLINE void LL_PLAY_ClearFlag_SWTriggerWriteComplete(PLAY_TypeDef *playx) @@ -2267,7 +2329,8 @@ __STATIC_INLINE void LL_PLAY_ClearFlag_SWTriggerWriteComplete(PLAY_TypeDef *play /** * @brief Check Edge Trigger write busy flag status. - * @rmtoll MSR FLCTLWBFS LL_PLAY_LUT_IsEdgeTriggerWriteBusy + * @rmtoll + * MSR FLCTLWBFS LL_PLAY_LUT_IsEdgeTriggerWriteBusy * @param playx PLAY Instance. * @return State of bit (1 or 0). */ @@ -2278,7 +2341,8 @@ __STATIC_INLINE uint32_t LL_PLAY_LUT_IsEdgeTriggerWriteBusy(const PLAY_TypeDef * /** * @brief Check Edge Trigger write complete flag status. - * @rmtoll ISR FLCTLWC LL_PLAY_LUT_IsEdgeTriggerWriteComplete + * @rmtoll + * ISR FLCTLWC LL_PLAY_LUT_IsEdgeTriggerWriteComplete * @param playx PLAY Instance. * @return State of bit (1 or 0). */ @@ -2289,7 +2353,8 @@ __STATIC_INLINE uint32_t LL_PLAY_LUT_IsEdgeTriggerWriteComplete(const PLAY_TypeD /** * @brief Clear Edge Trigger write complete flag. - * @rmtoll ICR FLCTLWC_CLR LL_PLAY_LUT_ClearFlag_EdgeTriggerWriteComplete + * @rmtoll + * ICR FLCTLWC_CLR LL_PLAY_LUT_ClearFlag_EdgeTriggerWriteComplete * @param playx PLAY Instance. */ __STATIC_INLINE void LL_PLAY_LUT_ClearFlag_EdgeTriggerWriteComplete(PLAY_TypeDef *playx) @@ -2299,7 +2364,8 @@ __STATIC_INLINE void LL_PLAY_LUT_ClearFlag_EdgeTriggerWriteComplete(PLAY_TypeDef /** * @brief Check Flags flag status. - * @rmtoll ISR FLAGS LL_PLAY_LUT_IsActiveFlag_FLAGS + * @rmtoll + * ISR FLAGS LL_PLAY_LUT_IsActiveFlag_FLAGS * @param playx PLAY Instance. * @return State of bit (1 or 0). */ @@ -2312,115 +2378,88 @@ __STATIC_INLINE uint32_t LL_PLAY_LUT_IsActiveFlag_FLAGS(const PLAY_TypeDef *play * @} */ -/** @defgroup PLAY_LL_EF_TrustZone TrustZone management functions +/** @defgroup PLAY_LL_EF_Privilege_Services Privilege Services * @{ */ /** - * @brief Configure Privilege mode. - * @rmtoll PRIVCFGR PRIV LL_PLAY_ConfigPrivilege - * @param playx PLAY Instance. - * @param attribute Value can be a one of the following values: - * @arg @ref LL_PLAY_NPRIV - * @arg @ref LL_PLAY_CONFIG_PRIV - * @arg @ref LL_PLAY_FULL_PRIV - */ -__STATIC_INLINE void LL_PLAY_ConfigPrivilege(PLAY_TypeDef *playx, uint32_t attribute) -{ - MODIFY_REG(playx->PRIVCFGR, PLAY_PRIVCFGR_PRIV_Msk, attribute); -} - -/** - * @brief Get Privilege mode configuration. - * @rmtoll PRIVCFGR PRIV LL_PLAY_GetConfigPrivilege + * @brief Set the privileged access level attribute for item(s). + * @rmtoll + * PRIVCFGR PRIV LL_PLAY_SetPrivAttr * @param playx PLAY Instance. - * @return Returned value can be one of the following values: - * @arg @ref LL_PLAY_NPRIV - * @arg @ref LL_PLAY_CONFIG_PRIV - * @arg @ref LL_PLAY_FULL_PRIV - */ -__STATIC_INLINE uint32_t LL_PLAY_GetConfigPrivilege(const PLAY_TypeDef *playx) + * @param item This parameter can be one or a combination of the following values: + * @arg @ref LL_PLAY_PRIV_ITEM_CONFIG + * @arg @ref LL_PLAY_PRIV_ITEM_ALL + * @param priv_attr This parameter can be one of the following values: + * @arg @ref LL_PLAY_ATTR_NPRIV + * @arg @ref LL_PLAY_ATTR_PRIV + */ +__STATIC_INLINE void LL_PLAY_SetPrivAttr(PLAY_TypeDef *playx, uint32_t item, uint32_t priv_attr) { - return (uint32_t)(READ_BIT(playx->PRIVCFGR, PLAY_PRIVCFGR_PRIV_Msk)); + MODIFY_REG(playx->PRIVCFGR, PLAY_PRIVCFGR_PRIV, (item & ((~priv_attr) + 1U))); } /** - * @brief Indicates if the PLAY Configuration registers require a Privilege access. - * @rmtoll PRIVCFGR PRIV LL_PLAY_IsEnabledConfigPrivilege + * @brief Get the privileged access level attribute of an item. + * @rmtoll + * PRIVCFGR PRIV LL_PLAY_GetPrivAttr * @param playx PLAY Instance. - * @return State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PLAY_IsEnabledConfigPrivilege(const PLAY_TypeDef *playx) + * @param item This parameter can be one of the following values: + * @arg @ref LL_PLAY_PRIV_ITEM_CONFIG + * @arg @ref LL_PLAY_PRIV_ITEM_ALL + * @return Current privileged level attributes: + * @arg @ref LL_PLAY_ATTR_NPRIV + * @arg @ref LL_PLAY_ATTR_PRIV + */ +__STATIC_INLINE uint32_t LL_PLAY_GetPrivAttr(const PLAY_TypeDef *playx, uint32_t item) { - return ((READ_BIT(playx->PRIVCFGR, PLAY_PRIVCFGR_PRIV_Msk) == LL_PLAY_CONFIG_PRIV) ? 1UL : 0UL); + return ((READ_BIT(playx->PRIVCFGR, item) == item) ? LL_PLAY_ATTR_PRIV : LL_PLAY_ATTR_NPRIV); } /** - * @brief Indicates if all PLAY registers require a Privilege access. - * @rmtoll PRIVCFGR PRIV LL_PLAY_IsEnabledFullPrivilege - * @param playx PLAY Instance. - * @return State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PLAY_IsEnabledFullPrivilege(const PLAY_TypeDef *playx) -{ - return ((READ_BIT(playx->PRIVCFGR, PLAY_PRIVCFGR_PRIV_Msk) == LL_PLAY_FULL_PRIV) ? 1UL : 0UL); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Configure Secure mode - * @rmtoll SECCFGR SEC LL_PLAY_ConfigSecure - * @param playx PLAY Instance. - * @param attribute Value can be a one of the following values: - * @arg @ref LL_PLAY_NSEC - * @arg @ref LL_PLAY_CONFIG_SEC - * @arg @ref LL_PLAY_FULL_SEC - * @note Only available when system implements security (TZEN=1). + * @} */ -__STATIC_INLINE void LL_PLAY_ConfigSecure(PLAY_TypeDef *playx, uint32_t attribute) -{ - MODIFY_REG(playx->SECCFGR, PLAY_SECCFGR_SEC_Msk, attribute); -} -/** - * @brief Get Secure mode configuration - * @rmtoll SECCFGR SEC LL_PLAY_GetConfigSecure - * @param playx PLAY Instance. - * @note Only available when system implements security (TZEN=1). - * @return Returned value of configuration can be one of the following values: - * @arg @ref LL_PLAY_NSEC - * @arg @ref LL_PLAY_CONFIG_SEC - * @arg @ref LL_PLAY_FULL_SEC +/** @defgroup PLAY_LL_EF_Security_Services Security Services + * @{ */ -__STATIC_INLINE uint32_t LL_PLAY_GetConfigSecure(const PLAY_TypeDef *playx) -{ - return (uint32_t)(READ_BIT(playx->SECCFGR, PLAY_SECCFGR_SEC_Msk)); -} +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** - * @brief Indicates if the PLAY Configuration registers require a Secure access. - * @rmtoll SECCFGR SEC LL_PLAY_IsEnabledConfigSecure + * @brief Set the security access level attribute for item(s). + * @rmtoll + * SECCFGR SEC LL_PLAY_SetSecAttr * @param playx PLAY Instance. - * @return State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PLAY_IsEnabledConfigSecure(const PLAY_TypeDef *playx) + * @param item This parameter can be one or a combination of the following values: + * @arg @ref LL_PLAY_SEC_ITEM_CONFIG + * @arg @ref LL_PLAY_SEC_ITEM_ALL + * @param sec_attr This parameter can be one of the following values: + * @arg @ref LL_PLAY_ATTR_NSEC + * @arg @ref LL_PLAY_ATTR_SEC + */ +__STATIC_INLINE void LL_PLAY_SetSecAttr(PLAY_TypeDef *playx, uint32_t item, uint32_t sec_attr) { - return ((READ_BIT(playx->SECCFGR, PLAY_SECCFGR_SEC_Msk) == LL_PLAY_CONFIG_SEC) ? 1UL : 0UL); + MODIFY_REG(playx->SECCFGR, PLAY_SECCFGR_SEC, (item & ((~sec_attr) + 1U))); } +#endif /* __ARM_FEATURE_CMSE */ /** - * @brief Indicates if all PLAY registers require a Secure access. - * @rmtoll SECCFGR SEC LL_PLAY_IsEnabledFullSecure + * @brief Get the security access level attribute of an item. + * @rmtoll + * SECCFGR SEC LL_PLAY_GetSecAttr * @param playx PLAY Instance. - * @return State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PLAY_IsEnabledFullSecure(const PLAY_TypeDef *playx) + * @param item This parameter can be one of the following values: + * @arg @ref LL_PLAY_SEC_ITEM_CONFIG + * @arg @ref LL_PLAY_SEC_ITEM_ALL + * @return Current security level attributes: + * @arg @ref LL_PLAY_ATTR_NSEC + * @arg @ref LL_PLAY_ATTR_SEC + */ +__STATIC_INLINE uint32_t LL_PLAY_GetSecAttr(const PLAY_TypeDef *playx, uint32_t item) { - return ((READ_BIT(playx->SECCFGR, PLAY_SECCFGR_SEC_Msk) == LL_PLAY_FULL_SEC) ? 1UL : 0UL); + return ((READ_BIT(playx->SECCFGR, item) == item) ? LL_PLAY_ATTR_SEC : LL_PLAY_ATTR_NSEC); } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h index 7f624f298a..5b75feda36 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h @@ -2933,7 +2933,7 @@ __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescale * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (**) * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P - * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P (*) * @arg @ref LL_RCC_SPI1_CLKSOURCE_PIN * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL1Q @@ -2966,7 +2966,7 @@ __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescale * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE (*) * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK3 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R (*) * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP @@ -3105,13 +3105,13 @@ __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL2Q - * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL3Q (*) * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI * @arg @ref LL_RCC_UART7_CLKSOURCE_CSI * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL2Q - * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL3Q (*) * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI * @arg @ref LL_RCC_UART8_CLKSOURCE_CSI * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE @@ -3128,6 +3128,8 @@ __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) * @arg @ref LL_RCC_UART12_CLKSOURCE_CSI * @arg @ref LL_RCC_UART12_CLKSOURCE_LSE * @retval None + * + * (*) value not defined in all devices */ __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) { @@ -3864,7 +3866,7 @@ __STATIC_INLINE void LL_RCC_SetETHPTPClockDivider(uint32_t ETHPTPxDivider) * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL3R (*) * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL2R (**) * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI * @arg @ref LL_RCC_I2C2_CLKSOURCE_CSI @@ -3888,7 +3890,7 @@ __STATIC_INLINE void LL_RCC_SetETHPTPClockDivider(uint32_t ETHPTPxDivider) * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (**) * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P - * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P (*) * @arg @ref LL_RCC_SPI1_CLKSOURCE_PIN * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL1Q @@ -3921,7 +3923,7 @@ __STATIC_INLINE void LL_RCC_SetETHPTPClockDivider(uint32_t ETHPTPxDivider) * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE (*) * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK3 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R (*) * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP @@ -4072,13 +4074,13 @@ __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL2Q - * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL3Q (*) * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI * @arg @ref LL_RCC_UART7_CLKSOURCE_CSI * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL2Q - * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL3Q (*) * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI * @arg @ref LL_RCC_UART8_CLKSOURCE_CSI * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE @@ -4094,6 +4096,8 @@ __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) * @arg @ref LL_RCC_UART12_CLKSOURCE_HSI * @arg @ref LL_RCC_UART12_CLKSOURCE_CSI * @arg @ref LL_RCC_UART12_CLKSOURCE_LSE + * + * (*) value not defined in all devices */ __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) { @@ -4362,8 +4366,8 @@ __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx) * @rmtoll CCIPR2 SAI1SEL LL_RCC_GetSAIClockSource\n * CCIPR2 SAI2SEL LL_RCC_GetSAIClockSource * @param SAIx This parameter can be one of the following values: - * @arg @ref LL_RCC_SAI1_CLKSOURCE - * @arg @ref LL_RCC_SAI2_CLKSOURCE + * @arg @ref LL_RCC_SAI1_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P @@ -4375,6 +4379,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx) * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP + * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h index eaa79df907..0438bc579e 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h @@ -134,6 +134,28 @@ typedef struct * @} */ +#if (defined(RNG_NSCR_EN_OSC1) || defined(RNG_NSCR_EN_OSC2) ||defined(RNG_NSCR_EN_OSC3)) +/** @defgroup RNG_LL_NSCR_Oscillator_Sources Oscillator Sources Defines + * @{ + */ +#define LL_RNG_OSC_1 RNG_NSCR_EN_OSC1 +#define LL_RNG_OSC_2 RNG_NSCR_EN_OSC2 +#define LL_RNG_OSC_3 RNG_NSCR_EN_OSC3 +/** + * @} + */ + +/** @defgroup RNG_LL_NSCR_Noise_Sources_Ports Noise Sources Ports Defines + * @{ + */ +#define LL_RNG_NOISE_SRC_1 (0x01UL) +#define LL_RNG_NOISE_SRC_2 (0x02UL) +#define LL_RNG_NOISE_SRC_3 (0x04UL) +/** + * @} + */ + +#endif /* RNG_CR_CONDRST */ /** @defgroup RNG_LL_EC_IT IT Defines * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros * @{ @@ -677,7 +699,11 @@ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) #if defined(RNG_HTCR_NIST_VALUE) /* For NIST compliance we can fin the recommended value in the application note AN4230 */ #endif /* defined(RNG_HTCR_NIST_VALUE) */ +#if defined(RNG_HTCR3_HTCFG) + WRITE_REG(RNGx->HTCR[0], HTCFG); +#else WRITE_REG(RNGx->HTCR, HTCFG); +#endif /* RNG_HTCR0_HTCFG || RNG_HTCR1_HTCFG || RNG_HTCR2_HTCFG || RNG_HTCR3_HTCFG */ } /** @@ -688,12 +714,51 @@ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) */ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx) { +#if defined(RNG_HTCR3_HTCFG) + return (uint32_t)READ_REG(RNGx->HTCR[0]); +#else return (uint32_t)READ_REG(RNGx->HTCR); +#endif /* RNG_HTCR0_HTCFG || RNG_HTCR1_HTCFG || RNG_HTCR2_HTCFG || RNG_HTCR3_HTCFG */ +} + +/** + * @} + */ +#if defined(RNG_HTCR3_HTCFG) + +/** @defgroup RNG_LL_EF_Additional_Health_Test_Control Additional Health Test Control + * @{ + */ + +/** + * @brief Set RNG Additional Health Test Control + * @rmtoll HTCR HTCFG LL_RNG_SetAdditionalHealthTest + * @param RNGx RNG Instance + * @param htcr_idx Additional health tests registers index can be one f the following values + * @param HTCFG can be values of 32 bits + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetAdditionalHealthTest(RNG_TypeDef *RNGx, uint32_t htcr_idx, uint32_t HTCFG) +{ + WRITE_REG(RNGx->HTCR[htcr_idx], HTCFG); } +/** + * @brief Get RNG Additional Health Test Control + * @rmtoll HTCR HTCFG LL_RNG_GetAdditionalHealthTest + * @param RNGx RNG Instance + * @param htcr_idx Additional health tests registers index + * @retval Return 32-bit RNG Health Test configuration + */ +__STATIC_INLINE uint32_t LL_RNG_GetAdditionalHealthTest(const RNG_TypeDef *RNGx, uint32_t htcr_idx) +{ + return (uint32_t)READ_REG(RNGx->HTCR[htcr_idx]); +} /** * @} */ + +#endif /* RNG_HTCR0_HTCFG || RNG_HTCR1_HTCFG || RNG_HTCR2_HTCFG || RNG_HTCR3_HTCFG */ #if defined(RNG_NSCR_NIST_VALUE) /** @defgroup RNG_LL_EF_Noise_Test_Control Noise Test Control @@ -721,7 +786,6 @@ __STATIC_INLINE void LL_RNG_SetNoiseConfig(RNG_TypeDef *RNGx, uint32_t NOISECFG) */ __STATIC_INLINE uint32_t LL_RNG_GetNoiseConfig(const RNG_TypeDef *RNGx) { - return (uint32_t)READ_REG(RNGx->NSCR); } @@ -730,6 +794,108 @@ __STATIC_INLINE uint32_t LL_RNG_GetNoiseConfig(const RNG_TypeDef *RNGx) */ #endif /* defined(RNG_NSCR_NIST_VALUE) */ +#if defined(RNG_HTCR3_HTCFG) +/** @defgroup RNG_LL_EF_Health_Tests_Status_Control Health Tests Status control + * @{ + */ + +/** + * @brief Get RNG Health Tests Status. + * @rmtoll HTSR htsr_idx LL_RNG_GetHealthTestStatus + * @param RNGx RNG Instance + * @param htsr_idx Health tests registers status index + * @retval Return 32-bit RNG Health Test Status + */ +__STATIC_INLINE uint32_t LL_RNG_GetHealthTestStatus(const RNG_TypeDef *RNGx, uint32_t htsr_idx) +{ + return (uint32_t)READ_REG(RNGx->HTSR[htsr_idx]); +} + +/** + * @} + */ + +#endif /* defined(RNG_HTCR0_HTCFG) || defined(RNG_HTCR1_HTCFG) || defined(RNG_HTCR2_HTCFG) */ +#if defined(RNG_NSMR_MOSC1) +/** @defgroup RNG_LL_EF_Noise_Source_Mask_Control noise source mask Control + * @{ + */ + +/** + * @brief Set RNG noise source mask. + * @rmtoll NSMR htsr_idx LL_RNG_GetNoiseSourceMask + * @param RNGx RNG Instance + * @param nsmr can be values of 32 bits + */ +__STATIC_INLINE void LL_RNG_SetNoiseSourceMask(RNG_TypeDef *RNGx, uint32_t nsmr) +{ + WRITE_REG(RNGx->NSMR, nsmr); +} + +/** + * @brief Get RNG noise source mask. + * @rmtoll NSMR htsr_idx LL_RNG_GetNoiseSourceMask + * @param RNGx RNG Instance + * @retval Return 32-bit RNG Noise Source Mask + */ +__STATIC_INLINE uint32_t LL_RNG_GetNoiseSourceMask(const RNG_TypeDef *RNGx) +{ + return READ_REG(RNGx->NSMR); +} + +/** + * @} + */ + +#endif /* RNG_NSMR_MOSC1 */ +#if (defined(RNG_NSCR_EN_OSC1) || defined(RNG_NSCR_EN_OSC2) || defined(RNG_NSCR_EN_OSC3)) +/** @defgroup RNG_LL_EF_Noise_Source_Control noise source Control + * @{ + */ + +/** + * @brief Set RNG Noise Source Configuration. + * @rmtoll + * NSCR NSCR LL_RNG_GetOscNoiseSrc + * @param RNGx RNG Instance + * @param osc be one of the following values: + * @arg @ref LL_RNG_OSC_1 + * @arg @ref LL_RNG_OSC_2 + * @arg @ref LL_RNG_OSC_3 + * @retval can be one of the following values: + * @arg @ref LL_RNG_NOISE_SRC_1 + * @arg @ref LL_RNG_NOISE_SRC_2 + * @arg @ref LL_RNG_NOISE_SRC_3 + */ +__STATIC_INLINE void LL_RNG_SetOscNoiseSrc(RNG_TypeDef *RNGx, uint32_t osc) +{ + WRITE_REG(RNGx->NSCR, osc); +} + +/** + * @brief Get RNG Noise Source Configuration. + * @rmtoll + * NSCR NSCR LL_RNG_GetOscNoiseSrc + * @param RNGx RNG Instance + * @param osc be one of the following values: + * @arg @ref LL_RNG_OSC_1 + * @arg @ref LL_RNG_OSC_2 + * @arg @ref LL_RNG_OSC_3 + * @retval can be one of the following values: + * @arg @ref LL_RNG_NOISE_SRC_1 + * @arg @ref LL_RNG_NOISE_SRC_2 + * @arg @ref LL_RNG_NOISE_SRC_3 + */ +__STATIC_INLINE uint32_t LL_RNG_GetOscNoiseSrc(const RNG_TypeDef *RNGx, uint32_t osc) +{ + return (READ_BIT(RNGx->NSCR, osc) >> POSITION_VAL(osc)); +} + +/** + * @} + */ + +#endif /* defined(defined(RNG_NSCR_EN_OSC1) || RNG_NSCR_EN_OSC2 ||RNG_NSCR_EN_OSC3) */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h index 863c96040c..97863c994e 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h @@ -748,6 +748,24 @@ typedef struct * @} */ +#if defined(TAMP_OR_IN2_RMP) || defined(TAMP_OR_IN3_RMP) || defined(TAMP_OR_IN4_RMP) || \ + defined(TAMP_OR_OUT3_RMP) || defined(TAMP_OR_OUT5_RMP) +/** @defgroup RTC_LL_EC_TAMPER_REMAP TAMPER REMAP + * @{ + */ +#define LL_RTC_TAMPER_RMP_TAMP_IN2_PA0_TO_PI8 TAMP_OR_IN2_RMP +#define LL_RTC_TAMPER_RMP_TAMP_IN3_PC1_TO_PE6 TAMP_OR_IN3_RMP +#define LL_RTC_TAMPER_RMP_TAMP_IN4_PA2_TO_PI11 TAMP_OR_IN4_RMP +#define LL_RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PI8 TAMP_OR_OUT3_RMP_0 +#define LL_RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PE3 TAMP_OR_OUT3_RMP_1 +#define LL_RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PA2 TAMP_OR_OUT3_RMP +#define LL_RTC_TAMPER_RMP_TAMP_OUT5_PI11_TO_PC1 TAMP_OR_OUT5_RMP +/** + * @} + */ +#endif /* defined(TAMP_OR_IN2_RMP) || defined(TAMP_OR_IN3_RMP) || defined(TAMP_OR_IN4_RMP) || \ + defined(TAMP_OR_OUT3_RMP) || defined(TAMP_OR_OUT5_RMP) */ + /** @defgroup RTC_LL_EC_BKP BACKUP * @{ */ @@ -3731,6 +3749,83 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_SEEDF(void) * @} */ +#if defined(TAMP_OR_IN2_RMP) || defined(TAMP_OR_IN3_RMP) || defined(TAMP_OR_IN4_RMP) || \ + defined(TAMP_OR_OUT3_RMP) || defined(TAMP_OR_OUT5_RMP) +/** @defgroup RTC_LL_EF_Remap_Tamper Remap Tamper + * @{ + */ +/** + * @brief Enable remap of TAMP INx on a different pin. + * @rmtoll + * TAMP_OR IN2_RMP LL_RTC_TAMPER_EnableRemap \n + * TAMP_OR IN3_RMP LL_RTC_TAMPER_EnableRemap \n + * TAMP_OR IN4_RMP LL_RTC_TAMPER_EnableRemap \n + * TAMP_OR OUT3_RMP LL_RTC_TAMPER_EnableRemap \n + * TAMP_OR OUT5_RMP LL_RTC_TAMPER_EnableRemap + * @param tamp_remap This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_IN2_PA0_TO_PI8 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_IN3_PC1_TO_PE6 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_IN4_PA2_TO_PI11 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PI8 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PE3 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PA2 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_OUT5_PI11_TO_PC1 + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableRemap(uint32_t tamp_remap) +{ + SET_BIT(TAMP->OR, tamp_remap); +} + +/** + * @brief Disable remap of TAMP INx on a different pin. + * @rmtoll + * TAMP_OR IN2_RMP LL_RTC_TAMPER_EnableRemap \n + * TAMP_OR IN3_RMP LL_RTC_TAMPER_EnableRemap \n + * TAMP_OR IN4_RMP LL_RTC_TAMPER_EnableRemap \n + * TAMP_OR OUT3_RMP LL_RTC_TAMPER_EnableRemap \n + * TAMP_OR OUT5_RMP LL_RTC_TAMPER_EnableRemap + * @param tamp_remap This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_IN2_PA0_TO_PI8 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_IN3_PC1_TO_PE6 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_IN4_PA2_TO_PI11 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PI8 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PE3 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PA2 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_OUT5_PI11_TO_PC1 + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableRemap(uint32_t tamp_remap) +{ + CLEAR_BIT(TAMP->OR, tamp_remap); +} + +/** + * @brief Check if remap of TAMP INx is enabled or disabled. + * @rmtoll + * TAMP_OR IN2_RMP LL_RTC_TAMPER_EnableRemap \n + * TAMP_OR IN3_RMP LL_RTC_TAMPER_EnableRemap \n + * TAMP_OR IN4_RMP LL_RTC_TAMPER_EnableRemap \n + * TAMP_OR OUT3_RMP LL_RTC_TAMPER_EnableRemap \n + * TAMP_OR OUT5_RMP LL_RTC_TAMPER_EnableRemap + * @param tamp_remap This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_IN2_PA0_TO_PI8 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_IN3_PC1_TO_PE6 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_IN4_PA2_TO_PI11 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PI8 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PE3 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_OUT3_PC13_TO_PA2 + * @arg @ref LL_RTC_TAMPER_RMP_TAMP_OUT5_PI11_TO_PC1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_IsEnabledRemap(uint32_t tamp_remap) +{ + return ((READ_BIT(TAMP->OR, tamp_remap) == tamp_remap) ? 1UL : 0UL); +} +/** + * @} + */ +#endif /* defined(TAMP_OR_IN2_RMP) || defined(TAMP_OR_IN3_RMP) || defined(TAMP_OR_IN4_RMP) || \ + defined(TAMP_OR_OUT3_RMP) || defined(TAMP_OR_OUT5_RMP)*/ + /** @defgroup RTC_LL_EF_Wakeup Wakeup * @{ */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h index acf4586b48..c8d29508f8 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h @@ -1559,14 +1559,16 @@ __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_I3C1_STOP * @retval None + * + * (*) value not defined in all devices */ __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) { @@ -1596,14 +1598,16 @@ __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_I3C1_STOP * @retval None + * + * (*) value not defined in all devices */ __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) { @@ -1629,9 +1633,11 @@ __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) * @retval None + * + * (*) value not defined in all devices */ __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) { @@ -1645,9 +1651,11 @@ __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) * @retval None + * + * (*) value not defined in all devices */ __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) { @@ -1659,10 +1667,12 @@ __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) * @rmtoll DBGMCU_APB3FZ DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_FreezePeriph * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP - * @arg @ref LL_DBGMCU_APB3_GRP1_I2C4_STOP + * @arg @ref LL_DBGMCU_APB3_GRP1_I2C4_STOP (*) * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP * @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP * @retval None + * + * (*) value not defined in all devices */ __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs) { @@ -1674,10 +1684,12 @@ __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs) * @rmtoll DBGMCU_APB3FZR DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_UnFreezePeriph * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP - * @arg @ref LL_DBGMCU_APB3_GRP1_I2C4_STOP + * @arg @ref LL_DBGMCU_APB3_GRP1_I2C4_STOP (*) * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP * @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP * @retval None + * + * (*) value not defined in all devices */ __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs) { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usb.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usb.h index d721151231..a61d470eda 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usb.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usb.h @@ -955,21 +955,21 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; #define USB_DRD_SET_CHEP_CNT_RX_REG(pdwReg, wCount) \ do { \ uint32_t wNBlocks; \ - \ - (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ + uint32_t wRegVal = (uint32_t)(pdwReg) & ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ \ if ((wCount) == 0U) \ { \ - (pdwReg) |= USB_CNTRX_BLSIZE; \ + wRegVal |= USB_CNTRX_BLSIZE; \ } \ else if ((wCount) <= 62U) \ { \ - USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + USB_DRD_CALC_BLK2(wRegVal, (wCount), wNBlocks); \ } \ else \ { \ - USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + USB_DRD_CALC_BLK32(wRegVal, (wCount), wNBlocks); \ } \ + (pdwReg) = wRegVal; \ } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ @@ -1228,9 +1228,10 @@ HAL_StatusTypeDef USB_HC_Activate(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uin #endif /* defined (HAL_HCD_MODULE_ENABLED) */ uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx); -uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx); HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx); +uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx); + HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/LICENSE.md b/system/Drivers/STM32H5xx_HAL_Driver/LICENSE.md index 9226612aea..5d67eddecd 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/LICENSE.md +++ b/system/Drivers/STM32H5xx_HAL_Driver/LICENSE.md @@ -24,4 +24,4 @@ ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/system/Drivers/STM32H5xx_HAL_Driver/README.md b/system/Drivers/STM32H5xx_HAL_Driver/README.md index e13efbe77f..fb3a1eec3b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/README.md +++ b/system/Drivers/STM32H5xx_HAL_Driver/README.md @@ -1,6 +1,6 @@ # STM32CubeH5 HAL Driver MCU Component -![tag](https://img.shields.io/badge/tag-v1.6.0-brightgreen.svg) +![tag](https://img.shields.io/badge/tag-v1.7.0-brightgreen.svg) ## Overview @@ -33,4 +33,4 @@ The full **STM32CubeH5** MCU package is available [here](https://github.com/STMi ## Troubleshooting -Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. \ No newline at end of file diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html index 423be98ec1..22151f7194 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html @@ -69,12 +69,136 @@

Purpose

Update History

- - + +

Main Changes

    +

  • Offical Release V1.7.0 of STM32CubeH5 Firmware Package, to +support STM32H543xx and STM32H553xx +devices.

    • +

  • Support added for H5 1M devices in all HAL/LL drivers.

    • +

  • General updates to fix known defects and implementation +enhancements

    • +

  • HAL Drivers updates:

    +
      +
    • HAL CCB driver +
        +
      • Fixed Coverity issues.
        • +
      • Updated support for recovery from seed error sequence after RNG +v4.4.
        • +
      • Aligned STM32H5 code with the common code structure.
        • +
      • Fixed transient variable handling in sanity check support.
        • +
      • Fixed preprocessor handling for sanity check compilation.
        • +
      • Added RNG handle support for resilient seed error recovery.
        • +
      • Updated support for wrap keys from secure domain to non-secure +domain.
        • +
      • Fixed MISRA Rule 12.2 issues in HAL CCB.
        • +
      • Fixed MISRA-C and Coverity warnings.
        • +
      • Updated support to CCB v2.1.
        • +
      • +
    • HAL CRYP driver +
        +
      • Fixed MISRA-C Rule 7.1 in hal_cryp.c.
        • +
      • Fixed MISRA-C Rule 2.2_c warning in stm32h5xx_hal_cryp.c.
        • +
      • Fixed CCM partial output handling for non-32-bit aligned +payloads.
        • +
      • Fixed missing second CRYP handle usage in SAES shared-key mode.
        • +
      • Fixed a typo in the CR->SR register call.
        • +
      • Updated seed recovery handling after the RNG v4.4.
        • +
      • Fixed tickstart handling in SAES.
        • +
      • Fixed Coverity issue INTEGER_OVERFLOW.
        • +
      • Updated implementation related to AES GCM decryption tag +handling.
        • +
      • +
    • HAL DMA2D driver +
        +
      • DMA2D3 downscaling implementation added to expose the full 4K-step +scaling range with equidistant increments.
        • +
      • +
    • HAL FLASH driver +
        +
      • Removed smart prefetch APIs from the FLASH driver.
        • +
      • Added dedicated HAL functions to independently lock and unlock +secure and non-secure FLASH control registers.
        • +
      • +
    • HAL FMC driver +
        +
      • Fixed MISRA warning Rule 11.3 on the NOR driver.
        • +
      • Removed 8-bit configuration support from the FMC NOR driver.
        • +
      • Fixed NAND status handling when HAL_NAND_Read_Status returns +NAND_ERROR.
        • +
      • +
    • HAL RNG driver +
        +
      • Updated comment for NistCompliance field in +RNG_ConfigTypeDef.
        • +
      • Updated seed recovery handling after the RNG v4.4.
        • +
      • Fixed the clear logic for the clock error flag during interrupt +handling.
        • +
      • Added error-state check at the start of seed recovery.
        • +
      • Added resilient __HAL_UNLOCK.
        • +
      • Added warning handling related to resilient seed recovery.
        • +
      • Fixed missing NSCR register.
        • +
      • Improved recovery from seed error handling related to RNG v4.4.
        • +
      • Fixed resilient recovery warning handling.
        • +
      • +
    • HAL SDMMC driver +
        +
      • Fixed MISRA-C warning Rule 10.3 in +stm32h5xx_hal_sdio.c.
        • +
      • Fixed Coverity warnings.
        • +
      • Fixed MISRA-C Rule 8.13 violation.
        • +
      • Fixed SD card initialization at frequencies below 3 MHz.
        • +
      • Fixed MISRA-C Rule 12.2 violations.
        • +
      • Improved support for SD card V1.
        • +
      • Fixed command argument handling for block and byte modes.
        • +
      • +
    • HAL SMARTCARD driver +
        +
      • Fixed improper initialization of the smartcard clock.
        • +
      • +
    • HAL USB driver +
        +
      • Added support for get frame number.
        • +
      • Updated RX count register handling.
        • +
      • Avoided out-of-band reads.
        • +
      • Fixed MISRA-C Rule 8.13 issues.
        • +
      • +
    • +

  • HAL Drivers updates:

    +
      +
    • LL RNG driver +
        +
      • Updated recovery from seed error handling after RNG v4.4.
        • +
      • Updated interrupt clear handling and resilient recovery logic.
        • +
      • Added support for resilient unlock behavior.
        • +
      • Fixed warnings related to resilient seed recovery.
        • +
      • Fixed missing NSCR register.
        • +
      • Updated NIST compliance parameter handling.
        • +
      • +
    • +
+

Note: HAL/LL Backward compatibility ensured by legacy defines.

+

Known Limitations

+
    +
  • None
    • +
+

Backward compatibility

+
    +
  • No compatibility break
    • +
+
+
+
+ + +
+

Main Changes

+

  • Maintenance Release V1.6.0 of STM32CubeH5 Firmware Package, to support STM32H503xx, STM32H523xx, STM32H533xx, STM32H562xx, @@ -455,11 +579,11 @@

    Main Changes

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • No compatibility break
@@ -470,7 +594,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • Maintenance Release V1.5.0 of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx / @@ -595,11 +719,11 @@

    Main Changes

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • No compatibility break
@@ -610,7 +734,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • Maintenance Release V1.4.0 of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx / @@ -729,11 +853,11 @@

    Main Changes

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • No compatibility break
@@ -744,7 +868,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • Maintenance release V1.3.0 of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx / @@ -787,11 +911,11 @@

    Main Changes

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • No compatibility break
@@ -802,7 +926,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • First offiicial release of HAL and LL drivers to support STM32H533xx and STM32H523xx devices

    @@ -1011,11 +1135,11 @@

    Main Changes

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • No compatibility break
@@ -1026,7 +1150,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • Maintenance Release of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx @@ -1110,11 +1234,11 @@

    Main Changes

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • No compatibility break
@@ -1125,17 +1249,17 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • First official release of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx devices
-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • Not Applicable
diff --git a/system/Drivers/STM32H5xx_HAL_Driver/SW_Security_Level.md b/system/Drivers/STM32H5xx_HAL_Driver/SW_Security_Level.md new file mode 100644 index 0000000000..2a6286a448 --- /dev/null +++ b/system/Drivers/STM32H5xx_HAL_Driver/SW_Security_Level.md @@ -0,0 +1,47 @@ + + +## Copyright (c) 2026 STMicroelectronics. +## All rights reserved +
+
+ +## SW Security Classification + +[STM32Trust software security policies](https://wiki.st.com/stm32mcu/wiki/Security:STM32Trust_software_security_policies) define four levels of SW Security classification, each level defines a set of security policies for the applicable SW. + +| SW | SW Security Level +|:--------- |:-------| +| **STM32H5xx HAL Driver** | Medium| + + +
+ +## IMPORTANT SECURITY NOTICE + +The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that: + +- ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified. + +- Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product. + +- Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies. + +- While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application. + +- All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. + +AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise. + +
+ +## IMPORTANT NOTICE - READ CAREFULLY + +STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgment. + +Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers' products. +No license, express or implied, to any intellectual property right is granted by ST herein. +Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. +ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. +Information in this document supersedes and replaces information previously supplied in any prior versions of this document. + +Copyright (c) 2026 STMicroelectronics - All rights reserved diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c index 13106e882d..19282b8864 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c @@ -51,7 +51,7 @@ * @brief STM32H5xx HAL Driver version number 1.6.0 */ #define __STM32H5XX_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ -#define __STM32H5XX_HAL_VERSION_SUB1 (0x06UL) /*!< [23:16] sub1 version */ +#define __STM32H5XX_HAL_VERSION_SUB1 (0x07UL) /*!< [23:16] sub1 version */ #define __STM32H5XX_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */ #define __STM32H5XX_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32H5XX_HAL_VERSION ((__STM32H5XX_HAL_VERSION_MAIN << 24U)\ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_ccb.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_ccb.c index e166485381..300310f34b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_ccb.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_ccb.c @@ -93,7 +93,9 @@ #ifndef HAL_CCB_TIMEOUT_DEFAULT_VALUE #define HAL_CCB_TIMEOUT_DEFAULT_VALUE 0xFFFFU /* CCB Timeout.*/ #endif /*HAL_CCB_TIMEOUT_DEFAULT_VALUE */ - +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +#define CCB_RNG_TIMEOUT_VALUE 0x00000002U +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ /** * @} */ @@ -118,12 +120,12 @@ /** @defgroup CCB_PKA_Mode CCB PKA mode * @{ */ -#define CCB_PKA_MODE_MODULAR_EXP_PROTECT (0x00000003U) /*!< PKA Modular exponentiation */ -#define CCB_PKA_ECC_MUL_MODE (0x00000020U) /*!< PKA ECC scalar multiplication */ -#define CCB_PKA_ECDSA_SIGNATURE_MODE (0x00000024U) /*!< PKA ECDSA signature */ -#define CCB_PKA_MODE_ECDSA_VERIFICATION (0x00000026U) /*!< PKA ECDSA verification */ -#define CCB_PKA_ERROR_OPERATION_NONE (0x0000D60DU) /*!< No PKA Hardware operation error */ -#define CCB_PKA_RAM_SIZE (0x00000536U) /*!< CCB PKA Ram Size */ +#define CCB_PKA_MODE_MODULAR_EXP_PROTECT (0x00000003UL) /*!< PKA Modular exponentiation */ +#define CCB_PKA_ECC_MUL_MODE (0x00000020UL) /*!< PKA ECC scalar multiplication */ +#define CCB_PKA_ECDSA_SIGNATURE_MODE (0x00000024UL) /*!< PKA ECDSA signature */ +#define CCB_PKA_MODE_ECDSA_VERIFICATION (0x00000026UL) /*!< PKA ECDSA verification */ +#define CCB_PKA_ERROR_OPERATION_NONE (0x0000D60DUL) /*!< No PKA Hardware operation error */ +#define CCB_PKA_RAM_SIZE (0x00000536UL) /*!< CCB PKA Ram Size */ /** * @} @@ -162,14 +164,37 @@ #define HAL_CCB_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\ & (__FLAG__)) == (__FLAG__)) ? SET : RESET) -#define HAL_CCB_GET_SAES_FLAG(__FLAG__) (((__FLAG__)>1U) ? \ - (((SAES->SR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) :\ - (((SAES->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) ) - -#define HAL_CCB_GET_PKA_FLAG(__FLAG__) ((((PKA->SR)\ - & (__FLAG__)) == (__FLAG__)) ? SET : RESET) - -#define HAL_CCB_CLEAR_PKA_FLAG(__FLAG__) WRITE_REG(PKA->CLRFR, (__FLAG__)) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_CCB_GET_SAES_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance == CCB_S)?\ + SAES_S : SAES_NS) +#else +#define HAL_CCB_GET_SAES_INSTANCE(__HANDLE__) SAES_NS +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_CCB_GET_PKA_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance == CCB_S)?\ + PKA_S : PKA_NS) +#else +#define HAL_CCB_GET_PKA_INSTANCE(__HANDLE__) PKA_NS +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_CCB_GET_RNG_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance == CCB_S)?\ + RNG_S : RNG_NS) +#else +#define HAL_CCB_GET_RNG_INSTANCE(__HANDLE__) RNG_NS +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#define HAL_CCB_GET_SAES_FLAG(__HANDLE__,__FLAG__) (((__FLAG__)>1U) ? \ + (((HAL_CCB_GET_SAES_INSTANCE(__HANDLE__)->SR\ + & (__FLAG__)) == (__FLAG__)) ? SET : RESET) :\ + (((HAL_CCB_GET_SAES_INSTANCE(__HANDLE__)->ISR\ + & (__FLAG__)) == (__FLAG__)) ? SET : RESET) ) + +#define HAL_CCB_GET_PKA_FLAG(__HANDLE__,__FLAG__) ((((HAL_CCB_GET_PKA_INSTANCE(__HANDLE__)->SR)\ + & (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +#define HAL_CCB_CLEAR_PKA_FLAG(__HANDLE__,__FLAG__) WRITE_REG(HAL_CCB_GET_PKA_INSTANCE(__HANDLE__)->CLRFR, (__FLAG__)) /** * @} @@ -183,8 +208,8 @@ static HAL_StatusTypeDef CCB_WaitOperStep(CCB_HandleTypeDef *hccb, uint32_t step, uint32_t Timeout); static HAL_StatusTypeDef CCB_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t flag, uint32_t Timeout); static HAL_StatusTypeDef Protect_PKA_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t flag, uint32_t Timeout); -static HAL_StatusTypeDef Unprotect_PKA_WaitFLAG(uint32_t flag, uint32_t Timeout); -static HAL_StatusTypeDef CCB_RNG_Wait_SET_FLAG(uint32_t flag, uint32_t Timeout); +static HAL_StatusTypeDef Unprotect_PKA_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t flag, uint32_t Timeout); +static HAL_StatusTypeDef CCB_RNG_Wait_SET_FLAG(CCB_HandleTypeDef *hccb, uint32_t flag, uint32_t Timeout); static HAL_StatusTypeDef Protect_SAES_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t flag, FlagStatus Status, uint32_t Timeout); @@ -197,8 +222,8 @@ static HAL_StatusTypeDef CCB_SetPram(CCB_HandleTypeDef *hccb, uint32_t modulusSi /* Initialization Private function */ static HAL_StatusTypeDef Protect_PKA_Init(CCB_HandleTypeDef *hccb, uint32_t Operation); -static HAL_StatusTypeDef Unprotected_PKA_Init(void); -static HAL_StatusTypeDef CCB_RNG_Init(void); +static HAL_StatusTypeDef Unprotected_PKA_Init(CCB_HandleTypeDef *hccb); +static HAL_StatusTypeDef CCB_RNG_Init(CCB_HandleTypeDef *hccb); /* Wrapping Private function */ static HAL_StatusTypeDef WrappingKeyConfiguration(CCB_HandleTypeDef *hccb, uint32_t Operation, @@ -225,15 +250,15 @@ static HAL_StatusTypeDef CCB_BlobCreation_FinalPhase(CCB_HandleTypeDef *hccb, ui static HAL_StatusTypeDef CCB_BlobUse_FinalPhase(CCB_HandleTypeDef *hccb, uint32_t Operation, uint32_t sizeparam); static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *pCurveParam, const uint8_t *pClearPrivateKey, - CCB_WrappingKeyTypeDef *pWrappingKey, - uint32_t *pIV, uint32_t *pTag, uint32_t *pWarappedKey, - uint8_t CCB_Operation); + CCB_WrappingKeyTypeDef *pWrappingKey, uint32_t *pIV, + uint32_t *pTag, uint32_t *pWarappedKey, uint8_t *pHash, + CCB_ECDSASignTypeDef *pSignature, uint8_t CCB_Operation); static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb, CCB_ECCMulCurveParamTypeDef *pCurveParam, const uint8_t *pClearPrivateKey, CCB_WrappingKeyTypeDef *pWrappingKey, uint32_t *pIV, uint32_t *pTag, uint32_t *pWarappedKey, - uint8_t CCB_Operation); + uint32_t PublicKey[2U][20U], uint8_t CCB_Operation); static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_ECCMulCurveParamTypeDef *pCurveParam, CCB_WrappingKeyTypeDef *pWrappingKey, uint32_t *pIV, uint32_t *pTag, uint32_t *pWarappedKey, @@ -244,27 +269,34 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RSAParamTypeDef *pParam, const CCB_RSAClearKeyTypeDef *pRSAClearPrivateKey, CCB_WrappingKeyTypeDef *pWrappingKey, uint32_t *pIV, - uint32_t *pTag, uint32_t *pWrappedExp, uint32_t *pWrappedPhi); + uint32_t *pTag, uint32_t *pWrappedExp, uint32_t *pWrappedPhi, + uint8_t *pOperand, uint32_t *pReferenceModularExp); static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_RSAParamTypeDef *pParam, CCB_WrappingKeyTypeDef *pWrappingKey, uint32_t *pIV, uint32_t *pTag, uint32_t *pWrappedExp, uint32_t *pWrappedPhi, const uint8_t *pOperand, uint8_t *pModularExp, const uint32_t *pReferenceModularExp, uint8_t VerifOperation); -static HAL_StatusTypeDef PKA_ECDSASign(CCB_ECDSACurveParamTypeDef *pCurveParam, +#if defined(SW_SANITY_CHECK_SUPPORT) +static HAL_StatusTypeDef PKA_ECDSASign(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *pCurveParam, const uint8_t *pClearPrivateKey, uint8_t *pInteger, uint8_t *pHash, CCB_ECDSASignTypeDef *pSignature); -static HAL_StatusTypeDef PKA_ECC_ComputeScalarMul(CCB_ECCMulCurveParamTypeDef *pCurveParam, +static HAL_StatusTypeDef PKA_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_ECCMulCurveParamTypeDef *pCurveParam, const uint8_t *pClearPrivateKey, uint32_t PublicKey[2][20]); -static HAL_StatusTypeDef PKA_RSA_ComputeModularExp(CCB_RSAParamTypeDef *pParam, +static HAL_StatusTypeDef PKA_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_RSAParamTypeDef *pParam, const CCB_RSAClearKeyTypeDef *pRSAClearPrivateKey, uint8_t *pOp1, uint32_t *pReferenceModularExp); -static HAL_StatusTypeDef PKA_ECDSAVerif(CCB_ECDSACurveParamTypeDef *pCurveParam, +static HAL_StatusTypeDef PKA_RAM_Erase(CCB_HandleTypeDef *hccb); +#endif /* GENERATOR_SW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ +static HAL_StatusTypeDef PKA_ECDSAVerif(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *pCurveParam, CCB_ECCMulPointTypeDef *pPublicKeyOut, const uint8_t *pHash, CCB_ECDSASignTypeDef *pSignature); -static uint32_t PKA_ECDSAVerif_Result(void); -static HAL_StatusTypeDef PKA_RAM_Erase(void); -static void CCB_PKA_RAMReset(void); +static uint32_t PKA_ECDSAVerif_Result(CCB_HandleTypeDef *hccb); +static void CCB_PKA_RAMReset(CCB_HandleTypeDef *hccb); +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +HAL_StatusTypeDef CCB_RNG_ResilientRecoverSeedError(CCB_HandleTypeDef *hccb); +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ + /** @defgroup CCB_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @@ -306,7 +338,7 @@ HAL_StatusTypeDef HAL_CCB_Init(CCB_HandleTypeDef *hccb) HAL_CCB_MspInit(hccb); /* PKA RAM RESET*/ - CCB_PKA_RAMReset(); + CCB_PKA_RAMReset(hccb); /* Update the CCB state */ hccb->State = HAL_CCB_STATE_READY; @@ -527,7 +559,10 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS { uint32_t count; __IO uint16_t f_count; +#if defined(SW_SANITY_CHECK_SUPPORT) uint16_t random0 = 0; + uint8_t integer[80U] = {0}; +#endif /* GENERATOR_SW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ uint16_t random1 = 0; uint16_t random2 = 0; uint16_t random3 = 0; @@ -539,7 +574,6 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS uint8_t s_sign[80U] = {0}; uint8_t point_x[80U] = {0}; uint8_t point_y[80U] = {0}; - uint8_t integer[80U] = {0}; uint32_t iv_temp[4] = {0}; uint32_t tag_temp[4] = {0}; uint32_t wrapped_key_temp[80U] = {0}; @@ -547,7 +581,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS CCB_ECDSASignTypeDef signature = {r_sign, s_sign}; CCB_ECCMulPointTypeDef publicKeyOut = {(uint8_t *)point_x, (uint8_t *)point_y}; - if (CCB_RNG_Init() != HAL_OK) + if (CCB_RNG_Init(hccb) != HAL_OK) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -556,7 +590,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS for (count = 0U; count < (pCurveParam->primeOrderSizeByte); count++) { - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } @@ -565,7 +599,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS while (hash[count] == 0U) { - hash[count] = (uint8_t)((RNG->DR) & 0x000000FFU); + hash[count] = (uint8_t)((HAL_CCB_GET_RNG_INSTANCE(hccb)->DR) & 0x000000FFU); if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* Set state and return error */ @@ -574,24 +608,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS } } - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return HAL_ERROR; - } - - tickstart = HAL_GetTick(); - - while (random0 == 0U) - { - random0 = (uint16_t)(RNG->DR & 0x3FFU); - if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) - { - /* Set state and return error */ - return HAL_ERROR; - } - } - - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } @@ -600,7 +617,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS while (random1 == 0U) { - random1 = (uint16_t)(RNG->DR & 0x3FFU); + random1 = (uint16_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0x3FFU); if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* Set state and return error */ @@ -608,7 +625,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS } } - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } @@ -617,7 +634,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS while (random2 == 0U) { - random2 = (uint16_t)(RNG->DR & 0x3FFU); + random2 = (uint16_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0x3FFU); if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* Set state and return error */ @@ -625,7 +642,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS } } - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } @@ -634,21 +651,21 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS while (random3 == 0U) { - random3 = (uint16_t)(RNG->DR & 0x3FFU); + random3 = (uint16_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0x3FFU); if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* Set state and return error */ return HAL_ERROR; } } - - for (count = 0U; count < (pCurveParam->primeOrderSizeByte); count++) + if (hccb->State == HAL_CCB_STATE_READY) { +#if defined(SW_SANITY_CHECK_SUPPORT) tickstart = HAL_GetTick(); - while (integer[count] == 0U) + while (random0 == 0U) { - integer[count] = (uint8_t)((RNG->DR) & 0x000000FFU); + random0 = (uint16_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0x3FFU); if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* Set state and return error */ @@ -656,26 +673,42 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS } } - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } - } - if (hccb->State == HAL_CCB_STATE_READY) - { + for (count = 0U; count < (pCurveParam->primeOrderSizeByte); count++) + { + tickstart = HAL_GetTick(); + + while (integer[count] == 0U) + { + integer[count] = (uint8_t)((HAL_CCB_GET_RNG_INSTANCE(hccb)->DR) & 0x000000FFU); + if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) + { + /* Set state and return error */ + return HAL_ERROR; + } + } - if (Unprotected_PKA_Init() != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return HAL_ERROR; + } + } + + if (Unprotected_PKA_Init(hccb) != HAL_OK) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; return HAL_ERROR; } - if (PKA_ECDSASign(pCurveParam, pClearPrivateKey, (uint8_t *)integer, (uint8_t *)hash, + if (PKA_ECDSASign(hccb, pCurveParam, pClearPrivateKey, (uint8_t *)integer, (uint8_t *)hash, &signature) != HAL_OK) { - if (PKA_RAM_Erase() != HAL_OK) + if (PKA_RAM_Erase(hccb) != HAL_OK) { hccb->ErrorCode |= HAL_CCB_ERROR_PKARAM_ERASE; } @@ -690,7 +723,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS /* Signature blob creation */ if (CCB_ECDSA_SignBlobCreation(hccb, pCurveParam, pClearPrivateKey, pWrappingKey, iv_temp, tag_temp, - wrapped_key_temp, CCB_ECDSA_SIGN_CPU_BLOB_CREATION) != HAL_OK) + wrapped_key_temp, NULL, NULL, CCB_ECDSA_SIGN_CPU_BLOB_CREATION) != HAL_OK) { /* Set state, and intrusion error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -701,9 +734,17 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS for (uint32_t index = 0U; index < CCB_PKA_RAM_SIZE; index++) { /* Clear the content */ - PKA->RAM[index] = 0UL; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[index] = 0UL; + } +#elif defined (HW_SANITY_CHECK_SUPPORT) + /* Signature blob creation */ + if (CCB_ECDSA_SignBlobCreation(hccb, pCurveParam, pClearPrivateKey, pWrappingKey, iv_temp, tag_temp, + wrapped_key_temp, hash, &signature, CCB_ECDSA_SIGN_CPU_BLOB_CREATION) != HAL_OK) + { + return HAL_ERROR; } +#endif /* GENERATOR_SW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ /* Create ECDSA public key */ if (CCB_ECC_ComputeScalarMul(hccb, pCurveParam, pWrappingKey, iv_temp, tag_temp, wrapped_key_temp, NULL, &publicKeyOut, NULL, @@ -714,7 +755,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS HAL_CCB_IntrusionCallback(hccb); } - if (Unprotected_PKA_Init() != HAL_OK) + if (Unprotected_PKA_Init(hccb) != HAL_OK) { /* Set state, and intrusion error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -722,7 +763,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS } /* PKA ECDSA valid R & S signature */ - if (PKA_ECDSAVerif(pCurveParam, &publicKeyOut, hash, &signature) != HAL_OK) + if (PKA_ECDSAVerif(hccb, pCurveParam, &publicKeyOut, hash, &signature) != HAL_OK) { /* Set state, and intrusion error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -736,7 +777,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS } /* Check if it is valid signature and improve robustness against intrusion (intentional) */ - if ((PKA_ECDSAVerif_Result() != CCB_PKA_ECDSA_VERIF_OK) || (f_count != random1) || (f_count == 0U)) + if ((PKA_ECDSAVerif_Result(hccb) != CCB_PKA_ECDSA_VERIF_OK) || (f_count != random1) || (f_count == 0U)) { /* Set state, and intrusion error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -750,7 +791,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS } /* Check if it is valid signature and improve robustness against intrusion (intentional) */ - if ((PKA_ECDSAVerif_Result() != CCB_PKA_ECDSA_VERIF_OK) || (f_count != random2) || (f_count == 0U)) + if ((PKA_ECDSAVerif_Result(hccb) != CCB_PKA_ECDSA_VERIF_OK) || (f_count != random2) || (f_count == 0U)) { /* Set state, and intrusion error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -764,7 +805,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDS } /* Check if it is valid signature and improve robustness against intrusion (intentional) */ - if ((PKA_ECDSAVerif_Result() != CCB_PKA_ECDSA_VERIF_OK) || (f_count != random3) || (f_count == 0U)) + if ((PKA_ECDSAVerif_Result(hccb) != CCB_PKA_ECDSA_VERIF_OK) || (f_count != random3) || (f_count == 0U)) { /* Set state, and intrusion error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -812,23 +853,195 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_GenerateWrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_WrappingKeyTypeDef *pWrappingKey, CCB_ECDSAKeyBlobTypeDef *pWrappedPrivateKeyBlob) { - uint32_t count; + uint32_t count; uint32_t key_size; uint32_t iv_temp[4] = {0}; uint32_t tag_temp[4] = {0}; uint32_t wrapped_key_temp[80U] = {0}; +#if defined (HW_SANITY_CHECK_SUPPORT) + uint32_t tickstart; + __IO uint16_t f_count; + uint16_t random1 = 0; + uint16_t random2 = 0; + uint16_t random3 = 0; + uint8_t hash[80U] = {0}; + uint8_t r_sign[80U] = {0}; + uint8_t s_sign[80U] = {0}; + uint8_t point_x[80U] = {0}; + uint8_t point_y[80U] = {0}; + + CCB_ECDSASignTypeDef signature = {r_sign, s_sign}; + CCB_ECCMulPointTypeDef public_key_out = {(uint8_t *)point_x, (uint8_t *)point_y}; +#endif /* GENERATOR_HW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ + if (hccb->State == HAL_CCB_STATE_READY) { +#if defined(SW_SANITY_CHECK_SUPPORT) + /* Signature blob creation */ + if (CCB_ECDSA_SignBlobCreation(hccb, pCurveParam, NULL, pWrappingKey, iv_temp, tag_temp, wrapped_key_temp, + NULL, NULL, CCB_ECDSA_SIGN_RNG_BLOB_CREATION) != HAL_OK) + { + /* Set state, error code and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } +#elif defined (HW_SANITY_CHECK_SUPPORT) + if (CCB_RNG_Init(hccb) != HAL_OK) + { + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + + tickstart = HAL_GetTick(); + while (random1 == 0U) + { + random1 = (uint16_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0x3FFU); + if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) + { + /* Set state and return error */ + return HAL_ERROR; + } + } + + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return HAL_ERROR; + } + + tickstart = HAL_GetTick(); + + while (random2 == 0U) + { + random2 = (uint16_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0x3FFU); + if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) + { + /* Set state and return error */ + return HAL_ERROR; + } + } + + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return HAL_ERROR; + } + + tickstart = HAL_GetTick(); + + while (random3 == 0U) + { + random3 = (uint16_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0x3FFU); + if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) + { + /* Set state and return error */ + return HAL_ERROR; + } + } + + for (count = 0U; count < (pCurveParam->primeOrderSizeByte); count++) + { + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return HAL_ERROR; + } + + tickstart = HAL_GetTick(); + + while (hash[count] == 0U) + { + hash[count] = (uint8_t)((HAL_CCB_GET_RNG_INSTANCE(hccb)->DR) & 0x000000FFU); + if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) + { + /* Set state and return error */ + return HAL_ERROR; + } + } + } /* Signature blob creation */ if (CCB_ECDSA_SignBlobCreation(hccb, pCurveParam, NULL, pWrappingKey, iv_temp, tag_temp, wrapped_key_temp, - CCB_ECDSA_SIGN_RNG_BLOB_CREATION) != HAL_OK) + (uint8_t *)hash, + &signature, CCB_ECDSA_SIGN_RNG_BLOB_CREATION) != HAL_OK) + { /* Set state, error code and return error */ hccb->State = HAL_CCB_STATE_ERROR; return HAL_ERROR; } + + /* Reset each element in the PKA RAM */ + for (uint32_t index = 0U; index < CCB_PKA_RAM_SIZE; index++) + { + /* Clear the content */ + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[index] = 0UL; + } + /* Create ECDSA public key */ + if (CCB_ECC_ComputeScalarMul(hccb, pCurveParam, pWrappingKey, iv_temp, tag_temp, wrapped_key_temp, NULL, + &public_key_out, NULL, CCB_COMPUTE_PUBLIC_KEY) != HAL_OK) + { + /* Set state, and intrusion error */ + hccb->State = HAL_CCB_STATE_ERROR; + HAL_CCB_IntrusionCallback(hccb); + } + + if (Unprotected_PKA_Init(hccb) != HAL_OK) + { + /* Set state, and intrusion error */ + hccb->State = HAL_CCB_STATE_ERROR; + HAL_CCB_IntrusionCallback(hccb); + } + + /* PKA ECDSA valid R & S signature */ + if (PKA_ECDSAVerif(hccb, pCurveParam, &public_key_out, hash, &signature) != HAL_OK) + { + /* Set state, and intrusion error */ + hccb->State = HAL_CCB_STATE_ERROR; + HAL_CCB_IntrusionCallback(hccb); + } + + f_count = 0; + while (f_count < random1) + { + f_count++; + } + + /* Check if it is valid signature and improve robustness against intrusion (intentional) */ + if ((PKA_ECDSAVerif_Result(hccb) != CCB_PKA_ECDSA_VERIF_OK) || (f_count != random1) || (f_count == 0U)) + { + /* Set state, and intrusion error */ + hccb->State = HAL_CCB_STATE_ERROR; + HAL_CCB_IntrusionCallback(hccb); + } + + f_count = 0; + while (f_count < random2) + { + f_count++; + } + + /* Check if it is valid signature and improve robustness against intrusion (intentional) */ + if ((PKA_ECDSAVerif_Result(hccb) != CCB_PKA_ECDSA_VERIF_OK) || (f_count != random2) || (f_count == 0U)) + { + /* Set state, and intrusion error */ + hccb->State = HAL_CCB_STATE_ERROR; + HAL_CCB_IntrusionCallback(hccb); + } + + f_count = 0; + while (f_count < random3) + { + f_count++; + } + + /* Check if it is valid signature and improve robustness against intrusion (intentional) */ + if ((PKA_ECDSAVerif_Result(hccb) != CCB_PKA_ECDSA_VERIF_OK) || (f_count != random3) || (f_count == 0U)) + { + /* Set state, and intrusion error */ + hccb->State = HAL_CCB_STATE_ERROR; + HAL_CCB_IntrusionCallback(hccb); + } +#endif /* GENERATOR_HW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ } else { @@ -892,7 +1105,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_Sign(CCB_HandleTypeDef *hccb, CCB_ECDSACurvePara } /* Initialize RNG */ - if (CCB_RNG_Init() != HAL_OK) + if (CCB_RNG_Init(hccb) != HAL_OK) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -910,12 +1123,22 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_Sign(CCB_HandleTypeDef *hccb, CCB_ECDSACurvePara /* Initialize SAES */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* Disable the SAES peripheral */ - SAES->CR &= ~AES_CR_EN; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + /* Disable the SAES peripheral */ + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; - /* Set state and return error */ - hccb->State = HAL_CCB_STATE_ERROR; - return HAL_ERROR; + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Update the state */ @@ -952,7 +1175,8 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_Sign(CCB_HandleTypeDef *hccb, CCB_ECDSACurvePara } /* Set Hash message */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_HASH_E ], pHash, pCurveParam->modulusSizeByte); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_HASH_E ], pHash, + pCurveParam->modulusSizeByte); /* Initial Phase Processing */ if (CCB_BlobUse_InitialPhase(hccb, pWrappedPrivateKeyBlob->pIV, pWrappedPrivateKeyBlob->pTag) != HAL_OK) @@ -976,7 +1200,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_Sign(CCB_HandleTypeDef *hccb, CCB_ECDSACurvePara } /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x13 --> 0x14 */ - MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_1); + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_GCMPH, AES_CR_GCMPH_1); /* Wait until OPSTEP is set to 0x14 */ if (CCB_WaitOperStep(hccb, 0x14, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -988,7 +1212,8 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_Sign(CCB_HandleTypeDef *hccb, CCB_ECDSACurvePara /* Write encrypted Key*/ for (offset = 0UL; offset < cipherkey_size; offset++) { - WRITE_REG(SAES->DINR, pWrappedPrivateKeyBlob->pWrappedKey[cipherkey_size - (offset + 1UL)]); + WRITE_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->DINR, \ + pWrappedPrivateKeyBlob->pWrappedKey[cipherkey_size - (offset + 1UL)]); if ((offset % 4UL) == 0x3UL) { @@ -1002,7 +1227,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_Sign(CCB_HandleTypeDef *hccb, CCB_ECDSACurvePara /* Write key in PKA RAM */ for (count = 0UL; count < 4UL; count++) { - PKA->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + count_block + count] = CCB_MAGIC_VALUE; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + count_block + count] = CCB_MAGIC_VALUE; } count_block += 4UL; } @@ -1010,7 +1235,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_Sign(CCB_HandleTypeDef *hccb, CCB_ECDSACurvePara if ((operand_size % 4UL) != 0UL) { - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + cipherkey_size); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + cipherkey_size); } /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x14 --> 0x16 */ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_DATAOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -1030,16 +1255,16 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_Sign(CCB_HandleTypeDef *hccb, CCB_ECDSACurvePara for (offset = 0UL; offset < (operand_size - 2UL); offset++) { /* Wait for RNG Data Ready flag */ - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { /* return error */ return HAL_ERROR; } - PKA->RAM[PKA_ECDSA_SIGN_IN_K + offset] = CCB_FAKE_VALUE; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_K + offset] = CCB_FAKE_VALUE; } /* Padding at zero */ - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_K + offset); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_ECDSA_SIGN_IN_K + offset); /* Wait for PKA RNGOK flag : GCMPH = 0x3 (final phase) as events that trig OPSTEP transition 0x16 --> 0x17 */ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_RNGOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -1070,7 +1295,7 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_Sign(CCB_HandleTypeDef *hccb, CCB_ECDSACurvePara } /* SET PKA START operation bit and trig OPSTEP transition 0x18 --> 0x19 */ - SET_BIT(PKA->CR, PKA_CR_START); + SET_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_START); /* Wait until OPSTEP is set to 0x19 */ if (CCB_WaitOperStep(hccb, 0x19, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -1094,16 +1319,18 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_Sign(CCB_HandleTypeDef *hccb, CCB_ECDSACurvePara } /* Check PKA Operation error result */ - if ((PKA->RAM[PKA_ECDSA_SIGN_OUT_ERROR]) != CCB_PKA_ERROR_OPERATION_NONE) + if ((HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_OUT_ERROR]) != CCB_PKA_ERROR_OPERATION_NONE) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; return HAL_ERROR; } /* Read r part signature */ - CCB_Memcpy_u32_to_u8(pSignature->pRSign, &PKA->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], pCurveParam->modulusSizeByte); + CCB_Memcpy_u32_to_u8(pSignature->pRSign, &HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], + pCurveParam->modulusSizeByte); /* Read s part signature */ - CCB_Memcpy_u32_to_u8(pSignature->pSSign, &PKA->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], pCurveParam->modulusSizeByte); + CCB_Memcpy_u32_to_u8(pSignature->pSSign, &HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], + pCurveParam->modulusSizeByte); /* set CCB IPRST */ @@ -1183,43 +1410,45 @@ HAL_StatusTypeDef HAL_CCB_ECC_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECCMul const uint8_t *pClearPrivateKey, CCB_WrappingKeyTypeDef *pWrappingKey, CCB_ECCMulKeyBlobTypeDef *pWrappedPrivateKeyBlob) { +#if defined(SW_SANITY_CHECK_SUPPORT) uint8_t random = 0; - uint32_t public_key[2][20] = {{0UL}, {0UL}}; __IO uint8_t f_count; + uint32_t tickstart; +#endif /* GENERATOR_SW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ + uint32_t public_key[2][20] = {{0UL}, {0UL}}; uint32_t count; uint32_t key_size; uint32_t iv_temp[4] = {0}; uint32_t tag_temp[4] = {0}; uint32_t wrapped_key_temp[80] = {0}; - uint32_t tickstart; if (hccb->State == HAL_CCB_STATE_READY) { - - if (Unprotected_PKA_Init() != HAL_OK) +#if defined(SW_SANITY_CHECK_SUPPORT) + if (Unprotected_PKA_Init(hccb) != HAL_OK) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; return HAL_ERROR; } - if (CCB_RNG_Init() != HAL_OK) + if (CCB_RNG_Init(hccb) != HAL_OK) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; return HAL_ERROR; } - if (PKA_ECC_ComputeScalarMul(pCurveParam, pClearPrivateKey, public_key) != HAL_OK) + if (PKA_ECC_ComputeScalarMul(hccb, pCurveParam, pClearPrivateKey, public_key) != HAL_OK) { - if (PKA_RAM_Erase() != HAL_OK) + if (PKA_RAM_Erase(hccb) != HAL_OK) { hccb->ErrorCode |= HAL_CCB_ERROR_PKARAM_ERASE; } return HAL_ERROR; } - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } @@ -1228,7 +1457,7 @@ HAL_StatusTypeDef HAL_CCB_ECC_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECCMul while (random == 0U) { - random = (uint8_t)(RNG->DR & 0xFFU); + random = (uint8_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0xFFU); if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* Set state and return error */ @@ -1243,7 +1472,7 @@ HAL_StatusTypeDef HAL_CCB_ECC_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECCMul } if (CCB_ECC_ScalarMulBlobCreation(hccb, pCurveParam, pClearPrivateKey, pWrappingKey, - iv_temp, tag_temp, wrapped_key_temp, + iv_temp, tag_temp, wrapped_key_temp, NULL, CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION) != HAL_OK) { /* Set state, and intrusion error */ @@ -1251,6 +1480,16 @@ HAL_StatusTypeDef HAL_CCB_ECC_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECCMul HAL_CCB_IntrusionCallback(hccb); } +#elif defined (HW_SANITY_CHECK_SUPPORT) + /* CCB ECC generate private wrap key */ + if (CCB_ECC_ScalarMulBlobCreation(hccb, pCurveParam, pClearPrivateKey, pWrappingKey, + iv_temp, tag_temp, wrapped_key_temp, public_key, + CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION) != HAL_OK) + { + return HAL_ERROR; + } + +#endif /* GENERATOR_HW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ /* Compute CCB public key */ if (CCB_ECC_ComputeScalarMul(hccb, pCurveParam, pWrappingKey, iv_temp, tag_temp, wrapped_key_temp, NULL, NULL, &public_key[0][0], CCB_VERIF_OPERATION_ENABLED) != HAL_OK) @@ -1303,17 +1542,43 @@ HAL_StatusTypeDef HAL_CCB_ECC_GenerateWrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_WrappingKeyTypeDef *pWrappingKey, CCB_ECCMulKeyBlobTypeDef *pWrappedPrivateKeyBlob) { - +#if defined (HW_SANITY_CHECK_SUPPORT) + uint32_t PublicKey[2U][20U] = {0U}; +#endif /* GENERATOR_HW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ + uint32_t count; + uint32_t key_size; + uint32_t iv_temp[4] = {0}; + uint32_t tag_temp[4] = {0}; + uint32_t wrapped_key_temp[80] = {0}; if (hccb->State == HAL_CCB_STATE_READY) { +#if defined (HW_SANITY_CHECK_SUPPORT) + /* CCB ECC generate private wrap key */ + if (CCB_ECC_ScalarMulBlobCreation(hccb, pCurveParam, NULL, pWrappingKey, + iv_temp, tag_temp, wrapped_key_temp, PublicKey, + CCB_ECC_SCALAR_MUL_RNG_BLOB_CREATION) != HAL_OK) + { + return HAL_ERROR; + } + + /* Compute ECC public key */ + if (CCB_ECC_ComputeScalarMul(hccb, pCurveParam, pWrappingKey, iv_temp, tag_temp, wrapped_key_temp, + NULL, NULL, &PublicKey[0][0], CCB_VERIF_OPERATION_ENABLED) != HAL_OK) + { + /* Set state, and intrusion error */ + hccb->State = HAL_CCB_STATE_ERROR; + HAL_CCB_IntrusionCallback(hccb); + } +#elif defined(SW_SANITY_CHECK_SUPPORT) + /* CCB ECC generate private wrap key */ if (CCB_ECC_ScalarMulBlobCreation(hccb, pCurveParam, NULL, pWrappingKey, - pWrappedPrivateKeyBlob->pIV, pWrappedPrivateKeyBlob->pTag, - pWrappedPrivateKeyBlob->pWrappedKey, + iv_temp, tag_temp, wrapped_key_temp, NULL, CCB_ECC_SCALAR_MUL_RNG_BLOB_CREATION) != HAL_OK) { return HAL_ERROR; } +#endif /* GENERATOR_HW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ } else { @@ -1325,6 +1590,17 @@ HAL_StatusTypeDef HAL_CCB_ECC_GenerateWrapPrivateKey(CCB_HandleTypeDef *hccb, /* Update the CCB state */ hccb->State = HAL_CCB_STATE_READY; + /* Export created Blob */ + key_size = CCB_get_cipherkey_size(pCurveParam); + for (count = 0U; count < key_size; count++) + { + if (count < CCB_BLOCK_SIZE) + { + pWrappedPrivateKeyBlob->pIV[count] = iv_temp[count]; + pWrappedPrivateKeyBlob->pTag[count] = tag_temp[count]; + } + pWrappedPrivateKeyBlob->pWrappedKey[count] = wrapped_key_temp[count]; + } /* Return HAL OK */ return HAL_OK; @@ -1384,8 +1660,10 @@ HAL_StatusTypeDef HAL_CCB_RSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_RSAPar { uint8_t exp_base[520U] = {0}; uint32_t count; +#if defined(SW_SANITY_CHECK_SUPPORT) __IO uint16_t f_count; uint16_t random0 = 0; +#endif /* GENERATOR_SW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ uint32_t modular_exp_ref[520U] = {0}; uint32_t operand_size; uint32_t cipherkey_size; @@ -1397,7 +1675,7 @@ HAL_StatusTypeDef HAL_CCB_RSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_RSAPar if (hccb->State == HAL_CCB_STATE_READY) { - if (CCB_RNG_Init() != HAL_OK) + if (CCB_RNG_Init(hccb) != HAL_OK) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -1406,7 +1684,7 @@ HAL_StatusTypeDef HAL_CCB_RSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_RSAPar for (uint32_t offset = 0U; offset < pParam->modulusSizeByte; offset++) { - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } @@ -1415,7 +1693,7 @@ HAL_StatusTypeDef HAL_CCB_RSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_RSAPar while (exp_base[offset] == 0U) { - exp_base[offset] = (uint8_t)(RNG->DR & 0xFFU); + exp_base[offset] = (uint8_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0xFFU); if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* Set state and return error */ @@ -1424,7 +1702,8 @@ HAL_StatusTypeDef HAL_CCB_RSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_RSAPar } } - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) +#if defined(SW_SANITY_CHECK_SUPPORT) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } @@ -1433,7 +1712,7 @@ HAL_StatusTypeDef HAL_CCB_RSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_RSAPar while (random0 == 0U) { - random0 = (uint16_t)(RNG->DR & 0x3FFU); + random0 = (uint16_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0x3FFU); if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* Set state and return error */ @@ -1441,30 +1720,23 @@ HAL_StatusTypeDef HAL_CCB_RSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_RSAPar } } - if (Unprotected_PKA_Init() != HAL_OK) + if (Unprotected_PKA_Init(hccb) != HAL_OK) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; return HAL_ERROR; } - if (PKA_RSA_ComputeModularExp(pParam, pRSAClearPrivateKey, (uint8_t *)exp_base, modular_exp_ref) != HAL_OK) + if (PKA_RSA_ComputeModularExp(hccb, pParam, pRSAClearPrivateKey, (uint8_t *)exp_base, modular_exp_ref) != HAL_OK) { - if (PKA_RAM_Erase() != HAL_OK) + if (PKA_RAM_Erase(hccb) != HAL_OK) { hccb->ErrorCode |= HAL_CCB_ERROR_PKARAM_ERASE; } return HAL_ERROR; } - if (CCB_RNG_Init() != HAL_OK) - { - /* Set state and return error */ - hccb->State = HAL_CCB_STATE_ERROR; - return HAL_ERROR; - } - - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } @@ -1476,12 +1748,21 @@ HAL_StatusTypeDef HAL_CCB_RSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_RSAPar } if (CCB_RSA_ExpBlobCreation(hccb, pParam, pRSAClearPrivateKey, pWrappingKey, iv_temp, tag_temp, wrapped_exp, - wrapped_phi) != HAL_OK) + wrapped_phi, NULL, NULL) != HAL_OK) { /* Set state, and intrusion error */ hccb->State = HAL_CCB_STATE_ERROR; HAL_CCB_IntrusionCallback(hccb); } +#elif defined (HW_SANITY_CHECK_SUPPORT) + if (CCB_RSA_ExpBlobCreation(hccb, pParam, pRSAClearPrivateKey, pWrappingKey, iv_temp, tag_temp, wrapped_exp, + wrapped_phi, (uint8_t *)exp_base, modular_exp_ref) != HAL_OK) + { + /* Set state, and intrusion error */ + hccb->State = HAL_CCB_STATE_ERROR; + HAL_CCB_IntrusionCallback(hccb); + } +#endif /* GENERATOR_SW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ if (CCB_RSA_ComputeModularExp(hccb, pParam, pWrappingKey, iv_temp, tag_temp, wrapped_exp, wrapped_phi, (uint8_t *)exp_base, NULL, modular_exp_ref, @@ -1662,11 +1943,11 @@ static HAL_StatusTypeDef Protect_PKA_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t { uint32_t tickstart = HAL_GetTick(); - while (HAL_IS_BIT_CLR(PKA->SR, flag)) + while (HAL_IS_BIT_CLR(HAL_CCB_GET_PKA_INSTANCE(hccb)->SR, flag)) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - CLEAR_BIT(PKA->CR, PKA_CR_EN); + CLEAR_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_EN); /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -1675,7 +1956,7 @@ static HAL_StatusTypeDef Protect_PKA_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t } /* Clear flag */ - SET_BIT(PKA->CLRFR, flag); + SET_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CLRFR, flag); /* Return function status */ return HAL_OK; @@ -1683,19 +1964,20 @@ static HAL_StatusTypeDef Protect_PKA_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t /** * @brief Wait PKA Flag + * @param hccb CCB handle * @param flag Specifies the flag to check * @param Timeout Timeout duration * @retval HAL status. */ -static HAL_StatusTypeDef Unprotect_PKA_WaitFLAG(uint32_t flag, uint32_t Timeout) +static HAL_StatusTypeDef Unprotect_PKA_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t flag, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); - while (HAL_IS_BIT_CLR(PKA->SR, flag)) + while (HAL_IS_BIT_CLR(HAL_CCB_GET_PKA_INSTANCE(hccb)->SR, flag)) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - CLEAR_BIT(PKA->CR, PKA_CR_EN); + CLEAR_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_EN); /* return error */ return HAL_ERROR; @@ -1703,7 +1985,7 @@ static HAL_StatusTypeDef Unprotect_PKA_WaitFLAG(uint32_t flag, uint32_t Timeout) } /* Clear flag */ - SET_BIT(PKA->CLRFR, flag); + SET_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CLRFR, flag); /* Return function status */ return HAL_OK; @@ -1711,19 +1993,20 @@ static HAL_StatusTypeDef Unprotect_PKA_WaitFLAG(uint32_t flag, uint32_t Timeout) /** * @brief Wait RNG Flag + * @param hccb CCB handle * @param flag Specifies the flag to check * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef CCB_RNG_Wait_SET_FLAG(uint32_t flag, uint32_t Timeout) +static HAL_StatusTypeDef CCB_RNG_Wait_SET_FLAG(CCB_HandleTypeDef *hccb, uint32_t flag, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); - while (HAL_IS_BIT_CLR(RNG->SR, flag)) + while (HAL_IS_BIT_CLR(HAL_CCB_GET_RNG_INSTANCE(hccb)->SR, flag)) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - RNG->CR &= ~RNG_CR_RNGEN; + HAL_CCB_GET_RNG_INSTANCE(hccb)->CR &= ~RNG_CR_RNGEN; /* Set state and return error */ return HAL_ERROR; @@ -1747,11 +2030,11 @@ static HAL_StatusTypeDef Protect_SAES_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t { uint32_t tickstart = HAL_GetTick(); - while (HAL_CCB_GET_SAES_FLAG(flag) != Status) + while (HAL_CCB_GET_SAES_FLAG(hccb, flag) != Status) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - SAES->CR &= ~AES_CR_EN; + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -1760,7 +2043,7 @@ static HAL_StatusTypeDef Protect_SAES_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t } /* Clear flag */ - SET_BIT(SAES->ICR, flag); + SET_BIT(HAL_CCB_GET_SAES_INSTANCE(hccb)->ICR, flag); /* Return function status */ @@ -1776,9 +2059,9 @@ static HAL_StatusTypeDef Protect_SAES_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t static HAL_StatusTypeDef CCB_ECDSASign_SetPram(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *in) { /* Get the prime order n length */ - PKA->RAM[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS] + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS] = GetOptBitSize_u8(in->primeOrderSizeByte, *(in->pPrimeOrder)); - PKA->RAM[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS + 1U] = 0x0U; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS + 1U] = 0x0U; if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { hccb->State = HAL_CCB_STATE_ERROR; @@ -1786,8 +2069,9 @@ static HAL_StatusTypeDef CCB_ECDSASign_SetPram(CCB_HandleTypeDef *hccb, CCB_ECDS } /* Get the modulus p length */ - PKA->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS] = GetOptBitSize_u8(in->modulusSizeByte, *(in->pModulus)); - PKA->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS + 1U] = 0x0U; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS] = GetOptBitSize_u8(in->modulusSizeByte, + *(in->pModulus)); + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS + 1U] = 0x0U; if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { hccb->State = HAL_CCB_STATE_ERROR; @@ -1795,8 +2079,8 @@ static HAL_StatusTypeDef CCB_ECDSASign_SetPram(CCB_HandleTypeDef *hccb, CCB_ECDS } /* Get the coefficient a sign */ - PKA->RAM[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN] = in->coefSignA; - PKA->RAM[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN + 1U] = 0x0; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN] = in->coefSignA; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN + 1U] = 0x0; if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { hccb->State = HAL_CCB_STATE_ERROR; @@ -1852,9 +2136,9 @@ static HAL_StatusTypeDef CCB_ECDSASign_SetPram(CCB_HandleTypeDef *hccb, CCB_ECDS static HAL_StatusTypeDef CCB_ECCMul_SetPram(CCB_HandleTypeDef *hccb, CCB_ECCMulCurveParamTypeDef *in) { /* Get the prime order n length */ - PKA->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = GetOptBitSize_u8(in->primeOrderSizeByte, *(in->pPrimeOrder)); - PKA->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS + 1U] = 0x0; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS + 1U] = 0x0; if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { hccb->State = HAL_CCB_STATE_ERROR; @@ -1862,8 +2146,9 @@ static HAL_StatusTypeDef CCB_ECCMul_SetPram(CCB_HandleTypeDef *hccb, CCB_ECCMulC } /* Get the modulus p length */ - PKA->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = GetOptBitSize_u8(in->modulusSizeByte, *(in->pModulus)); - PKA->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS + 1U] = 0x0; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = GetOptBitSize_u8(in->modulusSizeByte, + *(in->pModulus)); + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS + 1U] = 0x0; if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { hccb->State = HAL_CCB_STATE_ERROR; @@ -1871,8 +2156,8 @@ static HAL_StatusTypeDef CCB_ECCMul_SetPram(CCB_HandleTypeDef *hccb, CCB_ECCMulC } /* Get the coefficient a sign */ - PKA->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSignA; - PKA->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN + 1U] = 0x0; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSignA; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN + 1U] = 0x0; if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { hccb->State = HAL_CCB_STATE_ERROR; @@ -1916,8 +2201,9 @@ static HAL_StatusTypeDef CCB_ECCMul_SetPram(CCB_HandleTypeDef *hccb, CCB_ECCMulC static HAL_StatusTypeDef CCB_RSAModExp_SetPram(CCB_HandleTypeDef *hccb, CCB_RSAParamTypeDef *in) { /* Get the exp length */ - PKA->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = GetOptBitSize_u8(in->expSizeByte, *(in->pMod)); - PKA->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS + 1U] = 0x0U; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = GetOptBitSize_u8(in->expSizeByte, + *(in->pMod)); + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS + 1U] = 0x0U; if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { hccb->State = HAL_CCB_STATE_ERROR; @@ -1925,8 +2211,9 @@ static HAL_StatusTypeDef CCB_RSAModExp_SetPram(CCB_HandleTypeDef *hccb, CCB_RSAP } /* Get the modulus n length */ - PKA->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = GetOptBitSize_u8(in->modulusSizeByte, *(in->pMod)); - PKA->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS + 1U] = 0x0U; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = GetOptBitSize_u8(in->modulusSizeByte, + *(in->pMod)); + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS + 1U] = 0x0U; if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { hccb->State = HAL_CCB_STATE_ERROR; @@ -1962,7 +2249,7 @@ static HAL_StatusTypeDef CCB_SetPram(CCB_HandleTypeDef *hccb, uint32_t modulusSi { for (offset = 0; offset < (operand_size - 4UL); offset += 2UL) { - CCB_Memcpy_u8_to_u64(&PKA->RAM[dst_address + offset], + CCB_Memcpy_u8_to_u64(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[dst_address + offset], &src[(modulusSizeByte) - ((offset * 4UL) + 1UL)]); if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { @@ -1971,7 +2258,7 @@ static HAL_StatusTypeDef CCB_SetPram(CCB_HandleTypeDef *hccb, uint32_t modulusSi } } - CCB_Memcpy_Not_Align(&PKA->RAM[dst_address + offset], + CCB_Memcpy_Not_Align(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[dst_address + offset], &src[(modulusSizeByte) - ((offset * 4UL) + 1UL)], modulusSizeByte % 8UL); if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -1979,7 +2266,7 @@ static HAL_StatusTypeDef CCB_SetPram(CCB_HandleTypeDef *hccb, uint32_t modulusSi hccb->State = HAL_CCB_STATE_ERROR; return HAL_ERROR; } - RAM_PARAM_END(PKA->RAM, dst_address + ((modulusSizeByte + 7UL) / 4UL)); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, dst_address + ((modulusSizeByte + 7UL) / 4UL)); if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { hccb->State = HAL_CCB_STATE_ERROR; @@ -1991,7 +2278,7 @@ static HAL_StatusTypeDef CCB_SetPram(CCB_HandleTypeDef *hccb, uint32_t modulusSi { for (offset = 0; offset < (operand_size - 2UL); offset += 2UL) { - CCB_Memcpy_u8_to_u64(&PKA->RAM[dst_address + offset], + CCB_Memcpy_u8_to_u64(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[dst_address + offset], &src[(modulusSizeByte) - ((offset * 4UL) + 1UL)]); if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { @@ -2000,7 +2287,7 @@ static HAL_StatusTypeDef CCB_SetPram(CCB_HandleTypeDef *hccb, uint32_t modulusSi } } - RAM_PARAM_END(PKA->RAM, dst_address + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, dst_address + ((modulusSizeByte + 3UL) / 4UL)); if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { @@ -2022,23 +2309,34 @@ static HAL_StatusTypeDef CCB_SetPram(CCB_HandleTypeDef *hccb, uint32_t modulusSi static HAL_StatusTypeDef Protect_PKA_Init(CCB_HandleTypeDef *hccb, uint32_t Operation) { /* Reset the control register and enable the PKA */ - PKA->CR = PKA_CR_EN; + HAL_CCB_GET_PKA_INSTANCE(hccb)->CR = PKA_CR_EN; /* Wait the INITOK flag Setting */ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_INITOK, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - return HAL_ERROR; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Reset any pending flag */ - SET_BIT(PKA->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + SET_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CLRFR, + PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); /* Set the mode and deactivate the interrupts */ if ((Operation == CCB_ECDSA_SIGN_CPU_BLOB_CREATION) || (Operation == CCB_ECDSA_SIGN_RNG_BLOB_CREATION) || (Operation == CCB_ECDSA_SIGN_BLOB_USE)) { - MODIFY_REG(PKA->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE + MODIFY_REG(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE, CCB_PKA_ECDSA_SIGNATURE_MODE << PKA_CR_MODE_Pos); } @@ -2046,14 +2344,14 @@ static HAL_StatusTypeDef Protect_PKA_Init(CCB_HandleTypeDef *hccb, uint32_t Oper || (Operation == CCB_ECC_SCALAR_MUL_RNG_BLOB_CREATION) || (Operation == CCB_ECC_SCALAR_MUL_BLOB_USE)) { - MODIFY_REG(PKA->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE + MODIFY_REG(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE, CCB_PKA_ECC_MUL_MODE << PKA_CR_MODE_Pos); } else if ((Operation == CCB_MODULAR_EXP_CPU_BLOB_CREATION) || (Operation == CCB_MODULAR_EXP_BLOB_USE)) { - MODIFY_REG(PKA->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE + MODIFY_REG(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE, CCB_PKA_MODE_MODULAR_EXP_PROTECT << PKA_CR_MODE_Pos); } else @@ -2067,16 +2365,17 @@ static HAL_StatusTypeDef Protect_PKA_Init(CCB_HandleTypeDef *hccb, uint32_t Oper /** * @brief Unprotected PKA Initialization + * @param hccb CCB handle * @retval HAL status. */ -static HAL_StatusTypeDef Unprotected_PKA_Init(void) +static HAL_StatusTypeDef Unprotected_PKA_Init(CCB_HandleTypeDef *hccb) { uint32_t tickstart = HAL_GetTick(); /* Reset the control register and enable the PKA (wait the end of PKA RAM erase) */ - while ((PKA->CR & PKA_CR_EN) != PKA_CR_EN) + while ((HAL_CCB_GET_PKA_INSTANCE(hccb)->CR & PKA_CR_EN) != PKA_CR_EN) { - PKA->CR = PKA_CR_EN; + HAL_CCB_GET_PKA_INSTANCE(hccb)->CR = PKA_CR_EN; /* Check the Timeout */ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) @@ -2086,55 +2385,67 @@ static HAL_StatusTypeDef Unprotected_PKA_Init(void) } } /* Wait the INITOK flag Setting */ - if (Unprotect_PKA_WaitFLAG(PKA_SR_INITOK, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (Unprotect_PKA_WaitFLAG(hccb, PKA_SR_INITOK, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - return HAL_ERROR; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Reset any pending flag */ - SET_BIT(PKA->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + SET_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CLRFR, + PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); return HAL_OK; } /** * @brief Initialize the RNG + * @param hccb CCB handle * @retval HAL status */ -static HAL_StatusTypeDef CCB_RNG_Init(void) +static HAL_StatusTypeDef CCB_RNG_Init(CCB_HandleTypeDef *hccb) { uint32_t tickstart; /* Disable RNG */ - RNG->CR &= ~RNG_CR_RNGEN; + HAL_CCB_GET_RNG_INSTANCE(hccb)->CR &= ~RNG_CR_RNGEN; /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ - MODIFY_REG(RNG->CR, RNG_CR_CONDRST, RNG_CR_CONDRST); + MODIFY_REG(HAL_CCB_GET_RNG_INSTANCE(hccb)->CR, RNG_CR_CONDRST, RNG_CR_CONDRST); #if defined(RNG_CR_NIST_VALUE) /* Recommended value for NIST compliance, refer to application note AN4230 */ - WRITE_REG(RNG->CR, RNG_CR_NIST_VALUE | RNG_CR_CONDRST); + WRITE_REG(HAL_CCB_GET_RNG_INSTANCE(hccb)->CR, RNG_CR_NIST_VALUE | RNG_CR_CONDRST); #endif /* defined(RNG_CR_NIST_VALUE) */ #if defined(RNG_HTCR_NIST_VALUE) /* Recommended value for NIST compliance, refer to application note AN4230 */ - WRITE_REG(RNG->HTCR, RNG_HTCR_NIST_VALUE); + WRITE_REG(HAL_CCB_GET_RNG_INSTANCE(hccb)->HTCR[0], RNG_HTCR_NIST_VALUE); #endif /* defined(RNG_HTCR_NIST_VALUE) */ #if defined(RNG_NSCR_NIST_VALUE) - WRITE_REG(RNG->NSCR, RNG_NSCR_NIST_VALUE); + WRITE_REG(HAL_CCB_GET_RNG_INSTANCE(hccb)->NSCR, RNG_NSCR_NIST_VALUE); #endif /* defined(RNG_NSCR_NIST_VALUE) */ /* Writing bit CONDRST=0 */ - CLEAR_BIT(RNG->CR, RNG_CR_CONDRST); + CLEAR_BIT(HAL_CCB_GET_RNG_INSTANCE(hccb)->CR, RNG_CR_CONDRST); /* Get tick */ tickstart = HAL_GetTick(); /* Wait for conditioning reset process to be completed */ - while (HAL_IS_BIT_SET(RNG->CR, RNG_CR_CONDRST)) + while (HAL_IS_BIT_SET(HAL_CCB_GET_RNG_INSTANCE(hccb)->CR, RNG_CR_CONDRST)) { if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* New check to avoid false timeout detection in case of preemption */ - if (HAL_IS_BIT_SET(RNG->CR, RNG_CR_CONDRST)) + if (HAL_IS_BIT_SET(HAL_CCB_GET_RNG_INSTANCE(hccb)->CR, RNG_CR_CONDRST)) { /* Set state and return error */ return HAL_ERROR; @@ -2143,19 +2454,32 @@ static HAL_StatusTypeDef CCB_RNG_Init(void) } /* Enable the RNG Peripheral */ - RNG->CR |= RNG_CR_RNGEN; + HAL_CCB_GET_RNG_INSTANCE(hccb)->CR |= RNG_CR_RNGEN; - /* verify that no seed error */ - if ((RNG->SR & (RNG_SR_SEIS)) != (uint32_t)RESET) - { - /* Set state and return error */ - return HAL_ERROR; - } + tickstart = HAL_GetTick(); /* Check if data register contains valid random data */ - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + while (HAL_IS_BIT_CLR(HAL_CCB_GET_RNG_INSTANCE(hccb)->SR, RNG_SR_DRDY)) { - return HAL_ERROR; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ + + if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) + { + HAL_CCB_GET_RNG_INSTANCE(hccb)->CR &= ~RNG_CR_RNGEN; + + /* Set state and return error */ + return HAL_ERROR; + } } /* Return function status */ @@ -2189,14 +2513,15 @@ static HAL_StatusTypeDef WrappingKeyConfiguration(CCB_HandleTypeDef *hccb, uint3 || (Operation == CCB_MODULAR_EXP_CPU_BLOB_CREATION)) { /* SAES: GCMPH = 0x0 (initial phase) as event that trig OPSTEP 0x1 --> 0x2 */ - WRITE_REG(SAES->CR, AES_CR_KEYSIZE | AES_CR_CHMOD_0 | AES_CR_CHMOD_1); + WRITE_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_KEYSIZE + | AES_CR_CHMOD_0 | AES_CR_CHMOD_1); } else if ((Operation == CCB_ECDSA_SIGN_BLOB_USE) || (Operation == CCB_ECC_SCALAR_MUL_BLOB_USE) || (Operation == CCB_MODULAR_EXP_BLOB_USE)) { /* SAES: GCMPH = 0x0 (initial phase) as event that trig OPSTEP 0x1 --> 0x12 */ - WRITE_REG(SAES->CR, AES_CR_KEYSIZE | AES_CR_CHMOD_0 + WRITE_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_KEYSIZE | AES_CR_CHMOD_0 | AES_CR_CHMOD_1 | AES_CR_MODE_1); } @@ -2214,16 +2539,16 @@ static HAL_StatusTypeDef WrappingKeyConfiguration(CCB_HandleTypeDef *hccb, uint3 || (Operation == CCB_MODULAR_EXP_CPU_BLOB_CREATION)) { /* SAES: GCMPH = 0x0 (initial phase) as event that trig OPSTEP 0x1 --> 0x2 */ - WRITE_REG(SAES->CR, AES_CR_KEYSEL_0 | AES_CR_KEYSIZE | AES_CR_CHMOD_0 - | AES_CR_CHMOD_1); + WRITE_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_KEYSEL_0 | AES_CR_KEYSIZE + | AES_CR_CHMOD_0 | AES_CR_CHMOD_1); } else if ((Operation == CCB_ECDSA_SIGN_BLOB_USE) || (Operation == CCB_ECC_SCALAR_MUL_BLOB_USE) || (Operation == CCB_MODULAR_EXP_BLOB_USE)) { /* SAES: GCMPH = 0x0 (initial phase) as event that trig OPSTEP 0x1 --> 0x12 */ - WRITE_REG(SAES->CR, AES_CR_KEYSEL_0 | AES_CR_KEYSIZE | AES_CR_CHMOD_0 - | AES_CR_CHMOD_1 | AES_CR_MODE_1); + WRITE_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_KEYSEL_0 | AES_CR_KEYSIZE + | AES_CR_CHMOD_0 | AES_CR_CHMOD_1 | AES_CR_MODE_1); } else @@ -2251,16 +2576,16 @@ static HAL_StatusTypeDef WrappingKeyConfiguration(CCB_HandleTypeDef *hccb, uint3 || (Operation == CCB_MODULAR_EXP_CPU_BLOB_CREATION)) { /* SAES: GCMPH = 0x0 (initial phase) as event that trig OPSTEP 0x1 --> 0x2 */ - WRITE_REG(SAES->CR, AES_CR_KEYSEL_0 | AES_CR_KEYSIZE | AES_CR_CHMOD_0 - | AES_CR_CHMOD_1); + WRITE_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_KEYSEL_0 | AES_CR_KEYSIZE + | AES_CR_CHMOD_0 | AES_CR_CHMOD_1); } else if ((Operation == CCB_ECDSA_SIGN_BLOB_USE) || (Operation == CCB_ECC_SCALAR_MUL_BLOB_USE) || (Operation == CCB_MODULAR_EXP_BLOB_USE)) { /* SAES: GCMPH = 0x0 (initial phase) as event that trig OPSTEP 0x1 --> 0x12 */ - WRITE_REG(SAES->CR, AES_CR_KEYSEL_0 | AES_CR_KEYSIZE | AES_CR_CHMOD_0 | - AES_CR_CHMOD_1 | AES_CR_MODE_1); + WRITE_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_KEYSEL_0 | AES_CR_KEYSIZE + | AES_CR_CHMOD_0 | AES_CR_CHMOD_1 | AES_CR_MODE_1); } else @@ -2322,11 +2647,13 @@ static HAL_StatusTypeDef Protect_SAES_UnwrapKey(CCB_HandleTypeDef *hccb, const C if (pWrappingKey->AES_Algorithm != CCB_AES_ECB) { - WRITE_REG(SAES->CR, AES_CR_KEYSEL_0 | AES_CR_KMOD_0 | AES_CR_KEYSIZE | AES_CR_CHMOD_0); + WRITE_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_KEYSEL_0 | AES_CR_KMOD_0 + | AES_CR_KEYSIZE | AES_CR_CHMOD_0); } else { - WRITE_REG(SAES->CR, AES_CR_KEYSEL_0 | AES_CR_KMOD_0 | AES_CR_KEYSIZE); + WRITE_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_KEYSEL_0 + | AES_CR_KMOD_0 | AES_CR_KEYSIZE); } /* Wait for Key valid to be set */ @@ -2336,14 +2663,14 @@ static HAL_StatusTypeDef Protect_SAES_UnwrapKey(CCB_HandleTypeDef *hccb, const C } /* Disable the SAES peripheral */ - SAES->CR &= ~AES_CR_EN; + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; /* wait for key valid */ - while (HAL_IS_BIT_CLR(SAES->SR, AES_SR_KEYVALID)) + while (HAL_IS_BIT_CLR(HAL_CCB_GET_SAES_INSTANCE(hccb)->SR, AES_SR_KEYVALID)) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - SAES->CR &= ~AES_CR_EN; + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -2352,13 +2679,13 @@ static HAL_StatusTypeDef Protect_SAES_UnwrapKey(CCB_HandleTypeDef *hccb, const C } /* Set the operating mode*/ - MODIFY_REG(SAES->CR, AES_CR_KMOD, AES_CR_KMOD_0); + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_KMOD, AES_CR_KMOD_0); /* key preparation for decryption, operating mode 2*/ - MODIFY_REG(SAES->CR, AES_CR_MODE, AES_CR_MODE_0); + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_MODE, AES_CR_MODE_0); /* Enable SAES */ - SAES->CR |= AES_CR_EN; + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR |= AES_CR_EN; /* wait CCF in SAES */ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -2367,30 +2694,30 @@ static HAL_StatusTypeDef Protect_SAES_UnwrapKey(CCB_HandleTypeDef *hccb, const C } /* Return to decryption operating mode(Mode 3)*/ - MODIFY_REG(SAES->CR, AES_CR_MODE, AES_CR_MODE_1); + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_MODE, AES_CR_MODE_1); if (pWrappingKey->AES_Algorithm != CCB_AES_ECB) { /* Set the Initialization Vector */ - SAES->IVR3 = *(uint32_t *)(pWrappingKey->pInitVect); - SAES->IVR2 = *(uint32_t *)(pWrappingKey->pInitVect + 1U); - SAES->IVR1 = *(uint32_t *)(pWrappingKey->pInitVect + 2U); - SAES->IVR0 = *(uint32_t *)(pWrappingKey->pInitVect + 3U); + HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR3 = *(uint32_t *)(pWrappingKey->pInitVect); + HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR2 = *(uint32_t *)(pWrappingKey->pInitVect + 1U); + HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR1 = *(uint32_t *)(pWrappingKey->pInitVect + 2U); + HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR0 = *(uint32_t *)(pWrappingKey->pInitVect + 3U); } /* Enable CRYP */ - SAES->CR |= AES_CR_EN; + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR |= AES_CR_EN; /* Set the phase */ while (in_count < 8UL) /* symmetric key size is always 256 */ { /* Write four times to input the key to encrypt */ - SAES->DINR = pWrappingKey->pUserWrappedWrappingKey[in_count]; + HAL_CCB_GET_SAES_INSTANCE(hccb)->DINR = pWrappingKey->pUserWrappedWrappingKey[in_count]; in_count++; - SAES->DINR = pWrappingKey->pUserWrappedWrappingKey[in_count]; + HAL_CCB_GET_SAES_INSTANCE(hccb)->DINR = pWrappingKey->pUserWrappedWrappingKey[in_count]; in_count++; - SAES->DINR = pWrappingKey->pUserWrappedWrappingKey[in_count]; + HAL_CCB_GET_SAES_INSTANCE(hccb)->DINR = pWrappingKey->pUserWrappedWrappingKey[in_count]; in_count++; - SAES->DINR = pWrappingKey->pUserWrappedWrappingKey[in_count]; + HAL_CCB_GET_SAES_INSTANCE(hccb)->DINR = pWrappingKey->pUserWrappedWrappingKey[in_count]; in_count++; /* wait CCF in SAES */ @@ -2401,8 +2728,8 @@ static HAL_StatusTypeDef Protect_SAES_UnwrapKey(CCB_HandleTypeDef *hccb, const C } /* Disable the SAES */ - SAES->CR &= ~AES_CR_EN; - SAES->ICR |= 0x0EUL; + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; + HAL_CCB_GET_SAES_INSTANCE(hccb)->ICR |= 0x0EUL; /* Return function status */ return HAL_OK; @@ -2659,7 +2986,7 @@ static HAL_StatusTypeDef CCB_WrapSymmetricKey(CCB_HandleTypeDef *hccb, const uin } /* Initialize RNG */ - if (CCB_RNG_Init() != HAL_OK) + if (CCB_RNG_Init(hccb) != HAL_OK) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -2669,12 +2996,22 @@ static HAL_StatusTypeDef CCB_WrapSymmetricKey(CCB_HandleTypeDef *hccb, const uin /* Initialize SAES */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* Disable the SAES peripheral clock */ - SAES->CR &= ~AES_CR_EN; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + /* Disable the SAES peripheral */ + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; - /* Set state and return error */ - hccb->State = HAL_CCB_STATE_ERROR; - return HAL_ERROR; + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Update the state */ @@ -2682,12 +3019,14 @@ static HAL_StatusTypeDef CCB_WrapSymmetricKey(CCB_HandleTypeDef *hccb, const uin if (pWrappingKey->AES_Algorithm != CCB_AES_ECB) { - WRITE_REG(SAES->CR, AES_CR_KEYSEL_0 | AES_CR_KMOD_0 | AES_CR_KEYSIZE | AES_CR_CHMOD_0); + WRITE_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_KEYSEL_0 | AES_CR_KMOD_0 \ + | AES_CR_KEYSIZE | AES_CR_CHMOD_0); } else { - WRITE_REG(SAES->CR, AES_CR_KEYSEL_0 | AES_CR_KMOD_0 | AES_CR_KEYSIZE); + WRITE_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_KEYSEL_0 | AES_CR_KMOD_0 \ + | AES_CR_KEYSIZE); } /* Wait for Key valid to be set */ @@ -2697,31 +3036,31 @@ static HAL_StatusTypeDef CCB_WrapSymmetricKey(CCB_HandleTypeDef *hccb, const uin } /* Disable the CRYP peripheral clock */ - SAES->CR &= ~AES_CR_EN; + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; /* Set the operating mode*/ - MODIFY_REG(SAES->CR, AES_CR_KMOD, AES_CR_KMOD_0); + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_KMOD, AES_CR_KMOD_0); /* Encryption operating mode(Mode 0)*/ - MODIFY_REG(SAES->CR, AES_CR_MODE, 0x0UL); /*!< Encryption mode */ + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_MODE, 0x0UL); /*!< Encryption mode */ if (pWrappingKey->AES_Algorithm != CCB_AES_ECB) { /* Set the Initialization Vector */ - SAES->IVR3 = *(uint32_t *)(pWrappingKey->pInitVect); - SAES->IVR2 = *(uint32_t *)(pWrappingKey->pInitVect + 1U); - SAES->IVR1 = *(uint32_t *)(pWrappingKey->pInitVect + 2U); - SAES->IVR0 = *(uint32_t *)(pWrappingKey->pInitVect + 3U); + HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR3 = *(uint32_t *)(pWrappingKey->pInitVect); + HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR2 = *(uint32_t *)(pWrappingKey->pInitVect + 1U); + HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR1 = *(uint32_t *)(pWrappingKey->pInitVect + 2U); + HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR0 = *(uint32_t *)(pWrappingKey->pInitVect + 3U); } /* Enable CRYP */ - SAES->CR |= AES_CR_EN; + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR |= AES_CR_EN; while (cryp_in_count < CCB_SIZE_SKEY_INWORD) { for (i = 0UL; i < 4UL; i++) { - SAES->DINR = pcryp_in_buff[cryp_in_count]; + HAL_CCB_GET_SAES_INSTANCE(hccb)->DINR = pcryp_in_buff[cryp_in_count]; cryp_in_count++; } @@ -2732,13 +3071,13 @@ static HAL_StatusTypeDef CCB_WrapSymmetricKey(CCB_HandleTypeDef *hccb, const uin } /* Clear CCF Flag */ - SET_BIT(SAES->ICR, AES_ICR_CCF); + SET_BIT(HAL_CCB_GET_SAES_INSTANCE(hccb)->ICR, AES_ICR_CCF); /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ for (i = 0UL; i < 4UL; i++) { - pcryp_out_buff[cryp_out_count] = SAES->DOUTR; + pcryp_out_buff[cryp_out_count] = HAL_CCB_GET_SAES_INSTANCE(hccb)->DOUTR; cryp_out_count++; } } @@ -2779,33 +3118,33 @@ static HAL_StatusTypeDef CCB_WrapSymmetricKey(CCB_HandleTypeDef *hccb, const uin static HAL_StatusTypeDef CCB_BlobCreation_InitialPhase(CCB_HandleTypeDef *hccb, uint32_t *pIV) { /* Load IVs from RNG to SAES */ - SAES->IVR0 = CCB_IV0_VALUE; /* SAES_IVR0 that must be equal to 0x2 */ - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR0 = CCB_IV0_VALUE; /* SAES_IVR0 that must be equal to 0x2 */ + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } /* For IV1, IV2 and IV3, random generated values are loaded from RNG to SAES by CCB */ - SAES->IVR1 = CCB_FAKE_VALUE; - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR1 = CCB_FAKE_VALUE; + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } - SAES->IVR2 = CCB_FAKE_VALUE; - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR2 = CCB_FAKE_VALUE; + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } - SAES->IVR3 = CCB_FAKE_VALUE; - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR3 = CCB_FAKE_VALUE; + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } /* if an error occurs, RNGERRF flag is set in PKA */ - if (HAL_CCB_GET_PKA_FLAG(PKA_SR_RNGERRF) == SET) + if (HAL_CCB_GET_PKA_FLAG(hccb, PKA_SR_RNGERRF) == SET) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -2815,14 +3154,14 @@ static HAL_StatusTypeDef CCB_BlobCreation_InitialPhase(CCB_HandleTypeDef *hccb, else { /* Read back IVs from SAES */ - pIV[3] = SAES->IVR3; - pIV[2] = SAES->IVR2; - pIV[1] = SAES->IVR1; - pIV[0] = SAES->IVR0; + pIV[3] = HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR3; + pIV[2] = HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR2; + pIV[1] = HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR1; + pIV[0] = HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR0; } /* Set EN in SAES_CR*/ - SAES->CR |= AES_CR_EN; + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR |= AES_CR_EN; /* Wait until CCF is SET in SAES_ISR (end of GCM init) */ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -2831,7 +3170,7 @@ static HAL_StatusTypeDef CCB_BlobCreation_InitialPhase(CCB_HandleTypeDef *hccb, } /* Set SAES GCMPH Header phase and trig OPSTEP transition 0x2 --> 0x3 */ - MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_0 | AES_CR_EN); + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_GCMPH, AES_CR_GCMPH_0 | AES_CR_EN); /* Return function status */ return HAL_OK; @@ -2849,13 +3188,13 @@ static HAL_StatusTypeDef CCB_BlobUse_InitialPhase(CCB_HandleTypeDef *hccb, const uint16_t count; /* Set IVs from created Blob */ - SAES->IVR0 = pIV[0]; - SAES->IVR1 = pIV[1]; - SAES->IVR2 = pIV[2]; - SAES->IVR3 = pIV[3]; + HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR0 = pIV[0]; + HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR1 = pIV[1]; + HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR2 = pIV[2]; + HAL_CCB_GET_SAES_INSTANCE(hccb)->IVR3 = pIV[3]; /* Set EN in SAES_CR*/ - SAES->CR |= AES_CR_EN; + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR |= AES_CR_EN; /* Wait until CCF is SET in SAES_ISR (end of GCM init) */ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -2870,7 +3209,7 @@ static HAL_StatusTypeDef CCB_BlobUse_InitialPhase(CCB_HandleTypeDef *hccb, const } /* Set SAES GCMPH Header phase and trig OPSTEP transition 0x12 --> 0x13 */ - MODIFY_REG(SAES->CR, AES_CR_GCMPH | AES_CR_EN, + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_GCMPH | AES_CR_EN, AES_CR_GCMPH_0 | AES_CR_EN); /* Return function status */ @@ -2904,7 +3243,7 @@ static HAL_StatusTypeDef CCB_BlobCreation_FinalPhase(CCB_HandleTypeDef *hccb, ui cipherkey_size = operand_size; } /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */ - HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC); + HAL_CCB_CLEAR_PKA_FLAG(hccb, PKA_CLRFR_CMFC); /* Preparing last Block */ if (Operation == CCB_MODULAR_EXP_CPU_BLOB_CREATION) @@ -2938,7 +3277,7 @@ static HAL_StatusTypeDef CCB_BlobCreation_FinalPhase(CCB_HandleTypeDef *hccb, ui for (count = 0; count < CCB_BLOCK_SIZE; count++) { - SAES->DINR = last_block[count]; + HAL_CCB_GET_SAES_INSTANCE(hccb)->DINR = last_block[count]; } /* Wait until CCF flag is SET in SAES */ @@ -2950,7 +3289,7 @@ static HAL_StatusTypeDef CCB_BlobCreation_FinalPhase(CCB_HandleTypeDef *hccb, ui /* Read Authentif Tag */ for (count = 0U; count < CCB_BLOCK_SIZE; count++) { - pTag[count] = SAES->DOUTR; + pTag[count] = HAL_CCB_GET_SAES_INSTANCE(hccb)->DOUTR; } /* Return function status */ @@ -2983,7 +3322,8 @@ static HAL_StatusTypeDef CCB_BlobUse_FinalPhase(CCB_HandleTypeDef *hccb, uint32_ } /* Set SAES GCMPH final phase */ - MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_0 | AES_CR_GCMPH_1); + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_GCMPH, + AES_CR_GCMPH_0 | AES_CR_GCMPH_1); /* Preparing last Block */ if (Operation == CCB_MODULAR_EXP_BLOB_USE) @@ -3017,7 +3357,7 @@ static HAL_StatusTypeDef CCB_BlobUse_FinalPhase(CCB_HandleTypeDef *hccb, uint32_ for (count = 0U; count < CCB_BLOCK_SIZE; count++) { - SAES->DINR = last_block[count]; + HAL_CCB_GET_SAES_INSTANCE(hccb)->DINR = last_block[count]; } /* Wait until CCF flag is SET in SAES */ @@ -3029,7 +3369,7 @@ static HAL_StatusTypeDef CCB_BlobUse_FinalPhase(CCB_HandleTypeDef *hccb, uint32_ /* Read Authentif Tag and check integrity of Blob as event that trig OPSTEP transition 0x17 --> 0x18 */ for (count = 0U; count < CCB_BLOCK_SIZE; count++) { - if ((SAES->DOUTR) != 0UL) + if ((HAL_CCB_GET_SAES_INSTANCE(hccb)->DOUTR) != 0UL) { /* Set state, error code and return error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -3051,13 +3391,16 @@ static HAL_StatusTypeDef CCB_BlobUse_FinalPhase(CCB_HandleTypeDef *hccb, uint32_ * @param pIV pointer to the IV. * @param pTag pointer to the Tag. * @param pWarappedKey pointer to the Warapped Key. + * @param pHash pointer to the Hash. + * @param pSignature pointer to the Signature. * @param CCB_Operation is the CCB Operations. * @retval HAL status. */ static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *pCurveParam, const uint8_t *pClearPrivateKey, CCB_WrappingKeyTypeDef *pWrappingKey, uint32_t *pIV, - uint32_t *pTag, uint32_t *pWarappedKey, uint8_t CCB_Operation) + uint32_t *pTag, uint32_t *pWarappedKey, uint8_t *pHash, + CCB_ECDSASignTypeDef *pSignature, uint8_t CCB_Operation) { uint16_t count; uint32_t countBlock = 0UL; @@ -3076,7 +3419,7 @@ static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB } /* Initialize RNG */ - if (CCB_RNG_Init() != HAL_OK) + if (CCB_RNG_Init(hccb) != HAL_OK) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -3091,15 +3434,37 @@ static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB return HAL_ERROR; } +#if defined (HW_SANITY_CHECK_SUPPORT) + /* Move the input hash value to PKA RAM */ + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_HASH_E], pHash, + pCurveParam->primeOrderSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_SIGN_IN_HASH_E + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); + +#else + /* Prevent unused argument(s) compilation warning */ + UNUSED(pHash); + +#endif /* GENERATOR_HW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ /* Initialize SAES */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* Disable the SAES peripheral clock */ - SAES->CR &= ~AES_CR_EN; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + /* Disable the SAES peripheral */ + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; - /* Set state and return error */ - hccb->State = HAL_CCB_STATE_ERROR; - return HAL_ERROR; + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Update the state */ @@ -3156,7 +3521,7 @@ static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB } /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x3 --> 0x4 */ - MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_1); + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_GCMPH, AES_CR_GCMPH_1); if (CCB_Operation == CCB_ECDSA_SIGN_CPU_BLOB_CREATION) { @@ -3168,31 +3533,31 @@ static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB } /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */ - HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC); + HAL_CCB_CLEAR_PKA_FLAG(hccb, PKA_CLRFR_CMFC); /* Write private Key d by CPU (user key) */ if ((pCurveParam->modulusSizeByte % 8UL) != 0UL) { for (offset = 0UL; offset < (operand_size - 4UL); offset += 2UL) { - CCB_Memcpy_u8_to_u64(&PKA->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset], + CCB_Memcpy_u8_to_u64(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset], &pClearPrivateKey[(pCurveParam->modulusSizeByte) - ((offset * 4UL) + 1UL)]); } - CCB_Memcpy_Not_Align(&PKA->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset], + CCB_Memcpy_Not_Align(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset], &pClearPrivateKey[(pCurveParam->modulusSizeByte) - ((offset * 4UL) + 1UL)], pCurveParam->modulusSizeByte % 8UL); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset + 2UL); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset + 2UL); } else { for (offset = 0UL; offset < (operand_size - 2UL); offset += 2UL) { - CCB_Memcpy_u8_to_u64(&PKA->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset], + CCB_Memcpy_u8_to_u64(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset], &pClearPrivateKey[(pCurveParam->modulusSizeByte) - ((offset * 4UL) + 1UL)]); } - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset); } /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x4 --> 0x8 */ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_DATAOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -3211,25 +3576,25 @@ static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB } /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */ - HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC); + HAL_CCB_CLEAR_PKA_FLAG(hccb, PKA_CLRFR_CMFC); /* Write private d Key from RNG */ for (offset = 0UL; offset < (operand_size - 2UL); offset++) { - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { /* return error */ return HAL_ERROR; } - PKA->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset] = CCB_FAKE_VALUE; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset] = CCB_FAKE_VALUE; } - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset); /* Check RNG Error Flag in PKA */ - if (HAL_CCB_GET_PKA_FLAG(PKA_SR_RNGERRF) != RESET) + if (HAL_CCB_GET_PKA_FLAG(hccb, PKA_SR_RNGERRF) != RESET) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -3256,12 +3621,12 @@ static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB } /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */ - HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC); + HAL_CCB_CLEAR_PKA_FLAG(hccb, PKA_CLRFR_CMFC); /* Read clear-text private key d for encryption */ for (offset = 0; offset < cipherkey_size; offset++) { - PKA->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset] = CCB_MAGIC_VALUE; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset] = CCB_MAGIC_VALUE; if ((offset % 4UL) == 3UL) { @@ -3276,7 +3641,7 @@ static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB for (count = 0U; count < CCB_BLOCK_SIZE; count++) { pWarappedKey[cipherkey_size - (countBlock + count + 1UL)] - = READ_REG(SAES->DOUTR); + = READ_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->DOUTR); } countBlock += 4UL; } @@ -3285,12 +3650,21 @@ static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB /* Wait for Galois Filter End of Computation */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* return error */ - return HAL_ERROR; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } if ((operand_size % 4UL) != 0UL) { - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + cipherkey_size); } /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x08 --> 0x09 */ @@ -3299,9 +3673,35 @@ static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB /* return error */ return HAL_ERROR; } +#if defined (HW_SANITY_CHECK_SUPPORT) + /* Wait until OPSTEP is set to 0x9 */ + if (CCB_WaitOperStep(hccb, 0x09, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + /* return error */ + return HAL_ERROR; + } + /* Write random k */ + for (offset = 0U; offset < (operand_size - 2U); offset++) + { + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + /* return error */ + return HAL_ERROR; + } + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_K + offset] = CCB_MAGIC_VALUE; + } + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_ECDSA_SIGN_IN_K + offset); + /* Wait for PKA RNGOK flag : GCMPH = 0x3 (final phase) as events that trig OPSTEP transition 0x09 --> 0x0A */ + if (Protect_PKA_WaitFLAG(hccb, PKA_SR_RNGOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + /* return error */ + return HAL_ERROR; + } +#endif /* GENERATOR_HW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ /* Set SAES GCMPH final phase */ - MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_0 | AES_CR_GCMPH_1); + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_GCMPH, + AES_CR_GCMPH_0 | AES_CR_GCMPH_1); /* Wait until OPSTEP is set to 0x0A */ if (CCB_WaitOperStep(hccb, 0x0A, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -3318,7 +3718,46 @@ static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB return HAL_ERROR; } +#if defined (HW_SANITY_CHECK_SUPPORT) + /* SET PKA START operation bit and trig OPSTEP transition 0x0A --> 0x19 */ + SET_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_START); + /* Wait until OPSTEP is set to 0x19 */ + if (CCB_WaitOperStep(hccb, 0x19, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + /* return error */ + return HAL_ERROR; + } + /* Wait until end of operation flag is SET in PKA and trig OPSTEP transition 0x19 --> 0x1A */ + if (Protect_PKA_WaitFLAG(hccb, PKA_SR_PROCENDF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + /* return error */ + return HAL_ERROR; + } + /* Wait until OPSTEP is set to 0x1A */ + if (CCB_WaitOperStep(hccb, 0x1A, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + /* return error */ + return HAL_ERROR; + } + /* Check PKA Operation error result */ + if ((HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_OUT_ERROR]) != CCB_PKA_ERROR_OPERATION_NONE) + { + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + /* Read r part signature */ + CCB_Memcpy_u32_to_u8(pSignature->pRSign, &HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], + pCurveParam->modulusSizeByte); + /* Read s part signature */ + CCB_Memcpy_u32_to_u8(pSignature->pSSign, &HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], + pCurveParam->modulusSizeByte); + +#else + /* Prevent unused argument(s) compilation warning */ + UNUSED(pSignature); +#endif /* GENERATOR_HW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ /* CCB IPRST set */ SET_BIT(hccb->Instance->CR, CCB_CR_IPRST); @@ -3349,6 +3788,7 @@ static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB * @param pIV pointer to the IV. * @param pTag pointer to the Tag. * @param pWarappedKey pointer to the Warapped Key. + * @param PublicKey is table of two coordinates X and Y of the publicKey. * @param CCB_Operation is the CCB Operations. * @retval HAL status. */ @@ -3357,7 +3797,7 @@ static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb, const uint8_t *pClearPrivateKey, CCB_WrappingKeyTypeDef *pWrappingKey, uint32_t *pIV, uint32_t *pTag, uint32_t *pWarappedKey, - uint8_t CCB_Operation) + uint32_t PublicKey[2U][20U], uint8_t CCB_Operation) { uint16_t count; uint32_t countBlock = 0UL; @@ -3378,7 +3818,7 @@ static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb, } /* Initialize RNG */ - if (CCB_RNG_Init() != HAL_OK) + if (CCB_RNG_Init(hccb) != HAL_OK) { /* return state and error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -3393,15 +3833,38 @@ static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb, return HAL_ERROR; } +#if defined (HW_SANITY_CHECK_SUPPORT) + /* Write point G coordinate */ + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ], + pCurveParam->pPointX, pCurveParam->primeOrderSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); + + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ], + pCurveParam->pPointY, pCurveParam->primeOrderSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); + +#endif /* GENERATOR_HW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ /* Initialize SAES */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* Disable the SAES peripheral clock */ - SAES->CR &= ~AES_CR_EN; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + /* Disable the SAES peripheral */ + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; - /* Set state and return error */ - hccb->State = HAL_CCB_STATE_ERROR; - return HAL_ERROR; + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Update the state */ @@ -3457,7 +3920,7 @@ static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb, } /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x3 --> 0x4 */ - MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_1); + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_GCMPH, AES_CR_GCMPH_1); /* Wait until OPSTEP is set to 0x04 */ if (CCB_WaitOperStep(hccb, 0x04, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -3467,7 +3930,7 @@ static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb, } /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */ - HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC); + HAL_CCB_CLEAR_PKA_FLAG(hccb, PKA_CLRFR_CMFC); if (CCB_Operation == CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION) { @@ -3477,24 +3940,24 @@ static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb, { for (offset = 0UL; offset < (operand_size - 4UL); offset += 2UL) { - CCB_Memcpy_u8_to_u64(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_K + offset], + CCB_Memcpy_u8_to_u64(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_K + offset], &pClearPrivateKey[(pCurveParam->modulusSizeByte) - ((offset * 4UL) + 1UL)]); } - CCB_Memcpy_Not_Align(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_K + offset], + CCB_Memcpy_Not_Align(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_K + offset], &pClearPrivateKey[(pCurveParam->modulusSizeByte) - ((offset * 4UL) + 1UL)], pCurveParam->modulusSizeByte % 8UL); - RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_K + offset + 2UL); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_ECC_SCALAR_MUL_IN_K + offset + 2UL); } else { for (offset = 0UL; offset < (operand_size - 2UL); offset += 2UL) { - CCB_Memcpy_u8_to_u64(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_K + offset], + CCB_Memcpy_u8_to_u64(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_K + offset], &pClearPrivateKey[(pCurveParam->modulusSizeByte) - ((offset * 4UL) + 1UL)]); } - RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_K + offset); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_ECC_SCALAR_MUL_IN_K + offset); } /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x4 --> 0x8 */ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_DATAOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -3508,17 +3971,17 @@ static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb, /* Write scalar k when RNG */ for (offset = 0UL; offset < (operand_size - 2UL); offset++) { - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { /* return error */ return HAL_ERROR; } - PKA->RAM[PKA_ECC_SCALAR_MUL_IN_K + offset] = CCB_FAKE_VALUE; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_K + offset] = CCB_FAKE_VALUE; } - RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_K + offset); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_ECC_SCALAR_MUL_IN_K + offset); /* PKA: Check RNG Error Flag */ - if (HAL_CCB_GET_PKA_FLAG(PKA_SR_RNGERRF) != RESET) + if (HAL_CCB_GET_PKA_FLAG(hccb, PKA_SR_RNGERRF) != RESET) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -3545,13 +4008,13 @@ static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb, } /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */ - HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC); + HAL_CCB_CLEAR_PKA_FLAG(hccb, PKA_CLRFR_CMFC); /* Read clear-text scalar K for encryption */ for (offset = 0; offset < cipherkey_size; offset++) { - PKA->RAM[PKA_ECC_SCALAR_MUL_IN_K + offset] = CCB_MAGIC_VALUE; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_K + offset] = CCB_MAGIC_VALUE; if ((offset % 4UL) == 3UL) { @@ -3566,7 +4029,7 @@ static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb, for (count = 0U; count < CCB_BLOCK_SIZE; count++) { pWarappedKey[cipherkey_size - (countBlock + count + 1U)] - = READ_REG(SAES->DOUTR); + = READ_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->DOUTR); } countBlock += 4UL; } @@ -3575,13 +4038,22 @@ static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb, /* Wait for Galois Filter End of Computation */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* return error */ - return HAL_ERROR; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } if ((operand_size % 4UL) != 0UL) { - RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_K + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_ECC_SCALAR_MUL_IN_K + cipherkey_size); } @@ -3593,7 +4065,8 @@ static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb, } /* Set SAES GCMPH final phase */ - MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_0 | AES_CR_GCMPH_1); + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_GCMPH, + AES_CR_GCMPH_0 | AES_CR_GCMPH_1); /* Wait until OPSTEP is set to 0x0A */ if (CCB_WaitOperStep(hccb, 0x0A, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -3610,7 +4083,45 @@ static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb, return HAL_ERROR; } +#if defined (HW_SANITY_CHECK_SUPPORT) + /* SET PKA START operation bit and trig OPSTEP transition 0x0A --> 0x19 */ + SET_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_START); + /* Wait until OPSTEP is set to 0x19 */ + if (CCB_WaitOperStep(hccb, 0x19, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + /* return error */ + return HAL_ERROR; + } + /* Wait until end of operation flag is SET in PKA and trig OPSTEP transition 0x19 --> 0x1A */ + if (Protect_PKA_WaitFLAG(hccb, PKA_SR_PROCENDF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + /* return error */ + return HAL_ERROR; + } + /* Wait until OPSTEP is set to 0x1A */ + if (CCB_WaitOperStep(hccb, 0x1A, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + /* return error */ + return HAL_ERROR; + } + /* Check PKA Operation error result */ + if ((HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_OUT_ERROR]) != CCB_PKA_ERROR_OPERATION_NONE) + { + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + /* Move the result from appropriate location */ + CCB_Memcpy_u32_to_u32(PublicKey[0], &HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X], + ((pCurveParam->modulusSizeByte + 3) / 4)); + CCB_Memcpy_u32_to_u32(PublicKey[1], &HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y], + ((pCurveParam->modulusSizeByte + 3) / 4)); + +#else + /* Prevent unused argument(s) compilation warning */ + UNUSED(PublicKey); +#endif /* GENERATOR_HW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ /* CCB IPRST set */ SET_BIT(hccb->Instance->CR, CCB_CR_IPRST); @@ -3683,14 +4194,14 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E } /* Initialize RNG */ - if (CCB_RNG_Init() != HAL_OK) + if (CCB_RNG_Init(hccb) != HAL_OK) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; return HAL_ERROR; } - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } @@ -3699,7 +4210,7 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E while (random1 == 0U) { - random1 = (uint16_t)(RNG->DR & 0x3FFU); + random1 = (uint16_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0x3FFU); if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* Set state and return error */ @@ -3707,7 +4218,7 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E } } - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } @@ -3716,7 +4227,7 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E while (random2 == 0U) { - random2 = (uint16_t)(RNG->DR & 0x3FFU); + random2 = (uint16_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0x3FFU); if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* Set state and return error */ @@ -3724,7 +4235,7 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E } } - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } @@ -3733,7 +4244,7 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E while (random3 == 0U) { - random3 = (uint16_t)(RNG->DR & 0x3FFU); + random3 = (uint16_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0x3FFU); if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* Set state and return error */ @@ -3753,22 +4264,26 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E if (VerifOperation == CCB_VERIF_OPERATION_DISABLED) { /* Write Customized point coordinate */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ], pInputPoint->pPointX, - pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ], pInputPoint->pPointY, - pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ], + pInputPoint->pPointX, pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ], + pInputPoint->pPointY, pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); } else if (VerifOperation == CCB_VERIF_OPERATION_ENABLED) { /* Write point G coordinate */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ], pCurveParam->pPointX, - pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ], pCurveParam->pPointY, - pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ], + pCurveParam->pPointX, pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ], + pCurveParam->pPointY, pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); } else { @@ -3778,12 +4293,22 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E /* Initialize SAES */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* Disable the SAES peripheral */ - SAES->CR &= ~AES_CR_EN; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + /* Disable the SAES peripheral */ + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; - /* Set state and return error */ - hccb->State = HAL_CCB_STATE_ERROR; - return HAL_ERROR; + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Update the state */ @@ -3852,7 +4377,7 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E } /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x13 --> 0x14 */ - MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_1); + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_GCMPH, AES_CR_GCMPH_1); /* Wait until OPSTEP is set to 0x14 */ if (CCB_WaitOperStep(hccb, 0x14, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -3864,7 +4389,7 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E for (offset = 0UL; offset < cipherkey_size; offset++) { /* Write Wrapped scalar k in PKA RAM */ - WRITE_REG(SAES->DINR, pWarappedKey[cipherkey_size - (offset + 1UL)]); + WRITE_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->DINR, pWarappedKey[cipherkey_size - (offset + 1UL)]); if ((offset % 4UL) == 0x3UL) { @@ -3878,14 +4403,14 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E /* Write Unrapped scalar k in PKA RAM */ for (count_ram = 0U; count_ram < 4U; count_ram++) { - PKA->RAM[PKA_ECDSA_SIGN_IN_K + (count_block + count_ram)] = CCB_MAGIC_VALUE; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_K + (count_block + count_ram)] = CCB_MAGIC_VALUE; } count_block += 4UL; } } if ((operand_size % 4UL) != 0UL) { - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_K + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_ECDSA_SIGN_IN_K + cipherkey_size); } @@ -3922,7 +4447,7 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E } /* SET PKA START operation bit and trig OPSTEP transition 0x18 --> 0x19 */ - SET_BIT(PKA->CR, PKA_CR_START); + SET_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_START); /* Wait until OPSTEP is set to 0x19 */ if (CCB_WaitOperStep(hccb, 0x19, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -3946,7 +4471,7 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E } /* Check PKA Operation error result */ - if ((PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_ERROR]) != CCB_PKA_ERROR_OPERATION_NONE) + if ((HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_OUT_ERROR]) != CCB_PKA_ERROR_OPERATION_NONE) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -3956,21 +4481,25 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E if (VerifOperation == CCB_VERIF_OPERATION_DISABLED) { /* P coordinate x */ - CCB_Memcpy_u32_to_u8(pOutputPoint->pPointX, &PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X], + CCB_Memcpy_u32_to_u8(pOutputPoint->pPointX, + &HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X], pCurveParam->modulusSizeByte); /* P coordinate y */ - CCB_Memcpy_u32_to_u8(pOutputPoint->pPointY, &PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y], + CCB_Memcpy_u32_to_u8(pOutputPoint->pPointY, + &HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y], pCurveParam->modulusSizeByte); } else if (VerifOperation == CCB_COMPUTE_PUBLIC_KEY) { /* P coordinate x */ - CCB_Memcpy_u32_to_u8(pOutputPoint->pPointX, &PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X], + CCB_Memcpy_u32_to_u8(pOutputPoint->pPointX, + &HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X], pCurveParam->modulusSizeByte); /* P coordinate y */ - CCB_Memcpy_u32_to_u8(pOutputPoint->pPointY, &PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y], + CCB_Memcpy_u32_to_u8(pOutputPoint->pPointY, + &HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y], pCurveParam->modulusSizeByte); } else /* (VerifOperation == CCB_VERIF_OPERATION_ENABLED) */ @@ -3985,7 +4514,7 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E for (offset = 0UL; offset < ((pCurveParam->modulusSizeByte + 3UL) / 4UL); offset++) { /* Check public key coordinate x and improve robustness against intrusion (intentional) */ - if (((PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + offset] != pPublicKey[offset]) || + if (((HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + offset] != pPublicKey[offset]) || (f_count != random1) || (f_count == 0U))) { /* Set state, and intrusion error */ @@ -3999,8 +4528,8 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E for (offset = 0UL; offset < ((pCurveParam->modulusSizeByte + 3UL) / 4UL); offset++) { /* Check public key coordinate y and improve robustness against intrusion (intentional) */ - if (((PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + offset] != pPublicKey[offset + 20U]) || - (f_count != random1) || (f_count == 0U))) + if (((HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + offset] + != pPublicKey[offset + 20U]) || (f_count != random1) || (f_count == 0U))) { /* Set state, and intrusion error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -4018,7 +4547,7 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E for (offset = 0UL; offset < ((pCurveParam->modulusSizeByte + 3UL) / 4UL); offset++) { /* Check public key coordinate x and improve robustness against intrusion (intentional) */ - if (((PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + offset] != pPublicKey[offset]) || + if (((HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + offset] != pPublicKey[offset]) || (f_count != random2) || (f_count == 0U))) { /* Set state, and intrusion error */ @@ -4032,8 +4561,8 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E for (offset = 0UL; offset < ((pCurveParam->modulusSizeByte + 3UL) / 4UL); offset++) { /* Check public key coordinate y and improve robustness against intrusion (intentional) */ - if (((PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + offset] != pPublicKey[offset + 20U]) || - (f_count != random2) || (f_count == 0U))) + if (((HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + offset] != + pPublicKey[offset + 20U]) || (f_count != random2) || (f_count == 0U))) { /* Set state, and intrusion error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -4051,7 +4580,7 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E for (offset = 0UL; offset < ((pCurveParam->modulusSizeByte + 3UL) / 4UL); offset++) { /* Check public key coordinate x and improve robustness against intrusion (intentional) */ - if (((PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + offset] != pPublicKey[offset]) || + if (((HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + offset] != pPublicKey[offset]) || (f_count != random3) || (f_count == 0U))) { /* Set state, and intrusion error */ @@ -4065,8 +4594,8 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E for (offset = 0UL; offset < ((pCurveParam->modulusSizeByte + 3UL) / 4UL); offset++) { /* Check public key coordinate y and improve robustness against intrusion (intentional) */ - if (((PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + offset] != pPublicKey[offset + 20U]) || - (f_count != random3) || (f_count == 0U))) + if (((HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + offset] != + pPublicKey[offset + 20U]) || (f_count != random3) || (f_count == 0U))) { /* Set state, and intrusion error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -4104,12 +4633,15 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E * @param pTag pointer to the Tag. * @param pWrappedExp pointer to the Warapped Exp. * @param pWrappedPhi pointer to the Warapped Phi. + * @param pOperand pointer to the constant K as operand A. + * @param pReferenceModularExp pointer to the output ReferenceModularExp. * @retval HAL status. */ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RSAParamTypeDef *pParam, const CCB_RSAClearKeyTypeDef *pRSAClearPrivateKey, CCB_WrappingKeyTypeDef *pWrappingKey, uint32_t *pIV, - uint32_t *pTag, uint32_t *pWrappedExp, uint32_t *pWrappedPhi) + uint32_t *pTag, uint32_t *pWrappedExp, uint32_t *pWrappedPhi, + uint8_t *pOperand, uint32_t *pReferenceModularExp) { uint16_t count; uint32_t countBlock = 0UL; @@ -4128,7 +4660,7 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS } /* Initialize RNG */ - if (CCB_RNG_Init() != HAL_OK) + if (CCB_RNG_Init(hccb) != HAL_OK) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -4143,15 +4675,37 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS return HAL_ERROR; } +#if defined (HW_SANITY_CHECK_SUPPORT) + /* Write a constant K as operand A (base of exponentiation) in the PKA RAM */ + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ], pOperand, + pParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + ((pParam->modulusSizeByte + 3UL))); + +#else + /* Prevent unused argument(s) compilation warning */ + UNUSED(pOperand); + +#endif /* GENERATOR_SW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ /* Initialize SAES */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* Disable the SAES peripheral clock */ - SAES->CR &= ~AES_CR_EN; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + /* Disable the SAES peripheral */ + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; - /* Set state, error code and return error */ - hccb->State = HAL_CCB_STATE_ERROR; - return HAL_ERROR; + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Update the state */ @@ -4207,7 +4761,7 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS } /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x3 --> 0x4 */ - MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_1); + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_GCMPH, AES_CR_GCMPH_1); /* Wait until OPSTEP is set to 0x04 */ if (CCB_WaitOperStep(hccb, 0x04, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -4217,31 +4771,31 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS } /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */ - HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC); + HAL_CCB_CLEAR_PKA_FLAG(hccb, PKA_CLRFR_CMFC); /* Write clear-text exponent e */ if ((pParam->modulusSizeByte % 8UL) != 0UL) { for (offset = 0UL; offset < (operand_size - 4UL); offset += 2UL) { - CCB_Memcpy_u8_to_u64(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + offset], + CCB_Memcpy_u8_to_u64(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + offset], &pRSAClearPrivateKey->pExp[(pParam->modulusSizeByte) - ((offset * 4UL) + 1UL)]); } - CCB_Memcpy_Not_Align(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + offset], + CCB_Memcpy_Not_Align(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + offset], &pRSAClearPrivateKey->pExp[(pParam->modulusSizeByte) - ((offset * 4UL) + 1UL)], pParam->modulusSizeByte % 8UL); - RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + offset + 2UL); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + offset + 2UL); } else { for (offset = 0; offset < (operand_size - 2UL); offset += 2UL) { - CCB_Memcpy_u8_to_u64(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + offset], + CCB_Memcpy_u8_to_u64(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + offset], &pRSAClearPrivateKey->pExp[(pParam->modulusSizeByte) - ((offset * 4UL) + 1UL)]); } - RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + offset); } @@ -4261,31 +4815,31 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS } /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */ - HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC); + HAL_CCB_CLEAR_PKA_FLAG(hccb, PKA_CLRFR_CMFC); /* Write clear-text phi */ if ((pParam->modulusSizeByte % 8UL) != 0UL) { for (offset = 0; offset < (operand_size - 4UL); offset += 2UL) { - CCB_Memcpy_u8_to_u64(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI + offset], + CCB_Memcpy_u8_to_u64(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI + offset], &pRSAClearPrivateKey->pPhi[(pParam->modulusSizeByte) - ((offset * 4UL) + 1UL)]); } - CCB_Memcpy_Not_Align(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI + offset], + CCB_Memcpy_Not_Align(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI + offset], &pRSAClearPrivateKey->pPhi[(pParam->modulusSizeByte) - ((offset * 4UL) + 1UL)], pParam->modulusSizeByte % 8UL); - RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + offset + 2UL); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + offset + 2UL); } else { for (offset = 0; offset < (operand_size - 2UL); offset += 2UL) { - CCB_Memcpy_u8_to_u64(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI + offset], + CCB_Memcpy_u8_to_u64(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI + offset], &pRSAClearPrivateKey->pPhi[(pParam->modulusSizeByte) - ((offset * 4UL) + 1UL)]); } - RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + offset); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + offset); } /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x5 --> 0x8: */ @@ -4303,13 +4857,13 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS } /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */ - HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC); + HAL_CCB_CLEAR_PKA_FLAG(hccb, PKA_CLRFR_CMFC); /* Read clear exponent e for encryption */ for (offset = 0UL; offset < cipherkey_size; offset++) { - PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + offset] = CCB_MAGIC_VALUE; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + offset] = CCB_MAGIC_VALUE; if ((offset % 4UL) == 3UL) { @@ -4324,7 +4878,7 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS for (count = 0U; count < CCB_BLOCK_SIZE; count++) { pWrappedExp[cipherkey_size - (countBlock + count + 1UL)] - = READ_REG(SAES->DOUTR); + = READ_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->DOUTR); } countBlock += 4UL; } @@ -4333,13 +4887,22 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS /* Wait for Galois Filter End of Computation */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* return error */ - return HAL_ERROR; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } if ((operand_size % 4UL) != 0UL) { - RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + cipherkey_size); } @@ -4358,7 +4921,7 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS } /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */ - HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC); + HAL_CCB_CLEAR_PKA_FLAG(hccb, PKA_CLRFR_CMFC); countBlock = 0U; @@ -4366,7 +4929,7 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS for (offset = 0; offset < cipherkey_size; offset++) { - PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI + offset] = CCB_MAGIC_VALUE; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI + offset] = CCB_MAGIC_VALUE; if ((offset % 4UL) == 3UL) { @@ -4381,7 +4944,7 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS for (count = 0U; count < CCB_BLOCK_SIZE; count++) { pWrappedPhi[cipherkey_size - (countBlock + count + 1UL)] - = READ_REG(SAES->DOUTR); + = READ_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->DOUTR); } countBlock += 4UL; } @@ -4390,13 +4953,22 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS /* Wait for Galois Filter End of Computation */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* return error */ - return HAL_ERROR; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } if ((operand_size % 4UL) != 0UL) { - RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + cipherkey_size); } @@ -4408,7 +4980,8 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS } /* Set SAES GCMPH final phase */ - MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_0 | AES_CR_GCMPH_1); + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_GCMPH, + AES_CR_GCMPH_0 | AES_CR_GCMPH_1); /* Wait until OPSTEP is set to 0x0A */ if (CCB_WaitOperStep(hccb, 0x0A, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -4425,6 +4998,45 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS return HAL_ERROR; } +#if defined (HW_SANITY_CHECK_SUPPORT) + /* SET PKA START operation bit and trig OPSTEP transition 0x0A --> 0x19 */ + SET_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_START); + /* Wait until OPSTEP is set to 0x19 */ + if (CCB_WaitOperStep(hccb, 0x19, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + /* return error */ + return HAL_ERROR; + } + /* Wait until end of operation flag is SET in PKA and trig OPSTEP transition 0x19 --> 0x1A */ + if (Protect_PKA_WaitFLAG(hccb, PKA_SR_PROCENDF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + /* return error */ + return HAL_ERROR; + } + /* Wait until OPSTEP is set to 0x1A */ + if (CCB_WaitOperStep(hccb, 0x1A, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + /* return error */ + return HAL_ERROR; + } + /* Check PKA Operation error result */ + if ((HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_OUT_ERROR]) != CCB_PKA_ERROR_OPERATION_NONE) + { + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + /* Read result output */ + for (offset = 0U; offset < (pParam->modulusSizeByte + 3) / 4; offset++) + { + pReferenceModularExp[offset] = HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_OUT_RESULT + offset]; + } + +#else + /* Prevent unused argument(s) compilation warning */ + UNUSED(pReferenceModularExp); + +#endif /* GENERATOR_HW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ /* CCB IPRST set */ SET_BIT(hccb->Instance->CR, CCB_CR_IPRST); @@ -4487,14 +5099,14 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ } /* Initialize RNG */ - if (CCB_RNG_Init() != HAL_OK) + if (CCB_RNG_Init(hccb) != HAL_OK) { /* Set State and return error */ hccb->State = HAL_CCB_STATE_ERROR; return HAL_ERROR; } - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } @@ -4503,7 +5115,7 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ while (random1 == 0U) { - random1 = (uint16_t)(RNG->DR & 0x3FFU); + random1 = (uint16_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0x3FFU); if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* Set state and return error */ @@ -4511,7 +5123,7 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ } } - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } @@ -4520,7 +5132,7 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ while (random2 == 0U) { - random2 = (uint16_t)(RNG->DR & 0x3FFU); + random2 = (uint16_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0x3FFU); if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* Set state and return error */ @@ -4528,7 +5140,7 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ } } - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } @@ -4537,7 +5149,7 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ while (random3 == 0U) { - random3 = (uint16_t)(RNG->DR & 0x3FFU); + random3 = (uint16_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0x3FFU); if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* Set state and return error */ @@ -4556,12 +5168,22 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ /* Initialize SAES */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* Disable the SAES peripheral */ - SAES->CR &= ~AES_CR_EN; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + /* Disable the SAES peripheral */ + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; - /* Set state and return error */ - hccb->State = HAL_CCB_STATE_ERROR; - return HAL_ERROR; + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Update the state */ @@ -4598,8 +5220,10 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ } /* Set Operand A - base of exponentiation */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ], pOperand, pParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + ((pParam->modulusSizeByte + 3UL))); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ], pOperand, + pParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + ((pParam->modulusSizeByte + 3UL))); /* Initial Phase Processing */ if (CCB_BlobUse_InitialPhase(hccb, pIV, pTag) != HAL_OK) @@ -4623,7 +5247,7 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ } /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x13 --> 0x14 */ - MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_1); + MODIFY_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->CR, AES_CR_GCMPH, AES_CR_GCMPH_1); /* Wait until OPSTEP is set to 0x14 */ if (CCB_WaitOperStep(hccb, 0x14, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -4635,7 +5259,7 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ /* Write encrypted exponent e in DINR of SAES */ for (offset = 0UL; offset < cipherkey_size; offset++) { - WRITE_REG(SAES->DINR, pWrappedExp[cipherkey_size - (offset + 1U)]); + WRITE_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->DINR, pWrappedExp[cipherkey_size - (offset + 1U)]); if ((offset % 4UL) == 0x3UL) { @@ -4649,7 +5273,8 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ /* Write key in PKA RAM */ for (count_ram = 0U; count_ram < 4U; count_ram++) { - PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + (count_block + count_ram)] = CCB_MAGIC_VALUE; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + + (count_block + count_ram)] = CCB_MAGIC_VALUE; } count_block += 4UL; } @@ -4657,7 +5282,7 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ if ((operand_size % 4UL) != 0UL) { - RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + cipherkey_size); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + cipherkey_size); } /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x14 --> 0x15 */ @@ -4674,14 +5299,14 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ } /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */ - HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC); + HAL_CCB_CLEAR_PKA_FLAG(hccb, PKA_CLRFR_CMFC); count_block = 0UL; /* Write encrypted phi in DINR of SAES */ for (offset = 0UL; offset < cipherkey_size; offset++) { - WRITE_REG(SAES->DINR, pWrappedPhi[cipherkey_size - (offset + 1UL)]); + WRITE_REG(HAL_CCB_GET_SAES_INSTANCE(hccb)->DINR, pWrappedPhi[cipherkey_size - (offset + 1UL)]); if ((offset % 4UL) == 0x3UL) { @@ -4695,7 +5320,8 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ /* Write key in PKA RAM */ for (count_ram = 0U; count_ram < 4U; count_ram++) { - PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI + (count_block + count_ram)] = CCB_MAGIC_VALUE; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI + + (count_block + count_ram)] = CCB_MAGIC_VALUE; } count_block += 4UL; } @@ -4703,7 +5329,7 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ if ((operand_size % 4UL) != 0UL) { - RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + cipherkey_size); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + cipherkey_size); } /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x15 --> 0x17 */ @@ -4735,7 +5361,7 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ } /* SET PKA START operation bit and trig OPSTEP transition 0x18 --> 0x19 */ - SET_BIT(PKA->CR, PKA_CR_START); + SET_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_START); /* Wait until OPSTEP is set to 0x19 */ if (CCB_WaitOperStep(hccb, 0x19, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) @@ -4759,7 +5385,7 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ } /* Check PKA Operation error result */ - if ((PKA->RAM[PKA_MODULAR_EXP_OUT_ERROR]) != CCB_PKA_ERROR_OPERATION_NONE) + if ((HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_OUT_ERROR]) != CCB_PKA_ERROR_OPERATION_NONE) { /* Set state and return error */ hccb->State = HAL_CCB_STATE_ERROR; @@ -4769,7 +5395,8 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ if (VerifOperation == CCB_VERIF_OPERATION_DISABLED) { /* Read result output */ - CCB_Memcpy_u32_to_u8(pModularExp, &PKA->RAM[PKA_MODULAR_EXP_OUT_RESULT], pParam->modulusSizeByte); + CCB_Memcpy_u32_to_u8(pModularExp, &HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_OUT_RESULT], + pParam->modulusSizeByte); } else /* CCB_VERIF_OPERATION_ENABLED */ { @@ -4782,7 +5409,8 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ for (offset = 0UL; offset < ((pParam->modulusSizeByte + 3UL) / 4UL); offset++) { /* Check Modular Exponentiation and improve robustness against intrusion (intentional) */ - if (((PKA->RAM[PKA_MODULAR_EXP_OUT_RESULT + offset] != pReferenceModularExp[offset]) || (f_count != random1) || + if (((HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_OUT_RESULT + offset] != pReferenceModularExp[offset]) + || (f_count != random1) || (f_count == 0U))) { /* Set state, and intrusion error */ @@ -4801,7 +5429,8 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ for (offset = 0UL; offset < ((pParam->modulusSizeByte + 3UL) / 4UL); offset++) { /* Check Modular Exponentiation and improve robustness against intrusion (intentional) */ - if (((PKA->RAM[PKA_MODULAR_EXP_OUT_RESULT + offset] != pReferenceModularExp[offset]) || (f_count != random2) || + if (((HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_OUT_RESULT + offset] != pReferenceModularExp[offset]) + || (f_count != random2) || (f_count == 0U))) { /* Set state, and intrusion error */ @@ -4819,7 +5448,8 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ for (offset = 0UL; offset < ((pParam->modulusSizeByte + 3UL) / 4UL); offset++) { /* Check Modular Exponentiation and improve robustness against intrusion (intentional) */ - if (((PKA->RAM[PKA_MODULAR_EXP_OUT_RESULT + offset] != pReferenceModularExp[offset]) || (f_count != random3) || + if (((HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_OUT_RESULT + offset] != pReferenceModularExp[offset]) + || (f_count != random3) || (f_count == 0U))) { /* Set state, and intrusion error */ @@ -4848,32 +5478,34 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ return HAL_OK; } +#if defined(SW_SANITY_CHECK_SUPPORT) /** * @brief Erase the PKA RAM. + * @param hccb CCB handle. * @retval HAL status. */ -static HAL_StatusTypeDef PKA_RAM_Erase(void) +static HAL_StatusTypeDef PKA_RAM_Erase(CCB_HandleTypeDef *hccb) { uint32_t index; __IO uint8_t random_nbr = 0U; uint32_t tickstart; - PKA->RAM[CCB_PKA_RAM_SIZE - 1U] = CCB_MAGIC_VALUE; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[CCB_PKA_RAM_SIZE - 1U] = CCB_MAGIC_VALUE; /* For each element in the PKA RAM */ for (index = 0; index < CCB_PKA_RAM_SIZE; index++) { - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } /* Clear the content */ - PKA->RAM[index] = RNG->DR; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[index] = HAL_CCB_GET_RNG_INSTANCE(hccb)->DR; } - if (PKA->RAM[CCB_PKA_RAM_SIZE - 1U] == CCB_MAGIC_VALUE) + if (HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[CCB_PKA_RAM_SIZE - 1U] == CCB_MAGIC_VALUE) { - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } @@ -4882,7 +5514,7 @@ static HAL_StatusTypeDef PKA_RAM_Erase(void) while (random_nbr == 0U) { - random_nbr = (uint8_t)(RNG->DR & 0xFFU); + random_nbr = (uint8_t)(HAL_CCB_GET_RNG_INSTANCE(hccb)->DR & 0xFFU); if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* Set state and return error */ @@ -4898,15 +5530,15 @@ static HAL_StatusTypeDef PKA_RAM_Erase(void) /* For each element in the PKA RAM */ for (index = 0; index < CCB_PKA_RAM_SIZE; index++) { - if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { return HAL_ERROR; } /* Clear the content */ - PKA->RAM[index] = RNG->DR; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[index] = HAL_CCB_GET_RNG_INSTANCE(hccb)->DR; } - if (PKA->RAM[CCB_PKA_RAM_SIZE - 1U] == CCB_MAGIC_VALUE) + if (HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[CCB_PKA_RAM_SIZE - 1U] == CCB_MAGIC_VALUE) { return HAL_ERROR; } @@ -4919,6 +5551,7 @@ static HAL_StatusTypeDef PKA_RAM_Erase(void) /** * @brief CCB PKA ECDSA Signature. + * @param hccb CCB handle. * @param pCurveParam pointer to the Curve parameters. * @param pClearPrivateKey pointer to the clear private key. * @param pInteger pointer to the integer k. @@ -4926,7 +5559,7 @@ static HAL_StatusTypeDef PKA_RAM_Erase(void) * @param pSignature Pointer to output signature * @retval HAL status. */ -static HAL_StatusTypeDef PKA_ECDSASign(CCB_ECDSACurveParamTypeDef *pCurveParam, +static HAL_StatusTypeDef PKA_ECDSASign(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *pCurveParam, const uint8_t *pClearPrivateKey, uint8_t *pInteger, uint8_t *pHash, CCB_ECDSASignTypeDef *pSignature) { @@ -4934,73 +5567,90 @@ static HAL_StatusTypeDef PKA_ECDSASign(CCB_ECDSACurveParamTypeDef *pCurveParam, uint32_t timeout = HAL_CCB_TIMEOUT_DEFAULT_VALUE; /* Get the prime order n length */ - PKA->RAM[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS] = GetOptBitSize_u8(pCurveParam->primeOrderSizeByte, - *(pCurveParam->pPrimeOrder)); + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS] \ + = GetOptBitSize_u8(pCurveParam->primeOrderSizeByte, *(pCurveParam->pPrimeOrder)); /* Get the modulus p length */ - PKA->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS] = GetOptBitSize_u8(pCurveParam->modulusSizeByte, *(pCurveParam->pModulus)); + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS] \ + = GetOptBitSize_u8(pCurveParam->modulusSizeByte, *(pCurveParam->pModulus)); /* Get the coefficient a sign */ - PKA->RAM[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN] = pCurveParam->coefSignA; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN] = pCurveParam->coefSignA; /* Move the input parameters coefficient |a| to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_A_COEFF], pCurveParam->pAbsCoefA, pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_A_COEFF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_A_COEFF], pCurveParam->pAbsCoefA, + pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_SIGN_IN_A_COEFF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); /* Move the input parameters coefficient B to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_B_COEFF], pCurveParam->pCoefB, pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_B_COEFF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_B_COEFF], pCurveParam->pCoefB, + pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_SIGN_IN_B_COEFF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); /* Move the input parameters modulus value p to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_MOD_GF], pCurveParam->pModulus, pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_MOD_GF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_MOD_GF], pCurveParam->pModulus, + pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_SIGN_IN_MOD_GF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); /* Move the input parameters integer k to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_K], pInteger, pCurveParam->primeOrderSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_K + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_K], pInteger, + pCurveParam->primeOrderSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_SIGN_IN_K + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); /* Move the input parameters base point G coordinate x to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_X], pCurveParam->pPointX, - pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_INITIAL_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_X], + pCurveParam->pPointX, pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_SIGN_IN_INITIAL_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); /* Move the input parameters base point G coordinate y to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y], pCurveParam->pPointY, - pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y], + pCurveParam->pPointY, pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); /* Move the input parameters hash of message z to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_HASH_E], pHash, pCurveParam->primeOrderSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_HASH_E + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_HASH_E], pHash, + pCurveParam->primeOrderSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_SIGN_IN_HASH_E + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); /* Move the input parameters private key d to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D], pClearPrivateKey, pCurveParam->primeOrderSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D], + pClearPrivateKey, pCurveParam->primeOrderSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); /* Move the input parameters prime order n to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_ORDER_N], pCurveParam->pPrimeOrder, - pCurveParam->primeOrderSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_ORDER_N + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_IN_ORDER_N], + pCurveParam->pPrimeOrder, pCurveParam->primeOrderSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_SIGN_IN_ORDER_N + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); /* Set the mode and deactivate the interrupts */ - MODIFY_REG(PKA->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE, + MODIFY_REG(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, + PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE, CCB_PKA_ECDSA_SIGNATURE_MODE << PKA_CR_MODE_Pos); /* Start the computation */ - PKA->CR |= PKA_CR_START; + HAL_CCB_GET_PKA_INSTANCE(hccb)->CR |= PKA_CR_START; /* Wait for the end of operation or timeout */ - while ((PKA->SR & PKA_SR_PROCENDF) == 0UL) + while ((HAL_CCB_GET_PKA_INSTANCE(hccb)->SR & PKA_SR_PROCENDF) == 0UL) { if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0UL)) { /* Abort any ongoing operation */ - CLEAR_BIT(PKA->CR, PKA_CR_EN); + CLEAR_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_EN); /* Make ready for the next operation */ - SET_BIT(PKA->CR, PKA_CR_EN); + SET_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_EN); return HAL_TIMEOUT; } @@ -5008,12 +5658,15 @@ static HAL_StatusTypeDef PKA_ECDSASign(CCB_ECDSACurveParamTypeDef *pCurveParam, } /* Clear all flags */ - PKA->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + HAL_CCB_GET_PKA_INSTANCE(hccb)->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC + | PKA_CLRFR_OPERRFC); - CCB_Memcpy_u32_to_u8(pSignature->pRSign, &PKA->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], pCurveParam->primeOrderSizeByte); - CCB_Memcpy_u32_to_u8(pSignature->pSSign, &PKA->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], pCurveParam->primeOrderSizeByte); + CCB_Memcpy_u32_to_u8(pSignature->pRSign, &HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], + pCurveParam->primeOrderSizeByte); + CCB_Memcpy_u32_to_u8(pSignature->pSSign, &HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], + pCurveParam->primeOrderSizeByte); - if (PKA_RAM_Erase() != HAL_OK) + if (PKA_RAM_Erase(hccb) != HAL_OK) { /* return error */ return HAL_ERROR; @@ -5024,95 +5677,110 @@ static HAL_StatusTypeDef PKA_ECDSASign(CCB_ECDSACurveParamTypeDef *pCurveParam, /** * @brief Blob Usage: ECC Compute Scalar Multiplication. + * @param hccb CCB handle. * @param pCurveParam pointer to the Curve parameters. * @param pClearPrivateKey pointer to the related wrapped Private Key Blob. * @param PublicKey is table of two coordinates X and Y of the publicKey. * @retval HAL status. */ -static HAL_StatusTypeDef PKA_ECC_ComputeScalarMul(CCB_ECCMulCurveParamTypeDef *pCurveParam, +static HAL_StatusTypeDef PKA_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_ECCMulCurveParamTypeDef *pCurveParam, const uint8_t *pClearPrivateKey, uint32_t PublicKey[2][20]) { uint32_t tickstart; uint32_t timeout = HAL_CCB_TIMEOUT_DEFAULT_VALUE; - /*********************************************************************************** Set input parameter in PKA RAM */ + /********************************************************************************** Set input parameter in PKA RAM */ /* Get the prime order n length */ - PKA->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = GetOptBitSize_u8(pCurveParam->primeOrderSizeByte, - *(pCurveParam->pPrimeOrder)); + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS]\ + = GetOptBitSize_u8(pCurveParam->primeOrderSizeByte, *(pCurveParam->pPrimeOrder)); /* Get the modulus length */ - PKA->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = GetOptBitSize_u8(pCurveParam->modulusSizeByte, - *(pCurveParam->pModulus)); + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS]\ + = GetOptBitSize_u8(pCurveParam->modulusSizeByte, *(pCurveParam->pModulus)); /* Get the coefficient a sign */ - PKA->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = pCurveParam->coefSignA; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = pCurveParam->coefSignA; /* Move the input parameters coefficient |a| to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], pCurveParam->pAbsCoefA, pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], pCurveParam->pAbsCoefA, + pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); /* Move the input parameters coefficient b to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], pCurveParam->pCoefB, pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], pCurveParam->pCoefB, + pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); /* Move the input parameters modulus value p to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], pCurveParam->pModulus, pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], pCurveParam->pModulus, + pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); /* Move the input parameters scalar multiplier k to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_K], pClearPrivateKey, pCurveParam->primeOrderSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_K], pClearPrivateKey, + pCurveParam->primeOrderSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECC_SCALAR_MUL_IN_K + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); /* Move the input parameters Point P coordinate x to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], pCurveParam->pPointX, - pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], + pCurveParam->pPointX, pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); /* Move the input parameters Point P coordinate y to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], pCurveParam->pPointY, - pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], + pCurveParam->pPointY, pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); /* Move the input parameters curve prime order N to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], pCurveParam->pPrimeOrder, + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], + pCurveParam->pPrimeOrder, pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); - /********************************************************************************************** Start the operation */ + /******************************************************************************************** Start the operation */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); /* Set the mode and deactivate the interrupts */ - MODIFY_REG(PKA->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE, + MODIFY_REG(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, + PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE, CCB_PKA_ECC_MUL_MODE << PKA_CR_MODE_Pos); /* Start the computation */ - PKA->CR |= PKA_CR_START; + HAL_CCB_GET_PKA_INSTANCE(hccb)->CR |= PKA_CR_START; /* Wait for the end of operation or timeout */ - while ((PKA->SR & PKA_SR_PROCENDF) == 0UL) + while ((HAL_CCB_GET_PKA_INSTANCE(hccb)->SR & PKA_SR_PROCENDF) == 0UL) { if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0UL)) { /* Abort any ongoing operation */ - CLEAR_BIT(PKA->CR, PKA_CR_EN); + CLEAR_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_EN); /* Make ready for the next operation */ - SET_BIT(PKA->CR, PKA_CR_EN); + SET_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_EN); return HAL_TIMEOUT; } } /* Clear all flags */ - PKA->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + HAL_CCB_GET_PKA_INSTANCE(hccb)->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC + | PKA_CLRFR_OPERRFC); /* get PublicKey result */ /* Move the result from appropriate location (with opprand size in 32bit word ) */ - CCB_Memcpy_u32_to_u32(PublicKey[0], &PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X], + CCB_Memcpy_u32_to_u32(PublicKey[0], &HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X], ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); - CCB_Memcpy_u32_to_u32(PublicKey[1], &PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y], + CCB_Memcpy_u32_to_u32(PublicKey[1], &HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y], ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); - if (PKA_RAM_Erase() != HAL_OK) + if (PKA_RAM_Erase(hccb) != HAL_OK) { /* return error */ return HAL_ERROR; @@ -5123,69 +5791,80 @@ static HAL_StatusTypeDef PKA_ECC_ComputeScalarMul(CCB_ECCMulCurveParamTypeDef *p /** * @brief Compute CCB Modular exponentiation. + * @param hccb CCB handle. * @param pParam pointer to the modular exponatiation parameters. * @param pRSAClearPrivateKey pointer to the clear Private Key. * @param pOp1 Pointer to Operand 1 (Array of size elements). * @param pReferenceModularExp pointer to the ReferenceModularExp computed in modular exponentiation Blob creation. * @retval HAL status. */ -static HAL_StatusTypeDef PKA_RSA_ComputeModularExp(CCB_RSAParamTypeDef *pParam, +static HAL_StatusTypeDef PKA_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_RSAParamTypeDef *pParam, const CCB_RSAClearKeyTypeDef *pRSAClearPrivateKey, uint8_t *pOp1, uint32_t *pReferenceModularExp) { uint32_t tickstart = HAL_GetTick(); /* Get the number of bit per operand */ - PKA->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = pParam->modulusSizeByte * 8U; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = pParam->modulusSizeByte * 8U; /* Get the number of bit of the exponent */ - PKA->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = pParam->expSizeByte * 8U; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = pParam->expSizeByte * 8U; /* Move the input parameters pOp1 to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE], pOp1, pParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + ((pParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE], pOp1, + pParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + ((pParam->modulusSizeByte + 3UL) / 4UL)); /* Move the exponent to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT], pRSAClearPrivateKey->pExp, pParam->expSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + ((pParam->expSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT], + pRSAClearPrivateKey->pExp, pParam->expSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + ((pParam->expSizeByte + 3UL) / 4UL)); /* Move the modulus to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_MODULUS], pParam->pMod, pParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_MODULUS + ((pParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_PROTECT_IN_MODULUS], pParam->pMod, + pParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_MODULAR_EXP_PROTECT_IN_MODULUS + ((pParam->modulusSizeByte + 3UL) / 4UL)); /* Move Phi value to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI], pRSAClearPrivateKey->pPhi, pParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + ((pParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI], + pRSAClearPrivateKey->pPhi, pParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_MODULAR_EXP_PROTECT_IN_PHI + ((pParam->modulusSizeByte + 3UL) / 4UL)); /* Set the mode and deactivate the interrupts */ - MODIFY_REG(PKA->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE, + MODIFY_REG(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, + PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE, CCB_PKA_MODE_MODULAR_EXP_PROTECT << PKA_CR_MODE_Pos); /* Start the computation */ - PKA->CR |= PKA_CR_START; + HAL_CCB_GET_PKA_INSTANCE(hccb)->CR |= PKA_CR_START; /* Wait for the end of operation or timeout */ - while ((PKA->SR & PKA_SR_PROCENDF) == 0UL) + while ((HAL_CCB_GET_PKA_INSTANCE(hccb)->SR & PKA_SR_PROCENDF) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) { /* Abort any ongoing operation */ - CLEAR_BIT(PKA->CR, PKA_CR_EN); + CLEAR_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_EN); /* Make ready for the next operation */ - SET_BIT(PKA->CR, PKA_CR_EN); + SET_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_EN); return HAL_TIMEOUT; } } /* Clear all flags */ - PKA->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + HAL_CCB_GET_PKA_INSTANCE(hccb)->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC + | PKA_CLRFR_OPERRFC); /* Move the result from appropriate location (with opprand size in 32bit word ) */ - CCB_Memcpy_u32_to_u32(pReferenceModularExp, &PKA->RAM[PKA_MODULAR_EXP_OUT_RESULT], + CCB_Memcpy_u32_to_u32(pReferenceModularExp, &HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_MODULAR_EXP_OUT_RESULT], ((pParam->modulusSizeByte + 3UL) / 4UL)); - if (PKA_RAM_Erase() != HAL_OK) + if (PKA_RAM_Erase(hccb) != HAL_OK) { /* return error */ return HAL_ERROR; @@ -5194,15 +5873,17 @@ static HAL_StatusTypeDef PKA_RSA_ComputeModularExp(CCB_RSAParamTypeDef *pParam, return HAL_OK; } +#endif /* GENERATOR_SW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ /** @brief Verify the validity of a signature using elliptic curves over prime fields in blocking mode. + * @param hccb CCB handle. * @param pCurveParam pointer to the Curve parameters. * @param pPublicKeyOut pointer to the public key. * @param pHash pointer to the hash. * @param pSignature Pointer to input signature * @retval HAL status. */ -static HAL_StatusTypeDef PKA_ECDSAVerif(CCB_ECDSACurveParamTypeDef *pCurveParam, +static HAL_StatusTypeDef PKA_ECDSAVerif(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *pCurveParam, CCB_ECCMulPointTypeDef *pPublicKeyOut, const uint8_t *pHash, CCB_ECDSASignTypeDef *pSignature) { @@ -5211,102 +5892,124 @@ static HAL_StatusTypeDef PKA_ECDSAVerif(CCB_ECDSACurveParamTypeDef *pCurveParam, /* Set CCB input parameter in PKA RAM */ /* Get the prime order n length */ - PKA->RAM[PKA_ECDSA_VERIF_IN_ORDER_NB_BITS] = GetOptBitSize_u8(pCurveParam->primeOrderSizeByte, - *(pCurveParam->pPrimeOrder)); + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_VERIF_IN_ORDER_NB_BITS] \ + = GetOptBitSize_u8(pCurveParam->primeOrderSizeByte, *(pCurveParam->pPrimeOrder)); /* Get the modulus p length */ - PKA->RAM[PKA_ECDSA_VERIF_IN_MOD_NB_BITS] = GetOptBitSize_u8(pCurveParam->modulusSizeByte, *(pCurveParam->pModulus)); + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_VERIF_IN_MOD_NB_BITS] \ + = GetOptBitSize_u8(pCurveParam->modulusSizeByte, *(pCurveParam->pModulus)); /* Get the coefficient a sign */ - PKA->RAM[PKA_ECDSA_VERIF_IN_A_COEFF_SIGN] = pCurveParam->coefSignA; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_VERIF_IN_A_COEFF_SIGN] = pCurveParam->coefSignA; /* Move the input parameters coefficient |a| to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_A_COEFF], pCurveParam->pAbsCoefA, pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_A_COEFF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_VERIF_IN_A_COEFF], pCurveParam->pAbsCoefA, + pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_VERIF_IN_A_COEFF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); /* Move the input parameters modulus value p to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_MOD_GF], pCurveParam->pModulus, pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_MOD_GF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_VERIF_IN_MOD_GF], pCurveParam->pModulus, + pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_VERIF_IN_MOD_GF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); /* Move the input parameters base point G coordinate x to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_X], pCurveParam->pPointX, - pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_X], + pCurveParam->pPointX, pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_VERIF_IN_INITIAL_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); /* Move the input parameters base point G coordinate y to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y], pCurveParam->pPointY, - pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y], + pCurveParam->pPointY, pCurveParam->modulusSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X], pPublicKeyOut->pPointX, + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X], + pPublicKeyOut->pPointX, pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y], pPublicKeyOut->pPointY, + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y], + pPublicKeyOut->pPointY, pCurveParam->modulusSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); /* Move the input parameters signature part r to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_R], pSignature->pRSign, pCurveParam->primeOrderSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_SIGNATURE_R + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_R], pSignature->pRSign, + pCurveParam->primeOrderSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_VERIF_IN_SIGNATURE_R + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); /* Move the input parameters signature part s to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_S], pSignature->pSSign, pCurveParam->primeOrderSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_SIGNATURE_S + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_S], pSignature->pSSign, + pCurveParam->primeOrderSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_VERIF_IN_SIGNATURE_S + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); /* Move the input parameters hash of message z to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_HASH_E], pHash, pCurveParam->primeOrderSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_HASH_E + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_VERIF_IN_HASH_E], pHash, + pCurveParam->primeOrderSizeByte); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_VERIF_IN_HASH_E + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); /* Move the input parameters curve prime order n to PKA RAM */ - CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_ORDER_N], pCurveParam->pPrimeOrder, + CCB_Memcpy_u8_to_u32(&HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_VERIF_IN_ORDER_N], pCurveParam->pPrimeOrder, pCurveParam->primeOrderSizeByte); - RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_ORDER_N + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); + RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, + PKA_ECDSA_VERIF_IN_ORDER_N + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL)); /* Set the mode and deactivate the interrupts */ - MODIFY_REG(PKA->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE, + MODIFY_REG(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, + PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE, CCB_PKA_MODE_ECDSA_VERIFICATION << PKA_CR_MODE_Pos); /* Start the computation */ - PKA->CR |= PKA_CR_START; + HAL_CCB_GET_PKA_INSTANCE(hccb)->CR |= PKA_CR_START; tickstart = HAL_GetTick(); /* Wait for the end of operation or timeout */ - while ((PKA->SR & PKA_SR_PROCENDF) == 0UL) + while ((HAL_CCB_GET_PKA_INSTANCE(hccb)->SR & PKA_SR_PROCENDF) == 0UL) { if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0UL)) { /* Abort any ongoing operation */ - CLEAR_BIT(PKA->CR, PKA_CR_EN); + CLEAR_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_EN); /* Make ready for the next operation */ - SET_BIT(PKA->CR, PKA_CR_EN); + SET_BIT(HAL_CCB_GET_PKA_INSTANCE(hccb)->CR, PKA_CR_EN); return HAL_TIMEOUT; } } /* Clear all flags */ - PKA->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + HAL_CCB_GET_PKA_INSTANCE(hccb)->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC + | PKA_CLRFR_OPERRFC); return HAL_OK; } /** * @brief Return the result of the ECDSA verification operation. + * @param hccb CCB handle. * @retval 1 if signature is verified, 0 in other case */ -static uint32_t PKA_ECDSAVerif_Result(void) +static uint32_t PKA_ECDSAVerif_Result(CCB_HandleTypeDef *hccb) { - return (PKA->RAM[PKA_ECDSA_VERIF_OUT_RESULT]); + return (HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECDSA_VERIF_OUT_RESULT]); } /** * @brief Reset the PKA RAM. + * @param hccb CCB handle. * @retval None */ -static void CCB_PKA_RAMReset(void) +static void CCB_PKA_RAMReset(CCB_HandleTypeDef *hccb) { uint32_t index; @@ -5314,9 +6017,191 @@ static void CCB_PKA_RAMReset(void) for (index = 0; index < CCB_PKA_RAM_SIZE; index++) { /* Clear the content */ - PKA->RAM[index] = 0UL; + HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[index] = 0UL; + } +} + +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +/** + * @brief RNG sequence to resilient recover from a seed error + * @retval HAL status + */ +HAL_StatusTypeDef CCB_RNG_ResilientRecoverSeedError(CCB_HandleTypeDef *hccb) +{ + uint32_t timeout; + uint32_t htsr_temp = 0U; + uint32_t htsr_previous_temp = 0U; + uint32_t htsr_count = 0U; + uint32_t nsmr_temp = 0U; + uint32_t tickstart1 = 0U; + uint32_t tickstart2 = 0U; + uint32_t tickstart3 = 0U; + uint32_t oscillators_count = 0U; + uint32_t config_b_fewer_than_6_osc_count = 0U; + uint8_t count = 0U; + + /* timeout here is an emperic value */ + timeout = (1UL + ((1UL << (READ_BIT(HAL_CCB_GET_RNG_INSTANCE(hccb)->CR, RNG_CR_CLKDIV) >> 16UL)) + * CCB_RNG_TIMEOUT_VALUE / 8UL)); + LL_RNG_Enable(HAL_CCB_GET_RNG_INSTANCE(hccb)); + + tickstart1 = HAL_GetTick(); + + /* Check if seed error current status indicates no error and auto-reset succeeded */ + if (LL_RNG_IsActiveFlag_SECS(HAL_CCB_GET_RNG_INSTANCE(hccb)) == 0U) + { + /* Clear SEIS flag when automatic reset is activated */ + LL_RNG_ClearFlag_SEIS(HAL_CCB_GET_RNG_INSTANCE(hccb)); + } + + else /* Sequence to fully recover from a seed error*/ + { + if (LL_RNG_IsConfigLocked(HAL_CCB_GET_RNG_INSTANCE(hccb)) == 0U) + { + do + { + if (LL_RNG_IsActiveFlag_SECS(HAL_CCB_GET_RNG_INSTANCE(hccb)) == 0U) + { + break; + } + /* Read oscillator status registers combined */ + htsr_temp = LL_RNG_GetHealthTestStatus(HAL_CCB_GET_RNG_INSTANCE(hccb), 0U); + htsr_temp |= LL_RNG_GetHealthTestStatus(HAL_CCB_GET_RNG_INSTANCE(hccb), 1U); + if (htsr_temp > 0U) + { + /* If any oscillator status bits overlap with previous status, increment counter */ + if ((htsr_temp & htsr_previous_temp) != 0U) + { + htsr_count++; + } + + if (htsr_count > 3U) + { + /* if the same repetitive or adaptative error is detected 3 times */ + nsmr_temp = LL_RNG_GetNoiseSourceMask(HAL_CCB_GET_RNG_INSTANCE(hccb)); + + /* deactivate the same osc in each triple oscillator (Mask oscillators with the seed error by + clearing bits shifted right by 1) */ + nsmr_temp = nsmr_temp & ~(htsr_temp >> 1U); + + /* Count the number of active oscillators in nsmr */ + oscillators_count = 0U; + for (count = 0U; count < 9U; count++) + { + if (((nsmr_temp >> count) & 0x1U) != 0U) + { + /* increment count1 for each 1 in nsmr */ + oscillators_count++; + } + } + + if (oscillators_count < 6U) + { + /* If fewer than 6 oscillators remain active, unmask all oscillators --> Reset masking */ + nsmr_temp = LL_RNG_GetOscNoiseSrc(HAL_CCB_GET_RNG_INSTANCE(hccb), + LL_RNG_NOISE_SRC_1 | LL_RNG_NOISE_SRC_2 | LL_RNG_NOISE_SRC_3); + htsr_previous_temp = 0; + htsr_count = 0U; + if ((HAL_CCB_GET_RNG_INSTANCE(hccb)->CR & RNG_CR_CLKDIV_Msk) < + ((uint32_t)RNG_CAND_NIST_CR_VALUE & RNG_CR_CLKDIV_Msk)) + { + config_b_fewer_than_6_osc_count++; + } + } + + if (config_b_fewer_than_6_osc_count > 2U) + { + /* Reset RNG condition */ + WRITE_REG(HAL_CCB_GET_RNG_INSTANCE(hccb)->CR, (RNG_CR_CONDRST_Msk | (uint32_t)RNG_CAND_NIST_CR_VALUE)); + + /* Update mask register with new oscillator mask */ + LL_RNG_SetNoiseSourceMask(HAL_CCB_GET_RNG_INSTANCE(hccb), nsmr_temp); + + /* Clear condition reset bit to resume operation */ + LL_RNG_DisableCondReset(HAL_CCB_GET_RNG_INSTANCE(hccb)); + } + + else + { + /* Reset RNG condition */ + WRITE_REG(HAL_CCB_GET_RNG_INSTANCE(hccb)->CR, + (HAL_CCB_GET_RNG_INSTANCE(hccb)->CR & ~RNG_CR_RNGEN_Msk) | RNG_CR_CONDRST_Msk); + + /* Update mask register with new oscillator mask */ + LL_RNG_SetNoiseSourceMask(HAL_CCB_GET_RNG_INSTANCE(hccb), nsmr_temp); + + /* Clear condition reset bit to resume operation */ + LL_RNG_DisableCondReset(HAL_CCB_GET_RNG_INSTANCE(hccb)); + } + } + + else + { + /* Briefly toggle conditional reset to recover RNG */ + WRITE_REG(HAL_CCB_GET_RNG_INSTANCE(hccb)->CR, + (HAL_CCB_GET_RNG_INSTANCE(hccb)->CR & ~RNG_CR_RNGEN_Msk) | RNG_CR_CONDRST_Msk); + + /* unmask all oscillators to find another working condition */ + LL_RNG_SetNoiseSourceMask(HAL_CCB_GET_RNG_INSTANCE(hccb), + LL_RNG_GetOscNoiseSrc(RNG, LL_RNG_OSC_1 | LL_RNG_OSC_2 | LL_RNG_OSC_3)); + LL_RNG_DisableCondReset(HAL_CCB_GET_RNG_INSTANCE(hccb)); + } + + /* Wait until RNG is not busy */ + tickstart2 = HAL_GetTick(); + do + { + if ((HAL_GetTick() - tickstart2) > CCB_RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + LL_RNG_Disable(HAL_CCB_GET_RNG_INSTANCE(hccb)); + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(HAL_CCB_GET_RNG_INSTANCE(hccb)->SR, RNG_SR_BUSY)); + + /* No timeout --> Enable RNG */ + LL_RNG_Enable(HAL_CCB_GET_RNG_INSTANCE(hccb)); + tickstart3 = HAL_GetTick(); + do + { + if (LL_RNG_IsActiveFlag_DRDY(HAL_CCB_GET_RNG_INSTANCE(hccb)) != 0UL) + { + break; + } + if ((HAL_GetTick() - tickstart3) > timeout) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_RNG_IsActiveFlag_DRDY(HAL_CCB_GET_RNG_INSTANCE(hccb)) == 0UL) + { + if (LL_RNG_IsActiveFlag_SECS(HAL_CCB_GET_RNG_INSTANCE(hccb)) == 0UL) + { + LL_RNG_Disable(HAL_CCB_GET_RNG_INSTANCE(hccb)); + return HAL_ERROR; + } + } + } + } while (LL_RNG_IsActiveFlag_SECS(HAL_CCB_GET_RNG_INSTANCE(hccb)) == 0UL); + + /* Accumulate seed error status bits */ + htsr_previous_temp = htsr_previous_temp | htsr_temp; + } + } while ((HAL_GetTick() - tickstart1) <= timeout); + } + } + + /*Check if seed error current status (SECS)is set */ + if (LL_RNG_IsActiveFlag_SECS(HAL_CCB_GET_RNG_INSTANCE(hccb)) != 0U) + { + return HAL_ERROR; } + + return HAL_OK; } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ + +/** + * @} + */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_crc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_crc.c index 0b280ef1ff..cdbfa5a018 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_crc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_crc.c @@ -154,11 +154,19 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) /* set input data inversion mode */ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); +#if defined(CRC_CR_RTYPE_OUT) + MODIFY_REG(hcrc->Instance->CR, (CRC_CR_RTYPE_IN | CRC_CR_REV_IN), hcrc->Init.InputDataInversionMode); +#else MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); +#endif /* CRC_CR_RTYPE_OUT */ /* set output data inversion mode */ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); +#if defined(CRC_CR_RTYPE_OUT) + MODIFY_REG(hcrc->Instance->CR, (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT), hcrc->Init.OutputDataInversionMode); +#else MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); +#endif /* CRC_CR_RTYPE_OUT */ /* makes sure the input data format (bytes, halfwords or words stream) * is properly specified by user */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c index 96159c23ae..d6f166b0fe 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c @@ -306,6 +306,9 @@ * @{ */ #define CRYP_GENERAL_TIMEOUT 82U +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +#define CRYP_RNG_TIMEOUT_VALUE 2U +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ #define CRYP_TIMEOUT_KEYPREPARATION 82U /*!< The latency of key preparation operation is 82 clock cycles.*/ #define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /*!< The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/ @@ -383,6 +386,7 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static void CRYP_CopyPartialOutputWord(uint32_t *pOutputWord, uint32_t word, uint32_t dataType, uint32_t validBytes); #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output); static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input); @@ -392,6 +396,52 @@ static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Ou static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input, uint32_t KeySize); static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +HAL_StatusTypeDef CRYP_RNG_ResilientRecoverSeedError(void); +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ + +static void CRYP_CopyPartialOutputWord(uint32_t *pOutputWord, uint32_t word, uint32_t dataType, uint32_t validBytes) +{ + uint8_t *pDst = (uint8_t *)pOutputWord; + uint8_t *pSrc = (uint8_t *)&word; + uint32_t dstIndex = 0U; + uint32_t index; + uint32_t maskValue; + /* DataType-dependent byte maps used to keep only valid bytes from the last partial CCM word. */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; + + if (validBytes >= 4U) + { + *pOutputWord = word; + return; + } + + /* Select bytes that are valid for the active DataType, then compact them at output start. */ + maskValue = mask[(dataType * 2U) + validBytes]; + + for (index = 0U; index < 4U; index++) + { + if ((maskValue & ((uint32_t)0xFFU << (index * 8U))) != 0U) + { + pDst[dstIndex] = pSrc[index]; + dstIndex++; + if (dstIndex == validBytes) + { + break; + } + } + } + + for (index = dstIndex; index < 4U; index++) + { + /* Zero-fill trailing bytes to keep deterministic output for non-aligned payload sizes. */ + pDst[index] = 0U; + } +} /** @@ -494,6 +544,20 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } else { +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CRYP_RNG_ResilientRecoverSeedError() != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear Rng error interrupt flag */ + SET_BIT(hcryp->Instance->ICR, AES_ICR_RNGEIF); + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ /* SAES is initializing, fetching random number from the RNG */ tickstart = HAL_GetTick(); while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)) @@ -3181,6 +3245,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) uint32_t lastwordsize; uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t mode; + uint32_t crypoutcount; CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; @@ -3255,7 +3320,17 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) count = 0U; while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (count < 4U)) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count]; + crypoutcount = hcryp->CrypOutCount; + if ((((hcryp->Size % 4U) != 0U) && (crypoutcount == ((((uint32_t)hcryp->Size + 3U) / 4U) - 1U))) + && (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[count], + hcryp->Init.DataType, (((uint32_t)hcryp->Size) % 4U)); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count]; + } hcryp->CrypOutCount++; count++; } @@ -3503,6 +3578,7 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t i; + uint32_t crypoutcount; /* Write the input block in the IN FIFO */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); @@ -3538,7 +3614,17 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) i = 0U; while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + crypoutcount = hcryp->CrypOutCount; + if ((((hcryp->Size % 4U) != 0U) && (crypoutcount == ((((uint32_t)hcryp->Size + 3U) / 4U) - 1U))) + && (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[i], + hcryp->Init.DataType, (((uint32_t)hcryp->Size) % 4U)); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + } hcryp->CrypOutCount++; i++; } @@ -3747,10 +3833,18 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t npblb; uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t index; - uint32_t lastwordsize; + uint32_t tmp; + uint32_t lastwordsize ; + uint32_t lastoutputwordsize; + uint32_t nolastpaddingbytes; uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32- bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 1- bit data type */ + }; if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { if (hcryp->KeyIVConfig == 1U) @@ -3910,14 +4004,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); } /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } + lastwordsize = (16U - npblb) / 4U; + /* last block optionally pad the data with zeros*/ for (index = 0U; index < lastwordsize; index ++) { @@ -3925,6 +4013,16 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } + + if ((npblb % 4U) != 0U) + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + tmp &= mask[((hcryp->Init.DataType) * 2U) + ((16U - npblb) % 4U)]; + hcryp->Instance->DINR = tmp; + index++; + } + while (index < 4U) { /* pad the data with zeros to have a complete block */ @@ -3946,6 +4044,17 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + /* Number of words in last block to read from DOUT*/ + if ((npblb % 4U) == 0U) + { + lastoutputwordsize = (16U - npblb) / 4U; + } + else + { + lastoutputwordsize = ((16U - npblb) / 4U) + 1U; + } + + /*Read the output block from the output FIFO */ for (index = 0U; index < 4U; index++) { @@ -3953,9 +4062,20 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t get CrypOutBuff from temporary buffer */ temp[index] = hcryp->Instance->DOUTR; } - for (index = 0U; index < lastwordsize; index++) + for (index = 0U; index < lastoutputwordsize; index++) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index]; + if ((index == (lastoutputwordsize - 1U)) && ((npblb % 4U) != 0U) + && (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + nolastpaddingbytes = npblb % 4U; + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[index], + hcryp->Init.DataType, 4U - nolastpaddingbytes); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index]; + } + hcryp->CrypOutCount++; } } @@ -4509,10 +4629,17 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t loopcounter; uint32_t npblb; uint32_t lastwordsize; + uint32_t lastoutputwordsize; uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ + uint32_t tmp; uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32- bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 1- bit data type */ + }; if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { @@ -4675,14 +4802,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t } /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } + lastwordsize = (16U - npblb) / 4U; /* Write the last input block in the IN FIFO */ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++) @@ -4690,6 +4810,15 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } + if ((npblb % 4U) != 0U) + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + /* Keep only valid bytes of the last partial input word, according to DataType byte ordering. */ + tmp &= mask[(hcryp->Init.DataType * 2U) + ((16U - npblb) % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + } /* Pad the data with zeros to have a complete block */ while (loopcounter < 4U) @@ -4697,6 +4826,15 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t hcryp->Instance->DINR = 0U; loopcounter++; } + /* Number of words in last block to read from DOUT*/ + if ((npblb % 4U) == 0U) + { + lastoutputwordsize = (16U - npblb) / 4U; + } + else + { + lastoutputwordsize = ((16U - npblb) / 4U) + 1U; + } /* just wait for hash computation */ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { @@ -4711,9 +4849,17 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t get CrypOutBuff from temporary buffer */ temp[loopcounter] = hcryp->Instance->DOUTR; } - for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + for (loopcounter = 0U; loopcounter < lastoutputwordsize; loopcounter++) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter]; + if ((loopcounter == (lastoutputwordsize - 1U)) && ((npblb % 4U) != 0U)) + { + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[loopcounter], + hcryp->Init.DataType, 4U - (npblb % 4U)); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter]; + } hcryp->CrypOutCount++; } } @@ -5266,6 +5412,7 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) uint16_t incount; /* Temporary CrypInCount Value */ uint16_t outcount; /* Temporary CrypOutCount Value */ uint32_t i; + uint32_t crypoutcount; /***************************** Payload phase *******************************/ @@ -5278,7 +5425,17 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) i = 0U; while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + crypoutcount = hcryp->CrypOutCount; + if ((((hcryp->Size % 4U) != 0U) && (crypoutcount == ((((uint32_t)hcryp->Size + 3U) / 4U) - 1U))) + && (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[i], + hcryp->Init.DataType, (((uint32_t)hcryp->Size) % 4U)); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + } hcryp->CrypOutCount++; i++; } @@ -5499,7 +5656,16 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr } for (index = 0U; index < lastwordsize; index++) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; + if ((index == (lastwordsize - 1U)) && ((npblb % 4U) != 0U) + && (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[index], + hcryp->Init.DataType, 4U - (npblb % 4U)); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; + } hcryp->CrypOutCount++; } @@ -6401,6 +6567,179 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) } } #endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */ +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +/** + * @brief RNG sequence to resilient recover from a seed error + * @retval HAL status + */ +HAL_StatusTypeDef CRYP_RNG_ResilientRecoverSeedError(void) +{ + uint32_t timeout; + uint32_t htsr_temp = 0U; + uint32_t htsr_previous_temp = 0U; + uint32_t htsr_count = 0U; + uint32_t nsmr_temp = 0U; + uint32_t tickstart1 = 0U; + uint32_t tickstart2 = 0U; + uint32_t tickstart3 = 0U; + uint32_t oscillators_count = 0U; + uint32_t config_b_fewer_than_6_osc_count = 0U; + uint8_t count = 0U; + + /* timeout here is an emperic value */ + timeout = (1UL + ((1UL << (READ_BIT(RNG->CR, RNG_CR_CLKDIV) >> 16UL)) * CRYP_RNG_TIMEOUT_VALUE / 8UL)); + LL_RNG_Enable(RNG); + + tickstart1 = HAL_GetTick(); + + /* Check if seed error current status indicates no error and auto-reset succeeded */ + if (LL_RNG_IsActiveFlag_SECS(RNG) == 0U) + { + /* Clear SEIS flag when automatic reset is activated */ + LL_RNG_ClearFlag_SEIS(RNG); + } + + else /* Sequence to fully recover from a seed error*/ + { + if (LL_RNG_IsConfigLocked(RNG) == 0U) + { + do + { + if (LL_RNG_IsActiveFlag_SECS(RNG) == 0U) + { + break; + } + /* Read oscillator status registers combined */ + htsr_temp = LL_RNG_GetHealthTestStatus(RNG, 0U); + htsr_temp |= LL_RNG_GetHealthTestStatus(RNG, 1U); + if (htsr_temp > 0U) + { + /* If any oscillator status bits overlap with previous status, increment counter */ + if ((htsr_temp & htsr_previous_temp) != 0U) + { + htsr_count++; + } + + if (htsr_count > 3U) + { + /* if the same repetitive or adaptative error is detected 3 times */ + nsmr_temp = LL_RNG_GetNoiseSourceMask(RNG); + + /* deactivate the same osc in each triple oscillator (Mask oscillators with the seed error by + clearing bits shifted right by 1) */ + nsmr_temp = nsmr_temp & ~(htsr_temp >> 1U); + + /* Count the number of active oscillators in nsmr */ + oscillators_count = 0U; + for (count = 0U; count < 9U; count++) + { + if (((nsmr_temp >> count) & 0x1U) != 0U) + { + /* increment count1 for each 1 in nsmr */ + oscillators_count++; + } + } + + if (oscillators_count < 6U) + { + /* If fewer than 6 oscillators remain active, unmask all oscillators --> Reset masking */ + nsmr_temp = LL_RNG_GetOscNoiseSrc(RNG, LL_RNG_NOISE_SRC_1 | LL_RNG_NOISE_SRC_2 \ + | LL_RNG_NOISE_SRC_3); + htsr_previous_temp = 0; + htsr_count = 0U; + if ((RNG->CR & RNG_CR_CLKDIV_Msk) < ((uint32_t)RNG_CAND_NIST_CR_VALUE & RNG_CR_CLKDIV_Msk)) + { + config_b_fewer_than_6_osc_count++; + } + } + + if (config_b_fewer_than_6_osc_count > 2U) + { + /* Reset RNG condition */ + WRITE_REG(RNG->CR, (RNG_CR_CONDRST_Msk | (uint32_t)RNG_CAND_NIST_CR_VALUE)); + + /* Update mask register with new oscillator mask */ + LL_RNG_SetNoiseSourceMask(RNG, nsmr_temp); + + /* Clear condition reset bit to resume operation */ + LL_RNG_DisableCondReset(RNG); + } + + else + { + /* Reset RNG condition */ + WRITE_REG(RNG->CR, (RNG->CR & ~RNG_CR_RNGEN_Msk) | RNG_CR_CONDRST_Msk); + + /* Update mask register with new oscillator mask */ + LL_RNG_SetNoiseSourceMask(RNG, nsmr_temp); + + /* Clear condition reset bit to resume operation */ + LL_RNG_DisableCondReset(RNG); + } + } + + else + { + /* Briefly toggle conditional reset to recover RNG */ + WRITE_REG(RNG->CR, (RNG->CR & ~RNG_CR_RNGEN_Msk) | RNG_CR_CONDRST_Msk); + + /* unmask all oscillators to find another working condition */ + LL_RNG_SetNoiseSourceMask(RNG, LL_RNG_GetOscNoiseSrc(RNG, LL_RNG_OSC_1\ + | LL_RNG_OSC_2 | LL_RNG_OSC_3)); + LL_RNG_DisableCondReset(RNG); + } + + /* Wait until RNG is not busy */ + tickstart2 = HAL_GetTick(); + do + { + if ((HAL_GetTick() - tickstart2) > CRYP_RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + LL_RNG_Disable(RNG); + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(RNG->SR, RNG_SR_BUSY)); + + /* No timeout --> Enable RNG */ + LL_RNG_Enable(RNG); + tickstart3 = HAL_GetTick(); + do + { + if (LL_RNG_IsActiveFlag_DRDY(RNG) != 0UL) + { + break; + } + if ((HAL_GetTick() - tickstart3) > timeout) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_RNG_IsActiveFlag_DRDY(RNG) == 0UL) + { + if (LL_RNG_IsActiveFlag_SECS(RNG) == 0UL) + { + LL_RNG_Disable(RNG); + return HAL_ERROR; + } + } + } + } while (LL_RNG_IsActiveFlag_SECS(RNG) == 0UL); + + /* Accumulate seed error status bits */ + htsr_previous_temp = htsr_previous_temp | htsr_temp; + } + } while ((HAL_GetTick() - tickstart1) <= timeout); + } + } + + /*Check if seed error current status (SECS)is set */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + return HAL_ERROR; + } + + return HAL_OK; +} +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma2d.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma2d.c index 5d378ac36c..87631d3564 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma2d.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma2d.c @@ -238,7 +238,8 @@ the HAL_DMA2D_CL_AddConfigDownscalingCMD() function for the foreground layer, background layer, or blender output. - (#) Optionally, configure the line watermark in using the function HAL_DMA2D_CL_AddLineEventCMD(). + (#) Optionally, configure the line watermark in using the function + HAL_DMA2D_CL_AddProgramLineEventCMD(). [...] Command List Copy ans Data Transfers Enable Use the following APIs to enable data transfer for the selected operating mode and to copy @@ -407,6 +408,7 @@ const uint32_t LDM_Decoder[HAL_DMA2D_CL_LDM_REG_NUM] = #define DMA2D_CL_LDM_WRITE_REG(HANDLE, REG, VALUE) \ ((HANDLE)->LDM_Reg_values[(REG)] = (VALUE), \ (HANDLE)->LDM_Instruction |= LDM_Decoder[(REG)]) +#define RBS_TO_RING_BUFFER_SIZE(val) (1UL << ((val) + 6U)) #endif /* USE_DMA2D_COMMAND_LIST_MODE == 1 */ /** * @} @@ -2179,8 +2181,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigRotation(DMA2D_HandleTypeDef *hdma2d, uint32_t /** * @brief Configures the DMA2D Downscaling for the selected source Foreground, Background or Blender output * @param hdma2d Pointer to DMA2D handle structure. - * @param Source Specifies the source of the tile buffer. - * This parameter can be a value from @ref DMA2D_SOURCE + * @param Source Specifies the source of the tile buffer. + * This parameter can be a value from @ref DMA2D_SOURCE * @param pDownscalingCfg Pointer to DMA2D_DownscalingCfgTypeDef that contains * the configuration information for downscaling. * @retval HAL status @@ -2188,35 +2190,55 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigRotation(DMA2D_HandleTypeDef *hdma2d, uint32_t HAL_StatusTypeDef HAL_DMA2D_ConfigDownscaling(DMA2D_HandleTypeDef *hdma2d, uint32_t Source, DMA2D_DownscalingCfgTypeDef *pDownscalingCfg) { - /* HSEP and VSTEP Calculation */ - uint16_t hstep = (4096U / (pDownscalingCfg->HRatio) - 1U); - uint16_t vstep = (4096U / (pDownscalingCfg->VRatio) - 1U); + uint32_t hstep; + uint32_t vstep; + uint32_t hq12; + uint32_t vq12; /* Check parameters */ + if ((hdma2d == NULL) || (pDownscalingCfg == NULL)) + { + return HAL_ERROR; + } + assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance)); assert_param(IS_DMA2D_SCALE_SRC(Source)); - assert_param(IS_DMA2D_SCALE_HSTEP(hstep)); - assert_param(IS_DMA2D_SCALE_VSTEP(vstep)); assert_param(IS_DMA2D_SCALE_PIXEL_PER_LINE(pDownscalingCfg->PixelPerLines)); assert_param(IS_DMA2D_SCALE_NUMBER_OF_LINES(pDownscalingCfg->NumberOfLines)); assert_param(IS_DMA2D_SCALE_HPHASE(pDownscalingCfg->HPhase)); assert_param(IS_DMA2D_SCALE_VPHASE(pDownscalingCfg->VPhase)); + if ((pDownscalingCfg->HRatioDiv == 0U) || (pDownscalingCfg->VRatioDiv == 0U)) + { + return HAL_ERROR; + } + + hq12 = (((uint32_t)pDownscalingCfg->HRatio * 4096U) / (uint32_t)pDownscalingCfg->HRatioDiv); + vq12 = (((uint32_t)pDownscalingCfg->VRatio * 4096U) / (uint32_t)pDownscalingCfg->VRatioDiv); + + hstep = hq12 - 1U; + vstep = vq12 - 1U; + + assert_param(IS_DMA2D_SCALE_HSTEP(hstep)); + assert_param(IS_DMA2D_SCALE_VSTEP(vstep)); + /* Config scaling source */ MODIFY_REG(hdma2d->Instance->SCR, DMA2D_SCR_SRC, Source); - /* Config scaling Height and Width */ - MODIFY_REG(hdma2d->Instance->SNLR, (DMA2D_SNLR_NL | DMA2D_SNLR_PL), (pDownscalingCfg->NumberOfLines | - (pDownscalingCfg->PixelPerLines << - DMA2D_SNLR_PL_Pos))); + /* Config scaling height and width */ + MODIFY_REG(hdma2d->Instance->SNLR, + (DMA2D_SNLR_NL | DMA2D_SNLR_PL), + (pDownscalingCfg->NumberOfLines | + (pDownscalingCfg->PixelPerLines << DMA2D_SNLR_PL_Pos))); - /* Config scaling HSEP and VSTEP */ - MODIFY_REG(hdma2d->Instance->SSR, (DMA2D_SSR_HSTEP | DMA2D_SSR_VSTEP), (hstep | (((uint32_t)vstep) << - DMA2D_SSR_VSTEP_Pos))); + /* Config scaling HSTEP and VSTEP */ + WRITE_REG(hdma2d->Instance->SSR, (hstep | (vstep << DMA2D_SSR_VSTEP_Pos))); /* Config scaling HPHASE and VPHASE */ - MODIFY_REG(hdma2d->Instance->SPR, (DMA2D_SPR_HPHASE | DMA2D_SPR_VPHASE), - (pDownscalingCfg->HPhase | (((uint32_t)pDownscalingCfg->VPhase) << DMA2D_SPR_VPHASE_Pos))); + MODIFY_REG(hdma2d->Instance->SPR, + (DMA2D_SPR_HPHASE | DMA2D_SPR_VPHASE), + (pDownscalingCfg->HPhase | + ((uint32_t)pDownscalingCfg->VPhase << DMA2D_SPR_VPHASE_Pos))); return HAL_OK; } @@ -2476,6 +2498,32 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ } #endif /* USE_DMA2D_COMMAND_LIST_MODE == 0 */ #if (USE_DMA2D_COMMAND_LIST_MODE == 1) +/** @defgroup DMA2D_Exported_Functions_Group5 DMA2D Command List (CL) functions + * @brief Initialization and IO/Control functions for Command List mode + * +@verbatim + =============================================================================== + ##### Command List (CL) mode functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and de-initialize the DMA2D in Command List mode + using HAL_DMA2D_CL_Init() and HAL_DMA2D_CL_DeInit(). + (+) Prepare command lists using APIs such as: + HAL_DMA2D_CL_Init_CommandList(), HAL_DMA2D_CL_AddConfigLayerCMD(), + HAL_DMA2D_CL_AddConfigRotationCMD(), HAL_DMA2D_CL_AddConfigStencilCMD(), + HAL_DMA2D_CL_AddConfigDownscalingCMD(), + HAL_DMA2D_CL_AddProgramLineEventCMD(), HAL_DMA2D_CL_AddCopyCMD(), + HAL_DMA2D_CL_AddBlendingCMD(), HAL_DMA2D_CL_AddCLUTStartLoadCMD(). + (+) Insert prepared command lists into the ring buffer and start + execution using HAL_DMA2D_CL_InsertCommandList(), HAL_DMA2D_CL_Start() + and HAL_DMA2D_CL_StartOpt(). + (+) Handle DMA2D CL interrupts through HAL_DMA2D_CL_IRQHandler() and + related callbacks, and control execution using + HAL_DMA2D_CL_Suspend(), HAL_DMA2D_CL_Resume() and HAL_DMA2D_CL_Abort(). + +@endverbatim + * @{ + */ /** * @brief Initialize the DMA2D CL (Command List) Mode * This function configures the DMA2D ring buffer according to RingBuffer parameter of DMA2D_CL_HandleTypeDef @@ -2776,26 +2824,38 @@ HAL_StatusTypeDef HAL_DMA2D_CL_AddConfigRotationCMD(DMA2D_CL_HandleTypeDef *hdma HAL_StatusTypeDef HAL_DMA2D_CL_AddConfigDownscalingCMD(DMA2D_CL_HandleTypeDef *const hdma2d, uint32_t Source, DMA2D_DownscalingCfgTypeDef *pDownscalingCfg) { - /* HSET and VSTEP Calculation */ - uint16_t hstep = (4096 / (pDownscalingCfg->HRatio) - 1); - uint16_t vstep = (4096 / (pDownscalingCfg->VRatio) - 1); + uint32_t hstep; + uint32_t vstep; + uint32_t hq12; + uint32_t vq12; - /* Check the DMA2D channel handle parameter */ - if (hdma2d == NULL) + /* Check parameters */ + if ((hdma2d == NULL) || (pDownscalingCfg == NULL)) { return HAL_ERROR; } - /* Check parameters */ assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance)); assert_param(IS_DMA2D_SCALE_SRC(Source)); - assert_param(IS_DMA2D_SCALE_HSTEP(hstep)); - assert_param(IS_DMA2D_SCALE_VSTEP(vstep)); assert_param(IS_DMA2D_SCALE_PIXEL_PER_LINE(pDownscalingCfg->PixelPerLines)); assert_param(IS_DMA2D_SCALE_NUMBER_OF_LINES(pDownscalingCfg->NumberOfLines)); assert_param(IS_DMA2D_SCALE_HPHASE(pDownscalingCfg->HPhase)); assert_param(IS_DMA2D_SCALE_VPHASE(pDownscalingCfg->VPhase)); + if ((pDownscalingCfg->HRatioDiv == 0U) || (pDownscalingCfg->VRatioDiv == 0U)) + { + return HAL_ERROR; + } + + hq12 = (((uint32_t)pDownscalingCfg->HRatio * 4096U) / (uint32_t)pDownscalingCfg->HRatioDiv); + vq12 = (((uint32_t)pDownscalingCfg->VRatio * 4096U) / (uint32_t)pDownscalingCfg->VRatioDiv); + + hstep = hq12 - 1U; + vstep = vq12 - 1U; + + assert_param(IS_DMA2D_SCALE_HSTEP(hstep)); + assert_param(IS_DMA2D_SCALE_VSTEP(vstep)); + /* Config scaling source */ DMA2D_CL_LDM_WRITE_REG(hdma2d, DMA2D_CL_SCR_REG, Source); @@ -2804,7 +2864,7 @@ HAL_StatusTypeDef HAL_DMA2D_CL_AddConfigDownscalingCMD(DMA2D_CL_HandleTypeDef *c (pDownscalingCfg->PixelPerLines << DMA2D_SNLR_PL_Pos))); /* Config scaling HSEP and VSTEP */ - DMA2D_CL_LDM_WRITE_REG(hdma2d, DMA2D_CL_SSR_REG, (hstep | (vstep << DMA2D_SSR_VSTEP_Pos))); + DMA2D_CL_LDM_WRITE_REG(hdma2d, DMA2D_CL_SSR_REG, (hstep |(vstep << DMA2D_SSR_VSTEP_Pos))); /* Config scaling HPHASE and VPHASE */ DMA2D_CL_LDM_WRITE_REG(hdma2d, DMA2D_CL_SPR_REG, (pDownscalingCfg->HPhase | @@ -2862,6 +2922,36 @@ HAL_StatusTypeDef HAL_DMA2D_CL_AddConfigStencilCMD(DMA2D_CL_HandleTypeDef *hdma2 return HAL_OK; } +/** + * @brief Configure the line watermark in Command List (CL) mode. + * @param hdma2d pointer to a DMA2D_CL_HandleTypeDef structure that contains the configuration information + * @param Line Line Watermark configuration (maximum 16-bit long value expected). + * @note This API programs the line watermark register and enables the transfer watermark interrupt. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CL_AddProgramLineEventCMD(DMA2D_CL_HandleTypeDef *hdma2d, uint32_t Line) +{ + /* Check the DMA2D channel handle parameter */ + if (hdma2d == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if (Line > DMA2D_LWR_LW) + { + return HAL_ERROR; + } + + /* Sets the Line watermark configuration */ + WRITE_REG(hdma2d->Instance->LWR, Line); + + /* Enable the Line interrupt (transfer watermark) */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW); + + return HAL_OK; +} + /** * @brief Add a CLUT Loading operation LDM with the specified parameters in DMA2D_CLUTCfgTypeDef * and copy the prepared LDM instructions and register values. to the chosen Command List address. @@ -3155,17 +3245,22 @@ HAL_StatusTypeDef HAL_DMA2D_CL_Init_CommandList(uint32_t *Address, uint32_t Size * Must be a valid pre/post flag operation. * @retval HAL status */ -#define RBS_TO_RING_BUFFER_SIZE(val) (1U << ((val) + 6)) HAL_StatusTypeDef HAL_DMA2D_CL_InsertCommandList(DMA2D_CL_HandleTypeDef *hdma2d, DMA2D_CL_CommandListTypeDef *pCommandList, uint32_t gpflag, uint32_t post_flag_config, uint32_t pre_flag_config) { uint32_t write_ptr; uint64_t *descriptor; + + if ((hdma2d == NULL) || (pCommandList == NULL)) + { + return HAL_ERROR; + } + uint32_t *CLaddress = (uint32_t *)pCommandList->Address; uint32_t ring_buffer_size = RBS_TO_RING_BUFFER_SIZE(((hdma2d->Instance->CLCR & DMA2D_CLCR_RBS_Msk) >> - DMA2D_CLCR_RBS_Pos)); + DMA2D_CLCR_RBS_Pos)); assert_param(IS_DMA2D_CL_GPFLAG(gpflag)); @@ -3174,10 +3269,6 @@ HAL_StatusTypeDef HAL_DMA2D_CL_InsertCommandList(DMA2D_CL_HandleTypeDef *hdma2d, assert_param(IS_DMA2D_CL_ADDRESS_VALID((uint32_t)pCommandList->Address)); assert_param(IS_DMA2D_CL_SIZE(pCommandList->Size)); - if ((hdma2d == NULL) || (pCommandList == NULL)) - { - return HAL_ERROR; - } if (pCommandList->Address[pCommandList->Index] != 0xFFFFFFFF) { @@ -3507,15 +3598,15 @@ void HAL_DMA2D_CL_IRQHandler(DMA2D_CL_HandleTypeDef *hdma2d) __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CLE); /* Check the error source */ - if ((clsrflags & DMA2D_CLSR_LCLMSE) != 0U) + if ((clsrflags & DMA2D_FLAG_LCLMSE) != 0U) { hdma2d->ErrorCode |= HAL_DMA2D_ERROR_LCLMSE; } - if ((clsrflags & DMA2D_CLSR_LCLIE) != 0U) + if ((clsrflags & DMA2D_FLAG_LCLIE) != 0U) { hdma2d->ErrorCode |= HAL_DMA2D_ERROR_LCLIE ; } - if ((clsrflags & DMA2D_CLSR_LCLRE) != 0U) + if ((clsrflags & DMA2D_FLAG_LCLRE) != 0U) { hdma2d->ErrorCode |= HAL_DMA2D_ERROR_LCLRE; } @@ -4125,6 +4216,10 @@ HAL_StatusTypeDef HAL_DMA2D_CL_UnRegister_GeneralPurposeEvent_Callback(DMA2D_CL_ } #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ +/** + * @} + */ + /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions * @brief Peripheral State functions * diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c index 0405a17d5c..bc8bf23b6c 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c @@ -196,11 +196,13 @@ * @{ */ #define ETH_MACCR_MASK 0xFFFB7F7CU -#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) +#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) \ + || defined(STM32H553xx) || defined(STM32H543xx) #define ETH_MACECR_MASK 0x7F077FFFU #else #define ETH_MACECR_MASK 0x3F077FFFU -#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) */ +#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) || + defined(STM32H553xx) || defined(STM32H543xx) */ #define ETH_MACPFR_MASK 0x800007FFU #if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) \ || defined(STM32H553xx) || defined(STM32H543xx) @@ -216,11 +218,13 @@ #define ETH_DMAMR_MASK 0x00007802U #define ETH_DMASBMR_MASK 0x0000D001U -#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) +#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) \ + || defined(STM32H553xx) || defined(STM32H543xx) #define ETH_DMACCR_MASK 0x04013FFFU #else #define ETH_DMACCR_MASK 0x00013FFFU -#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) */ +#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) || + defined(STM32H553xx) || defined(STM32H543xx) */ #define ETH_DMACTCR_MASK 0x003F1010U #define ETH_DMACRCR_MASK 0x803F0000U #define ETH_MACPCSR_MASK (ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \ @@ -232,11 +236,13 @@ ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\ ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE)) -#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) +#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) \ + || defined(STM32H553xx) || defined(STM32H543xx) #define ETH_MACTSCR_MASK 0x3F07FF6FU #else #define ETH_MACTSCR_MASK 0x0087FF2FU -#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) */ +#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) || + defined(STM32H553xx) || defined(STM32H543xx) */ #define ETH_MACSTSUR_VALUE 0xFFFFFFFFU #define ETH_MACSTNUR_VALUE 0xBB9ACA00U @@ -1562,12 +1568,14 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT ((uint32_t)ptpconfig->TimestampMaster << ETH_MACTSCR_TSMSTRENA_Pos) | ((uint32_t)ptpconfig->TimestampSnapshots << ETH_MACTSCR_SNAPTYPSEL_Pos) | ((uint32_t)ptpconfig->TimestampFilter << ETH_MACTSCR_TSENMACADDR_Pos) | -#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) +#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) \ + || defined(STM32H553xx) || defined(STM32H543xx) ((uint32_t)ptpconfig->TimestampPCS << ETH_MACTSCR_EPCSL_Pos) | ((uint32_t)ptpconfig->TimestampCapturing << ETH_MACTSCR_ECPD_Pos) | ((uint32_t)ptpconfig->TimestampLatencyAccuracy << ETH_MACTSCR_LITA_Pos) | ((uint32_t)ptpconfig->AV8021ASMEN << ETH_MACTSCR_AV8021ASMEN_Pos) | -#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) */ +#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) || + defined(STM32H553xx) || defined(STM32H543xx) */ ((uint32_t)ptpconfig->TimestampStatusMode << ETH_MACTSCR_TXTSSTSM_Pos); /* Write to MACTSCR */ @@ -1651,14 +1659,15 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT ptpconfig->TimestampFilter = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENMACADDR) >> ETH_MACTSCR_TSENMACADDR_Pos) > 0U) ? ENABLE : DISABLE; -#if !defined(STM32H5E5xx) && !defined(STM32H5E4xx) && !defined(STM32H5F5xx) && !defined(STM32H5F4xx) +#if defined(STM32H563xx) || defined(STM32H573xx) ptpconfig->TimestampChecksumCorrection = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_CSC) >> ETH_MACTSCR_CSC_Pos) > 0U) ? ENABLE : DISABLE; -#endif /* !defined(STM32H5E5xx) && !defined(STM32H5E4xx) && !defined(STM32H5F5xx) && !defined(STM32H5F4xx) */ +#endif /* defined(STM32H563xx) || defined(STM32H573xx) */ ptpconfig->TimestampStatusMode = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TXTSSTSM) >> ETH_MACTSCR_TXTSSTSM_Pos) > 0U) ? ENABLE : DISABLE; -#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) +#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) \ + || defined(STM32H553xx) || defined(STM32H543xx) ptpconfig->TimestampPCS = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_EPCSL) >> ETH_MACTSCR_EPCSL_Pos) > 0U) ? ENABLE : DISABLE; ptpconfig->TimestampCapturing = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_ECPD) >> @@ -1667,7 +1676,8 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT ETH_MACTSCR_LITA_Pos) > 0U) ? ENABLE : DISABLE; ptpconfig->AV8021ASMEN = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_AV8021ASMEN) >> ETH_MACTSCR_AV8021ASMEN_Pos) > 0U) ? ENABLE : DISABLE; -#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) */ +#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) || + defined(STM32H553xx) || defined(STM32H543xx) */ /* Return function status */ return HAL_OK; @@ -1692,7 +1702,7 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef * heth->Instance->MACSTNUR = time->NanoSeconds; /* the system time is updated */ - SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT); + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT); /* Return function status */ return HAL_OK; @@ -3037,9 +3047,11 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth) macDefaultConf.PauseTime = 0x0U; macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7; macDefaultConf.ProgrammableWatchdog = DISABLE; -#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) +#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) \ + || defined(STM32H553xx) || defined(STM32H543xx) macDefaultConf.ProgrammableJabber = DISABLE; -#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) */ +#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) || + defined(STM32H553xx) || defined(STM32H543xx) */ macDefaultConf.ReceiveFlowControl = DISABLE; macDefaultConf.ReceiveOwn = ENABLE; macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth_ex.c index 6a6ca98fa8..84db7bc96c 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth_ex.c @@ -296,16 +296,16 @@ HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t /* Set Bits[63:32] of 128-bit IP addr */ WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[1]); /* update Bits[95:64] of 128-bit IP addr */ - WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[2]); + WRITE_REG(heth->Instance->MACL3A2R1R, pL3FilterConfig->Ip6Addr[2]); /* update Bits[127:96] of 128-bit IP addr */ - WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[3]); + WRITE_REG(heth->Instance->MACL3A3R1R, pL3FilterConfig->Ip6Addr[3]); } else /* IPv4 protocol is selected */ { /* Set the IPv4 source address match */ WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4SrcAddr); /* Set the IPv4 destination address match */ - WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4DestAddr); + WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip4DestAddr); } } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c index fd8e3bfcd4..db0ce2cb4a 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c @@ -554,6 +554,13 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) /** * @brief Unlock the FLASH control registers access + * @note When called from secure context on TrustZone-enabled devices, + * this function unlocks BOTH secure and non-secure FLASH control + * registers. This prevents non-secure code from controlling its + * own FLASH access independently until a new unlock sequence is + * performed. + * For per-domain control, use HAL_FLASH_Unlock_S(), + * HAL_FLASH_Unlock_NS() instead. * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) @@ -596,6 +603,11 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void) /** * @brief Locks the FLASH control registers access + * @note When called from secure context on TrustZone-enabled devices, + * this function locks BOTH secure and non-secure FLASH control + * registers. This may interfere with ongoing non-secure FLASH + * operations. For per-domain control, use HAL_FLASH_Lock_S(), + * HAL_FLASH_Lock_NS() instead. * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) @@ -628,6 +640,94 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) return status; } +/** + * @brief Unlock the non-secure FLASH control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock_NS(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (READ_BIT(FLASH->NSCR, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Control Register access */ + WRITE_REG(FLASH->NSKEYR, FLASH_KEY1); + WRITE_REG(FLASH->NSKEYR, FLASH_KEY2); + + /* Verify Flash CR is unlocked */ + if (READ_BIT(FLASH->NSCR, FLASH_CR_LOCK) != 0U) + { + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Lock the non-secure FLASH control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock_NS(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Set the LOCK Bit to lock the FLASH Control Register access */ + SET_BIT(FLASH->NSCR, FLASH_CR_LOCK); + + /* Verify Flash is locked */ + if (READ_BIT(FLASH->NSCR, FLASH_CR_LOCK) == 0U) + { + status = HAL_ERROR; + } + return status; +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Unlock the secure FLASH control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock_S(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (READ_BIT(FLASH->SECCR, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Control Register access */ + WRITE_REG(FLASH->SECKEYR, FLASH_KEY1); + WRITE_REG(FLASH->SECKEYR, FLASH_KEY2); + + /* verify Flash CR is unlocked */ + if (READ_BIT(FLASH->SECCR, FLASH_CR_LOCK) != 0U) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Lock the secure FLASH control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock_S(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Set the LOCK Bit to lock the FLASH Control Register access */ + SET_BIT(FLASH->SECCR, FLASH_CR_LOCK); + + /* verify Flash is locked */ + if (READ_BIT(FLASH->SECCR, FLASH_CR_LOCK) == 0U) + { + status = HAL_ERROR; + } + + return status; +} +#endif /* __ARM_FEATURE_CMSE && __ARM_FEATURE_CMSE == 3U */ + /** * @brief Unlock the FLASH Option Control Registers access. * @retval HAL Status diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c index 9006937e5b..213fcb2da3 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c @@ -135,6 +135,9 @@ (#) To check if I2C target device is ready for communication, use the function HAL_I3C_Ctrl_IsDeviceI2C_Ready() (#) To send a message header {S + 0x7E + W + STOP}, use the function HAL_I3C_Ctrl_GenerateArbitration(). + + (#) To send a target reset pattern or HDR exit pattern, use the function HAL_I3C_Ctrl_GeneratePattern(). + (#) To insert a target reset pattern before the STOP of a transmitted frame containing a RSTACT CCC command, the application must enable the reset pattern configuration using HAL_I3C_Ctrl_SetConfigResetPattern() before calling HAL_I3C_Ctrl_TransmitCCC() or HAL_I3C_Ctrl_ReceiveCCC() interfaces. @@ -1615,10 +1618,14 @@ void HAL_I3C_ER_IRQHandler(I3C_HandleTypeDef *hi3c) */ void HAL_I3C_EV_IRQHandler(I3C_HandleTypeDef *hi3c) /* Derogation MISRAC2012-Rule-8.13 */ { +#if defined(I3C_MISR_CFNFMIS) + uint32_t it_masks = READ_REG(hi3c->Instance->MISR); +#else uint32_t it_flags = READ_REG(hi3c->Instance->EVR); uint32_t it_sources = READ_REG(hi3c->Instance->IER); uint32_t it_masks = (uint32_t)(it_flags & it_sources); +#endif /* I3C_MISR_CFNFMIS */ /* I3C events treatment */ if (hi3c->XferISR != NULL) @@ -1911,6 +1918,11 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Config(I3C_HandleTypeDef *hi3c, const I3C_CtrlCon assert_param(IS_I3C_DYNAMICADDRESS_VALUE(pConfig->DynamicAddr)); assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->HighKeeperSDA)); assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->HotJoinAllowed)); +#if defined(I3C_TIMINGR2_STALLL) + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->ACKI2CAddrState)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->ACKI2CWriteState)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->ACKI2CReadState)); +#endif /* I3C_TIMINGR2_STALLL */ assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->ACKStallState)); assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->CCCStallState)); assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->TxStallState)); @@ -1921,6 +1933,11 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Config(I3C_HandleTypeDef *hi3c, const I3C_CtrlCon /* Calculate value to be written in timing register 2 */ timing2_value = (((uint32_t)pConfig->StallTime << I3C_TIMINGR2_STALL_Pos) | +#if defined(I3C_TIMINGR2_STALLL) + ((uint32_t)pConfig->ACKI2CAddrState << I3C_TIMINGR2_STALLL_Pos) | + ((uint32_t)pConfig->ACKI2CWriteState << I3C_TIMINGR2_STALLS_Pos) | + ((uint32_t)pConfig->ACKI2CReadState << I3C_TIMINGR2_STALLR_Pos) | +#endif /* I3C_TIMINGR2_STALLL */ ((uint32_t)pConfig->ACKStallState << I3C_TIMINGR2_STALLA_Pos) | ((uint32_t)pConfig->CCCStallState << I3C_TIMINGR2_STALLC_Pos) | ((uint32_t)pConfig->TxStallState << I3C_TIMINGR2_STALLD_Pos) | @@ -2716,6 +2733,8 @@ HAL_StatusTypeDef HAL_I3C_GetConfigFifo(I3C_HandleTypeDef *hi3c, I3C_FifoConfTyp during the Dynamic Address Assignment processus. (+) Call the function HAL_I3C_Ctrl_IsDeviceI3C_Ready() to check if I3C target device is ready. (+) Call the function HAL_I3C_Ctrl_IsDeviceI2C_Ready() to check if I2C target device is ready. + (+) Call the function HAL_I3C_Ctrl_GeneratePatterns() to send target reset pattern or HDR exit pattern with + arbitration in polling mode (+) Call the function HAL_I3C_Ctrl_GenerateArbitration to send arbitration (message header {S + 0x7E + W + STOP}) in polling mode @@ -5118,6 +5137,8 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign(I3C_HandleTypeDef *hi3c, /* Check TX FIFO not full flag */ if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_TXFNFF) == SET) { + *target_payload = 0UL; + /* Check on the Rx FIFO threshold to know the Rx treatment process : byte or word */ if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) { @@ -5352,6 +5373,123 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI2C_Ready(I3C_HandleTypeDef *hi3c, return status; } +/** + * @brief Controller generates patterns (target reset pattern or HDR exit pattern) with arbitration in polling mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains + * the configuration information for the specified I3C. + * @param pattern : [IN] Specifies the generated pattern. + * It can be a value of @ref I3C_PATTERN_CONFIGURATION + * @param timeout : [IN] Timeout duration + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_GeneratePatterns(I3C_HandleTypeDef *hi3c, uint32_t pattern, uint32_t timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_I3C_StateTypeDef handle_state; + __IO uint32_t exit_condition; + uint32_t tickstart; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + assert_param(IS_I3C_PATTERN(pattern)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* check on the Mode */ + if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + hi3c->State = HAL_I3C_STATE_BUSY; + + /* The target reset pattern is sent after the issued message header */ + if (pattern == HAL_I3C_TARGET_RESET_PATTERN) + { + /* Enable reset pattern */ + LL_I3C_EnableResetPattern(hi3c->Instance); + + /* Disable exit pattern */ + LL_I3C_DisableExitPattern(hi3c->Instance); + } + /* The HDR exit pattern is sent after the issued message header */ + else + { + /* Disable reset pattern */ + LL_I3C_DisableResetPattern(hi3c->Instance); + + /* Enable exit pattern */ + LL_I3C_EnableExitPattern(hi3c->Instance); + } + + /* Write message control register */ + WRITE_REG(hi3c->Instance->CR, LL_I3C_CONTROLLER_MTYPE_HEADER | LL_I3C_GENERATE_STOP); + + /* Calculate exit_condition value based on Frame complete and error flags */ + exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF)); + + tickstart = HAL_GetTick(); + + while (exit_condition == 0U) + { + if (timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U)) + { + /* Update I3C error code */ + hi3c->ErrorCode |= HAL_I3C_ERROR_TIMEOUT; + status = HAL_TIMEOUT; + + break; + } + } + /* Calculate exit_condition value based on Frame complete and error flags */ + exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF)); + } + + if (status == HAL_OK) + { + /* Check if the FCF flag has been set */ + if (__HAL_I3C_GET_FLAG(hi3c, I3C_EVR_FCF) == SET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + } + else + { + /* Clear error flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + + /* Update handle error code parameter */ + I3C_GetErrorSources(hi3c); + + /* Update returned status value */ + status = HAL_ERROR; + } + } + /* At the end of Rx process update state to Previous state */ + I3C_StateUpdate(hi3c); + } + } + + return status; +} /** * @brief Controller generates arbitration (message header {S/Sr + 0x7E addr + W}) in polling mode. @@ -7177,14 +7315,22 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin uint32_t tmpevent = 0U; /* I3C Rx FIFO not empty interrupt Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_RXFNEMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Call receive treatment function */ hi3c->ptrRxFunc(hi3c); } /* I3C target complete controller-role hand-off procedure (direct GETACCR CCC) event management --------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_CRUPDMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRUPDF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear controller-role update flag */ LL_I3C_ClearFlag_CRUPD(hi3c->Instance); @@ -7194,7 +7340,11 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive any direct GETxxx CCC event management -------------------------------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_GETMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_GETF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear GETxxx CCC flag */ LL_I3C_ClearFlag_GET(hi3c->Instance); @@ -7204,7 +7354,11 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive get status command (direct GETSTATUS CCC) event management -----------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_STAMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_STAF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear GETSTATUS CCC flag */ LL_I3C_ClearFlag_STA(hi3c->Instance); @@ -7214,7 +7368,11 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive a dynamic address update (ENTDAA/RSTDAA/SETNEWDA CCC) event management -----------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_DAUPDMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_DAUPDF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear dynamic address update flag */ LL_I3C_ClearFlag_DAUPD(hi3c->Instance); @@ -7224,7 +7382,11 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive maximum write length update (direct SETMWL CCC) event management -----------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_MWLUPDMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_MWLUPDF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear SETMWL CCC flag */ LL_I3C_ClearFlag_MWLUPD(hi3c->Instance); @@ -7234,7 +7396,11 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive maximum read length update(direct SETMRL CCC) event management -------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_MRLUPDMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_MRLUPDF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear SETMRL CCC flag */ LL_I3C_ClearFlag_MRLUPD(hi3c->Instance); @@ -7244,7 +7410,11 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target detect reset pattern (broadcast or direct RSTACT CCC) event management -------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_RSTMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_RSTF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear reset pattern flag */ LL_I3C_ClearFlag_RST(hi3c->Instance); @@ -7254,7 +7424,11 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive activity state update (direct or broadcast ENTASx) CCC event management ----------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_ASUPDMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_ASUPDF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear ENTASx CCC flag */ LL_I3C_ClearFlag_ASUPD(hi3c->Instance); @@ -7264,7 +7438,11 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive a direct or broadcast ENEC/DISEC CCC event management ----------------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_INTUPDMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_INTUPDF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear ENEC/DISEC CCC flag */ LL_I3C_ClearFlag_INTUPD(hi3c->Instance); @@ -7274,7 +7452,11 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive a broadcast DEFTGTS CCC event management -----------------------------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_DEFMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_DEFF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear DEFTGTS CCC flag */ LL_I3C_ClearFlag_DEF(hi3c->Instance); @@ -7284,7 +7466,11 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive a group addressing (broadcast DEFGRPA CCC) event management ----------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_GRPMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_GRPF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear DEFGRPA CCC flag */ LL_I3C_ClearFlag_GRP(hi3c->Instance); @@ -7294,7 +7480,11 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target wakeup event management ----------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_WKPMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear WKP flag */ LL_I3C_ClearFlag_WKP(hi3c->Instance); @@ -7330,7 +7520,11 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin static HAL_StatusTypeDef I3C_Ctrl_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* I3C controller receive IBI event management ---------------------------------------------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_IBIMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear IBI request flag */ LL_I3C_ClearFlag_IBI(hi3c->Instance); @@ -7345,7 +7539,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Event_ISR(struct __I3C_HandleTypeDef *hi3c, ui } /* I3C controller controller-role request event management ---------------------------------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_CRMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear controller-role request flag */ LL_I3C_ClearFlag_CR(hi3c->Instance); @@ -7360,7 +7558,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Event_ISR(struct __I3C_HandleTypeDef *hi3c, ui } /* I3C controller hot-join event management ------------------------------------------------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_HJMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_HJF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear hot-join flag */ LL_I3C_ClearFlag_HJ(hi3c->Instance); @@ -7390,7 +7592,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Event_ISR(struct __I3C_HandleTypeDef *hi3c, ui static HAL_StatusTypeDef I3C_Tgt_HotJoin_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* I3C target receive a dynamic address update event management */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_DAUPDMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_DAUPDF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear dynamic address update flag */ LL_I3C_ClearFlag_DAUPD(hi3c->Instance); @@ -7435,7 +7641,11 @@ static HAL_StatusTypeDef I3C_Tgt_HotJoin_ISR(struct __I3C_HandleTypeDef *hi3c, u static HAL_StatusTypeDef I3C_Tgt_CtrlRole_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* I3C target complete controller-role hand-off procedure (direct GETACCR CCC) event management -------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_CRUPDMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRUPDF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear controller-role update flag */ LL_I3C_ClearFlag_CRUPD(hi3c->Instance); @@ -7469,7 +7679,11 @@ static HAL_StatusTypeDef I3C_Tgt_CtrlRole_ISR(struct __I3C_HandleTypeDef *hi3c, static HAL_StatusTypeDef I3C_Tgt_IBI_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* I3C target IBI end process event management ---------------------------------------------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_IBIENDMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIENDF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear IBI end flag */ LL_I3C_ClearFlag_IBIEND(hi3c->Instance); @@ -7506,7 +7720,11 @@ static HAL_StatusTypeDef I3C_Tgt_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32 if (hi3c->State == HAL_I3C_STATE_BUSY_TX) { /* I3C Tx FIFO not full interrupt Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_TXFNFMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { if (hi3c->TxXferCount > 0U) { @@ -7516,7 +7734,11 @@ static HAL_StatusTypeDef I3C_Tgt_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32 } /* I3C target frame complete event Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_FCMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7549,7 +7771,11 @@ static HAL_StatusTypeDef I3C_Tgt_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32 } /* I3C target wakeup event management ----------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_WKPMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear WKP flag */ LL_I3C_ClearFlag_WKP(hi3c->Instance); @@ -7580,7 +7806,11 @@ static HAL_StatusTypeDef I3C_Tgt_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32 if (hi3c->State == HAL_I3C_STATE_BUSY_RX) { /* I3C Rx FIFO not empty interrupt Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_RXFNEMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { if (hi3c->RxXferCount > 0U) { @@ -7590,7 +7820,11 @@ static HAL_StatusTypeDef I3C_Tgt_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32 } /* I3C target frame complete event Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_FCMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7623,7 +7857,11 @@ static HAL_StatusTypeDef I3C_Tgt_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32 } /* I3C target wakeup event management ----------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_WKPMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear WKP flag */ LL_I3C_ClearFlag_WKP(hi3c->Instance); @@ -7655,7 +7893,11 @@ static HAL_StatusTypeDef I3C_Tgt_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, ui if (hi3c->State == HAL_I3C_STATE_BUSY_TX) { /* I3C target frame complete event Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_FCMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7691,7 +7933,11 @@ static HAL_StatusTypeDef I3C_Tgt_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, ui } /* I3C target wakeup event management ----------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_WKPMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear WKP flag */ LL_I3C_ClearFlag_WKP(hi3c->Instance); @@ -7722,7 +7968,11 @@ static HAL_StatusTypeDef I3C_Tgt_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, ui if (hi3c->State == HAL_I3C_STATE_BUSY_RX) { /* I3C target frame complete event Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_FCMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7758,7 +8008,11 @@ static HAL_StatusTypeDef I3C_Tgt_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, ui } /* I3C target wakeup event management ----------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_WKPMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear WKP flag */ LL_I3C_ClearFlag_WKP(hi3c->Instance); @@ -7790,7 +8044,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 if (hi3c->State == HAL_I3C_STATE_BUSY_TX) { /* Check if Control FIFO requests data */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_CFNFMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CFNFF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { if (hi3c->ControlXferCount > 0U) { @@ -7800,7 +8058,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 } /* I3C Tx FIFO not full interrupt Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_TXFNFMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { if (hi3c->TxXferCount > 0U) { @@ -7810,7 +8072,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 } /* I3C target frame complete event Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_FCMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7865,7 +8131,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 if (hi3c->State == HAL_I3C_STATE_BUSY_RX) { /* Check if Control FIFO requests data */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_CFNFMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CFNFF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { if (hi3c->ControlXferCount > 0U) { @@ -7875,7 +8145,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 } /* I3C Rx FIFO not empty interrupt Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_RXFNEMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { if (hi3c->RxXferCount > 0U) { @@ -7885,7 +8159,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 } /* I3C Tx FIFO not full interrupt Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_TXFNFMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { if (hi3c->TxXferCount > 0U) { @@ -7895,7 +8173,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 } /* I3C target frame complete event Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_FCMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7949,7 +8231,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef * if (hi3c->State == HAL_I3C_STATE_BUSY_TX_RX) { /* Check if Control FIFO requests data */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_CFNFMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CFNFF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { if (hi3c->ControlXferCount > 0U) { @@ -7959,7 +8245,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef * } /* I3C Tx FIFO not full interrupt Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_TXFNFMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { if (hi3c->TxXferCount > 0U) { @@ -7969,7 +8259,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef * } /* I3C Rx FIFO not empty interrupt Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_RXFNEMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { if (hi3c->RxXferCount > 0U) { @@ -7979,7 +8273,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef * } /* I3C target frame complete event Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_FCMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -8027,7 +8325,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef * static HAL_StatusTypeDef I3C_Ctrl_Tx_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* I3C controller receive IBI event management ---------------------------------------------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_IBIMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear IBI request flag */ LL_I3C_ClearFlag_IBI(hi3c->Instance); @@ -8042,7 +8344,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Tx_Listen_Event_ISR(struct __I3C_HandleTypeDef } /* I3C controller controller-role request event management ---------------------------------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_CRMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear controller-role request flag */ LL_I3C_ClearFlag_CR(hi3c->Instance); @@ -8057,7 +8363,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Tx_Listen_Event_ISR(struct __I3C_HandleTypeDef } /* I3C controller hot-join event management ------------------------------------------------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_HJMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_HJF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear hot-join flag */ LL_I3C_ClearFlag_HJ(hi3c->Instance); @@ -8085,7 +8395,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Tx_Listen_Event_ISR(struct __I3C_HandleTypeDef static HAL_StatusTypeDef I3C_Ctrl_Rx_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* I3C controller receive IBI event management ---------------------------------------------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_IBIMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear IBI request flag */ LL_I3C_ClearFlag_IBI(hi3c->Instance); @@ -8100,7 +8414,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_Listen_Event_ISR(struct __I3C_HandleTypeDef } /* I3C controller controller-role request event management ---------------------------------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_CRMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear controller-role request flag */ LL_I3C_ClearFlag_CR(hi3c->Instance); @@ -8115,7 +8433,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_Listen_Event_ISR(struct __I3C_HandleTypeDef } /* I3C controller hot-join event management ------------------------------------------------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_HJMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_HJF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear hot-join flag */ LL_I3C_ClearFlag_HJ(hi3c->Instance); @@ -8144,7 +8466,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_Listen_Event_ISR(struct __I3C_HandleTypeDef static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* I3C controller receive IBI event management ---------------------------------------------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_IBIMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear IBI request flag */ LL_I3C_ClearFlag_IBI(hi3c->Instance); @@ -8159,7 +8485,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_Listen_Event_ISR(struct __I3C_Ha } /* I3C controller controller-role request event management ---------------------------------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_CRMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear controller-role request flag */ LL_I3C_ClearFlag_CR(hi3c->Instance); @@ -8174,7 +8504,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_Listen_Event_ISR(struct __I3C_Ha } /* I3C controller hot-join event management ------------------------------------------------------------------------*/ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_HJMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_HJF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear hot-join flag */ LL_I3C_ClearFlag_HJ(hi3c->Instance); @@ -8206,14 +8540,22 @@ static HAL_StatusTypeDef I3C_Ctrl_DAA_ISR(struct __I3C_HandleTypeDef *hi3c, uint if (hi3c->State == HAL_I3C_STATE_BUSY_DAA) { /* I3C Control FIFO not full interrupt Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_CFNFMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CFNFF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Write ENTDAA CCC information in the control register */ LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_ENTDAA, 0U, LL_I3C_GENERATE_STOP); } /* I3C Tx FIFO not full interrupt Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_TXFNFMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Check on the Rx FIFO threshold to know the Dynamic Address Assignment treatment process : byte or word */ if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) @@ -8243,7 +8585,11 @@ static HAL_StatusTypeDef I3C_Ctrl_DAA_ISR(struct __I3C_HandleTypeDef *hi3c, uint } /* I3C frame complete event Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_FCMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -8281,7 +8627,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, u if (hi3c->State == HAL_I3C_STATE_BUSY_TX) { /* I3C target frame complete event Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_FCMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -8349,7 +8699,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, u if (hi3c->State == HAL_I3C_STATE_BUSY_RX) { /* I3C target frame complete event Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_FCMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -8417,7 +8771,11 @@ static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_DMA_ISR(struct __I3C_HandleTypeD if (hi3c->State == HAL_I3C_STATE_BUSY_TX_RX) { /* I3C target frame complete event Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_FCMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -8492,7 +8850,11 @@ static HAL_StatusTypeDef I3C_Abort_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_ if (hi3c->State == HAL_I3C_STATE_ABORT) { /* I3C Rx FIFO not empty interrupt Check */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_RXFNEMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { if (LL_I3C_IsActiveFlag_DOVR(hi3c->Instance) == 1U) { @@ -8504,7 +8866,11 @@ static HAL_StatusTypeDef I3C_Abort_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_ /* I3C Abort frame complete event Check */ /* Evenif abort is called, the Frame completion can arrive if abort is requested at the end of the processus */ /* Evenif completion occurs, treat this end of processus as abort completion process */ +#if defined(I3C_MISR_CFNFMIS) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_IT_MASKS_FCMIS) != RESET) +#else if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) +#endif /* I3C_MISR_CFNFMIS */ { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_mmc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_mmc.c index 6dd5f5d097..46666f52c7 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_mmc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_mmc.c @@ -516,7 +516,14 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) hmmc->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; return HAL_ERROR; } - Init.ClockDiv = sdmmc_clk / (2U * MMC_INIT_FREQ); + if (sdmmc_clk <= MMC_INIT_FREQ) + { + Init.ClockDiv = 0U; + } + else + { + Init.ClockDiv = (sdmmc_clk / (2U * MMC_INIT_FREQ)) + 1U; + } #if (USE_SD_TRANSCEIVER != 0U) Init.TranceiverPresent = SDMMC_TRANSCEIVER_NOT_PRESENT; @@ -3381,7 +3388,7 @@ HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc) { /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and SLEEP as argument */ errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, - ((hmmc->MmcCard.RelCardAdd << 16U) | (0x1UL << 15U))); + ((hmmc->MmcCard.RelCardAdd << 16UL) | (0x1UL << 15UL))); if (errorstate == HAL_MMC_ERROR_NONE) { /* Wait that the device is ready by checking the D0 line */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c index 9b882a8fb7..f791018f73 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c @@ -525,6 +525,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_Ad uint32_t deviceaddress; uint32_t nandaddress; uint32_t nbpages = NumPageToRead; + uint32_t status; uint8_t *buff = pBuffer; /* Check the NAND controller state */ @@ -615,9 +616,11 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_Ad tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -625,9 +628,28 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_Ad /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } + + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Go back to read mode */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); @@ -679,6 +701,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_A uint32_t deviceaddress; uint32_t nandaddress; uint32_t nbpages = NumPageToRead; + uint32_t status; uint16_t *buff = pBuffer; /* Check the NAND controller state */ @@ -768,9 +791,11 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_A tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -778,9 +803,28 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_A /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } + + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Go back to read mode */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); @@ -843,6 +887,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_A uint32_t deviceaddress; uint32_t nandaddress; uint32_t nbpages = NumPageToWrite; + uint32_t status; const uint8_t *buff = pBuffer; /* Check the NAND controller state */ @@ -940,9 +985,11 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_A tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -950,9 +997,28 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_A /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } + + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Decrement pages to write */ nbpages--; @@ -992,6 +1058,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_ uint32_t deviceaddress; uint32_t nandaddress; uint32_t nbpages = NumPageToWrite; + uint32_t status; const uint16_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1100,9 +1167,11 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_ tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -1110,9 +1179,28 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_ /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } + + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Decrement pages to write */ nbpages--; @@ -1153,6 +1241,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NA uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaToRead; + uint32_t status; uint8_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1249,9 +1338,11 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NA tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -1259,9 +1350,28 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NA /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } + + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Go back to read mode */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); @@ -1314,6 +1424,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const N uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaToRead; + uint32_t status; uint16_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1410,9 +1521,11 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const N tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -1420,9 +1533,28 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const N /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } + + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Go back to read mode */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); @@ -1475,6 +1607,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const N uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaTowrite; + uint32_t status; const uint8_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1581,9 +1714,11 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const N tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -1591,9 +1726,28 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const N /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } + + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Decrement spare areas to write */ nbspare--; @@ -1634,6 +1788,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaTowrite; + uint32_t status; const uint16_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1740,9 +1895,11 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -1750,9 +1907,28 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } + + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Decrement spare areas to write */ nbspare--; @@ -1873,13 +2049,11 @@ uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeD * @param hnand : NAND handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: - * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID (*) - * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID (*) - * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID (*) + * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID + * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID + * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID * @param pCallback : pointer to the Callback function * @retval status - * - * (*) : For all h5 series */ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback) @@ -1941,12 +2115,10 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_ * @param hnand : NAND handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: - * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID (*) - * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID (*) - * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID (*) + * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID + * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID + * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID * @retval status - * - * (*) : For all h5 series */ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId) { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nor.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nor.c index 28b07eae8c..c70f37a789 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nor.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nor.c @@ -24,7 +24,7 @@ [..] This driver is a generic layered driver which contains a set of APIs used to control NOR flash memories. It uses the FMC layer functions to interface - with NOR devices. This driver is used as follows: + with NOR 16-bit devices. The NOR 8-bit support is deprecated. This driver is used as follows: (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() with control and timing parameters for both normal and extended mode. @@ -127,11 +127,6 @@ */ /* Constants to define address to set to write a command */ -#define NOR_CMD_ADDRESS_FIRST_BYTE (uint16_t)0x0AAA -#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE (uint16_t)0x00AA -#define NOR_CMD_ADDRESS_SECOND_BYTE (uint16_t)0x0555 -#define NOR_CMD_ADDRESS_THIRD_BYTE (uint16_t)0x0AAA - #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA @@ -196,8 +191,6 @@ * @{ */ -static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; - /** * @} */ @@ -243,6 +236,12 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe return HAL_ERROR; } + /* Check if deprecated 8-bit support is used */ + if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8) + { + return HAL_ERROR; + } + if (hnor->State == HAL_NOR_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -275,16 +274,6 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe /* Enable the NORSRAM device */ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); - /* Initialize NOR Memory Data Width*/ - if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8) - { - uwNORMemoryDataWidth = NOR_MEMORY_8B; - } - else - { - uwNORMemoryDataWidth = NOR_MEMORY_16B; - } - /* Enable FMC Peripheral */ __FMC_ENABLE(); @@ -319,17 +308,9 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe else { /* Get the value of the command set */ - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), - NOR_CMD_DATA_CFI); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); + hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_ADDRESS_COMMAND_SET); status = HAL_NOR_ReturnToReadMode(hnor); } @@ -490,22 +471,9 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I /* Send read ID command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_AUTO_SELECT); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_AUTO_SELECT); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -520,13 +488,10 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I if (status != HAL_ERROR) { /* Read the NOR IDs */ - pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); - pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, - DEVICE_CODE1_ADDR); - pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, - DEVICE_CODE2_ADDR); - pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, - DEVICE_CODE3_ADDR); + pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, MC_ADDRESS); + pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, DEVICE_CODE1_ADDR); + pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, DEVICE_CODE2_ADDR); + pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, DEVICE_CODE3_ADDR); } /* Check the NOR controller state */ @@ -672,22 +637,9 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint /* Send read data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_READ_RESET); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_READ_RESET); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -702,7 +654,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint if (status != HAL_ERROR) { /* Read the data */ - *pData = (uint16_t)(*(__IO uint32_t *)pAddress); + *pData = NOR_READ(pAddress); } /* Check the NOR controller state */ @@ -766,21 +718,9 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u /* Send program data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_PROGRAM); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -870,22 +810,9 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress /* Send read data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_READ_RESET); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_READ_RESET); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -978,20 +905,10 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - } - else - { - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - } + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + /* Write Buffer Load Command */ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); @@ -1091,26 +1008,15 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd /* Send block erase command sequence */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) @@ -1188,28 +1094,16 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) /* Send NOR chip erase command sequence */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), - NOR_CMD_DATA_CHIP_ERASE); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SIXTH), + NOR_CMD_DATA_CHIP_ERASE); } else { @@ -1280,20 +1174,13 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR } /* Send read CFI query command */ - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), - NOR_CMD_DATA_CFI); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + /* read the NOR CFI information */ - pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); - pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); - pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS); - pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS); + pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, CFI1_ADDRESS); + pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, CFI2_ADDRESS); + pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, CFI3_ADDRESS); + pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, CFI4_ADDRESS); /* Check the NOR controller state */ hnor->State = state; @@ -1316,12 +1203,10 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR * @param hnor : NOR handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: - * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID (*) - * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID (*) + * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID + * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID * @param pCallback : pointer to the Callback function * @retval status - * - * (*) : For all h5 series */ HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback) @@ -1366,11 +1251,9 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Call * @param hnor : NOR handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: - * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID (*) - * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID (*) + * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID + * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID * @retval status - * - * (*) : For all h5 series */ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId) { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c index 4c01dba4f0..2de839d7a7 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c @@ -791,7 +791,7 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) status = HAL_ERROR; } - return status; + return status; } /** @@ -1583,6 +1583,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + /* store current frame number */ + hpcd->FrameNumber = USB_GetCurrentFrame(hpcd->Instance); + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else @@ -2474,6 +2477,9 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) count = 0U; #endif /* USE_USB_DOUBLE_BUFFER */ + /* store current frame number */ + hpcd->FrameNumber = USB_GetCurrentFrame(hpcd->Instance); + /* stay in loop while pending interrupts */ while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) { @@ -2482,6 +2488,11 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_IDN); + if (epindex >= 8U) + { + return HAL_ERROR; + } + if (epindex == 0U) { /* Decode and service control endpoint interrupt */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pka.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pka.c index 19c742326e..235012b14a 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pka.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pka.c @@ -277,6 +277,9 @@ */ #define PKA_RAM_SIZE 1334U #define PKA_RAM_ERASE_TIMEOUT 1000U +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +#define PKA_RNG_TIMEOUT_VALUE 2U +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ /* Private macro -------------------------------------------------------------*/ #define __PKA_RAM_PARAM_END(TAB,INDEX) do{ \ @@ -324,6 +327,9 @@ void PKA_ECCCompleteAddition_Set(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditio HAL_StatusTypeDef PKA_WaitOnFlagUntilTimeout(PKA_HandleTypeDef *hpka, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); uint32_t PKA_Result_GetSize(const PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize); +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +HAL_StatusTypeDef PKA_RNG_ResilientRecoverSeedError(void); +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ /** * @} */ @@ -393,6 +399,17 @@ HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka) HAL_PKA_MspInit(hpka); #endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ } +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (PKA_RNG_ResilientRecoverSeedError() != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ /* Set the state to busy */ hpka->State = HAL_PKA_STATE_BUSY; @@ -526,6 +543,18 @@ __weak void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka) /* Release PKA from reset state */ __HAL_RCC_PKA_RELEASE_RESET(); +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (PKA_RNG_ResilientRecoverSeedError() != HAL_OK) + { + hpka->State = HAL_PKA_STATE_ERROR; + } + } + +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ /* Wait the INITOK flag Setting */ while (hpka->Instance->CR != PKA_CR_EN) { @@ -2389,20 +2418,20 @@ void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef /* Move the input parameters pOp1 to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + ((in->OpSize + 3UL) / 4UL)); /* Move the exponent to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + ((in->expSize + 3UL) / 4UL)); /* Move the modulus to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + ((in->OpSize + 3UL) / 4UL)); /* Move the Montgomery parameter to PKA RAM */ PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, in->OpSize / 4UL); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + ((in->OpSize + 3UL) / 4UL)); } /** @@ -2420,19 +2449,19 @@ void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInT /* Move the input parameters pOp1 to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE], in->pOp1, in->OpSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + ((in->OpSize + 3UL) / 4UL)); /* Move the exponent to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT], in->pExp, in->expSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + (in->expSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + ((in->expSize + 3UL) / 4UL)); /* Move the modulus to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_MODULUS], in->pMod, in->OpSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_MODULUS + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_MODULUS + ((in->OpSize + 3UL) / 4UL)); /* Move Phi value to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI], in->pPhi, in->OpSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + ((in->OpSize + 3UL) / 4UL)); } /** @@ -3066,6 +3095,179 @@ uint32_t PKA_Result_GetSize(const PKA_HandleTypeDef *hpka, uint32_t Startindex, return size; } +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +/** + * @brief RNG sequence to resilient recover from a seed error + * @retval HAL status + */ +HAL_StatusTypeDef PKA_RNG_ResilientRecoverSeedError(void) +{ + uint32_t timeout; + uint32_t htsr_temp = 0U; + uint32_t htsr_previous_temp = 0U; + uint32_t htsr_count = 0U; + uint32_t nsmr_temp = 0U; + uint32_t tickstart1 = 0U; + uint32_t tickstart2 = 0U; + uint32_t tickstart3 = 0U; + uint32_t oscillators_count = 0U; + uint32_t config_b_fewer_than_6_osc_count = 0U; + uint8_t count = 0U; + + /* timeout here is an emperic value */ + timeout = (1UL + ((1UL << (READ_BIT(RNG->CR, RNG_CR_CLKDIV) >> 16UL)) * PKA_RNG_TIMEOUT_VALUE / 8UL)); + LL_RNG_Enable(RNG); + + tickstart1 = HAL_GetTick(); + + /* Check if seed error current status indicates no error and auto-reset succeeded */ + if (LL_RNG_IsActiveFlag_SECS(RNG) == 0U) + { + /* Clear SEIS flag when automatic reset is activated */ + LL_RNG_ClearFlag_SEIS(RNG); + } + + else /* Sequence to fully recover from a seed error*/ + { + if (LL_RNG_IsConfigLocked(RNG) == 0U) + { + do + { + if (LL_RNG_IsActiveFlag_SECS(RNG) == 0U) + { + break; + } + /* Read oscillator status registers combined */ + htsr_temp = LL_RNG_GetHealthTestStatus(RNG, 0U); + htsr_temp |= LL_RNG_GetHealthTestStatus(RNG, 1U); + if (htsr_temp > 0U) + { + /* If any oscillator status bits overlap with previous status, increment counter */ + if ((htsr_temp & htsr_previous_temp) != 0U) + { + htsr_count++; + } + + if (htsr_count > 3U) + { + /* if the same repetitive or adaptative error is detected 3 times */ + nsmr_temp = LL_RNG_GetNoiseSourceMask(RNG); + + /* deactivate the same osc in each triple oscillator (Mask oscillators with the seed error by + clearing bits shifted right by 1) */ + nsmr_temp = nsmr_temp & ~(htsr_temp >> 1U); + + /* Count the number of active oscillators in nsmr */ + oscillators_count = 0U; + for (count = 0U; count < 9U; count++) + { + if (((nsmr_temp >> count) & 0x1U) != 0U) + { + /* increment count1 for each 1 in nsmr */ + oscillators_count++; + } + } + + if (oscillators_count < 6U) + { + /* If fewer than 6 oscillators remain active, unmask all oscillators --> Reset masking */ + nsmr_temp = LL_RNG_GetOscNoiseSrc(RNG, LL_RNG_NOISE_SRC_1 | LL_RNG_NOISE_SRC_2 \ + | LL_RNG_NOISE_SRC_3); + htsr_previous_temp = 0; + htsr_count = 0U; + if ((RNG->CR & RNG_CR_CLKDIV_Msk) < ((uint32_t)RNG_CAND_NIST_CR_VALUE & RNG_CR_CLKDIV_Msk)) + { + config_b_fewer_than_6_osc_count++; + } + } + + if (config_b_fewer_than_6_osc_count > 2U) + { + /* Reset RNG condition */ + WRITE_REG(RNG->CR, (RNG_CR_CONDRST_Msk | (uint32_t)RNG_CAND_NIST_CR_VALUE)); + + /* Update mask register with new oscillator mask */ + LL_RNG_SetNoiseSourceMask(RNG, nsmr_temp); + + /* Clear condition reset bit to resume operation */ + LL_RNG_DisableCondReset(RNG); + } + + else + { + /* Reset RNG condition */ + WRITE_REG(RNG->CR, (RNG->CR & ~RNG_CR_RNGEN_Msk) | RNG_CR_CONDRST_Msk); + + /* Update mask register with new oscillator mask */ + LL_RNG_SetNoiseSourceMask(RNG, nsmr_temp); + + /* Clear condition reset bit to resume operation */ + LL_RNG_DisableCondReset(RNG); + } + } + + else + { + /* Briefly toggle conditional reset to recover RNG */ + WRITE_REG(RNG->CR, (RNG->CR & ~RNG_CR_RNGEN_Msk) | RNG_CR_CONDRST_Msk); + + /* unmask all oscillators to find another working condition */ + LL_RNG_SetNoiseSourceMask(RNG, LL_RNG_GetOscNoiseSrc(RNG, LL_RNG_OSC_1\ + | LL_RNG_OSC_2 | LL_RNG_OSC_3)); + LL_RNG_DisableCondReset(RNG); + } + + /* Wait until RNG is not busy */ + tickstart2 = HAL_GetTick(); + do + { + if ((HAL_GetTick() - tickstart2) > PKA_RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + LL_RNG_Disable(RNG); + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(RNG->SR, RNG_SR_BUSY)); + + /* No timeout --> Enable RNG */ + LL_RNG_Enable(RNG); + tickstart3 = HAL_GetTick(); + do + { + if (LL_RNG_IsActiveFlag_DRDY(RNG) != 0UL) + { + break; + } + if ((HAL_GetTick() - tickstart3) > timeout) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_RNG_IsActiveFlag_DRDY(RNG) == 0UL) + { + if (LL_RNG_IsActiveFlag_SECS(RNG) == 0UL) + { + LL_RNG_Disable(RNG); + return HAL_ERROR; + } + } + } + } while (LL_RNG_IsActiveFlag_SECS(RNG) == 0UL); + + /* Accumulate seed error status bits */ + htsr_previous_temp = htsr_previous_temp | htsr_temp; + } + } while ((HAL_GetTick() - tickstart1) <= timeout); + } + } + + /*Check if seed error current status (SECS)is set */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + return HAL_ERROR; + } + + return HAL_OK; +} +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_play.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_play.c index e13ae48f49..2e935ff686 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_play.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_play.c @@ -29,52 +29,51 @@ [..] The PLAY HAL driver can be used as follows: - (#) Declare a HAL_PLAY_HandleTypeDef handle structure (eg. HAL_PLAY_HandleTypeDef hplay). - (#) Initialize the PLAY low level resources by implementing the HAL_PLAY_MspInit() API: - (##) Select the PLAY kernel clock source with RCC API - (##) Configure the PLAY kernel clock prescaler with RCC API - (##) Enable the PLAY interface clock using __HAL_RCC_PLAYx_CLK_ENABLE() + (#) Declare a HAL_PLAY_HandleTypeDef handle structure, for example: + HAL_PLAY_HandleTypeDef hplay; + (#) Initialize the PLAY low-level resources by implementing the HAL_PLAY_MspInit() API: + (##) Select the PLAY kernel clock source + (##) Configure the PLAY kernel clock prescaler + (##) Enable the PLAY interface clock (##) PLAY pins configuration: (+++) Enable the clock for the PLAY GPIOs - (+++) Configure these PLAY pins as alternate function + (+++) Configure PLAY pins as alternate function (##) NVIC configuration if you need to use interrupt process: (+++) Configure the PLAY interrupt priority. - (+++) Enable the NVIC PLAY IRQ handler. + (+++) Enable the NVIC PLAY IRQ. (##) Optionally, reset the peripheral either by a full reset of all registers or - by an "application" reset for only the functional registers (refer to the RCC API) + by an "application" reset for only the functional registers (refer to the RCC APIs) (#) Initialize PLAY registers by calling the HAL_PLAY_Init() API which calls HAL_PLAY_MspInit() (#) To configure PLAY, call the following APIs: - HAL_PLAY_INPUT_SetConfig() : to select the input signals and configure filters - - HAL_PLAY_LUT_SetConfig() : to configure the Look-Up Tables - - Finalize the configuration by calling the API HAL_PLAY_OUTPUT_SetConfig. - This one allows to output some Look-Up Table Outputs and - indicates that the peripheral is ready to start (handle state = HAL_PLAY_STATE_READY). + - HAL_PLAY_LUT_SetConfig() : to configure the Look-Up Tables (LUTs) + - Finalize the configuration by calling the API HAL_PLAY_OUTPUT_SetConfig(). + This one allows to output some Look-Up Table Outputs and + indicates that the peripheral is ready to start (handle state = @ref HAL_PLAY_STATE_READY). (#) After ending the configuration, start the PLAY with HAL_PLAY_Start() to: - - lock the PLAYx configuration registers to prevent any accidental write access. - The kernel clock becomes operational. Then LUT Synchronized Outputs, Filters, SW Triggers and Edge Triggers - become functional. - - set a first configuration of Edge Trigger on LUT Outputs. + - Lock the PLAYx configuration registers to prevent any accidental write access. + The kernel clock becomes operational: LUT registered outputs, filters, software triggers and edge triggers + are functional. + - Set a first configuration of edge trigger on LUT outputs. - At this step, the PLAY Outputs can be connected to GPIOs or internal IPs. + At this step, the PLAY Outputs can be connected to GPIOs or internal peripherals. - (#) Stop the PLAY with the API HAL_PLAY_Stop. - This function disables all Look-Up Table Output ITs and unlocks the configuration. - The handle state is back to HAL_PLAY_STATE_READY and allows the Application to update the peripheral. + (#) Stop the PLAY with the API HAL_PLAY_Stop(). + This function disables all Look-Up Table (LUT) output interrupts and unlocks the configuration. + The handle state is back to @ref HAL_PLAY_STATE_READY and allows the Application to update the peripheral. - Before updating the PLAY configuration, it is strongly recommended to disconnect all peripherals connected - to PLAY Outputs to avoid any glitches. + Disconnect all peripherals connected to PLAY outputs before updating the configuration to avoid glitches. - (#) At then end of the PLAY processor User application, call the function HAL_PLAY_DeInit() - to restore the default configuration which calls HAL_PLAY_MspDeInit(). + (#) At the end of the PLAY processor User application, call the function HAL_PLAY_DeInit() to restore the default + configuration which calls HAL_PLAY_MspDeInit(). *** Look-Up Table Output *** ============================ [..] - (+) The Truth Table of a Look-Up table is composed of 16 combinations (with 4 inputs): + (+) The Truth Table of a Look-Up Table is composed of 16 combinations (with 4 inputs): Combination ID | IN3 | IN2 | IN1 | IN0 | OUT O(y) -------------- | --- | --- | --- | --- | -------- 0 | 0 | 0 | 0 | 0 | O0 @@ -98,8 +97,8 @@ (O0 * 2^0) + (O1 * 2^1) + (O2 * 2^2) + ... + ((O15 * 2^15)) - There are several Truth Table values for a logic gate depending of the selected inputs. - For example the Truth Table value for the logic 'AND' are (non-exhaustive list): + There are several Truth Table values for a logic gate depending on the selected inputs. + For example the Truth Table values for the logic 'AND' are (non-exhaustive list): - for IN1 & IN0: 0x8888 - for IN2 & IN1: 0xC0C0 - for IN3 & IN2: 0xF000 @@ -107,32 +106,32 @@ - for IN3, IN2, IN1 & IN0: 0x8000 - ... (+) A Look-Up Table generates a single output which can be stored with a register. - Each output has a flag which is triggered on a Rising or Falling edge (depends of user configuration). + Each output has a flag which is triggered on a rising or falling edge (depending on the user configuration). - The best way to use PLAY is to use the LUT Output interrupts to be advise when an output is changed. - You can also configure the interrupt mode using the HAL_PLAY_OUTPUT_EnableIT() function. - When an IT is triggered the callback HAL_PLAY_LUTOutputRisingCallback() or HAL_PLAY_LUTOutputFallingCallback() - is called (depending of the edge trigger configuration). + The LUT output interrupts can be enabled to advise when an output state change using the + HAL_PLAY_OUTPUT_EnableIT() function. + When an interrupt is triggered, the callbacks HAL_PLAY_LUTOutputRisingCallback() + or HAL_PLAY_LUTOutputFallingCallback() are called (depending on the edge trigger configuration). - Otherwise, you can work in polling mode by using the HAL_PLAY_OUTPUT_PollForEdgeTrigger(), but the LUT output - could changed in the time frame between the end of polling and the treatment to do for the related output. + In polling mode, HAL_PLAY_OUTPUT_PollForEdgeTrigger() can be used, but the LUT output might change in the time + frame between the end of polling and the treatment to do for the related output. *** Callback registration *** ============================= [..] - The compilation define USE_HAL_PLAY_REGISTER_CALLBACKS, when set to 1, - allows the user to configure dynamically the driver callbacks. + The compilation define USE_HAL_PLAY_REGISTER_CALLBACKS, when set to 1, allows the user to configure + dynamically the driver callbacks. [..] Use the function HAL_PLAY_RegisterCallback() to register a callback taking only the HAL peripheral handle as parameter. - Use the function HAL_PLAY_RegisterLUTOutputCallback() to register a callback taking - 2 parameters (handle + uint32_t) and which is dedicated to perform action when almost a LUT Output state changed. + Use the function HAL_PLAY_RegisterLUTOutputCallback() to register a callback taking two parameters + (handle + uint32_t) and which is dedicated to perform action when almost a LUT Output state changed. Both HAL_PLAY_RegisterCallback() and HAL_PLAY_RegisterLUTOutputCallback() take as parameters: - - the HAL peripheral handle, - - the Callback ID, - - the pointer to the user callback function. + - The HAL peripheral handle + - The Callback ID + - The pointer to the user callback function [..] Use function HAL_PLAY_UnRegisterCallback() and HAL_PLAY_UnRegisterLUTOutputCallback() to reset a callback @@ -141,8 +140,8 @@ handle and the Callback ID. [..] - Use respectively, the functions HAL_PLAY_RegisterCallback() / HAL_PLAY_UnRegisterCallback(), - to register / unregister following callbacks: + Use respectively, the functions HAL_PLAY_RegisterCallback() / HAL_PLAY_UnRegisterCallback() to register or + unregister following callbacks: (+) MspInitCallback : PLAY MspInit. (+) MspDeInitCallback : PLAY MspDeInit. (+) SWTriggerWriteCpltCallback : Software Trigger Write Complete callback. @@ -151,31 +150,29 @@ [..] Use respectively, the functions HAL_PLAY_RegisterLUTOutputCallback() / HAL_PLAY_UnRegisterLUTOutputCallback(), to register / unregister following callbacks: - (+) HAL_PLAY_LUTOutputRisingCallback() : Look-Up Table Output Rising Edge triggered callback. - (+) HAL_PLAY_LUTOutputFallingCallback() : Look-Up Table Output Falling Edge triggered callback. + (+) HAL_PLAY_LUTOutputRisingCallback() : Look-Up Table output rising edge triggered callback. + (+) HAL_PLAY_LUTOutputFallingCallback() : Look-Up Table output falling edge triggered callback. [..] - By default, after the HAL_PLAY_Init and when the state is HAL_PLAY_STATE_RESET, - all callbacks are reset to the corresponding legacy weak functions. + By default, after the HAL_PLAY_Init() and when the state is @ref HAL_PLAY_STATE_RESET, all callbacks are reset + to the corresponding legacy weak functions. - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak function in the HAL_PLAY_Init() and HAL_PLAY_DeInit() only when - these callbacks are NULL (not registered beforehand). - If not, MspInit or MspDeInit are not NULL, the HAL_PLAY_Init() and HAL_PLAY_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + Exception done for MspInit and MspDeInit callbacks that are respectively reset to the legacy weak function in + the HAL_PLAY_Init() and HAL_PLAY_DeInit() only when these callbacks are NULL (not registered beforehand). + If not, MspInit or MspDeInit are not NULL, the HAL_PLAY_Init() and HAL_PLAY_DeInit() keep and use the user + MspInit/MspDeInit callbacks (registered beforehand). [..] - Callbacks can be registered/unregistered in HAL_PLAY_STATE_READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in HAL_PLAY_STATE_READY or HAL_PLAY_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case, first register the MspInit/MspDeInit user callbacks - using HAL_PLAY_RegisterCallback before calling HAL_PLAY_DeInit() or HAL_PLAY_Init() function. + Callbacks can be registered/unregistered in @ref HAL_PLAY_STATE_INIT and @ref HAL_PLAY_STATE_READY states only. + Exception done for MspInit/MspDeInit callbacks that can also be registered/unregistered in + @ref HAL_PLAY_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during + the Init/DeInit. + To do so, register the MspInit/MspDeInit user callbacks using HAL_PLAY_RegisterCallback() before calling + HAL_PLAY_DeInit() or HAL_PLAY_Init() functions. [..] - When the compilation define USE_HAL_PLAY_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available and all callbacks - are set to the corresponding weak functions. + When the compilation define USE_HAL_PLAY_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering + feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim ****************************************************************************** @@ -212,13 +209,13 @@ /** * @brief PLAY Interrupt Definition */ -#define PLAY_IT_STATUS_SW_TRIGGER_WRITE_COMPLETE LL_PLAY_IER_SWINWC_IEN /*!< Interrupt Software Trigger write complete */ -#define PLAY_IT_STATUS_EDGE_TRIGGER_WRITE_COMPLETE LL_PLAY_IER_FLCTLWC_IEN /*!< Interrupt Edge Trigger write complete */ +#define PLAY_IT_STATUS_SW_TRIGGER_WRITE_COMPLETE LL_PLAY_IER_SWINWC_IEN /*!< Software trigger write complete interrupt */ +#define PLAY_IT_STATUS_EDGE_TRIGGER_WRITE_COMPLETE LL_PLAY_IER_FLCTLWC_IEN /*!< Edge trigger write complete interrupt */ /** * @brief Maximum Timeout for any write on Software Trigger or Edge Trigger register. * - * With a LSI as PLAY kernel clock source and a prescaler of 32768, the play_clk cycle is 1s. + * With LSI as PLAY kernel clock source and a prescaler of 32768, the play_clk cycle is 1s. * A write takes 3 cycles of play_clk + 2 cycles of PCLK, then a write can take almost 3s. */ #define PLAY_WRITE_TIMEOUT_MS (4000U) /*!< Maximum Write Timeout for Software Trigger or Edge Trigger register: 4000 ms */ @@ -235,35 +232,64 @@ /** * @brief Retrieve the bit status in a given register. * @param reg The register to check. - * @param bit The bit to check to check. - * @retval 1 Bit is set. - * @retval 0 Bit is reset. + * @param bit The bit to check. + * @retval 1 bit is set. + * @retval 0 bit is reset. */ #define IS_PLAY_BIT_SET(reg, bit) (((reg) & (bit)) == (bit)) /** * @brief Retrieve the PLAY hardware CMSIS instance from the hal handle. - * @param handle specifies the peripheral Handle. + * @param handle specifies the peripheral handle. */ #define PLAY_GET_INSTANCE(handle) ((handle)->instance) /** * @brief Retrieve the PLAYx instance ID from the HAL handle. - * @param handle Specifies the peripheral Handle. + * @param handle Specifies the peripheral handle. */ #define PLAY_GET_INSTANCE_ID(handle) \ (HAL_PLAY1_INSTANCE_ID) /** - * @brief Verifies the PLAY TrustZone access control value. - * @param access Value of TZ access control. - * @retval 1 access is a valid value. - * @retval 0 access is an invalid value. + * @brief Verifies the PLAY privileged access level attribute. + * @param attribute Value of PLAY attribute. + * @retval 1 attribute is a valid value. + * @retval 0 attribute is an invalid value. + */ +#define IS_PLAY_ITEM_PRIV_ATTR(attribute) \ + (((attribute) == HAL_PLAY_NPRIV) \ + || ((attribute) == HAL_PLAY_PRIV)) + +/** + * @brief Verifies the PLAY privileged item value. + * @param item Value of PLAY privileged item. + * @retval 1 item is a valid value. + * @retval 0 item is an invalid value. + */ +#define IS_PLAY_PRIV_ITEM(item) \ + (((item) == HAL_PLAY_PRIV_ITEM_CONFIG) \ + || ((item) == HAL_PLAY_PRIV_ITEM_ALL)) + +/** + * @brief Verifies the PLAY security access level attribute. + * @param attribute Value of PLAY attribute. + * @retval 1 attribute is a valid value. + * @retval 0 attribute is an invalid value. */ -#define IS_PLAY_TZ_ACCESS_CONTROL(access) \ - (((access) == HAL_PLAY_TZ_REG_UNPROTECTED) \ - || ((access) == HAL_PLAY_TZ_CONFIG_REG_PROTECTED) \ - || ((access) == HAL_PLAY_TZ_ALL_REG_PROTECTED)) +#define IS_PLAY_ITEM_SEC_ATTR(attribute) \ + (((attribute) == HAL_PLAY_NSEC) \ + || ((attribute) == HAL_PLAY_SEC)) + +/** + * @brief Verifies the PLAY security item value. + * @param item Value of PLAY security item. + * @retval 1 item is a valid value. + * @retval 0 item is an invalid value. + */ +#define IS_PLAY_SEC_ITEM(item) \ + (((item) == HAL_PLAY_SEC_ITEM_CONFIG) \ + || ((item) == HAL_PLAY_SEC_ITEM_ALL)) /** * @brief Verifies the minimum pulse width value. @@ -291,7 +317,7 @@ * @retval 1 mux is a valid value. * @retval 0 mux is an invalid value. */ -#define IS_PLAY_IN_ID(mux) \ +#define IS_PLAY_IN(mux) \ (((mux) == HAL_PLAY_IN0) \ || ((mux) == HAL_PLAY_IN1) \ || ((mux) == HAL_PLAY_IN2) \ @@ -455,7 +481,7 @@ /** * @brief Verifies the value of input multiplexer source. - * @param instance PLAYx instance (@ref PLAY_TypeDef). (*) + * @param instance PLAYx instance (PLAY_TypeDef). (*) * @param source Input signal (@ref HAL_PLAY_IN_SourceTypeDef). * @retval 1 source is a valid value. * @retval 0 source is an invalid value. @@ -491,7 +517,7 @@ /** * @brief Verifies the Look-Up Table. - * @param instance PLAYx instance (@ref PLAY_TypeDef). (*) + * @param instance PLAYx instance (PLAY_TypeDef). (*) * @param lut Look-Up Table (@ref HAL_PLAY_LUTTypeDef). * @retval 1 lut is a valid value. * @retval 0 lut is an invalid value. @@ -855,7 +881,7 @@ /** * @brief Verifies the input source of a look-up table - * @param instance PLAYx instance (@ref PLAY_TypeDef). (*) + * @param instance PLAYx instance (PLAY_TypeDef). (*) * @param lut Look-Up Table (@ref HAL_PLAY_LUTTypeDef). * @param input_source Value of input source (@ref HAL_PLAY_LUT_InputSourceTypeDef). * @retval 1 input_source is a valid value. @@ -927,7 +953,7 @@ /** * @brief Verifies the Clock Gate value. - * @param instance PLAYx instance (@ref PLAY_TypeDef). (*) + * @param instance PLAYx instance (PLAY_TypeDef). (*) * @param source Signal source for Clock Gate. * @retval 1 source is a valid value. * @retval 0 source is an invalid value. @@ -1011,7 +1037,7 @@ /** * @brief Verifies the Output Multiplexer source. - * @param instance PLAYx instance (@ref PLAY_TypeDef). (*) + * @param instance PLAYx instance (PLAY_TypeDef). (*) * @param source Value of output source. * @retval 1 source is a valid value. * @retval 0 source is an invalid value. @@ -1072,7 +1098,7 @@ * @retval 0 swtrig is an invalid value. */ #define IS_PLAY_SWTRIGGER_MSK(swtrig_msk) \ - ((((uint32_t)(swtrig_msk) & HAL_PLAY_SWTRIG_ALL) != 0x00U) \ + ((((uint32_t)(swtrig_msk) & HAL_PLAY_SWTRIG_ALL) != 0x00U) \ && (((uint32_t)(swtrig_msk) & ~HAL_PLAY_SWTRIG_ALL) == 0x00U)) /** @@ -1101,72 +1127,55 @@ static HAL_StatusTypeDef PLAY_LUT_SetEdgeTrigger(const HAL_PLAY_HandleTypeDef *h /** @addtogroup PLAY_Exported_Functions_Group1 * @{ A set of functions allowing to initialize and deinitialize the PLAYx peripheral: - - HAL_PLAY_Init() : initialize the selected device with the PLAY instance. - - HAL_PLAY_DeInit() : de-initialize the selected PLAYx peripheral and reset the handle and status flags. - - HAL_PLAY_MSPInit() : initialize the PLAY MSP (MCU Specific Package). - - HAL_PLAY_MSPDeInit() : de-initialize the PLAY MSP. + - HAL_PLAY_Init() Initialize the selected device with the PLAY instance. + - HAL_PLAY_DeInit() De-initialize the selected PLAYx peripheral and reset the handle and status flags. + - HAL_PLAY_MSPInit() Initialize the PLAY MSP (MCU Specific Package). + - HAL_PLAY_MSPDeInit() De-initialize the PLAY MSP. */ /** * @brief Initialize the PLAY according to the associated handle. * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. - * @retval HAL_OK PLAY instance has been correctly initialized. - * @retval HAL_INVALID_PARAM PLAY handle is NULL + * @retval HAL_OK PLAY instance has been correctly initialized. + * @retval HAL_ERROR Invalid parameter. */ HAL_StatusTypeDef HAL_PLAY_Init(HAL_PLAY_HandleTypeDef *hplay) { - const PLAY_TypeDef *p_playx; - - /* Check the PLAY handle allocation */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; } - p_playx = PLAY_GET_INSTANCE(hplay); - - if (p_playx == NULL) - { - hplay->last_error_codes = HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); + assert_param(IS_PLAY_ALL_INSTANCE(PLAY_GET_INSTANCE(hplay))); - /* Init the peripheral */ - if (hplay->global_state == HAL_PLAY_STATE_RESET) + /* Initialize the peripheral */ + if (hplay->State == HAL_PLAY_STATE_RESET) { #if (USE_HAL_PLAY_REGISTER_CALLBACKS == 1) /* Register the default callback functions */ - hplay->SWTriggerWriteCpltCallback = HAL_PLAY_SWTriggerWriteCpltCallback; + hplay->SWTriggerWriteCpltCallback = HAL_PLAY_SWTriggerWriteCpltCallback; hplay->EdgeTriggerWriteCpltCallback = HAL_PLAY_EdgeTriggerWriteCpltCallback; - hplay->LUTOutputRisingCallback = HAL_PLAY_LUTOutputRisingCallback; - hplay->LUTOutputFallingCallback = HAL_PLAY_LUTOutputFallingCallback; + hplay->LUTOutputRisingCallback = HAL_PLAY_LUTOutputRisingCallback; + hplay->LUTOutputFallingCallback = HAL_PLAY_LUTOutputFallingCallback; - if (NULL == hplay->MspInitCallback) + if (hplay->MspInitCallback == NULL) { hplay->MspInitCallback = HAL_PLAY_MspInit; } - if (NULL == hplay->MspDeInitCallback) - { - hplay->MspDeInitCallback = HAL_PLAY_MspDeInit; - } - - /* Init the low level hardware */ + /* Initialize the low-level hardware */ hplay->MspInitCallback(hplay); #else - /* Init the low level hardware */ + /* Initialize the low-level hardware */ HAL_PLAY_MspInit(hplay); #endif /* USE_HAL_PLAY_REGISTER_CALLBACKS */ } /* Reset error code */ - hplay->last_error_codes = HAL_PLAY_ERROR_NONE; + hplay->ErrorCode = HAL_PLAY_ERROR_NONE; - hplay->global_state = HAL_PLAY_STATE_INIT; + hplay->State = HAL_PLAY_STATE_INIT; return HAL_OK; } @@ -1174,7 +1183,7 @@ HAL_StatusTypeDef HAL_PLAY_Init(HAL_PLAY_HandleTypeDef *hplay) /** * @brief DeInitialize the PLAY peripheral. * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. - * @note HAL_PLAY_DeInit does not reset all PLAY registers. + * @note HAL_PLAY_DeInit() does not reset all PLAY registers. * The Application must call RCC API to force the reset of all PLAY registers. * @retval HAL_OK Operation completed successfully. * @retval HAL_ERROR Invalid parameter. @@ -1183,7 +1192,7 @@ HAL_StatusTypeDef HAL_PLAY_DeInit(HAL_PLAY_HandleTypeDef *hplay) { PLAY_TypeDef *p_playx; - /* Check the PLAY handle allocation */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; @@ -1191,18 +1200,8 @@ HAL_StatusTypeDef HAL_PLAY_DeInit(HAL_PLAY_HandleTypeDef *hplay) p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - hplay->last_error_codes = HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - /* Check the parameters */ assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); - p_playx = PLAY_GET_INSTANCE(hplay); - /* Clear only interrupts & flags. The rest of configuration must be reset by the application with MspDeInit */ LL_PLAY_LUT_DisableIT(p_playx, LL_PLAY_LUT_ALL_OUT_REGISTERED | LL_PLAY_LUT_ALL_OUT_DIRECT); LL_PLAY_LUT_DisableIT_EdgeTriggerWriteComplete(p_playx); @@ -1214,59 +1213,56 @@ HAL_StatusTypeDef HAL_PLAY_DeInit(HAL_PLAY_HandleTypeDef *hplay) LL_PLAY_Unlock(p_playx); #if (USE_HAL_PLAY_REGISTER_CALLBACKS == 1) - /* Register the default callback functions */ - hplay->SWTriggerWriteCpltCallback = HAL_PLAY_SWTriggerWriteCpltCallback; - hplay->EdgeTriggerWriteCpltCallback = HAL_PLAY_EdgeTriggerWriteCpltCallback; - hplay->LUTOutputRisingCallback = HAL_PLAY_LUTOutputRisingCallback; - hplay->LUTOutputFallingCallback = HAL_PLAY_LUTOutputFallingCallback; - hplay->MspInitCallback = HAL_PLAY_MspInit; - if (hplay->MspDeInitCallback == NULL) { - /* DeInit Callback not initialized as expected then force it to default MspDeInit */ + /* MspDeInit callback not set; reset to default HAL_PLAY_MspDeInit */ hplay->MspDeInitCallback = HAL_PLAY_MspDeInit; } - /* DeInit the low level hardware */ + /* DeInitialize the low-level hardware */ hplay->MspDeInitCallback(hplay); #else - /* DeInit the low level hardware */ + /* DeInitialize the low-level hardware */ HAL_PLAY_MspDeInit(hplay); #endif /* USE_HAL_PLAY_REGISTER_CALLBACKS == 1 */ /* Reset error code */ - hplay->last_error_codes = HAL_PLAY_ERROR_NONE; + hplay->ErrorCode = HAL_PLAY_ERROR_NONE; - hplay->global_state = HAL_PLAY_STATE_RESET; + hplay->State = HAL_PLAY_STATE_RESET; return HAL_OK; } /** - * @brief Initialize the PLAY MSP. - * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. + * @brief Initialize the PLAY MSP. + * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. + * @warning This weak function must not be modified. When the callback is needed, + * it must be implemented in the user file. */ __weak void HAL_PLAY_MspInit(HAL_PLAY_HandleTypeDef *hplay) { /* Prevent unused argument(s) compilation warning */ UNUSED(hplay); - /* NOTE: This function must not be modified, when the callback is needed, - the HAL_PLAY_MspInit can be implemented in the user file + /* WARNING: This function must not be modified, when the callback is needed, + function HAL_PLAY_MspInit() must be implemented in the user file. */ } /** - * @brief DeInitialize the PLAY MSP. - * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. + * @brief DeInitialize the PLAY MSP. + * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. + * @warning This weak function must not be modified. When the callback is needed, + * it must be implemented in the user file. */ __weak void HAL_PLAY_MspDeInit(HAL_PLAY_HandleTypeDef *hplay) { /* Prevent unused argument(s) compilation warning */ UNUSED(hplay); - /* NOTE: This function must not be modified, when the callback is needed, - the HAL_PLAY_MspDeInit can be implemented in the user file + /* WARNING: This function must not be modified, when the callback is needed, + function HAL_PLAY_MspDeInit() must be implemented in the user file. */ } @@ -1308,14 +1304,15 @@ A set of functions allowing to configure the PLAYx peripheral: * @brief Configure multiple input multiplexers for the PLAY peripheral. * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param p_config Pointer to an array of @ref HAL_PLAY_IN_ConfTypeDef. - * @param array_size Number of configuration in the array. + * @param array_size Number of configurations in the array. * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Array pointer or handle is NULL. + * @retval HAL_ERROR Invalid parameter or wrong state. */ HAL_StatusTypeDef HAL_PLAY_INPUT_SetConfig(HAL_PLAY_HandleTypeDef *hplay, const HAL_PLAY_IN_ConfTypeDef *p_config, uint32_t array_size) { PLAY_TypeDef *p_playx; + HAL_PLAY_StateTypeDef tmp_state; uint32_t is_locked; /* Check the parameters */ @@ -1326,32 +1323,25 @@ HAL_StatusTypeDef HAL_PLAY_INPUT_SetConfig(HAL_PLAY_HandleTypeDef *hplay, const p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - hplay->last_error_codes = HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - if (p_config == NULL) + if ((p_config == NULL) || (array_size > PLAY_INPUT_MUX_NBR(p_playx))) { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_PARAM; return HAL_ERROR; } - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); assert_param(((array_size > 0U) && (array_size <= PLAY_INPUT_MUX_NBR(p_playx)))); /* Check the peripheral state */ - if ((hplay->global_state != HAL_PLAY_STATE_INIT) && (hplay->global_state != HAL_PLAY_STATE_READY)) + tmp_state = hplay->State; + if ((tmp_state != HAL_PLAY_STATE_INIT) && (tmp_state != HAL_PLAY_STATE_READY)) { return HAL_ERROR; } - /* UnLock the configuration if not already done */ + /* Unlock the configuration if not already done */ is_locked = LL_PLAY_IsLocked(p_playx); - if (is_locked == 1U) + if (is_locked != 0U) { LL_PLAY_Unlock(p_playx); } @@ -1379,7 +1369,7 @@ HAL_StatusTypeDef HAL_PLAY_INPUT_SetConfig(HAL_PLAY_HandleTypeDef *hplay, const * where array_size specifies the number of configurations. * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param p_config Pointer to an array of @ref HAL_PLAY_IN_ConfTypeDef to be filled. - * @param array_size Number of configuration in the array. + * @param array_size Number of configurations in the array. * @retval HAL_OK Operation completed successfully. * @retval HAL_ERROR Invalid parameter. */ @@ -1396,21 +1386,13 @@ HAL_StatusTypeDef HAL_PLAY_INPUT_GetConfig(HAL_PLAY_HandleTypeDef *hplay, HAL_PL p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - if (p_config == NULL) + if ((p_config == NULL) || (array_size > PLAY_INPUT_MUX_NBR(p_playx))) { - hplay->last_error_codes = HAL_PLAY_ERROR_INVALID_PARAM; + hplay->ErrorCode = HAL_PLAY_ERROR_INVALID_PARAM; return HAL_ERROR; } - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); assert_param(((array_size > 0U) && (array_size <= PLAY_INPUT_MUX_NBR(p_playx)))); /* Rebuild the input source signal */ @@ -1434,17 +1416,18 @@ HAL_StatusTypeDef HAL_PLAY_INPUT_GetConfig(HAL_PLAY_HandleTypeDef *hplay, HAL_PL * @brief Configure multiple lookup tables for the PLAY peripheral. * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param p_config Pointer to an array of HAL_PLAY_LUT_ConfTypeDef. - * @param array_size Number of configuration in the array. + * @param array_size Number of configurations in the array. * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter. + * @retval HAL_ERROR Invalid parameter or wrong state. */ HAL_StatusTypeDef HAL_PLAY_LUT_SetConfig(HAL_PLAY_HandleTypeDef *hplay, const HAL_PLAY_LUT_ConfTypeDef *p_config, uint32_t array_size) { PLAY_TypeDef *p_playx; + HAL_PLAY_StateTypeDef tmp_state; uint32_t is_locked; - /* Check handle parameter */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; @@ -1452,32 +1435,25 @@ HAL_StatusTypeDef HAL_PLAY_LUT_SetConfig(HAL_PLAY_HandleTypeDef *hplay, const HA p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) + if ((p_config == NULL) || (array_size > PLAY_INPUT_MUX_NBR(p_playx))) { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_PARAM; return HAL_ERROR; } - if (p_config == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); assert_param(((array_size > 0UL) && (array_size <= PLAY_LUT_NBR(p_playx)))); /* Check the peripheral state */ - if ((hplay->global_state != HAL_PLAY_STATE_INIT) && (hplay->global_state != HAL_PLAY_STATE_READY)) + tmp_state = hplay->State; + if ((tmp_state != HAL_PLAY_STATE_INIT) && (tmp_state != HAL_PLAY_STATE_READY)) { return HAL_ERROR; } - /* UnLock the configuration if not already done */ + /* Unlock the configuration if not already done */ is_locked = LL_PLAY_IsLocked(p_playx); - if (is_locked == 1U) + if (is_locked != 0U) { LL_PLAY_Unlock(p_playx); } @@ -1511,9 +1487,9 @@ HAL_StatusTypeDef HAL_PLAY_LUT_SetConfig(HAL_PLAY_HandleTypeDef *hplay, const HA /** * @brief Retrieve the lookup table configurations of the PLAY peripheral in order from 0 to (array_size - 1), * where array_size specifies the number of configurations. - * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. - * @param p_config Pointer to an array of @ref HAL_PLAY_LUT_ConfTypeDef. - * @param array_size Number of configuration in the array. + * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. + * @param p_config Pointer to an array of @ref HAL_PLAY_LUT_ConfTypeDef. + * @param array_size Number of configurations in the array. * @retval HAL_OK Operation completed successfully. * @retval HAL_ERROR Invalid parameter. */ @@ -1522,7 +1498,7 @@ HAL_StatusTypeDef HAL_PLAY_LUT_GetConfig(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY { const PLAY_TypeDef *p_playx; - /* Check handle parameter */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; @@ -1530,22 +1506,13 @@ HAL_StatusTypeDef HAL_PLAY_LUT_GetConfig(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY p_playx = PLAY_GET_INSTANCE(hplay); - /* Check parameter setting */ - if (p_playx == NULL) + if ((p_config == NULL) || (array_size > PLAY_INPUT_MUX_NBR(p_playx))) { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_PARAM; return HAL_ERROR; } - if (p_config == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); assert_param(((array_size > 0UL) && (array_size <= PLAY_LUT_NBR(p_playx)))); for (uint32_t idx = 0; idx < array_size; idx++) @@ -1567,16 +1534,18 @@ HAL_StatusTypeDef HAL_PLAY_LUT_GetConfig(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY } /** - * @brief Configure a set of Output Multiplexer. + * @brief Configure a set of output multiplexers for the PLAY peripheral. * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param p_config Pointer to an array of @ref HAL_PLAY_OUT_ConfTypeDef. - * @param array_size Number of configuration in the array. - * @return HAL status. + * @param array_size Number of configurations in the array. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Invalid parameter or wrong state. */ HAL_StatusTypeDef HAL_PLAY_OUTPUT_SetConfig(HAL_PLAY_HandleTypeDef *hplay, const HAL_PLAY_OUT_ConfTypeDef *p_config, uint32_t array_size) { PLAY_TypeDef *p_playx; + HAL_PLAY_StateTypeDef tmp_state; uint32_t is_locked; /* Check the parameters */ @@ -1587,25 +1556,25 @@ HAL_StatusTypeDef HAL_PLAY_OUTPUT_SetConfig(HAL_PLAY_HandleTypeDef *hplay, const p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) + if ((p_config == NULL) || (array_size > PLAY_INPUT_MUX_NBR(p_playx))) { - hplay->last_error_codes = HAL_PLAY_ERROR_INVALID_PARAM; + hplay->ErrorCode = HAL_PLAY_ERROR_INVALID_PARAM; return HAL_ERROR; } - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); assert_param(((array_size > 0UL) && (array_size <= PLAY_OUTPUT_MUX_NBR(p_playx)))); /* Check the peripheral state */ - if ((hplay->global_state != HAL_PLAY_STATE_INIT) && (hplay->global_state != HAL_PLAY_STATE_READY)) + tmp_state = hplay->State; + if ((tmp_state != HAL_PLAY_STATE_INIT) && (tmp_state != HAL_PLAY_STATE_READY)) { return HAL_ERROR; } - /* UnLock the configuration if not already done */ + /* Unlock the configuration if not already done */ is_locked = LL_PLAY_IsLocked(p_playx); - if (is_locked == 1U) + if (is_locked != 0U) { LL_PLAY_Unlock(p_playx); } @@ -1619,7 +1588,7 @@ HAL_StatusTypeDef HAL_PLAY_OUTPUT_SetConfig(HAL_PLAY_HandleTypeDef *hplay, const LL_PLAY_OUTPUT_SetSource(p_playx, (uint32_t)p_config[idx].output_mux, (uint32_t)p_config[idx].lut_output); } - hplay->global_state = HAL_PLAY_STATE_READY; + hplay->State = HAL_PLAY_STATE_READY; return HAL_OK; } @@ -1629,7 +1598,7 @@ HAL_StatusTypeDef HAL_PLAY_OUTPUT_SetConfig(HAL_PLAY_HandleTypeDef *hplay, const * where array_size specifies the number of configurations. * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param p_config Pointer to an array of @ref HAL_PLAY_OUT_ConfTypeDef. - * @param array_size Number of configuration in the array. + * @param array_size Number of configurations in the array. * @retval HAL_OK Operation completed successfully. * @retval HAL_ERROR Invalid parameter. */ @@ -1646,21 +1615,13 @@ HAL_StatusTypeDef HAL_PLAY_OUTPUT_GetConfig(HAL_PLAY_HandleTypeDef *hplay, HAL_P p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - hplay->last_error_codes = HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - if (p_config == NULL) + if ((p_config == NULL) || (array_size > PLAY_INPUT_MUX_NBR(p_playx))) { - hplay->last_error_codes = HAL_PLAY_ERROR_INVALID_PARAM; + hplay->ErrorCode = HAL_PLAY_ERROR_INVALID_PARAM; return HAL_ERROR; } - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); assert_param(((array_size > 0UL) && (array_size <= PLAY_OUTPUT_MUX_NBR(p_playx)))); for (uint32_t idx = 0; idx < array_size; idx++) @@ -1679,9 +1640,9 @@ HAL_StatusTypeDef HAL_PLAY_OUTPUT_GetConfig(HAL_PLAY_HandleTypeDef *hplay, HAL_P * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param source Input source signal. * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter or current state is not @ref HAL_PLAY_STATE_READY. + * @retval HAL_ERROR Invalid parameter or wrong state. */ -HAL_StatusTypeDef HAL_PLAY_INPUT_SetSource(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_IN_SourceTypeDef source) +HAL_StatusTypeDef HAL_PLAY_INPUT_SetSource(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_IN_SourceTypeDef source) { PLAY_TypeDef *p_playx; @@ -1693,28 +1654,20 @@ HAL_StatusTypeDef HAL_PLAY_INPUT_SetSource(HAL_PLAY_HandleTypeDef *hplay, HAL_PL p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - hplay->last_error_codes = HAL_PLAY_ERROR_INVALID_PARAM; + assert_param(IS_PLAY_IN_SOURCE(p_playx, source)); + /* Check the peripheral state */ + if (hplay->State != HAL_PLAY_STATE_READY) + { return HAL_ERROR; } - assert_param(IS_PLAY_IN_SOURCE(p_playx, source)); - uint32_t src_u32 = (uint32_t)source; /* Retrieve the input mux */ uint32_t input_mux = (src_u32 & PLAY_IN_MUX_MASK) >> HAL_PLAY_IN_MUX_POS; uint32_t mux_sel = src_u32 & PLAY_IN_MUX_VALUE_MASK; - /* Check the peripheral state */ - if (hplay->global_state != HAL_PLAY_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the source signal */ LL_PLAY_INPUT_SetSource(p_playx, input_mux, mux_sel); return HAL_OK; @@ -1724,34 +1677,23 @@ HAL_StatusTypeDef HAL_PLAY_INPUT_SetSource(HAL_PLAY_HandleTypeDef *hplay, HAL_PL * @brief Retrieve the signal source for an input multiplexer of the PLAY peripheral. * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param input_mux Input multiplexer. - * @return Input source signal. * @note Function will return @ref HAL_PLAY_IN_SOURCE_INVALID if the parameters are invalid. + * @return Input source signal. */ HAL_PLAY_IN_SourceTypeDef HAL_PLAY_INPUT_GetSource(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_INTypeDef input_mux) { - const PLAY_TypeDef *p_playx; - /* Check the parameters */ if (hplay == NULL) { - /* Return 0 as default value */ - return HAL_PLAY_IN_SOURCE_INVALID; - } - - p_playx = PLAY_GET_INSTANCE(hplay); - - if (p_playx == NULL) - { - /* Return 0 as default value */ return HAL_PLAY_IN_SOURCE_INVALID; } - assert_param(IS_PLAY_IN_ID(input_mux)); + assert_param(IS_PLAY_IN(input_mux)); /* Rebuild the source signal */ uint32_t instance_id = (uint32_t)PLAY_GET_INSTANCE_ID(hplay); uint32_t mux_sel = (uint32_t)input_mux << HAL_PLAY_IN_MUX_POS; - uint32_t source = LL_PLAY_INPUT_GetSource(p_playx, (uint32_t)input_mux); + uint32_t source = LL_PLAY_INPUT_GetSource(PLAY_GET_INSTANCE(hplay), (uint32_t)input_mux); uint32_t ret = (instance_id | mux_sel | source); @@ -1765,38 +1707,27 @@ HAL_PLAY_IN_SourceTypeDef HAL_PLAY_INPUT_GetSource(const HAL_PLAY_HandleTypeDef * @param width Pulse width in play_clk clock cycles, in range [0..255]. * Value 0 means that the filter is bypassed. * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter or current state is not @ref HAL_PLAY_STATE_READY. + * @retval HAL_ERROR Invalid parameter or wrong state. */ -HAL_StatusTypeDef HAL_PLAY_INPUT_SetMinPulseWidth(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_INTypeDef input_mux, +HAL_StatusTypeDef HAL_PLAY_INPUT_SetMinPulseWidth(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_INTypeDef input_mux, uint32_t width) { - PLAY_TypeDef *p_playx; - - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; } - p_playx = PLAY_GET_INSTANCE(hplay); - - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - assert_param(IS_PLAY_IN_ID(input_mux)); + assert_param(IS_PLAY_IN(input_mux)); assert_param(IS_PLAY_MIN_PULSE_WIDTH(width)); /* Check the peripheral state */ - if (hplay->global_state != HAL_PLAY_STATE_READY) + if (hplay->State != HAL_PLAY_STATE_READY) { return HAL_ERROR; } - LL_PLAY_INPUT_SetMinimumPulseWidth(p_playx, (uint32_t)input_mux, width); + LL_PLAY_INPUT_SetMinimumPulseWidth(PLAY_GET_INSTANCE(hplay), (uint32_t)input_mux, width); return HAL_OK; } @@ -1805,29 +1736,20 @@ HAL_StatusTypeDef HAL_PLAY_INPUT_SetMinPulseWidth(HAL_PLAY_HandleTypeDef *hplay, * @brief Retrieve the minimum pulse width configured for an input filter of the PLAY peripheral. * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param input_mux Input multiplexer. - * @return Pulse width in play_clk clock cycles, in range [0..255]. Value 0 means that the filter is bypassed. * @note Function will return 0 if the parameters are invalid. + * @return Pulse width in play_clk clock cycles, in range [0..255]. Value 0 means that the filter is bypassed. */ uint32_t HAL_PLAY_INPUT_GetMinPulseWidth(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_INTypeDef input_mux) { - const PLAY_TypeDef *p_playx; - - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return 0U; } - p_playx = PLAY_GET_INSTANCE(hplay); - - if (p_playx == NULL) - { - return 0U; - } + assert_param(IS_PLAY_IN(input_mux)); - assert_param(IS_PLAY_IN_ID(input_mux)); - - return LL_PLAY_INPUT_GetMinimumPulseWidth(p_playx, (uint32_t)input_mux); + return LL_PLAY_INPUT_GetMinimumPulseWidth(PLAY_GET_INSTANCE(hplay), (uint32_t)input_mux); } /** @@ -1836,38 +1758,27 @@ uint32_t HAL_PLAY_INPUT_GetMinPulseWidth(const HAL_PLAY_HandleTypeDef *hplay, HA * @param input_mux Input multiplexer. * @param mode Mode of Edge Detection. * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter or current state is not @ref HAL_PLAY_STATE_READY. + * @retval HAL_ERROR Invalid parameter or wrong state. */ -HAL_StatusTypeDef HAL_PLAY_INPUT_SetEdgeDetectionMode(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_INTypeDef input_mux, +HAL_StatusTypeDef HAL_PLAY_INPUT_SetEdgeDetectionMode(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_INTypeDef input_mux, HAL_PLAY_EdgeDetectionModeTypeDef mode) { - PLAY_TypeDef *p_playx; - - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; } - p_playx = PLAY_GET_INSTANCE(hplay); - - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - assert_param(IS_PLAY_IN_ID(input_mux)); + assert_param(IS_PLAY_IN(input_mux)); assert_param(IS_PLAY_EDGE_DETECTION_MODE(mode)); /* Check the peripheral state */ - if (hplay->global_state != HAL_PLAY_STATE_READY) + if (hplay->State != HAL_PLAY_STATE_READY) { return HAL_ERROR; } - LL_PLAY_INPUT_SetEdgeDetectionMode(p_playx, (uint32_t)input_mux, (uint32_t)mode); + LL_PLAY_INPUT_SetEdgeDetectionMode(PLAY_GET_INSTANCE(hplay), (uint32_t)input_mux, (uint32_t)mode); return HAL_OK; } @@ -1876,32 +1787,22 @@ HAL_StatusTypeDef HAL_PLAY_INPUT_SetEdgeDetectionMode(HAL_PLAY_HandleTypeDef *hp * @brief Retrieve the edge detection mode configured for an input filter of the PLAY peripheral. * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param input_mux Input multiplexer. - * @return Edge Detection mode. * @note Function will return @ref HAL_PLAY_EDGE_DETECTION_BYPASSED if the parameters are invalid. + * @return Edge Detection mode. */ HAL_PLAY_EdgeDetectionModeTypeDef HAL_PLAY_INPUT_GetEdgeDetectionMode(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_INTypeDef input_mux) { - const PLAY_TypeDef *p_playx; - - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { - /* Return HAL_PLAY_EDGE_DETECTION_BYPASSED as default value */ return HAL_PLAY_EDGE_DETECTION_BYPASSED; } - p_playx = PLAY_GET_INSTANCE(hplay); - - if (p_playx == NULL) - { - /* Return HAL_PLAY_EDGE_DETECTION_BYPASSED as default value */ - return HAL_PLAY_EDGE_DETECTION_BYPASSED; - } + assert_param(IS_PLAY_IN(input_mux)); - assert_param(IS_PLAY_IN_ID(input_mux)); - - return (HAL_PLAY_EdgeDetectionModeTypeDef)LL_PLAY_INPUT_GetEdgeDetectionMode(p_playx, (uint32_t)input_mux); + return (HAL_PLAY_EdgeDetectionModeTypeDef)LL_PLAY_INPUT_GetEdgeDetectionMode(PLAY_GET_INSTANCE(hplay), + (uint32_t)input_mux); } /* PLAY Configuration - Unitary functions for lookup table *********************/ @@ -1912,14 +1813,14 @@ HAL_PLAY_EdgeDetectionModeTypeDef HAL_PLAY_INPUT_GetEdgeDetectionMode(const HAL_ * @param lut Lookup table. * @param truth_table_value The value can be in range [0..0xFFFF]. * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter or current state is not @ref HAL_PLAY_STATE_READY. + * @retval HAL_ERROR Invalid parameter or wrong state. */ -HAL_StatusTypeDef HAL_PLAY_LUT_SetTruthTable(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut, +HAL_StatusTypeDef HAL_PLAY_LUT_SetTruthTable(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut, uint32_t truth_table_value) { PLAY_TypeDef *p_playx; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; @@ -1927,18 +1828,11 @@ HAL_StatusTypeDef HAL_PLAY_LUT_SetTruthTable(HAL_PLAY_HandleTypeDef *hplay, HAL_ p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - assert_param(IS_PLAY_LUT(p_playx, lut)); assert_param(IS_PLAY_LUT_TRUTH_TABLE_VALUE(truth_table_value)); /* Check the peripheral state */ - if (hplay->global_state != HAL_PLAY_STATE_READY) + if (hplay->State != HAL_PLAY_STATE_READY) { return HAL_ERROR; } @@ -1953,28 +1847,21 @@ HAL_StatusTypeDef HAL_PLAY_LUT_SetTruthTable(HAL_PLAY_HandleTypeDef *hplay, HAL_ * @brief Retrieve the truth table value for a lookup table in the PLAY peripheral. * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param lut Lookup table. - * @return Value in range [0..0xFFFF]. * @note Function will return 0 if the parameters are invalid. + * @return Value in range [0..0xFFFF]. */ uint32_t HAL_PLAY_LUT_GetTruthTable(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut) { const PLAY_TypeDef *p_playx; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { - /* Return 0 as default value */ return 0U; } p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - /* Return 0 as default value */ - return 0U; - } - assert_param(IS_PLAY_LUT(p_playx, lut)); return LL_PLAY_LUT_GetTruthTable(p_playx, (uint32_t)lut); @@ -1987,15 +1874,15 @@ uint32_t HAL_PLAY_LUT_GetTruthTable(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLA * @param lut_input Lookup table Input. * @param input_source Signal source. * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter or current state is not @ref HAL_PLAY_STATE_READY. + * @retval HAL_ERROR Invalid parameter or wrong state. */ -HAL_StatusTypeDef HAL_PLAY_LUT_SetSource(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut, +HAL_StatusTypeDef HAL_PLAY_LUT_SetSource(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut, HAL_PLAY_LUT_InputTypeDef lut_input, HAL_PLAY_LUT_InputSourceTypeDef input_source) { PLAY_TypeDef *p_playx; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; @@ -2003,19 +1890,12 @@ HAL_StatusTypeDef HAL_PLAY_LUT_SetSource(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - assert_param(IS_PLAY_LUT(p_playx, lut)); assert_param(IS_PLAY_LUT_INPUT(lut_input)); assert_param(IS_PLAY_LUT_INPUT_SOURCE(p_playx, lut, input_source)); /* Check the peripheral state */ - if (hplay->global_state != HAL_PLAY_STATE_READY) + if (hplay->State != HAL_PLAY_STATE_READY) { return HAL_ERROR; } @@ -2030,29 +1910,22 @@ HAL_StatusTypeDef HAL_PLAY_LUT_SetSource(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param lut Lookup table. * @param lut_input Lookup table Input. - * @return Lookup table input source. * @note Function will return @ref HAL_PLAY_LUT_INPUT_DEFAULT if the parameters are invalid. + * @return Lookup table input source. */ HAL_PLAY_LUT_InputSourceTypeDef HAL_PLAY_LUT_GetSource(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut, HAL_PLAY_LUT_InputTypeDef lut_input) { const PLAY_TypeDef *p_playx; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { - /* Return HAL_PLAY_LUT_INPUT_DEFAULT as default value */ return HAL_PLAY_LUT_INPUT_DEFAULT; } p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - /* Return HAL_PLAY_LUT_INPUT_DEFAULT as default value */ - return HAL_PLAY_LUT_INPUT_DEFAULT; - } - assert_param(IS_PLAY_LUT(p_playx, lut)); assert_param(IS_PLAY_LUT_INPUT(lut_input)); @@ -2065,14 +1938,14 @@ HAL_PLAY_LUT_InputSourceTypeDef HAL_PLAY_LUT_GetSource(const HAL_PLAY_HandleType * @param lut Lookup table. * @param source Signal source. * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter or current state is not @ref HAL_PLAY_STATE_READY. + * @retval HAL_ERROR Invalid parameter or wrong state. */ -HAL_StatusTypeDef HAL_PLAY_LUT_SetClockGateSource(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut, +HAL_StatusTypeDef HAL_PLAY_LUT_SetClockGateSource(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut, HAL_PLAY_LUT_ClkGateSourceTypeDef source) { PLAY_TypeDef *p_playx; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; @@ -2080,18 +1953,11 @@ HAL_StatusTypeDef HAL_PLAY_LUT_SetClockGateSource(HAL_PLAY_HandleTypeDef *hplay, p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - assert_param(IS_PLAY_LUT(p_playx, lut)); assert_param(IS_PLAY_LUT_CLOCK_GATE_SOURCE(p_playx, source)); /* Check the peripheral state */ - if (hplay->global_state != HAL_PLAY_STATE_READY) + if (hplay->State != HAL_PLAY_STATE_READY) { return HAL_ERROR; } @@ -2105,29 +1971,22 @@ HAL_StatusTypeDef HAL_PLAY_LUT_SetClockGateSource(HAL_PLAY_HandleTypeDef *hplay, * @brief Retrieve the clock gate source for a lookup table in the PLAY peripheral. * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param lut Lookup table. - * @return Lookup table clock gate source. * @note Function will return @ref HAL_PLAY_LUT_CLK_GATE_OFF if the parameters are invalid. + * @return Lookup table clock gate source. */ HAL_PLAY_LUT_ClkGateSourceTypeDef HAL_PLAY_LUT_GetClockGateSource(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_LUTTypeDef lut) { const PLAY_TypeDef *p_playx; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { - /* Return HAL_PLAY_LUT_CLK_GATE_OFF as default value */ return HAL_PLAY_LUT_CLK_GATE_OFF; } p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - /* Return HAL_PLAY_LUT_CLK_GATE_OFF as default value */ - return HAL_PLAY_LUT_CLK_GATE_OFF; - } - assert_param(IS_PLAY_LUT(p_playx, lut)); return (HAL_PLAY_LUT_ClkGateSourceTypeDef)LL_PLAY_LUT_GetClockGate(p_playx, (uint32_t)lut); @@ -2140,47 +1999,47 @@ HAL_PLAY_LUT_ClkGateSourceTypeDef HAL_PLAY_LUT_GetClockGateSource(const HAL_PLAY * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param output_mux Output multiplexer. * @param source Lookup table output. This parameter can be one of the following values: - * @arg @ref HAL_PLAY_LUT0_OUT_DIRECT - * @arg @ref HAL_PLAY_LUT1_OUT_DIRECT - * @arg @ref HAL_PLAY_LUT2_OUT_DIRECT - * @arg @ref HAL_PLAY_LUT3_OUT_DIRECT - * @arg @ref HAL_PLAY_LUT4_OUT_DIRECT - * @arg @ref HAL_PLAY_LUT5_OUT_DIRECT - * @arg @ref HAL_PLAY_LUT6_OUT_DIRECT - * @arg @ref HAL_PLAY_LUT7_OUT_DIRECT - * @arg @ref HAL_PLAY_LUT8_OUT_DIRECT - * @arg @ref HAL_PLAY_LUT9_OUT_DIRECT - * @arg @ref HAL_PLAY_LUT10_OUT_DIRECT - * @arg @ref HAL_PLAY_LUT11_OUT_DIRECT - * @arg @ref HAL_PLAY_LUT12_OUT_DIRECT - * @arg @ref HAL_PLAY_LUT13_OUT_DIRECT - * @arg @ref HAL_PLAY_LUT14_OUT_DIRECT - * @arg @ref HAL_PLAY_LUT15_OUT_DIRECT - * @arg @ref HAL_PLAY_LUT0_OUT_REGISTERED - * @arg @ref HAL_PLAY_LUT1_OUT_REGISTERED - * @arg @ref HAL_PLAY_LUT2_OUT_REGISTERED - * @arg @ref HAL_PLAY_LUT3_OUT_REGISTERED - * @arg @ref HAL_PLAY_LUT4_OUT_REGISTERED - * @arg @ref HAL_PLAY_LUT5_OUT_REGISTERED - * @arg @ref HAL_PLAY_LUT6_OUT_REGISTERED - * @arg @ref HAL_PLAY_LUT7_OUT_REGISTERED - * @arg @ref HAL_PLAY_LUT8_OUT_REGISTERED - * @arg @ref HAL_PLAY_LUT9_OUT_REGISTERED - * @arg @ref HAL_PLAY_LUT10_OUT_REGISTERED - * @arg @ref HAL_PLAY_LUT11_OUT_REGISTERED - * @arg @ref HAL_PLAY_LUT12_OUT_REGISTERED - * @arg @ref HAL_PLAY_LUT13_OUT_REGISTERED - * @arg @ref HAL_PLAY_LUT14_OUT_REGISTERED - * @arg @ref HAL_PLAY_LUT15_OUT_REGISTERED + * @arg @ref HAL_PLAY_LUT0_OUT_DIRECT + * @arg @ref HAL_PLAY_LUT1_OUT_DIRECT + * @arg @ref HAL_PLAY_LUT2_OUT_DIRECT + * @arg @ref HAL_PLAY_LUT3_OUT_DIRECT + * @arg @ref HAL_PLAY_LUT4_OUT_DIRECT + * @arg @ref HAL_PLAY_LUT5_OUT_DIRECT + * @arg @ref HAL_PLAY_LUT6_OUT_DIRECT + * @arg @ref HAL_PLAY_LUT7_OUT_DIRECT + * @arg @ref HAL_PLAY_LUT8_OUT_DIRECT + * @arg @ref HAL_PLAY_LUT9_OUT_DIRECT + * @arg @ref HAL_PLAY_LUT10_OUT_DIRECT + * @arg @ref HAL_PLAY_LUT11_OUT_DIRECT + * @arg @ref HAL_PLAY_LUT12_OUT_DIRECT + * @arg @ref HAL_PLAY_LUT13_OUT_DIRECT + * @arg @ref HAL_PLAY_LUT14_OUT_DIRECT + * @arg @ref HAL_PLAY_LUT15_OUT_DIRECT + * @arg @ref HAL_PLAY_LUT0_OUT_REGISTERED + * @arg @ref HAL_PLAY_LUT1_OUT_REGISTERED + * @arg @ref HAL_PLAY_LUT2_OUT_REGISTERED + * @arg @ref HAL_PLAY_LUT3_OUT_REGISTERED + * @arg @ref HAL_PLAY_LUT4_OUT_REGISTERED + * @arg @ref HAL_PLAY_LUT5_OUT_REGISTERED + * @arg @ref HAL_PLAY_LUT6_OUT_REGISTERED + * @arg @ref HAL_PLAY_LUT7_OUT_REGISTERED + * @arg @ref HAL_PLAY_LUT8_OUT_REGISTERED + * @arg @ref HAL_PLAY_LUT9_OUT_REGISTERED + * @arg @ref HAL_PLAY_LUT10_OUT_REGISTERED + * @arg @ref HAL_PLAY_LUT11_OUT_REGISTERED + * @arg @ref HAL_PLAY_LUT12_OUT_REGISTERED + * @arg @ref HAL_PLAY_LUT13_OUT_REGISTERED + * @arg @ref HAL_PLAY_LUT14_OUT_REGISTERED + * @arg @ref HAL_PLAY_LUT15_OUT_REGISTERED * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter or current state is not @ref HAL_PLAY_STATE_READY. + * @retval HAL_ERROR Invalid parameter or wrong state. */ -HAL_StatusTypeDef HAL_PLAY_OUTPUT_SetSource(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_OUTTypeDef output_mux, +HAL_StatusTypeDef HAL_PLAY_OUTPUT_SetSource(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_OUTTypeDef output_mux, uint32_t source) { PLAY_TypeDef *p_playx; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; @@ -2188,18 +2047,11 @@ HAL_StatusTypeDef HAL_PLAY_OUTPUT_SetSource(HAL_PLAY_HandleTypeDef *hplay, HAL_P p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - assert_param(IS_PLAY_OUT(output_mux)); assert_param(IS_PLAY_OUT_SOURCE(p_playx, source)); /* Check the peripheral state */ - if (hplay->global_state != HAL_PLAY_STATE_READY) + if (hplay->State != HAL_PLAY_STATE_READY) { return HAL_ERROR; } @@ -2250,26 +2102,15 @@ HAL_StatusTypeDef HAL_PLAY_OUTPUT_SetSource(HAL_PLAY_HandleTypeDef *hplay, HAL_P */ uint32_t HAL_PLAY_OUTPUT_GetSource(const HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_OUTTypeDef output_mux) { - const PLAY_TypeDef *p_playx; - - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { - /* Return 0 as default value */ - return 0U; - } - - p_playx = PLAY_GET_INSTANCE(hplay); - - if (p_playx == NULL) - { - /* Return 0 as default value */ return 0U; } assert_param(IS_PLAY_OUT(output_mux)); - return LL_PLAY_OUTPUT_GetSource(p_playx, (uint32_t)output_mux); + return LL_PLAY_OUTPUT_GetSource(PLAY_GET_INSTANCE(hplay), (uint32_t)output_mux); } /** @@ -2290,14 +2131,14 @@ A set of functions allowing to start/stop the PLAYx peripheral: * @note The falling and rising edge configuration is exclusive and thus, a lookup table output cannot be * configured for both rising and falling edges at the same time. * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter. + * @retval HAL_ERROR Invalid parameter or wrong state. */ HAL_StatusTypeDef HAL_PLAY_Start(HAL_PLAY_HandleTypeDef *hplay, const HAL_PLAY_EdgeTriggerConfTypeDef *p_config) { PLAY_TypeDef *p_playx; uint32_t is_locked; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; @@ -2307,28 +2148,20 @@ HAL_StatusTypeDef HAL_PLAY_Start(HAL_PLAY_HandleTypeDef *hplay, const HAL_PLAY_E if (p_config == NULL) { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_PARAM; return HAL_ERROR; } - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); assert_param((p_config->lut_out_falling_mask & p_config->lut_out_rising_mask) == 0U); /* Check the peripheral state */ - if (hplay->global_state != HAL_PLAY_STATE_READY) + if (hplay->State != HAL_PLAY_STATE_READY) { return HAL_ERROR; } - /* Lock the configuration only if already done. + /* Lock the configuration only if it is currently unlocked. In context where configuration register requires a privilege and/or secure write access: - this check prevents generating an unexpected illegal access (ilac) event if the caller does not have the required permissions. @@ -2341,7 +2174,7 @@ HAL_StatusTypeDef HAL_PLAY_Start(HAL_PLAY_HandleTypeDef *hplay, const HAL_PLAY_E LL_PLAY_Lock(p_playx); } - hplay->global_state = HAL_PLAY_STATE_BUSY; + hplay->State = HAL_PLAY_STATE_BUSY; return PLAY_LUT_SetEdgeTrigger(hplay, p_config, PLAY_WRITE_TIMEOUT_MS); } @@ -2358,7 +2191,7 @@ HAL_StatusTypeDef HAL_PLAY_Stop(HAL_PLAY_HandleTypeDef *hplay) { PLAY_TypeDef *p_playx; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; @@ -2366,17 +2199,8 @@ HAL_StatusTypeDef HAL_PLAY_Stop(HAL_PLAY_HandleTypeDef *hplay) p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); - /* Check the peripheral state */ - if (hplay->global_state != HAL_PLAY_STATE_BUSY) + if (hplay->State != HAL_PLAY_STATE_BUSY) { return HAL_ERROR; } @@ -2386,7 +2210,7 @@ HAL_StatusTypeDef HAL_PLAY_Stop(HAL_PLAY_HandleTypeDef *hplay) LL_PLAY_Unlock(p_playx); - hplay->global_state = HAL_PLAY_STATE_READY; + hplay->State = HAL_PLAY_STATE_READY; return HAL_OK; } @@ -2415,41 +2239,29 @@ A set of functions allowing to manage the lookup table Output of PLAYx periphera * @note The falling and rising edge configuration is exclusive and thus, a lookup table output cannot be * configured for both rising and falling edges at the same time. * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter. * @retval HAL_BUSY A write is pending. + * @retval HAL_ERROR Invalid parameter or wrong state. */ HAL_StatusTypeDef HAL_PLAY_LUT_SetEdgeTrigger(HAL_PLAY_HandleTypeDef *hplay, const HAL_PLAY_EdgeTriggerConfTypeDef *p_config, uint32_t timeout_ms) { - PLAY_TypeDef *p_playx; - - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; } - p_playx = PLAY_GET_INSTANCE(hplay); - - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - if (p_config == NULL) { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_PARAM; return HAL_ERROR; } - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); assert_param((p_config->lut_out_falling_mask & p_config->lut_out_rising_mask) == 0U); - if (hplay->global_state != HAL_PLAY_STATE_BUSY) + if (hplay->State != HAL_PLAY_STATE_BUSY) { return HAL_ERROR; } @@ -2458,21 +2270,21 @@ HAL_StatusTypeDef HAL_PLAY_LUT_SetEdgeTrigger(HAL_PLAY_HandleTypeDef *hplay, } /** - * @brief Configure the Edge Triggers in mode: flag transition of lookup table outputs. + * @brief Configure the Edge Triggers in interrupt mode: flag transition of lookup table outputs. * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param p_config Pointer to a @ref HAL_PLAY_EdgeTriggerConfTypeDef structure for the Edge Triggers configuration. * @note The falling and rising edge configuration is exclusive and thus, a lookup table output cannot be * configured for both rising and falling edges at the same time. * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter. * @retval HAL_BUSY A write is pending. + * @retval HAL_ERROR Invalid parameter or wrong state. */ HAL_StatusTypeDef HAL_PLAY_LUT_SetEdgeTrigger_IT(HAL_PLAY_HandleTypeDef *hplay, const HAL_PLAY_EdgeTriggerConfTypeDef *p_config) { PLAY_TypeDef *p_playx; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; @@ -2480,24 +2292,16 @@ HAL_StatusTypeDef HAL_PLAY_LUT_SetEdgeTrigger_IT(HAL_PLAY_HandleTypeDef *hplay, p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - if (p_config == NULL) { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_PARAM; return HAL_ERROR; } - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); assert_param((p_config->lut_out_falling_mask & p_config->lut_out_rising_mask) == 0U); - if (hplay->global_state != HAL_PLAY_STATE_BUSY) + if (hplay->State != HAL_PLAY_STATE_BUSY) { return HAL_ERROR; } @@ -2527,7 +2331,7 @@ HAL_StatusTypeDef HAL_PLAY_LUT_GetEdgeTrigger(HAL_PLAY_HandleTypeDef *hplay, HAL { const PLAY_TypeDef *p_playx; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; @@ -2535,22 +2339,13 @@ HAL_StatusTypeDef HAL_PLAY_LUT_GetEdgeTrigger(HAL_PLAY_HandleTypeDef *hplay, HAL p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - if (p_config == NULL) { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_PARAM; return HAL_ERROR; } - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); - /* Retrieve the configuration */ p_config->lut_out_rising_mask = LL_PLAY_LUT_GetEdgeTrigger(p_playx); p_config->lut_out_falling_mask = ~p_config->lut_out_rising_mask; @@ -2564,45 +2359,45 @@ HAL_StatusTypeDef HAL_PLAY_LUT_GetEdgeTrigger(HAL_PLAY_HandleTypeDef *hplay, HAL * @param poll_mode Polling mode of type @ref HAL_PLAY_PollingEdgeTriggerTypeDef. * @param edge_trig_mask Mask of flags to poll. * This parameter can be a combination of the following values: - * @arg @ref HAL_PLAY_LUT0_OUT_DIRECT : The Flag of LUT0 direct output - * @arg @ref HAL_PLAY_LUT1_OUT_DIRECT : The Flag of LUT1 direct output - * @arg @ref HAL_PLAY_LUT2_OUT_DIRECT : The Flag of LUT2 direct output - * @arg @ref HAL_PLAY_LUT3_OUT_DIRECT : The Flag of LUT3 direct output - * @arg @ref HAL_PLAY_LUT4_OUT_DIRECT : The Flag of LUT4 direct output - * @arg @ref HAL_PLAY_LUT5_OUT_DIRECT : The Flag of LUT5 direct output - * @arg @ref HAL_PLAY_LUT6_OUT_DIRECT : The Flag of LUT6 direct output - * @arg @ref HAL_PLAY_LUT7_OUT_DIRECT : The Flag of LUT7 direct output - * @arg @ref HAL_PLAY_LUT8_OUT_DIRECT : The Flag of LUT8 direct output - * @arg @ref HAL_PLAY_LUT9_OUT_DIRECT : The Flag of LUT9 direct output - * @arg @ref HAL_PLAY_LUT10_OUT_DIRECT : The Flag of LUT10 direct output - * @arg @ref HAL_PLAY_LUT11_OUT_DIRECT : The Flag of LUT11 direct output - * @arg @ref HAL_PLAY_LUT12_OUT_DIRECT : The Flag of LUT12 direct output - * @arg @ref HAL_PLAY_LUT13_OUT_DIRECT : The Flag of LUT13 direct output - * @arg @ref HAL_PLAY_LUT14_OUT_DIRECT : The Flag of LUT14 direct output - * @arg @ref HAL_PLAY_LUT15_OUT_DIRECT : The Flag of LUT15 direct output - * @arg @ref HAL_PLAY_LUT_ALL_OUT_DIRECT : All Flags of LUTs direct outputs - * @arg @ref HAL_PLAY_LUT0_OUT_REGISTERED : The Flag of LUT0 registered output - * @arg @ref HAL_PLAY_LUT1_OUT_REGISTERED : The Flag of LUT1 registered output - * @arg @ref HAL_PLAY_LUT2_OUT_REGISTERED : The Flag of LUT2 registered output - * @arg @ref HAL_PLAY_LUT3_OUT_REGISTERED : The Flag of LUT3 registered output - * @arg @ref HAL_PLAY_LUT4_OUT_REGISTERED : The Flag of LUT4 registered output - * @arg @ref HAL_PLAY_LUT5_OUT_REGISTERED : The Flag of LUT5 registered output - * @arg @ref HAL_PLAY_LUT6_OUT_REGISTERED : The Flag of LUT6 registered output - * @arg @ref HAL_PLAY_LUT7_OUT_REGISTERED : The Flag of LUT7 registered output - * @arg @ref HAL_PLAY_LUT8_OUT_REGISTERED : The Flag of LUT8 registered output - * @arg @ref HAL_PLAY_LUT9_OUT_REGISTERED : The Flag of LUT9 registered output - * @arg @ref HAL_PLAY_LUT10_OUT_REGISTERED : The Flag of LUT10 registered output - * @arg @ref HAL_PLAY_LUT11_OUT_REGISTERED : The Flag of LUT11 registered output - * @arg @ref HAL_PLAY_LUT12_OUT_REGISTERED : The Flag of LUT12 registered output - * @arg @ref HAL_PLAY_LUT13_OUT_REGISTERED : The Flag of LUT13 registered output - * @arg @ref HAL_PLAY_LUT14_OUT_REGISTERED : The Flag of LUT14 registered output - * @arg @ref HAL_PLAY_LUT15_OUT_REGISTERED : The Flag of LUT15 registered output - * @arg @ref HAL_PLAY_LUT_ALL_OUT_REGISTERED : All Flags of LUTs registered outputs + * @arg @ref HAL_PLAY_LUT0_OUT_DIRECT : The flag of LUT0 direct output + * @arg @ref HAL_PLAY_LUT1_OUT_DIRECT : The flag of LUT1 direct output + * @arg @ref HAL_PLAY_LUT2_OUT_DIRECT : The flag of LUT2 direct output + * @arg @ref HAL_PLAY_LUT3_OUT_DIRECT : The flag of LUT3 direct output + * @arg @ref HAL_PLAY_LUT4_OUT_DIRECT : The flag of LUT4 direct output + * @arg @ref HAL_PLAY_LUT5_OUT_DIRECT : The flag of LUT5 direct output + * @arg @ref HAL_PLAY_LUT6_OUT_DIRECT : The flag of LUT6 direct output + * @arg @ref HAL_PLAY_LUT7_OUT_DIRECT : The flag of LUT7 direct output + * @arg @ref HAL_PLAY_LUT8_OUT_DIRECT : The flag of LUT8 direct output + * @arg @ref HAL_PLAY_LUT9_OUT_DIRECT : The flag of LUT9 direct output + * @arg @ref HAL_PLAY_LUT10_OUT_DIRECT : The flag of LUT10 direct output + * @arg @ref HAL_PLAY_LUT11_OUT_DIRECT : The flag of LUT11 direct output + * @arg @ref HAL_PLAY_LUT12_OUT_DIRECT : The flag of LUT12 direct output + * @arg @ref HAL_PLAY_LUT13_OUT_DIRECT : The flag of LUT13 direct output + * @arg @ref HAL_PLAY_LUT14_OUT_DIRECT : The flag of LUT14 direct output + * @arg @ref HAL_PLAY_LUT15_OUT_DIRECT : The flag of LUT15 direct output + * @arg @ref HAL_PLAY_LUT_ALL_OUT_DIRECT : All flags of LUTs direct outputs + * @arg @ref HAL_PLAY_LUT0_OUT_REGISTERED : The flag of LUT0 registered output + * @arg @ref HAL_PLAY_LUT1_OUT_REGISTERED : The flag of LUT1 registered output + * @arg @ref HAL_PLAY_LUT2_OUT_REGISTERED : The flag of LUT2 registered output + * @arg @ref HAL_PLAY_LUT3_OUT_REGISTERED : The flag of LUT3 registered output + * @arg @ref HAL_PLAY_LUT4_OUT_REGISTERED : The flag of LUT4 registered output + * @arg @ref HAL_PLAY_LUT5_OUT_REGISTERED : The flag of LUT5 registered output + * @arg @ref HAL_PLAY_LUT6_OUT_REGISTERED : The flag of LUT6 registered output + * @arg @ref HAL_PLAY_LUT7_OUT_REGISTERED : The flag of LUT7 registered output + * @arg @ref HAL_PLAY_LUT8_OUT_REGISTERED : The flag of LUT8 registered output + * @arg @ref HAL_PLAY_LUT9_OUT_REGISTERED : The flag of LUT9 registered output + * @arg @ref HAL_PLAY_LUT10_OUT_REGISTERED : The flag of LUT10 registered output + * @arg @ref HAL_PLAY_LUT11_OUT_REGISTERED : The flag of LUT11 registered output + * @arg @ref HAL_PLAY_LUT12_OUT_REGISTERED : The flag of LUT12 registered output + * @arg @ref HAL_PLAY_LUT13_OUT_REGISTERED : The flag of LUT13 registered output + * @arg @ref HAL_PLAY_LUT14_OUT_REGISTERED : The flag of LUT14 registered output + * @arg @ref HAL_PLAY_LUT15_OUT_REGISTERED : The flag of LUT15 registered output + * @arg @ref HAL_PLAY_LUT_ALL_OUT_REGISTERED : All flags of LUTs registered outputs * @param timeout_ms Timeout duration (in ms). * @param p_edge_trig_mask_status Pointer to return the triggered lookup table output flags. * @retval HAL_OK Operation completed successfully. * @retval HAL_TIMEOUT Operation timed out. - * @retval HAL_ERROR Invalid parameter. + * @retval HAL_ERROR Invalid parameter or wrong state. */ HAL_StatusTypeDef HAL_PLAY_LUT_PollForEdgeTrigger(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_PollingEdgeTriggerTypeDef poll_mode, @@ -2612,7 +2407,7 @@ HAL_StatusTypeDef HAL_PLAY_LUT_PollForEdgeTrigger(HAL_PLAY_HandleTypeDef *hplay, PLAY_TypeDef *p_playx; uint32_t tickstart; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; @@ -2620,28 +2415,23 @@ HAL_StatusTypeDef HAL_PLAY_LUT_PollForEdgeTrigger(HAL_PLAY_HandleTypeDef *hplay, p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) + if (p_edge_trig_mask_status == NULL) { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_PARAM; - - /* Return error status */ return HAL_ERROR; } assert_param(IS_PLAY_POLL_MODE(poll_mode)); assert_param((edge_trig_mask != 0U)); - assert_param((p_edge_trig_mask_status != NULL)); - - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); /* Check the peripheral state */ - if (hplay->global_state != HAL_PLAY_STATE_BUSY) + if (hplay->State != HAL_PLAY_STATE_BUSY) { return HAL_ERROR; } - /* Get tick count */ + /* Get the current tick value */ tickstart = HAL_GetTick(); /* Check selected event flag */ @@ -2684,71 +2474,59 @@ HAL_StatusTypeDef HAL_PLAY_LUT_PollForEdgeTrigger(HAL_PLAY_HandleTypeDef *hplay, * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param its_mask Mask of lookup table output interrupt to enable. * This parameter can be a combination of the following values: - * @arg @ref HAL_PLAY_LUT0_OUT_DIRECT : The Interrupt of LUT0 direct output - * @arg @ref HAL_PLAY_LUT1_OUT_DIRECT : The Interrupt of LUT1 direct output - * @arg @ref HAL_PLAY_LUT2_OUT_DIRECT : The Interrupt of LUT2 direct output - * @arg @ref HAL_PLAY_LUT3_OUT_DIRECT : The Interrupt of LUT3 direct output - * @arg @ref HAL_PLAY_LUT4_OUT_DIRECT : The Interrupt of LUT4 direct output - * @arg @ref HAL_PLAY_LUT5_OUT_DIRECT : The Interrupt of LUT5 direct output - * @arg @ref HAL_PLAY_LUT6_OUT_DIRECT : The Interrupt of LUT6 direct output - * @arg @ref HAL_PLAY_LUT7_OUT_DIRECT : The Interrupt of LUT7 direct output - * @arg @ref HAL_PLAY_LUT8_OUT_DIRECT : The Interrupt of LUT8 direct output - * @arg @ref HAL_PLAY_LUT9_OUT_DIRECT : The Interrupt of LUT9 direct output - * @arg @ref HAL_PLAY_LUT10_OUT_DIRECT : The Interrupt of LUT10 direct output - * @arg @ref HAL_PLAY_LUT11_OUT_DIRECT : The Interrupt of LUT11 direct output - * @arg @ref HAL_PLAY_LUT12_OUT_DIRECT : The Interrupt of LUT12 direct output - * @arg @ref HAL_PLAY_LUT13_OUT_DIRECT : The Interrupt of LUT13 direct output - * @arg @ref HAL_PLAY_LUT14_OUT_DIRECT : The Interrupt of LUT14 direct output - * @arg @ref HAL_PLAY_LUT15_OUT_DIRECT : The Interrupt of LUT15 direct output - * @arg @ref HAL_PLAY_LUT_ALL_OUT_DIRECT : All Interrupts of LUTs direct outputs - * @arg @ref HAL_PLAY_LUT0_OUT_REGISTERED : The Interrupt of LUT0 registered output - * @arg @ref HAL_PLAY_LUT1_OUT_REGISTERED : The Interrupt of LUT1 registered output - * @arg @ref HAL_PLAY_LUT2_OUT_REGISTERED : The Interrupt of LUT2 registered output - * @arg @ref HAL_PLAY_LUT3_OUT_REGISTERED : The Interrupt of LUT3 registered output - * @arg @ref HAL_PLAY_LUT4_OUT_REGISTERED : The Interrupt of LUT4 registered output - * @arg @ref HAL_PLAY_LUT5_OUT_REGISTERED : The Interrupt of LUT5 registered output - * @arg @ref HAL_PLAY_LUT6_OUT_REGISTERED : The Interrupt of LUT6 registered output - * @arg @ref HAL_PLAY_LUT7_OUT_REGISTERED : The Interrupt of LUT7 registered output - * @arg @ref HAL_PLAY_LUT8_OUT_REGISTERED : The Interrupt of LUT8 registered output - * @arg @ref HAL_PLAY_LUT9_OUT_REGISTERED : The Interrupt of LUT9 registered output - * @arg @ref HAL_PLAY_LUT10_OUT_REGISTERED : The Interrupt of LUT10 registered output - * @arg @ref HAL_PLAY_LUT11_OUT_REGISTERED : The Interrupt of LUT11 registered output - * @arg @ref HAL_PLAY_LUT12_OUT_REGISTERED : The Interrupt of LUT12 registered output - * @arg @ref HAL_PLAY_LUT13_OUT_REGISTERED : The Interrupt of LUT13 registered output - * @arg @ref HAL_PLAY_LUT14_OUT_REGISTERED : The Interrupt of LUT14 registered output - * @arg @ref HAL_PLAY_LUT15_OUT_REGISTERED : The Interrupt of LUT15 registered output - * @arg @ref HAL_PLAY_LUT_ALL_OUT_REGISTERED : All Interrupts of LUTs registered outputs + * @arg @ref HAL_PLAY_LUT0_OUT_DIRECT : The interrupt of LUT0 direct output + * @arg @ref HAL_PLAY_LUT1_OUT_DIRECT : The interrupt of LUT1 direct output + * @arg @ref HAL_PLAY_LUT2_OUT_DIRECT : The interrupt of LUT2 direct output + * @arg @ref HAL_PLAY_LUT3_OUT_DIRECT : The interrupt of LUT3 direct output + * @arg @ref HAL_PLAY_LUT4_OUT_DIRECT : The interrupt of LUT4 direct output + * @arg @ref HAL_PLAY_LUT5_OUT_DIRECT : The interrupt of LUT5 direct output + * @arg @ref HAL_PLAY_LUT6_OUT_DIRECT : The interrupt of LUT6 direct output + * @arg @ref HAL_PLAY_LUT7_OUT_DIRECT : The interrupt of LUT7 direct output + * @arg @ref HAL_PLAY_LUT8_OUT_DIRECT : The interrupt of LUT8 direct output + * @arg @ref HAL_PLAY_LUT9_OUT_DIRECT : The interrupt of LUT9 direct output + * @arg @ref HAL_PLAY_LUT10_OUT_DIRECT : The interrupt of LUT10 direct output + * @arg @ref HAL_PLAY_LUT11_OUT_DIRECT : The interrupt of LUT11 direct output + * @arg @ref HAL_PLAY_LUT12_OUT_DIRECT : The interrupt of LUT12 direct output + * @arg @ref HAL_PLAY_LUT13_OUT_DIRECT : The interrupt of LUT13 direct output + * @arg @ref HAL_PLAY_LUT14_OUT_DIRECT : The interrupt of LUT14 direct output + * @arg @ref HAL_PLAY_LUT15_OUT_DIRECT : The interrupt of LUT15 direct output + * @arg @ref HAL_PLAY_LUT_ALL_OUT_DIRECT : All interrupts of LUTs direct outputs + * @arg @ref HAL_PLAY_LUT0_OUT_REGISTERED : The interrupt of LUT0 registered output + * @arg @ref HAL_PLAY_LUT1_OUT_REGISTERED : The interrupt of LUT1 registered output + * @arg @ref HAL_PLAY_LUT2_OUT_REGISTERED : The interrupt of LUT2 registered output + * @arg @ref HAL_PLAY_LUT3_OUT_REGISTERED : The interrupt of LUT3 registered output + * @arg @ref HAL_PLAY_LUT4_OUT_REGISTERED : The interrupt of LUT4 registered output + * @arg @ref HAL_PLAY_LUT5_OUT_REGISTERED : The interrupt of LUT5 registered output + * @arg @ref HAL_PLAY_LUT6_OUT_REGISTERED : The interrupt of LUT6 registered output + * @arg @ref HAL_PLAY_LUT7_OUT_REGISTERED : The interrupt of LUT7 registered output + * @arg @ref HAL_PLAY_LUT8_OUT_REGISTERED : The interrupt of LUT8 registered output + * @arg @ref HAL_PLAY_LUT9_OUT_REGISTERED : The interrupt of LUT9 registered output + * @arg @ref HAL_PLAY_LUT10_OUT_REGISTERED : The interrupt of LUT10 registered output + * @arg @ref HAL_PLAY_LUT11_OUT_REGISTERED : The interrupt of LUT11 registered output + * @arg @ref HAL_PLAY_LUT12_OUT_REGISTERED : The interrupt of LUT12 registered output + * @arg @ref HAL_PLAY_LUT13_OUT_REGISTERED : The interrupt of LUT13 registered output + * @arg @ref HAL_PLAY_LUT14_OUT_REGISTERED : The interrupt of LUT14 registered output + * @arg @ref HAL_PLAY_LUT15_OUT_REGISTERED : The interrupt of LUT15 registered output + * @arg @ref HAL_PLAY_LUT_ALL_OUT_REGISTERED : All interrupts of LUTs registered outputs * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter. + * @retval HAL_ERROR Invalid parameter or wrong state. */ -HAL_StatusTypeDef HAL_PLAY_LUT_EnableIT(HAL_PLAY_HandleTypeDef *hplay, uint32_t its_mask) +HAL_StatusTypeDef HAL_PLAY_LUT_EnableIT(const HAL_PLAY_HandleTypeDef *hplay, uint32_t its_mask) { - PLAY_TypeDef *p_playx; - - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; } - p_playx = PLAY_GET_INSTANCE(hplay); - - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); assert_param((its_mask != 0U)); - if (hplay->global_state != HAL_PLAY_STATE_BUSY) + if (hplay->State != HAL_PLAY_STATE_BUSY) { return HAL_ERROR; } - LL_PLAY_LUT_EnableIT(p_playx, its_mask); + LL_PLAY_LUT_EnableIT(PLAY_GET_INSTANCE(hplay), its_mask); return HAL_OK; } @@ -2758,70 +2536,59 @@ HAL_StatusTypeDef HAL_PLAY_LUT_EnableIT(HAL_PLAY_HandleTypeDef *hplay, uint32_t * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param its_mask Mask of lookup table output interrupt to disable * This parameter can be a combination of the following values: - * @arg @ref HAL_PLAY_LUT0_OUT_DIRECT : The Interrupt of LUT0 direct output - * @arg @ref HAL_PLAY_LUT1_OUT_DIRECT : The Interrupt of LUT1 direct output - * @arg @ref HAL_PLAY_LUT2_OUT_DIRECT : The Interrupt of LUT2 direct output - * @arg @ref HAL_PLAY_LUT3_OUT_DIRECT : The Interrupt of LUT3 direct output - * @arg @ref HAL_PLAY_LUT4_OUT_DIRECT : The Interrupt of LUT4 direct output - * @arg @ref HAL_PLAY_LUT5_OUT_DIRECT : The Interrupt of LUT5 direct output - * @arg @ref HAL_PLAY_LUT6_OUT_DIRECT : The Interrupt of LUT6 direct output - * @arg @ref HAL_PLAY_LUT7_OUT_DIRECT : The Interrupt of LUT7 direct output - * @arg @ref HAL_PLAY_LUT8_OUT_DIRECT : The Interrupt of LUT8 direct output - * @arg @ref HAL_PLAY_LUT9_OUT_DIRECT : The Interrupt of LUT9 direct output - * @arg @ref HAL_PLAY_LUT10_OUT_DIRECT : The Interrupt of LUT10 direct output - * @arg @ref HAL_PLAY_LUT11_OUT_DIRECT : The Interrupt of LUT11 direct output - * @arg @ref HAL_PLAY_LUT12_OUT_DIRECT : The Interrupt of LUT12 direct output - * @arg @ref HAL_PLAY_LUT13_OUT_DIRECT : The Interrupt of LUT13 direct output - * @arg @ref HAL_PLAY_LUT14_OUT_DIRECT : The Interrupt of LUT14 direct output - * @arg @ref HAL_PLAY_LUT15_OUT_DIRECT : The Interrupt of LUT15 direct output - * @arg @ref HAL_PLAY_LUT_ALL_OUT_DIRECT : All Interrupts of LUTs direct outputs - * @arg @ref HAL_PLAY_LUT0_OUT_REGISTERED : The Interrupt of LUT0 registered output - * @arg @ref HAL_PLAY_LUT1_OUT_REGISTERED : The Interrupt of LUT1 registered output - * @arg @ref HAL_PLAY_LUT2_OUT_REGISTERED : The Interrupt of LUT2 registered output - * @arg @ref HAL_PLAY_LUT3_OUT_REGISTERED : The Interrupt of LUT3 registered output - * @arg @ref HAL_PLAY_LUT4_OUT_REGISTERED : The Interrupt of LUT4 registered output - * @arg @ref HAL_PLAY_LUT5_OUT_REGISTERED : The Interrupt of LUT5 registered output - * @arg @ref HAL_PLAY_LUT6_OUT_REGISTERED : The Interrupt of LUT6 registered output - * @arg @ref HAL_PLAY_LUT7_OUT_REGISTERED : The Interrupt of LUT7 registered output - * @arg @ref HAL_PLAY_LUT8_OUT_REGISTERED : The Interrupt of LUT8 registered output - * @arg @ref HAL_PLAY_LUT9_OUT_REGISTERED : The Interrupt of LUT9 registered output - * @arg @ref HAL_PLAY_LUT10_OUT_REGISTERED : The Interrupt of LUT10 registered output - * @arg @ref HAL_PLAY_LUT11_OUT_REGISTERED : The Interrupt of LUT11 registered output - * @arg @ref HAL_PLAY_LUT12_OUT_REGISTERED : The Interrupt of LUT12 registered output - * @arg @ref HAL_PLAY_LUT13_OUT_REGISTERED : The Interrupt of LUT13 registered output - * @arg @ref HAL_PLAY_LUT14_OUT_REGISTERED : The Interrupt of LUT14 registered output - * @arg @ref HAL_PLAY_LUT15_OUT_REGISTERED : The Interrupt of LUT15 registered output - * @arg @ref HAL_PLAY_LUT_ALL_OUT_REGISTERED : All Interrupts of LUTs registered outputs + * @arg @ref HAL_PLAY_LUT0_OUT_DIRECT : The interrupt of LUT0 direct output + * @arg @ref HAL_PLAY_LUT1_OUT_DIRECT : The interrupt of LUT1 direct output + * @arg @ref HAL_PLAY_LUT2_OUT_DIRECT : The interrupt of LUT2 direct output + * @arg @ref HAL_PLAY_LUT3_OUT_DIRECT : The interrupt of LUT3 direct output + * @arg @ref HAL_PLAY_LUT4_OUT_DIRECT : The interrupt of LUT4 direct output + * @arg @ref HAL_PLAY_LUT5_OUT_DIRECT : The interrupt of LUT5 direct output + * @arg @ref HAL_PLAY_LUT6_OUT_DIRECT : The interrupt of LUT6 direct output + * @arg @ref HAL_PLAY_LUT7_OUT_DIRECT : The interrupt of LUT7 direct output + * @arg @ref HAL_PLAY_LUT8_OUT_DIRECT : The interrupt of LUT8 direct output + * @arg @ref HAL_PLAY_LUT9_OUT_DIRECT : The interrupt of LUT9 direct output + * @arg @ref HAL_PLAY_LUT10_OUT_DIRECT : The interrupt of LUT10 direct output + * @arg @ref HAL_PLAY_LUT11_OUT_DIRECT : The interrupt of LUT11 direct output + * @arg @ref HAL_PLAY_LUT12_OUT_DIRECT : The interrupt of LUT12 direct output + * @arg @ref HAL_PLAY_LUT13_OUT_DIRECT : The interrupt of LUT13 direct output + * @arg @ref HAL_PLAY_LUT14_OUT_DIRECT : The interrupt of LUT14 direct output + * @arg @ref HAL_PLAY_LUT15_OUT_DIRECT : The interrupt of LUT15 direct output + * @arg @ref HAL_PLAY_LUT_ALL_OUT_DIRECT : All interrupts of LUTs direct outputs + * @arg @ref HAL_PLAY_LUT0_OUT_REGISTERED : The interrupt of LUT0 registered output + * @arg @ref HAL_PLAY_LUT1_OUT_REGISTERED : The interrupt of LUT1 registered output + * @arg @ref HAL_PLAY_LUT2_OUT_REGISTERED : The interrupt of LUT2 registered output + * @arg @ref HAL_PLAY_LUT3_OUT_REGISTERED : The interrupt of LUT3 registered output + * @arg @ref HAL_PLAY_LUT4_OUT_REGISTERED : The interrupt of LUT4 registered output + * @arg @ref HAL_PLAY_LUT5_OUT_REGISTERED : The interrupt of LUT5 registered output + * @arg @ref HAL_PLAY_LUT6_OUT_REGISTERED : The interrupt of LUT6 registered output + * @arg @ref HAL_PLAY_LUT7_OUT_REGISTERED : The interrupt of LUT7 registered output + * @arg @ref HAL_PLAY_LUT8_OUT_REGISTERED : The interrupt of LUT8 registered output + * @arg @ref HAL_PLAY_LUT9_OUT_REGISTERED : The interrupt of LUT9 registered output + * @arg @ref HAL_PLAY_LUT10_OUT_REGISTERED : The interrupt of LUT10 registered output + * @arg @ref HAL_PLAY_LUT11_OUT_REGISTERED : The interrupt of LUT11 registered output + * @arg @ref HAL_PLAY_LUT12_OUT_REGISTERED : The interrupt of LUT12 registered output + * @arg @ref HAL_PLAY_LUT13_OUT_REGISTERED : The interrupt of LUT13 registered output + * @arg @ref HAL_PLAY_LUT14_OUT_REGISTERED : The interrupt of LUT14 registered output + * @arg @ref HAL_PLAY_LUT15_OUT_REGISTERED : The interrupt of LUT15 registered output + * @arg @ref HAL_PLAY_LUT_ALL_OUT_REGISTERED : All interrupts of LUTs registered outputs * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter. + * @retval HAL_ERROR Invalid parameter or wrong state. */ -HAL_StatusTypeDef HAL_PLAY_LUT_DisableIT(HAL_PLAY_HandleTypeDef *hplay, uint32_t its_mask) +HAL_StatusTypeDef HAL_PLAY_LUT_DisableIT(const HAL_PLAY_HandleTypeDef *hplay, uint32_t its_mask) { - PLAY_TypeDef *p_playx; - - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; } - p_playx = PLAY_GET_INSTANCE(hplay); - - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); + assert_param((its_mask != 0U)); - if (hplay->global_state != HAL_PLAY_STATE_BUSY) + if (hplay->State != HAL_PLAY_STATE_BUSY) { return HAL_ERROR; } - LL_PLAY_LUT_DisableIT(p_playx, its_mask); + LL_PLAY_LUT_DisableIT(PLAY_GET_INSTANCE(hplay), its_mask); return HAL_OK; } @@ -2831,57 +2598,48 @@ HAL_StatusTypeDef HAL_PLAY_LUT_DisableIT(HAL_PLAY_HandleTypeDef *hplay, uint32_t * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @return Mask of enabled lookup table output interrupts. * This returned parameter can be a combination of the following values: - * @arg @ref HAL_PLAY_LUT0_OUT_DIRECT : The Interrupt of LUT0 direct output - * @arg @ref HAL_PLAY_LUT1_OUT_DIRECT : The Interrupt of LUT1 direct output - * @arg @ref HAL_PLAY_LUT2_OUT_DIRECT : The Interrupt of LUT2 direct output - * @arg @ref HAL_PLAY_LUT3_OUT_DIRECT : The Interrupt of LUT3 direct output - * @arg @ref HAL_PLAY_LUT4_OUT_DIRECT : The Interrupt of LUT4 direct output - * @arg @ref HAL_PLAY_LUT5_OUT_DIRECT : The Interrupt of LUT5 direct output - * @arg @ref HAL_PLAY_LUT6_OUT_DIRECT : The Interrupt of LUT6 direct output - * @arg @ref HAL_PLAY_LUT7_OUT_DIRECT : The Interrupt of LUT7 direct output - * @arg @ref HAL_PLAY_LUT8_OUT_DIRECT : The Interrupt of LUT8 direct output - * @arg @ref HAL_PLAY_LUT9_OUT_DIRECT : The Interrupt of LUT9 direct output - * @arg @ref HAL_PLAY_LUT10_OUT_DIRECT : The Interrupt of LUT10 direct output - * @arg @ref HAL_PLAY_LUT11_OUT_DIRECT : The Interrupt of LUT11 direct output - * @arg @ref HAL_PLAY_LUT12_OUT_DIRECT : The Interrupt of LUT12 direct output - * @arg @ref HAL_PLAY_LUT13_OUT_DIRECT : The Interrupt of LUT13 direct output - * @arg @ref HAL_PLAY_LUT14_OUT_DIRECT : The Interrupt of LUT14 direct output - * @arg @ref HAL_PLAY_LUT15_OUT_DIRECT : The Interrupt of LUT15 direct output - * @arg @ref HAL_PLAY_LUT0_OUT_REGISTERED : The Interrupt of LUT0 registered output - * @arg @ref HAL_PLAY_LUT1_OUT_REGISTERED : The Interrupt of LUT1 registered output - * @arg @ref HAL_PLAY_LUT2_OUT_REGISTERED : The Interrupt of LUT2 registered output - * @arg @ref HAL_PLAY_LUT3_OUT_REGISTERED : The Interrupt of LUT3 registered output - * @arg @ref HAL_PLAY_LUT4_OUT_REGISTERED : The Interrupt of LUT4 registered output - * @arg @ref HAL_PLAY_LUT5_OUT_REGISTERED : The Interrupt of LUT5 registered output - * @arg @ref HAL_PLAY_LUT6_OUT_REGISTERED : The Interrupt of LUT6 registered output - * @arg @ref HAL_PLAY_LUT7_OUT_REGISTERED : The Interrupt of LUT7 registered output - * @arg @ref HAL_PLAY_LUT8_OUT_REGISTERED : The Interrupt of LUT8 registered output - * @arg @ref HAL_PLAY_LUT9_OUT_REGISTERED : The Interrupt of LUT9 registered output - * @arg @ref HAL_PLAY_LUT10_OUT_REGISTERED : The Interrupt of LUT10 registered output - * @arg @ref HAL_PLAY_LUT11_OUT_REGISTERED : The Interrupt of LUT11 registered output - * @arg @ref HAL_PLAY_LUT12_OUT_REGISTERED : The Interrupt of LUT12 registered output - * @arg @ref HAL_PLAY_LUT13_OUT_REGISTERED : The Interrupt of LUT13 registered output - * @arg @ref HAL_PLAY_LUT14_OUT_REGISTERED : The Interrupt of LUT14 registered output - * @arg @ref HAL_PLAY_LUT15_OUT_REGISTERED : The Interrupt of LUT15 registered output + * @arg @ref HAL_PLAY_LUT0_OUT_DIRECT : The interrupt of LUT0 direct output + * @arg @ref HAL_PLAY_LUT1_OUT_DIRECT : The interrupt of LUT1 direct output + * @arg @ref HAL_PLAY_LUT2_OUT_DIRECT : The interrupt of LUT2 direct output + * @arg @ref HAL_PLAY_LUT3_OUT_DIRECT : The interrupt of LUT3 direct output + * @arg @ref HAL_PLAY_LUT4_OUT_DIRECT : The interrupt of LUT4 direct output + * @arg @ref HAL_PLAY_LUT5_OUT_DIRECT : The interrupt of LUT5 direct output + * @arg @ref HAL_PLAY_LUT6_OUT_DIRECT : The interrupt of LUT6 direct output + * @arg @ref HAL_PLAY_LUT7_OUT_DIRECT : The interrupt of LUT7 direct output + * @arg @ref HAL_PLAY_LUT8_OUT_DIRECT : The interrupt of LUT8 direct output + * @arg @ref HAL_PLAY_LUT9_OUT_DIRECT : The interrupt of LUT9 direct output + * @arg @ref HAL_PLAY_LUT10_OUT_DIRECT : The interrupt of LUT10 direct output + * @arg @ref HAL_PLAY_LUT11_OUT_DIRECT : The interrupt of LUT11 direct output + * @arg @ref HAL_PLAY_LUT12_OUT_DIRECT : The interrupt of LUT12 direct output + * @arg @ref HAL_PLAY_LUT13_OUT_DIRECT : The interrupt of LUT13 direct output + * @arg @ref HAL_PLAY_LUT14_OUT_DIRECT : The interrupt of LUT14 direct output + * @arg @ref HAL_PLAY_LUT15_OUT_DIRECT : The interrupt of LUT15 direct output + * @arg @ref HAL_PLAY_LUT0_OUT_REGISTERED : The interrupt of LUT0 registered output + * @arg @ref HAL_PLAY_LUT1_OUT_REGISTERED : The interrupt of LUT1 registered output + * @arg @ref HAL_PLAY_LUT2_OUT_REGISTERED : The interrupt of LUT2 registered output + * @arg @ref HAL_PLAY_LUT3_OUT_REGISTERED : The interrupt of LUT3 registered output + * @arg @ref HAL_PLAY_LUT4_OUT_REGISTERED : The interrupt of LUT4 registered output + * @arg @ref HAL_PLAY_LUT5_OUT_REGISTERED : The interrupt of LUT5 registered output + * @arg @ref HAL_PLAY_LUT6_OUT_REGISTERED : The interrupt of LUT6 registered output + * @arg @ref HAL_PLAY_LUT7_OUT_REGISTERED : The interrupt of LUT7 registered output + * @arg @ref HAL_PLAY_LUT8_OUT_REGISTERED : The interrupt of LUT8 registered output + * @arg @ref HAL_PLAY_LUT9_OUT_REGISTERED : The interrupt of LUT9 registered output + * @arg @ref HAL_PLAY_LUT10_OUT_REGISTERED : The interrupt of LUT10 registered output + * @arg @ref HAL_PLAY_LUT11_OUT_REGISTERED : The interrupt of LUT11 registered output + * @arg @ref HAL_PLAY_LUT12_OUT_REGISTERED : The interrupt of LUT12 registered output + * @arg @ref HAL_PLAY_LUT13_OUT_REGISTERED : The interrupt of LUT13 registered output + * @arg @ref HAL_PLAY_LUT14_OUT_REGISTERED : The interrupt of LUT14 registered output + * @arg @ref HAL_PLAY_LUT15_OUT_REGISTERED : The interrupt of LUT15 registered output */ uint32_t HAL_PLAY_LUT_GetIT(const HAL_PLAY_HandleTypeDef *hplay) { - const PLAY_TypeDef *p_playx; - - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return 0U; } - p_playx = PLAY_GET_INSTANCE(hplay); - - if (p_playx == NULL) - { - return 0U; - } - - return LL_PLAY_LUT_GetIT(p_playx); + return LL_PLAY_LUT_GetIT(PLAY_GET_INSTANCE(hplay)); } /** @@ -2923,16 +2681,16 @@ A set of functions allowing to manage the Software Triggers: * @param state State to set of type @ref HAL_PLAY_SWTriggerStateTypeDef. * @param timeout_ms Timeout duration (in ms). * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter. * @retval HAL_BUSY A write is pending. * @retval HAL_TIMEOUT Timeout reached. + * @retval HAL_ERROR Invalid parameter or wrong state. */ -HAL_StatusTypeDef HAL_PLAY_WriteSWTrigger(HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_triggers, +HAL_StatusTypeDef HAL_PLAY_WriteSWTrigger(const HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_triggers, HAL_PLAY_SWTriggerStateTypeDef state, uint32_t timeout_ms) { PLAY_TypeDef *p_playx; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; @@ -2940,17 +2698,10 @@ HAL_StatusTypeDef HAL_PLAY_WriteSWTrigger(HAL_PLAY_HandleTypeDef *hplay, uint32_ p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); assert_param(IS_PLAY_SWTRIGGER_MSK(sw_triggers)); + assert_param(IS_PLAY_SWTRIGGER_STATE(state)); - if (hplay->global_state != HAL_PLAY_STATE_BUSY) + if (hplay->State != HAL_PLAY_STATE_BUSY) { return HAL_ERROR; } @@ -3016,15 +2767,15 @@ HAL_StatusTypeDef HAL_PLAY_WriteSWTrigger(HAL_PLAY_HandleTypeDef *hplay, uint32_ * @arg @ref HAL_PLAY_SWTRIG_ALL : All software triggers * @param state State to set of type @ref HAL_PLAY_SWTriggerStateTypeDef. * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter. * @retval HAL_BUSY A write is pending. + * @retval HAL_ERROR Invalid parameter or wrong state. */ -HAL_StatusTypeDef HAL_PLAY_WriteSWTrigger_IT(HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_triggers, +HAL_StatusTypeDef HAL_PLAY_WriteSWTrigger_IT(const HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_triggers, HAL_PLAY_SWTriggerStateTypeDef state) { PLAY_TypeDef *p_playx; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; @@ -3032,17 +2783,10 @@ HAL_StatusTypeDef HAL_PLAY_WriteSWTrigger_IT(HAL_PLAY_HandleTypeDef *hplay, uint p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); assert_param(IS_PLAY_SWTRIGGER_MSK(sw_triggers)); + assert_param(IS_PLAY_SWTRIGGER_STATE(state)); - if (hplay->global_state != HAL_PLAY_STATE_BUSY) + if (hplay->State != HAL_PLAY_STATE_BUSY) { return HAL_ERROR; } @@ -3093,15 +2837,16 @@ HAL_StatusTypeDef HAL_PLAY_WriteSWTrigger_IT(HAL_PLAY_HandleTypeDef *hplay, uint * @arg @ref HAL_PLAY_SWTRIG_ALL : All software triggers * @param timeout_ms Timeout duration (in ms). * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter. * @retval HAL_BUSY A write is pending. * @retval HAL_TIMEOUT Timeout reached. + * @retval HAL_ERROR Invalid parameter or wrong state. */ -HAL_StatusTypeDef HAL_PLAY_ToggleSWTrigger(HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_triggers, uint32_t timeout_ms) +HAL_StatusTypeDef HAL_PLAY_ToggleSWTrigger(const HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_triggers, + uint32_t timeout_ms) { PLAY_TypeDef *p_playx; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; @@ -3109,17 +2854,9 @@ HAL_StatusTypeDef HAL_PLAY_ToggleSWTrigger(HAL_PLAY_HandleTypeDef *hplay, uint32 p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); assert_param(IS_PLAY_SWTRIGGER_MSK(sw_triggers)); - if (hplay->global_state != HAL_PLAY_STATE_BUSY) + if (hplay->State != HAL_PLAY_STATE_BUSY) { return HAL_ERROR; } @@ -3177,14 +2914,14 @@ HAL_StatusTypeDef HAL_PLAY_ToggleSWTrigger(HAL_PLAY_HandleTypeDef *hplay, uint32 * @arg @ref HAL_PLAY_SWTRIG15 : Software trigger 15 * @arg @ref HAL_PLAY_SWTRIG_ALL : All software triggers * @retval HAL_OK Operation completed successfully. - * @retval HAL_ERROR Invalid parameter. * @retval HAL_BUSY A write is pending. + * @retval HAL_ERROR Invalid parameter or wrong state. */ -HAL_StatusTypeDef HAL_PLAY_ToggleSWTrigger_IT(HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_triggers) +HAL_StatusTypeDef HAL_PLAY_ToggleSWTrigger_IT(const HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_triggers) { PLAY_TypeDef *p_playx; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; @@ -3192,17 +2929,9 @@ HAL_StatusTypeDef HAL_PLAY_ToggleSWTrigger_IT(HAL_PLAY_HandleTypeDef *hplay, uin p_playx = PLAY_GET_INSTANCE(hplay); - if (p_playx == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); assert_param(IS_PLAY_SWTRIGGER_MSK(sw_triggers)); - if (hplay->global_state != HAL_PLAY_STATE_BUSY) + if (hplay->State != HAL_PLAY_STATE_BUSY) { return HAL_ERROR; } @@ -3241,33 +2970,22 @@ HAL_StatusTypeDef HAL_PLAY_ToggleSWTrigger_IT(HAL_PLAY_HandleTypeDef *hplay, uin * @arg @ref HAL_PLAY_SWTRIG13 : Software trigger 13 * @arg @ref HAL_PLAY_SWTRIG14 : Software trigger 14 * @arg @ref HAL_PLAY_SWTRIG15 : Software trigger 15 - * @note This function will return HAL_PLAY_SW_TRIGGER_RESET in case of wrong parameter. + * @note This function will return @ref HAL_PLAY_SW_TRIGGER_RESET in case of wrong parameter. * @return State of Software Trigger. */ HAL_PLAY_SWTriggerStateTypeDef HAL_PLAY_ReadSWTrigger(const HAL_PLAY_HandleTypeDef *hplay, uint32_t sw_trig) { - const PLAY_TypeDef *p_playx; - - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { - /* Return HAL_PLAY_SW_TRIGGER_RESET as default value */ return HAL_PLAY_SW_TRIGGER_RESET; } - p_playx = PLAY_GET_INSTANCE(hplay); - - if (p_playx == NULL) - { - /* Return HAL_PLAY_SW_TRIGGER_RESET as default value */ - return HAL_PLAY_SW_TRIGGER_RESET; - } - - /* Check the parameters */ - assert_param(IS_PLAY_ALL_INSTANCE(hplay->instance)); + assert_param(IS_PLAY_SWTRIGGER(sw_trig)); /* Read the SW Trigger values */ - return ((LL_PLAY_IsSWTriggerSet(p_playx, sw_trig) != 0U) ? HAL_PLAY_SW_TRIGGER_SET : HAL_PLAY_SW_TRIGGER_RESET); + return ((LL_PLAY_IsSWTriggerSet(PLAY_GET_INSTANCE(hplay), sw_trig) != 0U) + ? HAL_PLAY_SW_TRIGGER_SET : HAL_PLAY_SW_TRIGGER_RESET); } /** @@ -3282,7 +3000,7 @@ A set of functions allowing to handle the PLAY interrupts in asynchronous mode. - HAL_PLAY_IRQHandler() - Callback functions: - - Depending on the process function used, different callback might be triggered: + - Depending on the process function used, different callbacks might be triggered: | Process API \n \ \n Callbacks | HAL_PLAY_WriteSWTrigger_IT() | HAL_PLAY_ToggleSWTrigger_IT() | |-----------------------------------------|:----------------------------:|:-----------------------------:| @@ -3313,7 +3031,6 @@ void HAL_PLAY_IRQHandler(HAL_PLAY_HandleTypeDef *hplay) PLAY_TypeDef *p_playx; p_playx = PLAY_GET_INSTANCE(hplay); - assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); /* Get status of general interrupts */ uint32_t reg_ier = LL_PLAY_READ_REG(p_playx, IER); @@ -3399,13 +3116,13 @@ void HAL_PLAY_IRQHandler(HAL_PLAY_HandleTypeDef *hplay) * @warning This weak function must not be modified. When the callback is needed, * it must be implemented in the user file. */ -__WEAK void HAL_PLAY_SWTriggerWriteCpltCallback(HAL_PLAY_HandleTypeDef *hplay) +__weak void HAL_PLAY_SWTriggerWriteCpltCallback(HAL_PLAY_HandleTypeDef *hplay) { /* Prevent unused argument(s) compilation warning */ UNUSED(hplay); /* WARNING: This function must not be modified. When the callback is needed, - function HAL_PLAY_SWTriggerWriteCpltCallback must be implemented in the user file. + function HAL_PLAY_SWTriggerWriteCpltCallback() must be implemented in the user file. */ } @@ -3415,13 +3132,13 @@ __WEAK void HAL_PLAY_SWTriggerWriteCpltCallback(HAL_PLAY_HandleTypeDef *hplay) * @warning This weak function must not be modified. When the callback is needed, * it must be implemented in the user file. */ -__WEAK void HAL_PLAY_EdgeTriggerWriteCpltCallback(HAL_PLAY_HandleTypeDef *hplay) +__weak void HAL_PLAY_EdgeTriggerWriteCpltCallback(HAL_PLAY_HandleTypeDef *hplay) { /* Prevent unused argument(s) compilation warning */ UNUSED(hplay); /* WARNING: This function must not be modified. When the callback is needed, - function HAL_PLAY_EdgeTriggerWriteCpltCallback must be implemented in the user file. + function HAL_PLAY_EdgeTriggerWriteCpltCallback() must be implemented in the user file. */ } @@ -3439,7 +3156,7 @@ __weak void HAL_PLAY_LUTOutputRisingCallback(HAL_PLAY_HandleTypeDef *hplay, uint UNUSED(edge_trig_mask_status); /* WARNING: This function must not be modified. When the callback is needed, - function HAL_PLAY_LUTOutputRisingCallback must be implemented in the user file. + function HAL_PLAY_LUTOutputRisingCallback() must be implemented in the user file. */ } @@ -3450,55 +3167,55 @@ __weak void HAL_PLAY_LUTOutputRisingCallback(HAL_PLAY_HandleTypeDef *hplay, uint * @warning This weak function must not be modified. When the callback is needed, * it must be implemented in the user file. */ -__WEAK void HAL_PLAY_LUTOutputFallingCallback(HAL_PLAY_HandleTypeDef *hplay, uint32_t edge_trig_mask_status) +__weak void HAL_PLAY_LUTOutputFallingCallback(HAL_PLAY_HandleTypeDef *hplay, uint32_t edge_trig_mask_status) { /* Prevent unused argument(s) compilation warning */ UNUSED(hplay); UNUSED(edge_trig_mask_status); /* WARNING: This function must not be modified. When the callback is needed, - function HAL_PLAY_LUTOutputFallingCallback must be implemented in the user file. + function HAL_PLAY_LUTOutputFallingCallback() must be implemented in the user file. */ } #if (USE_HAL_PLAY_REGISTER_CALLBACKS == 1) /** - * @brief Register an User PLAY Callback. - * @note The User PLAY Callback is to be used instead of the weak predefined callback. - * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. - * @param CallbackID ID of the callback to be registered. - * This parameter can be one of the following values: - * @arg @ref HAL_PLAY_SW_TRIGGER_WRITE_CPLT_CB_ID SWIN Write Complete callback ID - * @arg @ref HAL_PLAY_EDGE_TRIGGER_WRITE_CPLT_CB_ID Edge Trigger Write Complete callback ID - * @arg @ref HAL_PLAY_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_PLAY_MSPDEINIT_CB_ID MspDeInit callback ID + * @brief Register a user PLAY Callback. + * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_PLAY_SW_TRIGGER_WRITE_CPLT_CB_ID SWIN Write Complete callback ID + * @arg @ref HAL_PLAY_EDGE_TRIGGER_WRITE_CPLT_CB_ID Edge Trigger Write Complete callback ID + * @arg @ref HAL_PLAY_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_PLAY_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback Pointer to the callback function. - * @note The HAL_PLAY_RegisterCallback() may be called before HAL_PLAY_Init() in HAL_PLAY_STATE_RESET - * to register callbacks for HAL_PLAY_MSPINIT_CB_ID and HAL_PLAY_MSPDEINIT_CB_ID only. - * @return HAL status. + * @note The HAL_PLAY_RegisterCallback() must be called before HAL_PLAY_Init() in @ref HAL_PLAY_STATE_RESET + * to register callbacks for @ref HAL_PLAY_MSPINIT_CB_ID and @ref HAL_PLAY_MSPDEINIT_CB_ID only. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Invalid parameter. */ HAL_StatusTypeDef HAL_PLAY_RegisterCallback(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_CallbackIDTypeDef CallbackID, pPLAY_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; + HAL_PLAY_StateTypeDef tmp_state; - /* Check the PLAY handle allocation */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; } - /* Check the parameters */ - assert_param(IS_PLAY_ALL_INSTANCE(hplay->instance)); - if (pCallback == NULL) { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_PARAM; return HAL_ERROR; } - if (hplay->global_state == HAL_PLAY_STATE_READY) + /* Check the peripheral state */ + tmp_state = hplay->State; + if ((tmp_state == HAL_PLAY_STATE_INIT) || (tmp_state == HAL_PLAY_STATE_READY)) { switch (CallbackID) { @@ -3519,13 +3236,13 @@ HAL_StatusTypeDef HAL_PLAY_RegisterCallback(HAL_PLAY_HandleTypeDef *hplay, HAL_P break; default : - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_CALLBACK; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_CALLBACK; status = HAL_ERROR; break; } } - else if (hplay->global_state == HAL_PLAY_STATE_RESET) + else if (tmp_state == HAL_PLAY_STATE_RESET) { switch (CallbackID) { @@ -3538,7 +3255,7 @@ HAL_StatusTypeDef HAL_PLAY_RegisterCallback(HAL_PLAY_HandleTypeDef *hplay, HAL_P break; default : - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_CALLBACK; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_CALLBACK; status = HAL_ERROR; break; @@ -3546,49 +3263,49 @@ HAL_StatusTypeDef HAL_PLAY_RegisterCallback(HAL_PLAY_HandleTypeDef *hplay, HAL_P } else { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_CALLBACK; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_CALLBACK; status = HAL_ERROR; } - /* Return error status */ return status; } /** - * @brief Register a User PLAY LUT Output Callback. - * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. - * @param CallbackID ID of the callback to be registered. - * This parameter can be one of the following values: - * @arg @ref HAL_PLAY_LUT_OUTPUT_RISING_CB_ID LUT output rising callback ID - * @arg @ref HAL_PLAY_LUT_OUTPUT_FALLING_CB_ID LUT output falling callback ID + * @brief Register a user PLAY LUT Output Callback. + * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_PLAY_LUT_OUTPUT_RISING_CB_ID LUT output rising callback ID + * @arg @ref HAL_PLAY_LUT_OUTPUT_FALLING_CB_ID LUT output falling callback ID * @param pCallback Pointer to the callback function. - * @note The User PLAY Callback is to be used instead of the weak predefined callback. - * @return HAL status. + * @note The user PLAY Callback is to be used instead of the weak predefined callback. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Invalid parameter. */ HAL_StatusTypeDef HAL_PLAY_RegisterLUTOutputCallback(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_CallbackIDTypeDef CallbackID, pPLAY_LUTOutputCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; + HAL_PLAY_StateTypeDef tmp_state; - /* Check the PLAY handle allocation */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; } - /* Check the parameters */ - assert_param(IS_PLAY_ALL_INSTANCE(PLAY_GET_INSTANCE(hplay))); - if (pCallback == NULL) { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_PARAM; return HAL_ERROR; } - if (hplay->global_state == HAL_PLAY_STATE_READY) + /* Check the peripheral state */ + tmp_state = hplay->State; + if ((tmp_state == HAL_PLAY_STATE_INIT) || (tmp_state == HAL_PLAY_STATE_READY)) { switch (CallbackID) { @@ -3602,7 +3319,7 @@ HAL_StatusTypeDef HAL_PLAY_RegisterLUTOutputCallback(HAL_PLAY_HandleTypeDef *hpl default : - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_CALLBACK; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_CALLBACK; status = HAL_ERROR; break; @@ -3611,7 +3328,7 @@ HAL_StatusTypeDef HAL_PLAY_RegisterLUTOutputCallback(HAL_PLAY_HandleTypeDef *hpl else { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_CALLBACK; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_CALLBACK; status = HAL_ERROR; } @@ -3620,33 +3337,33 @@ HAL_StatusTypeDef HAL_PLAY_RegisterLUTOutputCallback(HAL_PLAY_HandleTypeDef *hpl } /** - * @brief Unregister an User PLAY Callback. - * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. + * @brief Unregister a user PLAY Callback. The PLAY callback will be redirected to the weak predefined callback. + * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_PLAY_SW_TRIGGER_WRITE_CPLT_CB_ID SW trigger write complete callback ID - * @arg @ref HAL_PLAY_EDGE_TRIGGER_WRITE_CPLT_CB_ID Edge trigger write complete callback ID - * @arg @ref HAL_PLAY_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_PLAY_MSPDEINIT_CB_ID MspDeInit callback ID - * @note The PLAY callback is redirected to the weak predefined callback. - * @note The HAL_PLAY_UnRegisterCallback() can be called before HAL_PLAY_Init() in HAL_PLAY_STATE_RESET - * to unregister callbacks for HAL_PLAY_MSPINIT_CB_ID and HAL_PLAY_MSPDEINIT_CB_ID only. - * @return HAL status. + * This parameter can be one of the following values: + * @arg @ref HAL_PLAY_SW_TRIGGER_WRITE_CPLT_CB_ID SW trigger write complete callback ID + * @arg @ref HAL_PLAY_EDGE_TRIGGER_WRITE_CPLT_CB_ID Edge trigger write complete callback ID + * @arg @ref HAL_PLAY_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_PLAY_MSPDEINIT_CB_ID MspDeInit callback ID + * @note The HAL_PLAY_UnRegisterCallback() can be called before HAL_PLAY_Init() in @ref HAL_PLAY_STATE_RESET + * to unregister callbacks for @ref HAL_PLAY_MSPINIT_CB_ID and @ref HAL_PLAY_MSPDEINIT_CB_ID only. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Invalid parameter. */ HAL_StatusTypeDef HAL_PLAY_UnRegisterCallback(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; + HAL_PLAY_StateTypeDef tmp_state; - /* Check the PLAY handle allocation */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; } - /* Check the parameters */ - assert_param(IS_PLAY_ALL_INSTANCE(PLAY_GET_INSTANCE(hplay))); - - if (hplay->global_state == HAL_PLAY_STATE_READY) + /* Check the peripheral state */ + tmp_state = hplay->State; + if ((tmp_state == HAL_PLAY_STATE_INIT) || (tmp_state == HAL_PLAY_STATE_READY)) { switch (CallbackID) { @@ -3668,12 +3385,12 @@ HAL_StatusTypeDef HAL_PLAY_UnRegisterCallback(HAL_PLAY_HandleTypeDef *hplay, HAL default: /* Update the error code */ - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_CALLBACK; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_CALLBACK; status = HAL_ERROR; break; } } - else if (hplay->global_state == HAL_PLAY_STATE_RESET) + else if (tmp_state == HAL_PLAY_STATE_RESET) { switch (CallbackID) { @@ -3687,14 +3404,14 @@ HAL_StatusTypeDef HAL_PLAY_UnRegisterCallback(HAL_PLAY_HandleTypeDef *hplay, HAL default: /* Update the error code */ - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_CALLBACK; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_CALLBACK; status = HAL_ERROR; break; } } else { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_CALLBACK; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_CALLBACK; status = HAL_ERROR; } @@ -3702,30 +3419,31 @@ HAL_StatusTypeDef HAL_PLAY_UnRegisterCallback(HAL_PLAY_HandleTypeDef *hplay, HAL } /** - * @brief Unregister a User PLAY LUT Output Callback. - * @note The PLAY callback is redirected to the weak predefined callback. - * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_PLAY_LUT_OUTPUT_RISING_CB_ID LUT output rising callback ID - * @arg @ref HAL_PLAY_LUT_OUTPUT_FALLING_CB_ID LUT output falling callback ID - * @return HAL status. + * @brief Unregister a user PLAY LUT Output Callback. The PLAY callback will be redirected to the weak + * predefined callback. + * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_PLAY_LUT_OUTPUT_RISING_CB_ID LUT output rising callback ID + * @arg @ref HAL_PLAY_LUT_OUTPUT_FALLING_CB_ID LUT output falling callback ID + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Invalid parameter. */ HAL_StatusTypeDef HAL_PLAY_UnRegisterLUTOutputCallback(HAL_PLAY_HandleTypeDef *hplay, HAL_PLAY_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; + HAL_PLAY_StateTypeDef tmp_state; - /* Check the PLAY handle allocation */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; } - /* Check the parameters */ - assert_param(IS_PLAY_ALL_INSTANCE(PLAY_GET_INSTANCE(hplay))); - - if (hplay->global_state == HAL_PLAY_STATE_READY) + /* Check the peripheral state */ + tmp_state = hplay->State; + if ((tmp_state == HAL_PLAY_STATE_INIT) || (tmp_state == HAL_PLAY_STATE_READY)) { switch (CallbackID) { @@ -3738,14 +3456,14 @@ HAL_StatusTypeDef HAL_PLAY_UnRegisterLUTOutputCallback(HAL_PLAY_HandleTypeDef *h break; default : - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_CALLBACK; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_CALLBACK; status = HAL_ERROR; break; } } else { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_CALLBACK; + hplay->ErrorCode |= HAL_PLAY_ERROR_INVALID_CALLBACK; status = HAL_ERROR; } @@ -3759,44 +3477,40 @@ HAL_StatusTypeDef HAL_PLAY_UnRegisterLUTOutputCallback(HAL_PLAY_HandleTypeDef *h /** @addtogroup PLAY_Exported_Functions_Group7 * @{ -A set of functions allowing to retrieve peripheral state,last process errors and kernel clock frequency. -- HAL_PLAY_GetState() : Return the PLAY handle state. -- HAL_PLAY_GetError() : Returns errors limited to the last process. +A set of functions allowing to retrieve peripheral state and last process errors. +- HAL_PLAY_GetState() Return the PLAY handle state. +- HAL_PLAY_GetError() Returns errors limited to the last process. */ /** * @brief Return the HAL PLAY handle state. * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. + * @note This function will return @ref HAL_PLAY_STATE_RESET in case of wrong parameter. * @return Current PLAY state. - * @note This function will return HAL_PLAY_STATE_RESET in case of wrong parameter. */ HAL_PLAY_StateTypeDef HAL_PLAY_GetState(const HAL_PLAY_HandleTypeDef *hplay) { - /* Check parameters */ if (hplay == NULL) { - /* Return HAL_PLAY_STATE_RESET in case of wrong parameter */ return HAL_PLAY_STATE_RESET; } - return hplay->global_state; + return hplay->State; } /** * @brief Get the HAL PLAY last error codes. * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. * @note This function will return 0 in case of wrong parameter. - * @return PLAY Error Code. + * @return PLAY Error Code. This value is a combination of @ref PLAY_Error_Codes values. */ uint32_t HAL_PLAY_GetError(const HAL_PLAY_HandleTypeDef *hplay) { - /* Check parameters */ if (hplay == NULL) { - /* Return 0 in case of wrong parameter */ return 0U; } - return hplay->last_error_codes; + return hplay->ErrorCode; } /** @@ -3805,96 +3519,153 @@ uint32_t HAL_PLAY_GetError(const HAL_PLAY_HandleTypeDef *hplay) /** @addtogroup PLAY_Exported_Functions_Group8 * @{ +A set of functions allowing to manage security and privileged access levels attributes: + - HAL_PLAY_SetSecAttr() Set the security access level attribute. + - HAL_PLAY_GetSecAttr() Get the security access level attribute. + - HAL_PLAY_SetPrivAttr() Set the privileged access level attribute. + - HAL_PLAY_GetPrivAttr() Get the privileged access level attribute. */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** - * @brief Configure the Secure & Privilege attributes. - * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. - * @param p_config Pointer to a @ref HAL_PLAY_AccessControlConfTypeDef structure - * @return HAL status. + * @brief Set the security access level attribute for item(s). + * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. + * @param item This parameter can be one or a combination of the following values: + * @arg @ref HAL_PLAY_SEC_ITEM_CONFIG + * @arg @ref HAL_PLAY_SEC_ITEM_ALL + * @param sec_attr This parameter can be one of the following values: + * @arg @ref HAL_PLAY_SEC + * @arg @ref HAL_PLAY_NSEC + * @retval HAL_OK Security attribute has been set successfully. + * @retval HAL_ERROR Invalid parameter or wrong state. */ -HAL_StatusTypeDef HAL_PLAY_ConfigAttributes(HAL_PLAY_HandleTypeDef *hplay, - const HAL_PLAY_AccessControlConfTypeDef *p_config) +HAL_StatusTypeDef HAL_PLAY_SetSecAttr(const HAL_PLAY_HandleTypeDef *hplay, uint32_t item, + HAL_PLAY_SecAttrTypeDef sec_attr) { PLAY_TypeDef *p_playx; + HAL_PLAY_StateTypeDef tmp_state; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { return HAL_ERROR; } - if (p_config == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; - - return HAL_ERROR; - } - p_playx = PLAY_GET_INSTANCE(hplay); assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); - assert_param(IS_PLAY_TZ_ACCESS_CONTROL(p_config->SecureAccess)); - assert_param(IS_PLAY_TZ_ACCESS_CONTROL(p_config->PrivilegeAccess)); + assert_param(IS_PLAY_SEC_ITEM(item)); + assert_param(IS_PLAY_ITEM_SEC_ATTR(sec_attr)); - if (hplay->global_state != HAL_PLAY_STATE_RESET) + /* Check the peripheral state */ + tmp_state = hplay->State; + if ((tmp_state != HAL_PLAY_STATE_INIT) && (tmp_state != HAL_PLAY_STATE_READY)) { return HAL_ERROR; } - /* Set Secure access */ - uint32_t reg_value = (uint32_t)(p_config->SecureAccess) << PLAY_SECCFGR_SEC_Pos; - ATOMIC_MODIFY_REG(p_playx->SECCFGR, PLAY_SECCFGR_SEC, reg_value); - - /* Set Privilege access */ - reg_value = (uint32_t)(p_config->PrivilegeAccess) << PLAY_PRIVCFGR_PRIV_Pos; - ATOMIC_MODIFY_REG(p_playx->PRIVCFGR, PLAY_PRIVCFGR_PRIV, reg_value); + LL_PLAY_SetSecAttr(p_playx, item, (uint32_t)sec_attr); return HAL_OK; } +#endif /* __ARM_FEATURE_CMSE */ /** - * @brief Get the Secure & Privilege attributes configuration. - * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. - * @param p_config Pointer to a @ref HAL_PLAY_AccessControlConfTypeDef structure. - * @return HAL status. + * @brief Get the security access level attribute of an item. + * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. + * @param item This parameter can be one of the following values: + * @arg @ref HAL_PLAY_SEC_ITEM_CONFIG + * @arg @ref HAL_PLAY_SEC_ITEM_ALL + * @note This function returns @ref HAL_PLAY_NSEC if the handle is NULL. + * @return The security access level attribute. */ -HAL_StatusTypeDef HAL_PLAY_GetConfigAttributes(HAL_PLAY_HandleTypeDef *hplay, - HAL_PLAY_AccessControlConfTypeDef *p_config) +HAL_PLAY_SecAttrTypeDef HAL_PLAY_GetSecAttr(const HAL_PLAY_HandleTypeDef *hplay, uint32_t item) { const PLAY_TypeDef *p_playx; - uint32_t reg_value; - uint32_t sec_value; - uint32_t priv_value; - /* Check parameters */ + /* Check the parameters */ if (hplay == NULL) { - return HAL_ERROR; + return HAL_PLAY_NSEC; } + p_playx = PLAY_GET_INSTANCE(hplay); - if (p_config == NULL) - { - hplay->last_error_codes |= HAL_PLAY_ERROR_INVALID_PARAM; + assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); + assert_param(IS_PLAY_SEC_ITEM(item)); + return ((HAL_PLAY_SecAttrTypeDef)LL_PLAY_GetSecAttr(p_playx, item)); +} + +/** + * @brief Set the privileged access level attribute for item(s). + * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. + * @param item This parameter can be one or a combination of the following values: + * @arg @ref HAL_PLAY_PRIV_ITEM_CONFIG + * @arg @ref HAL_PLAY_PRIV_ITEM_ALL + * @param priv_attr This parameter can be one of the following values: + * @arg @ref HAL_PLAY_PRIV + * @arg @ref HAL_PLAY_NPRIV + * @retval HAL_OK Privileged attribute has been set successfully. + * @retval HAL_ERROR Invalid parameter or wrong state. + */ +HAL_StatusTypeDef HAL_PLAY_SetPrivAttr(const HAL_PLAY_HandleTypeDef *hplay, uint32_t item, + HAL_PLAY_PrivAttrTypeDef priv_attr) +{ + PLAY_TypeDef *p_playx; + HAL_PLAY_StateTypeDef tmp_state; + + /* Check the parameters */ + if (hplay == NULL) + { return HAL_ERROR; } + p_playx = PLAY_GET_INSTANCE(hplay); + assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); + assert_param(IS_PLAY_PRIV_ITEM(item)); + assert_param(IS_PLAY_ITEM_PRIV_ATTR(priv_attr)); - /* Read Secure access */ - reg_value = READ_REG(p_playx->SECCFGR); - sec_value = (reg_value & PLAY_SECCFGR_SEC_Msk) >> PLAY_SECCFGR_SEC_Pos; - p_config->SecureAccess = (HAL_PLAY_TrustZone_AccessControlTypeDef)(sec_value); + /* Check the peripheral state */ + tmp_state = hplay->State; + if ((tmp_state != HAL_PLAY_STATE_INIT) && (tmp_state != HAL_PLAY_STATE_READY)) + { + return HAL_ERROR; + } - /* Read Privilege access */ - reg_value = READ_REG(p_playx->PRIVCFGR); - priv_value = (reg_value & PLAY_PRIVCFGR_PRIV_Msk) >> PLAY_PRIVCFGR_PRIV_Pos; - p_config->PrivilegeAccess = (HAL_PLAY_TrustZone_AccessControlTypeDef)(priv_value); + LL_PLAY_SetPrivAttr(p_playx, item, (uint32_t)priv_attr); return HAL_OK; } +/** + * @brief Get the privileged access level attribute of an item. + * @param hplay Pointer to a @ref HAL_PLAY_HandleTypeDef. + * @param item This parameter can be one of the following values: + * @arg @ref HAL_PLAY_PRIV_ITEM_CONFIG + * @arg @ref HAL_PLAY_PRIV_ITEM_ALL + * @note This function returns @ref HAL_PLAY_NPRIV if the handle is NULL. + * @return The privileged access level attribute. + */ +HAL_PLAY_PrivAttrTypeDef HAL_PLAY_GetPrivAttr(const HAL_PLAY_HandleTypeDef *hplay, uint32_t item) +{ + const PLAY_TypeDef *p_playx; + + /* Check the parameters */ + if (hplay == NULL) + { + return HAL_PLAY_NPRIV; + } + + p_playx = PLAY_GET_INSTANCE(hplay); + + assert_param(IS_PLAY_ALL_INSTANCE(p_playx)); + assert_param(IS_PLAY_PRIV_ITEM(item)); + + return ((HAL_PLAY_PrivAttrTypeDef)LL_PLAY_GetPrivAttr(p_playx, item)); +} + /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c index cb6ca88a7d..8339ef5bbf 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c @@ -115,7 +115,7 @@ /** @defgroup RNG_Private_Constants RNG Private Constants * @{ */ -#define RNG_TIMEOUT_VALUE 4U +#define RNG_TIMEOUT_VALUE 6U /** * @} */ @@ -206,7 +206,11 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) #endif /* RNG_CR_NIST_VALUE */ #if defined(RNG_HTCR_NIST_VALUE) /* Recommended value for NIST compliance, refer to application note AN4230 */ +#if defined(RNG_HTCR3_HTCFG) + WRITE_REG(hrng->Instance->HTCR[0], RNG_HTCR_NIST_VALUE); +#else WRITE_REG(hrng->Instance->HTCR, RNG_HTCR_NIST_VALUE); +#endif /* RNG_HTCR0_HTCFG || RNG_HTCR1_HTCFG || RNG_HTCR2_HTCFG || RNG_HTCR3_HTCFG */ #endif /* RNG_HTCR_NIST_VALUE */ #if defined(RNG_NSCR_NIST_VALUE) WRITE_REG(hrng->Instance->NSCR, RNG_NSCR_NIST_VALUE); @@ -645,11 +649,12 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; /* Check if there is a seed error */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; /* Reset from seed error */ +#if !((defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX))) status = RNG_RecoverSeedError(hrng); if (status == HAL_ERROR) { @@ -657,6 +662,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; return status; } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX) */ } /* Get tick */ @@ -665,6 +671,16 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t /* Check if data register contains valid random data */ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) { + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + { +#if !((defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX))) + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX) */ + hrng->State = HAL_RNG_STATE_READY; + return HAL_ERROR; + } + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { /* New check to avoid false timeout detection in case of preemption */ @@ -811,7 +827,11 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Clear the clock error flag */ +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI); +#else __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI); +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX) */ return; } @@ -1002,7 +1022,7 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng) if (count == 0U) { hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ __HAL_UNLOCK(hrng); #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) @@ -1017,6 +1037,10 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng) } while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_FLAG_SECS)); } /* Update the error code */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + { + return HAL_ERROR; + } hrng->ErrorCode &= ~ HAL_RNG_ERROR_SEED; return HAL_OK; } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c index 693747bdeb..41e369dcc6 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c @@ -51,6 +51,9 @@ /* Private macros ------------------------------------------------------------*/ /* Private functions prototypes ----------------------------------------------*/ /* Private functions --------------------------------------------------------*/ +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +HAL_StatusTypeDef RNG_ResilientRecoverSeedError(RNG_HandleTypeDef *hrng); +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ /* Exported functions --------------------------------------------------------*/ /** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions @@ -127,7 +130,11 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigT (uint32_t)(RNG_CR_CONDRST | cr_value)); /* RNG health test control in accordance with NIST */ +#if defined(RNG_HTCR3_HTCFG) + WRITE_REG(hrng->Instance->HTCR[0], pConf->HealthTest); +#else WRITE_REG(hrng->Instance->HTCR, pConf->HealthTest); +#endif /* RNG_HTCR0_HTCFG || RNG_HTCR1_HTCFG || RNG_HTCR2_HTCFG || RNG_HTCR3_HTCFG */ /* Writing bit CONDRST=0*/ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); @@ -155,6 +162,14 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigT /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; + /*Check if seed error current status (SECS)is set */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_SR_SECS) != RESET) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; + return HAL_ERROR; + } + /* function status */ status = HAL_OK; } @@ -202,7 +217,11 @@ HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef pConf->ClockDivider = (hrng->Instance->CR & RNG_CR_CLKDIV); pConf->NistCompliance = (hrng->Instance->CR & RNG_CR_NISTC); pConf->AutoReset = (hrng->Instance->CR & RNG_CR_ARDIS); +#if defined(RNG_HTCR3_HTCFG) + pConf->HealthTest = (hrng->Instance->HTCR[0]); +#else pConf->HealthTest = (hrng->Instance->HTCR); +#endif /* RNG_HTCR0_HTCFG || RNG_HTCR1_HTCFG || RNG_HTCR2_HTCFG || RNG_HTCR3_HTCFG */ /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; @@ -286,11 +305,13 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) /** * @brief RNG sequence to recover from a seed error * @param hrng: pointer to a RNG_HandleTypeDef structure. + * @warning Recover from seed error will adapt the parameters config1,2,3 to overcome seed error. * @retval HAL status */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) { HAL_StatusTypeDef status; + HAL_RNG_StateTypeDef state; /* Check the RNG handle allocation */ if (hrng == NULL) @@ -298,14 +319,20 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) return HAL_ERROR; } + state = hrng->State; + /* Check RNG peripheral state */ - if (hrng->State == HAL_RNG_STATE_READY) + if ((state == HAL_RNG_STATE_READY) || (state == HAL_RNG_STATE_ERROR)) { /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; /* sequence to fully recover from a seed error */ +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + status = RNG_ResilientRecoverSeedError(hrng); +#else status = RNG_RecoverSeedError(hrng); +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX) */ if (status == HAL_ERROR) { /* Update the error code */ @@ -322,6 +349,77 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) return status; } +#if defined(RNG_HTCR3_HTCFG) +/** + * @brief Configure the RNG additional health tests. + * @param hrng hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @param htcr_idx is a value of the htcr. + * @param htcr_value Health test value. + * @retval HAL_OK configuration succeeded. + * @retval HAL_ERROR configuration fail. + * @retval HAL_INVALID_PARAM invalid parameter. + */ +HAL_StatusTypeDef HAL_RNGEx_SetHealthFactorConfig(RNG_HandleTypeDef *hrng, uint32_t htcr_idx, uint32_t htcr_value) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t tickstart; + + assert_param(IS_RNG_HTCR_INDEX(htcr_idx)); + assert_param(IS_RNG_HTCR_VALUE(htcr_value)); + + /* Check the RNG handle allocation */ + if (hrng == NULL) + { + return HAL_ERROR; + } + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + if (LL_RNG_IsConfigLocked(hrng->Instance) == 0U) + { + LL_RNG_EnableCondReset(hrng->Instance); + LL_RNG_SetAdditionalHealthTest(hrng->Instance, htcr_idx, htcr_value); + LL_RNG_DisableCondReset(hrng->Instance); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for conditioning reset process to be completed */ + while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of prememption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } + } + } + } + + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_READY; + + /* function status */ + status = HAL_OK; + } + else + { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + return status; +} +#endif /* defined(RNG_HTCR0_HTCFG || RNG_HTCR1_HTCFG || RNG_HTCR2_HTCFG) */ /** * @} */ @@ -330,6 +428,202 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) * @} */ +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions + * @brief RNGEx Private Functions + * @{ + */ + +/** + * @brief RNG sequence to resilient recover from a seed error + * @param hrng pointer to a RNG_HandleTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef RNG_ResilientRecoverSeedError(RNG_HandleTypeDef *hrng) +{ + uint32_t timeout; + uint32_t htsr_temp = 0U; + uint32_t htsr_previous_temp = 0U; + uint32_t htsr_count = 0U; + uint32_t nsmr_temp = 0U; + uint32_t tickstart1 = 0U; + uint32_t tickstart2 = 0U; + uint32_t tickstart3 = 0U; + uint32_t oscillators_count = 0U; + uint32_t config_b_fewer_than_6_osc_count = 0U; + uint8_t count = 0U; + + /* timeout here is an emperic value */ + timeout = (1UL + ((1UL << (READ_BIT(hrng->Instance->CR, RNG_CR_CLKDIV) >> 16UL)) * RNG_TIMEOUT_VALUE / 8UL)); + LL_RNG_Enable(hrng->Instance); + + tickstart1 = HAL_GetTick(); + + /* Check if seed error current status indicates no error and auto-reset succeeded */ + if (LL_RNG_IsActiveFlag_SECS(hrng->Instance) == 0U) + { + /* Clear SEIS flag when automatic reset is activated */ + LL_RNG_ClearFlag_SEIS(hrng->Instance); + } + + else /* Sequence to fully recover from a seed error*/ + { + if (LL_RNG_IsConfigLocked(hrng->Instance) == 0U) + { + do + { + if (LL_RNG_IsActiveFlag_SECS(hrng->Instance) == 0U) + { + break; + } + /* Read oscillator status registers combined */ + htsr_temp = LL_RNG_GetHealthTestStatus(hrng->Instance, 0U); + htsr_temp |= LL_RNG_GetHealthTestStatus(hrng->Instance, 1U); + if (htsr_temp > 0U) + { + /* If any oscillator status bits overlap with previous status, increment counter */ + if ((htsr_temp & htsr_previous_temp) != 0U) + { + htsr_count++; + } + + if (htsr_count > 3U) + { + /* if the same repetitive or adaptative error is detected 3 times */ + nsmr_temp = LL_RNG_GetNoiseSourceMask(hrng->Instance); + + /* deactivate the same osc in each triple oscillator (Mask oscillators with the seed error by + clearing bits shifted right by 1) */ + nsmr_temp = nsmr_temp & ~(htsr_temp >> 1U); + + /* Count the number of active oscillators in nsmr */ + oscillators_count = 0U; + for (count = 0U; count < 9U; count++) + { + if (((nsmr_temp >> count) & 0x1U) != 0U) + { + /* increment count1 for each 1 in nsmr */ + oscillators_count++; + } + } + + if (oscillators_count < 6U) + { + /* If fewer than 6 oscillators remain active, unmask all oscillators --> Reset masking */ + nsmr_temp = LL_RNG_GetOscNoiseSrc(hrng->Instance, LL_RNG_NOISE_SRC_1 | LL_RNG_NOISE_SRC_2 \ + | LL_RNG_NOISE_SRC_3); + htsr_previous_temp = 0; + htsr_count = 0U; + if ((hrng->Instance->CR & RNG_CR_CLKDIV_Msk) < ((uint32_t)RNG_CAND_NIST_CR_VALUE & RNG_CR_CLKDIV_Msk)) + { + config_b_fewer_than_6_osc_count++; + } + } + + if (config_b_fewer_than_6_osc_count > 2U) + { + /* Reset RNG condition */ + WRITE_REG(hrng->Instance->CR, (RNG_CR_CONDRST_Msk | (uint32_t)RNG_CAND_NIST_CR_VALUE)); + + /* Update mask register with new oscillator mask */ + LL_RNG_SetNoiseSourceMask(hrng->Instance, nsmr_temp); + + /* Clear condition reset bit to resume operation */ + LL_RNG_DisableCondReset(hrng->Instance); + } + + else + { + /* Reset RNG condition */ + WRITE_REG(hrng->Instance->CR, (hrng->Instance->CR & ~RNG_CR_RNGEN_Msk) | RNG_CR_CONDRST_Msk); + + /* Update mask register with new oscillator mask */ + LL_RNG_SetNoiseSourceMask(hrng->Instance, nsmr_temp); + + /* Clear condition reset bit to resume operation */ + LL_RNG_DisableCondReset(hrng->Instance); + } + } + + else + { + /* Briefly toggle conditional reset to recover RNG */ + WRITE_REG(hrng->Instance->CR, (hrng->Instance->CR & ~RNG_CR_RNGEN_Msk) | RNG_CR_CONDRST_Msk); + + /* unmask all oscillators to find another working condition */ + LL_RNG_SetNoiseSourceMask(hrng->Instance, LL_RNG_GetOscNoiseSrc(hrng->Instance, LL_RNG_OSC_1\ + | LL_RNG_OSC_2 | LL_RNG_OSC_3)); + LL_RNG_DisableCondReset(hrng->Instance); + } + + /* Wait until RNG is not busy */ + tickstart2 = HAL_GetTick(); + do + { + if ((HAL_GetTick() - tickstart2) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + LL_RNG_Disable(hrng->Instance); + hrng->State = HAL_RNG_STATE_ERROR; + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_SR_BUSY)); + + /* No timeout --> Enable RNG */ + LL_RNG_Enable(hrng->Instance); + tickstart3 = HAL_GetTick(); + do + { + if (LL_RNG_IsActiveFlag_DRDY(hrng->Instance) != 0UL) + { + break; + } + if ((HAL_GetTick() - tickstart3) > timeout) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_RNG_IsActiveFlag_DRDY(hrng->Instance) == 0UL) + { + if (LL_RNG_IsActiveFlag_SECS(hrng->Instance) == 0UL) + { + LL_RNG_Disable(hrng->Instance); + hrng->State = HAL_RNG_STATE_ERROR; + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } + } + } + } while (LL_RNG_IsActiveFlag_SECS(hrng->Instance) == 0UL); + + /* Accumulate seed error status bits */ + htsr_previous_temp = htsr_previous_temp | htsr_temp; + } + } while ((HAL_GetTick() - tickstart1) <= timeout); + } + } + + /*Check if seed error current status (SECS)is set */ + if (LL_RNG_IsActiveFlag_SECS(hrng->Instance) != 0U) + { + hrng->ErrorCode &= HAL_RNG_ERROR_SEED; + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } + + /* Update the error code */ + hrng->ErrorCode &= ~ HAL_RNG_ERROR_SEED; + + /* Return the function status */ + hrng->State = HAL_RNG_STATE_READY; + __HAL_UNLOCK(hrng); + return HAL_OK; +} + +/** + * @} + */ +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ #endif /* RNG_CR_CONDRST */ #endif /* HAL_RNG_MODULE_ENABLED */ /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c index 37e5767a9b..31d6db9a1c 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c @@ -491,7 +491,14 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; return HAL_ERROR; } - Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ); + if (sdmmc_clk <= SD_INIT_FREQ) + { + Init.ClockDiv = 0U; + } + else + { + Init.ClockDiv = (sdmmc_clk / (2U * SD_INIT_FREQ)) + 1U; + } #if (USE_SD_TRANSCEIVER != 0U) Init.TranceiverPresent = hsd->Init.TranceiverPresent; @@ -3128,7 +3135,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ errorstate = SDMMC_CmdOperCond(hsd->Instance); - if (errorstate == SDMMC_ERROR_TIMEOUT) /* No response to CMD8 */ + if (errorstate == SDMMC_ERROR_CMD_RSP_TIMEOUT) /* No response to CMD8 */ { hsd->SdCard.CardVersion = CARD_V1_X; /* CMD0: GO_IDLE_STATE */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdio.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdio.c index e9a18d3294..2f80c3ec33 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdio.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdio.c @@ -228,21 +228,21 @@ /** @addtogroup SDIO_Private_Defines * @{ */ -#define SDIO_INIT_FREQ 400000UL /*!< Initialization phase : 400 kHz max */ -#define SDIO_TIMEOUT 1000UL /*!< SDIO timeout millisecond */ +#define SDIO_INIT_FREQ 400000U /*!< Initialization phase : 400 kHz max */ +#define SDIO_TIMEOUT 1000U /*!< SDIO timeout millisecond */ -#define SDIO_FUNCTION_0 0x00UL /*!< SDIO_Functions 0 */ -#define SDIO_FUNCTION_1 0x01UL /*!< SDIO_Functions 1 */ +#define SDIO_FUNCTION_0 0x00UL /*!< SDIO_Functions 0 */ +#define SDIO_FUNCTION_1 0x01UL /*!< SDIO_Functions 1 */ -#define SDIO_READ 0x0UL /*!< Read flag for cmd52 and cmd53 */ -#define SDIO_WRITE 0x1UL /*!< Write flag for cmd52 and cmd53 */ +#define SDIO_READ 0x0UL /*!< Read flag for cmd52 and cmd53 */ +#define SDIO_WRITE 0x1UL /*!< Write flag for cmd52 and cmd53 */ -#define SDIO_BUS_SPEED_SDR12 0x00UL /*!< SDIO bus speed mode SDR12 */ -#define SDIO_BUS_SPEED_SDR25 0x02UL /*!< SDIO bus speed mode SDR25 */ -#define SDIO_BUS_SPEED_SDR50 0x04UL /*!< SDIO bus speed mode SDR50 */ -#define SDIO_BUS_SPEED_DDR50 0x08UL /*!< SDIO bus speed mode DDR50 */ +#define SDIO_BUS_SPEED_SDR12 0x00U /*!< SDIO bus speed mode SDR12 */ +#define SDIO_BUS_SPEED_SDR25 0x02U /*!< SDIO bus speed mode SDR25 */ +#define SDIO_BUS_SPEED_SDR50 0x04U /*!< SDIO bus speed mode SDR50 */ +#define SDIO_BUS_SPEED_DDR50 0x08U /*!< SDIO bus speed mode DDR50 */ -#define SDIO_CCCR_REG_NUMBER 0x16UL /*!< SDIO card cccr register number */ +#define SDIO_CCCR_REG_NUMBER 0x16U /*!< SDIO card cccr register number */ #define SDIO_OCR_VDD_32_33 (1UL << 20U) #define SDIO_OCR_SDIO_S18R (1UL << 24U) @@ -1036,7 +1036,14 @@ HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDI cmd |= Argument->Block_Mode << 27U; cmd |= Argument->OpCode << 26U; cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; - cmd |= (Size_byte & 0x1FFU); + if (Argument->Block_Mode == HAL_SDIO_MODE_BYTE) + { + cmd |= (((uint32_t)Size_byte) & 0x1FFU); + } + else /* HAL_SDIO_BLOCK_MODE_BLOCK */ + { + cmd |= nbr_of_block & 0x1FFU; + } errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); if (errorstate != HAL_SDIO_ERROR_NONE) { @@ -1181,7 +1188,7 @@ HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, const HAL_SD uint8_t byteCount; uint32_t data; uint32_t dataremaining; - uint8_t *u32tempbuff = pData; + uint32_t *u32tempbuff = (uint32_t *)(uint32_t)pData; uint32_t nbr_of_block; /* Check the parameters */ @@ -1241,7 +1248,14 @@ HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, const HAL_SD cmd |= Argument->Block_Mode << 27U; cmd |= Argument->OpCode << 26U; cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; - cmd |= (Size_byte & 0x1FFU); + if (Argument->Block_Mode == HAL_SDIO_MODE_BYTE) + { + cmd |= (((uint32_t)Size_byte) & 0x1FFU); + } + else /* HAL_SDIO_BLOCK_MODE_BLOCK */ + { + cmd |= nbr_of_block & 0x1FFU; + } errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); if (errorstate != HAL_SDIO_ERROR_NONE) { @@ -1693,7 +1707,6 @@ void HAL_SDIO_IRQHandler(SDIO_HandleTypeDef *hsdio) } hsdio->Context = SDIO_CONTEXT_NONE; - hsdio->State = HAL_SDIO_STATE_READY; } if (hsdio->remaining_data != 0U) @@ -2517,7 +2530,7 @@ static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio) uint32_t errorstate; uint32_t timeout = 0U; uint16_t sdio_rca = 1U; - uint32_t Resp4; + uint32_t Resp4 = 0U; uint32_t nbr_of_func; /* Identify card operating voltage */ @@ -2858,7 +2871,7 @@ static uint8_t SDIO_Convert_Block_Size(const SDIO_HandleTypeDef *hsdio, uint32_t static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio) { uint8_t count; - uint8_t pendingInt; + uint8_t pendingInt = 0U; if (hsdio->IOInterruptNbr == 1U) { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdram.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdram.c index 9b533b41ca..e69c7da910 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdram.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdram.c @@ -916,13 +916,11 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd * @param hsdram : SDRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: - * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID (*) - * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID (*) - * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID (*) + * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID + * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID + * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID * @param pCallback : pointer to the Callback function * @retval status - * - * (*) : For all h5 series */ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback) @@ -986,14 +984,12 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SD * @param hsdram : SDRAM handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: - * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID (*) - * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID (*) - * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID (*) - * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID (*) - * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID (*) + * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID + * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID + * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID + * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID * @retval status - * - * (*) : For all h5 series */ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId) { @@ -1057,12 +1053,10 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_ * @param hsdram : SDRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: - * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID (*) - * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID (*) + * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID * @param pCallback : pointer to the Callback function * @retval status - * - * (*) : For all h5 series */ HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c index 62a740c020..b90717f272 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c @@ -2510,14 +2510,6 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard ((uint32_t)hsmartcard->Init.WordLength)); MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); - /*-------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = hsmartcard->Init.StopBits; - /* Synchronous mode is activated by default */ - tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; - tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; - tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; - MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); - /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure * - one-bit sampling method versus three samples' majority rule @@ -2539,6 +2531,14 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos)); MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg); + /*-------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = hsmartcard->Init.StopBits; + /* Synchronous mode is activated by default */ + tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; + tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; + tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); + /*-------------------------- USART RTOR Configuration ----------------------*/ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c index 46adf27fe8..9190ff38d9 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c @@ -865,12 +865,10 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre * @param hsram : SRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: - * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID (*) - * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID (*) + * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID + * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID * @param pCallback : pointer to the Callback function * @retval status - * - * (*) : For all h5 series */ HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback) @@ -915,13 +913,11 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_ * @param hsram : SRAM handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: - * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID (*) - * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID (*) - * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID (*) - * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID (*) + * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID + * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID + * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID * @retval status - * - * (*) : For all h5 series */ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId) { @@ -982,12 +978,10 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRA * @param hsram : SRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: - * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID (*) - * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID (*) + * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID * @param pCallback : pointer to the Callback function * @retval status - * - * (*) : For all h5 series */ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c index f70c8c2a13..47fb47b622 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c @@ -89,7 +89,7 @@ ErrorStatus LL_EXTI_DeInit(void) LL_EXTI_WriteReg(IMR2, 0x07DBFFFFU); #elif defined(STM32H503xx) LL_EXTI_WriteReg(IMR2, 0x001BFFFFU); -#elif defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) ||defined(STM32H5E4xx) +#elif defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H553xx) || defined(STM32H543xx) LL_EXTI_WriteReg(IMR2, 0xF3D9BFFFU); #else LL_EXTI_WriteReg(IMR2, 0x03DBBFFFU); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_play.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_play.c index 506188b8ac..7c75eaeb9f 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_play.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_play.c @@ -54,9 +54,8 @@ /** * @brief De-Initialize PLAY peripheral registers to their default reset values. * @param PLAYx PLAY Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: PLAY registers are de-initialized - * - ERROR: PLAY registers are not de-initialized + * @retval SUCCESS Operation completed successfully. + * @retval ERROR Invalid instance. */ ErrorStatus LL_PLAY_DeInit(PLAY_TypeDef *PLAYx) { @@ -70,7 +69,6 @@ ErrorStatus LL_PLAY_DeInit(PLAY_TypeDef *PLAYx) /* Unlock the Configuration Registers */ LL_PLAY_Unlock(PLAYx); - /* Reset Configuration Registers which are not reset by */ /* Force PLAY reset */ LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_PLAY1APB); @@ -78,11 +76,11 @@ ErrorStatus LL_PLAY_DeInit(PLAY_TypeDef *PLAYx) LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_PLAY1APB); /* Privilege register set to default reset values */ - LL_PLAY_ConfigPrivilege(PLAYx, LL_PLAY_NPRIV); + LL_PLAY_SetPrivAttr(PLAYx, LL_PLAY_PRIV_ITEM_ALL, LL_PLAY_ATTR_NPRIV); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Secure register set to default reset values */ - LL_PLAY_ConfigSecure(PLAYx, LL_PLAY_NSEC); + LL_PLAY_SetSecAttr(PLAYx, LL_PLAY_SEC_ITEM_ALL, LL_PLAY_ATTR_NSEC); #endif /* __ARM_FEATURE_CMSE */ } else diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c index 55d6b77f10..20bd49d2c6 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c @@ -3324,6 +3324,16 @@ void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABu } } +/** + * @brief Return Current Frame number + * @param USBx Selected device + * @retval current frame number + */ +uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx) +{ + return (uint32_t)(USBx->FNR & 0x7FFU); +} + /*------------------------------------------------------------------------*/ /* HOST API */ @@ -3403,16 +3413,6 @@ uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx) } } -/** - * @brief Return Host Current Frame number - * @param USBx Selected device - * @retval current frame number - */ -uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx) -{ - return USBx->FNR & 0x7FFU; -} - #if defined (HAL_HCD_MODULE_ENABLED) /** * @brief Initialize a host channel diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 1a099a3214..556d2f6f33 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -9,7 +9,7 @@ * STM32F7: 1.3.3 * STM32G0: 1.4.7 * STM32G4: 1.2.7 - * STM32H5: 1.6.0 + * STM32H5: 1.7.0 * STM32H7: 1.11.6 * STM32L0: 1.10.7 * STM32L1: 1.4.6 From facd24703c425ef73d2af6ed59aacdde4d16c66f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Jul 2026 09:31:38 +0200 Subject: [PATCH 2/3] system(h5): update STM32H5xx CMSIS Drivers to v1.7.0 Included in STM32CubeH5 FW v1.7.0 Signed-off-by: Frederic Pillon --- .../Include/Templates/partition_stm32h543xx.h | 669 + .../Include/Templates/partition_stm32h553xx.h | 672 + .../STM32H5xx/Include/partition_stm32h5xx.h | 4 + .../Device/ST/STM32H5xx/Include/stm32h503xx.h | 82 +- .../Device/ST/STM32H5xx/Include/stm32h523xx.h | 82 +- .../Device/ST/STM32H5xx/Include/stm32h533xx.h | 82 +- .../Device/ST/STM32H5xx/Include/stm32h543xx.h | 24782 +++++++++++++++ .../Device/ST/STM32H5xx/Include/stm32h553xx.h | 25428 ++++++++++++++++ .../Device/ST/STM32H5xx/Include/stm32h562xx.h | 64 +- .../Device/ST/STM32H5xx/Include/stm32h563xx.h | 64 +- .../Device/ST/STM32H5xx/Include/stm32h573xx.h | 64 +- .../Device/ST/STM32H5xx/Include/stm32h5e4xx.h | 321 +- .../Device/ST/STM32H5xx/Include/stm32h5e5xx.h | 321 +- .../Device/ST/STM32H5xx/Include/stm32h5f4xx.h | 257 +- .../Device/ST/STM32H5xx/Include/stm32h5f5xx.h | 257 +- .../Device/ST/STM32H5xx/Include/stm32h5xx.h | 12 +- .../CMSIS/Device/ST/STM32H5xx/README.md | 4 +- .../Device/ST/STM32H5xx/Release_Notes.html | 70 +- .../Device/ST/STM32H5xx/Release_Notes.md | 175 + .../Templates/gcc/linker/STM32H543xx_FLASH.ld | 188 + .../gcc/linker/STM32H543xx_FLASH_ns.ld | 188 + .../gcc/linker/STM32H543xx_FLASH_s.ld | 197 + .../Templates/gcc/linker/STM32H553xx_FLASH.ld | 188 + .../gcc/linker/STM32H553xx_FLASH_ns.ld | 188 + .../gcc/linker/STM32H553xx_FLASH_s.ld | 197 + .../Templates/gcc/startup_stm32h543xx.s | 679 + .../Templates/gcc/startup_stm32h553xx.s | 691 + .../Templates/gcc/startup_stm32h562xx.s | 4 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 29 files changed, 55389 insertions(+), 543 deletions(-) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h543xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h553xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h543xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h553xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.md create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H543xx_FLASH.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H543xx_FLASH_ns.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H543xx_FLASH_s.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H553xx_FLASH.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H553xx_FLASH_ns.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H553xx_FLASH_s.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h543xx.s create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h553xx.s diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h543xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h543xx.h new file mode 100644 index 0000000000..f12f8a1e65 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h543xx.h @@ -0,0 +1,669 @@ +/** + ****************************************************************************** + * @file partition_stm32h543xx.h + * @author MCD Application Team + * @brief CMSIS STM32H543xx Device Header File for Initial Setup for Secure / + * Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h + * Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32H543XX_H +#define PARTITION_STM32H543XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C07E000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C07FFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08080000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x080FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20034000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x2004BFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// ADC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..124 +// GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// UART7_IRQn <0=> Secure state <1=> Non-Secure state +// UART8_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE_IRQn <0=> Secure state <1=> Non-Secure state +// ETH_IRQn <0=> Secure state <1=> Non-Secure state +// ETH_WKUP_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// CEC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 131..149 +// I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// PLA_NS_IRQn <0=> Secure state <1=> Non-Secure state +// PLA_S_IRQn <0=> Secure state <1=> Non-Secure state +// ADC3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32H543XX_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h553xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h553xx.h new file mode 100644 index 0000000000..ac4e10f53d --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h553xx.h @@ -0,0 +1,672 @@ +/** + ****************************************************************************** + * @file partition_stm32h553xx.h + * @author MCD Application Team + * @brief CMSIS STM32H553xx Device Header File for Initial Setup for Secure / + * Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h + * Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32H553XX_H +#define PARTITION_STM32H553XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C07E000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C07FFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08080000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x080FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20034000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x2004BFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// ADC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..124 +// GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// UART7_IRQn <0=> Secure state <1=> Non-Secure state +// UART8_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE_IRQn <0=> Secure state <1=> Non-Secure state +// ETH_IRQn <0=> Secure state <1=> Non-Secure state +// ETH_WKUP_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// CEC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 131..149 +// I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// PLA_NS_IRQn <0=> Secure state <1=> Non-Secure state +// PLA_S_IRQn <0=> Secure state <1=> Non-Secure state +// ADC3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32H553XX_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/partition_stm32h5xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/partition_stm32h5xx.h index 3b353f10d5..cec9da5a90 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/partition_stm32h5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/partition_stm32h5xx.h @@ -56,6 +56,10 @@ #include "partition_stm32h563xx.h" #elif defined(STM32H562xx) #include "partition_stm32h562xx.h" +#elif defined(STM32H553xx) + #include "partition_stm32h553xx.h" +#elif defined(STM32H543xx) + #include "partition_stm32h543xx.h" #elif defined(STM32H533xx) #include "partition_stm32h533xx.h" #elif defined(STM32H523xx) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h index d6d4715ddc..9bb9784a0f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h @@ -339,10 +339,11 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /** @@ -2690,6 +2691,7 @@ typedef struct #define COMP_CFGR1_POLARITY_Msk (0x1UL << COMP_CFGR1_POLARITY_Pos) /*!< 0x00000008 */ #define COMP_CFGR1_POLARITY COMP_CFGR1_POLARITY_Msk /*!< COMP1 polarity selection bit */ + #define COMP_CFGR1_ITEN_Pos (6U) #define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ #define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< COMP1 interrupt enable */ @@ -2706,6 +2708,7 @@ typedef struct #define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ #define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ + #define COMP_CFGR1_INMSEL_Pos (16U) #define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ #define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< COMP1 input minus selection bit */ @@ -2965,42 +2968,42 @@ typedef struct /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2U) -#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3U) -#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5U) -#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7U) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8U) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12U) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13U) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16U) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30U) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31U) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0U) @@ -3019,6 +3022,25 @@ typedef struct #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ #define RNG_SR_SEIS RNG_SR_SEIS_Msk +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9U) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12U) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15U) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk /******************** Bits definition for RNG_HTCR register *******************/ #define RNG_HTCR_HTCFG_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h523xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h523xx.h index c86716de5a..9a2c9dbe0f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h523xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h523xx.h @@ -368,10 +368,11 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /** @@ -4034,42 +4035,42 @@ typedef struct /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2U) -#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3U) -#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5U) -#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7U) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8U) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12U) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13U) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16U) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30U) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31U) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0U) @@ -4088,6 +4089,25 @@ typedef struct #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ #define RNG_SR_SEIS RNG_SR_SEIS_Msk +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9U) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12U) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15U) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk /******************** Bits definition for RNG_HTCR register *******************/ #define RNG_HTCR_HTCFG_Pos (0U) @@ -10828,7 +10848,7 @@ typedef struct /**************** Bit definition for XSPI_DCR3 register ******************/ #define XSPI_DCR3_CSBOUND_Pos (16U) #define XSPI_DCR3_CSBOUND_Msk (0x1FUL << XSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */ -#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< Maximum transfer */ +#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< NCS boundary */ /**************** Bit definition for XSPI_DCR4 register ******************/ #define XSPI_DCR4_REFRESH_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h index 0c843a0c54..521851965f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h @@ -405,10 +405,11 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /** @@ -4193,42 +4194,42 @@ typedef struct /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2U) -#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3U) -#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5U) -#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7U) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8U) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12U) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13U) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16U) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30U) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31U) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0U) @@ -4247,6 +4248,25 @@ typedef struct #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ #define RNG_SR_SEIS RNG_SR_SEIS_Msk +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9U) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12U) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15U) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk /******************** Bits definition for RNG_HTCR register *******************/ #define RNG_HTCR_HTCFG_Pos (0U) @@ -11220,7 +11240,7 @@ typedef struct /**************** Bit definition for XSPI_DCR3 register ******************/ #define XSPI_DCR3_CSBOUND_Pos (16U) #define XSPI_DCR3_CSBOUND_Msk (0x1FUL << XSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */ -#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< Maximum transfer */ +#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< NCS boundary */ /**************** Bit definition for XSPI_DCR4 register ******************/ #define XSPI_DCR4_REFRESH_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h543xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h543xx.h new file mode 100644 index 0000000000..bace8aaef8 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h543xx.h @@ -0,0 +1,24782 @@ +/** + ****************************************************************************** + * @file stm32h543xx.h + * @author MCD Application Team + * @brief CMSIS STM32H543xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32H543xx_H +#define STM32H543xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32H543xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32H543xx Specific Interrupt Numbers ====================================== */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + GPDMA1_Channel0_IRQn = 27, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 28, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 29, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 30, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 31, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 32, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 33, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 34, /*!< GPDMA1 Channel 7 global interrupt */ + IWDG_IRQn = 35, /*!< IWDG global interrupt */ + ADC1_IRQn = 37, /*!< ADC1 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + I2C1_EV_IRQn = 51, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 52, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 53, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 54, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 55, /*!< SPI1 global interrupt */ + SPI2_IRQn = 56, /*!< SPI2 global interrupt */ + SPI3_IRQn = 57, /*!< SPI3 global interrupt */ + USART1_IRQn = 58, /*!< USART1 global interrupt */ + USART2_IRQn = 59, /*!< USART2 global interrupt */ + USART3_IRQn = 60, /*!< USART3 global interrupt */ + UART4_IRQn = 61, /*!< UART4 global interrupt */ + UART5_IRQn = 62, /*!< UART5 global interrupt */ + LPUART1_IRQn = 63, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 64, /*!< LPTIM1 global interrupt */ + TIM8_BRK_IRQn = 65, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 66, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 67, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 68, /*!< TIM8 Capture Compare interrupt */ + ADC2_IRQn = 69, /*!< ADC2 global interrupt */ + LPTIM2_IRQn = 70, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 71, /*!< TIM15 global interrupt */ + USB_DRD_FS_IRQn = 74, /*!< USB FS global interrupt */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + UCPD1_IRQn = 76, /*!< UCPD1 global interrupt */ + FMC_IRQn = 77, /*!< FMC global interrupt */ + OCTOSPI1_IRQn = 78, /*!< OctoSPI1 global interrupt */ + SDMMC1_IRQn = 79, /*!< SDMMC1 global interrupt */ + I2C3_EV_IRQn = 80, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 81, /*!< I2C3 error interrupt */ + SPI4_IRQn = 82, /*!< SPI4 global interrupt */ + USART6_IRQn = 85, /*!< USART6 global interrupt */ + GPDMA2_Channel0_IRQn = 90, /*!< GPDMA2 Channel 0 global interrupt */ + GPDMA2_Channel1_IRQn = 91, /*!< GPDMA2 Channel 1 global interrupt */ + GPDMA2_Channel2_IRQn = 92, /*!< GPDMA2 Channel 2 global interrupt */ + GPDMA2_Channel3_IRQn = 93, /*!< GPDMA2 Channel 3 global interrupt */ + GPDMA2_Channel4_IRQn = 94, /*!< GPDMA2 Channel 4 global interrupt */ + GPDMA2_Channel5_IRQn = 95, /*!< GPDMA2 Channel 5 global interrupt */ + GPDMA2_Channel6_IRQn = 96, /*!< GPDMA2 Channel 6 global interrupt */ + GPDMA2_Channel7_IRQn = 97, /*!< GPDMA2 Channel 7 global interrupt */ + UART7_IRQn = 98, /*!< UART7 global interrupt */ + UART8_IRQn = 99, /*!< UART8 global interrupt */ + FPU_IRQn = 103, /*!< FPU global interrupt */ + ICACHE_IRQn = 104, /*!< Instruction cache global interrupt */ + DCACHE1_IRQn = 105, /*!< Data cache global interrupt */ + ETH_IRQn = 106, /*!< Ethernet global interrupt */ + ETH_WKUP_IRQn = 107, /*!< Ethernet Wakeup global interrupt */ + FDCAN2_IT0_IRQn = 109, /*!< FDCAN2 interrupt 0 */ + FDCAN2_IT1_IRQn = 110, /*!< FDCAN2 interrupt 1 */ + CORDIC_IRQn = 111, /*!< CORDIC global interrupt */ + DTS_IRQn = 113, /*!< DTS global interrupt */ + RNG_IRQn = 114, /*!< RNG global interrupt */ + HASH_IRQn = 117, /*!< HASH global interrupt */ + PKA_IRQn = 118, /*!< PKA global interrupt */ + CEC_IRQn = 119, /*!< CEC-HDMI global interrupt */ + TIM12_IRQn = 120, /*!< TIM12 global interrupt */ + I3C1_EV_IRQn = 123, /*!< I3C1 event interrupt */ + I3C1_ER_IRQn = 124, /*!< I3C1 error interrupt */ + I3C2_EV_IRQn = 131, /*!< I3C2 Event interrupt */ + I3C2_ER_IRQn = 132, /*!< I3C2 Error interrupt */ + COMP_IRQn = 133, /*!< COMP1 COMP2 global interrupt */ + PLAY1_IRQn = 147, /*!< PLAY1 global non-secure interrupt */ + PLAY1_S_IRQn = 148, /*!< PLAY1 global secure interrupt */ + ADC3_IRQn = 149, /*!< ADC3 global interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + __IO uint32_t MISR; /*!< masked interrupt status register, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HRA[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[42]; /*!< HASH digest registers, Address offset: 0x310-0x3B4 */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2[23]; /*!< Reserved, 0x24 - 0x7C */ + __IO uint32_t EDBGRQ; /*!< Debug MCU EDBGRQ register, Address offset: 0x80 */ + uint32_t RESERVED3[30]; /*!< Reserved, 0x84 - 0xF8 */ + __IO uint32_t SR; /*!< Debug MCU SR register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug DBG_AUTH_HOST register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug DBG_AUTH_DEV register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug DBG_AUTH_ACK register, Address offset: 0x108 */ + uint32_t RESERVED4[945]; /*!< Reserved, 0x10C - 0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU Peripheral ID register 4, Address offset: 0xFD0 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xFD4 - 0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU Peripheral ID register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU Peripheral ID register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU Peripheral ID register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU Peripheral ID register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU Component ID register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU Component ID register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU Component ID register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU Component ID register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWJBTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + __IO uint32_t MACHWF3R; + uint32_t RESERVED11[53]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[4]; + uint32_t RESERVED14[3]; + __IO uint32_t MACCSRSWCR; + uint32_t RESERVED15[3]; + __IO uint32_t MACPRSTIMR; + __IO uint32_t MACPRSTIMUR; + uint32_t RESERVED16[46]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED17[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED18[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED19[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED20[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED21[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED22[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED23[41]; + __IO uint32_t MMCFPETISR; + __IO uint32_t MMCFPETIMR; + __IO uint32_t MMCFPETFCR; + __IO uint32_t MMCTHRCR; + uint32_t RESERVED24[4]; + __IO uint32_t MMCFPERISR; + __IO uint32_t MMCFPERIMR; + __IO uint32_t MMCRPAER; + __IO uint32_t MMCRPSMDER; + __IO uint32_t MMCRPAOKR; + __IO uint32_t MMCFPERFCR; + uint32_t RESERVED25[10]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED26[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED27[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED28[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED29[72]; + __IO uint32_t MACIACR; + __IO uint32_t MACTMRQR; + uint32_t RESERVED30[34]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED31; + __IO uint32_t MACTSSR; + __IO uint32_t MACRXDTI; + __IO uint32_t MACTXDTI; + uint32_t RESERVED32; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED33[2]; + __IO uint32_t MACACR; + uint32_t RESERVED34; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED35[2]; + __IO uint32_t MACTSILR; + __IO uint32_t MACTSELR; + __IO uint32_t MACPPSCR; + uint32_t RESERVED36[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED37[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED38[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED39[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED40[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED41[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED42[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED43[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED44[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED45; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED46; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; + uint32_t RESERVED47[2]; + __IO uint32_t DMACCATDR; + uint32_t RESERVED48; + __IO uint32_t DMACCARDR; + uint32_t RESERVED49; + __IO uint32_t DMACCATBR; + uint32_t RESERVED50; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; + __IO uint32_t DMACMFCR; +}ETH_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ + __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */ + __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x3C */ + __IO uint32_t RTSR3; /*!< EXTI Rising Trigger Selection Register 3, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling Trigger Selection Register 3, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software Interrupt event Register 3, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Pending Register 3, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Pending Register 3, Address offset: 0x50 */ + __IO uint32_t SECCFGR3; /*!< EXTI Security Configuration Register 3, Address offset: 0x54 */ + __IO uint32_t PRIVCFGR3; /*!< EXTI Privilege Configuration Register 3, Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved 3, Address offset: 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED4[3]; /*!< Reserved 4, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED5[2]; /*!< Reserved 5, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ + uint32_t RESERVED6[2]; /*!< Reserved 6, 0x98 -- 0x9C */ + __IO uint32_t IMR3; /*!< EXTI Interrupt Mask Register 3, Address offset: 0xA0 */ + __IO uint32_t EMR3; /*!< EXTI Event Mask Register 3, Address offset: 0xA4 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x04 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t NSOBKKEYR; /*!< FLASH non-secure option bytes keys key register, Address offset: 0x10 */ + __IO uint32_t SECOBKKEYR; /*!< FLASH secure option bytes keys key register, Address offset: 0x14 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x18 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, Address offset: 0x30 */ + __IO uint32_t SECCCR; /*!< FLASH secure clear control register, Address offset: 0x34 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x38 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x3C */ + __IO uint32_t NSOBKCFGR; /*!< FLASH non-secure option byte key configuration register, Address offset: 0x40 */ + __IO uint32_t SECOBKCFGR; /*!< FLASH secure option byte key configuration register, Address offset: 0x44 */ + __IO uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x4C */ + __IO uint32_t OPTSR_CUR; /*!< FLASH option status current register, Address offset: 0x50 */ + __IO uint32_t OPTSR_PRG; /*!< FLASH option status to program register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x58-0x5C */ + __IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, Address offset: 0x60 */ + __IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, Address offset: 0x64 */ + __IO uint32_t SECEPOCHR_CUR; /*!< FLASH secure epoch current register, Address offset: 0x68 */ + __IO uint32_t SECEPOCHR_PRG; /*!< FLASH secure epoch to program register, Address offset: 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< FLASH option status current register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< FLASH option status to program register 2, Address offset: 0x74 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x78-0x7C */ + __IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, Address offset: 0x80 */ + __IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, Address offset: 0x84 */ + __IO uint32_t SECBOOTR_CUR; /*!< FLASH secure unique boot entry current register, Address offset: 0x88 */ + __IO uint32_t SECBOOTR_PRG; /*!< FLASH secure unique boot entry to program register, Address offset: 0x8C */ + __IO uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock current register, Address offset: 0x90 */ + __IO uint32_t OTPBLR_PRG; /*!< FLASH OTP block Lock to program register, Address offset: 0x94 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x98-0x9C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0xA4 */ + uint32_t RESERVED6[6]; /*!< Reserved6, Address offset: 0xA8-0xBC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xC0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xC4 */ + uint32_t RESERVED7[6]; /*!< Reserved7, Address offset: 0xC8-0xDC */ + __IO uint32_t SECWM1R_CUR; /*!< FLASH secure watermark 1 current register, Address offset: 0xE0 */ + __IO uint32_t SECWM1R_PRG; /*!< FLASH secure watermark 1 to program register, Address offset: 0xE4 */ + __IO uint32_t WRP1R_CUR; /*!< FLASH write sector group protection current register for bank1, Address offset: 0xE8 */ + __IO uint32_t WRP1R_PRG; /*!< FLASH write sector group protection to program register for bank1, Address offset: 0xEC */ + __IO uint32_t EDATA1R_CUR; /*!< FLASH data sectors configuration current register for bank1, Address offset: 0xF0 */ + __IO uint32_t EDATA1R_PRG; /*!< FLASH data sectors configuration to program register for bank1, Address offset: 0xF4 */ + __IO uint32_t HDP1R_CUR; /*!< FLASH HDP configuration current register for bank1, Address offset: 0xF8 */ + __IO uint32_t HDP1R_PRG; /*!< FLASH HDP configuration to program register for bank1, Address offset: 0xFC */ + __IO uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IO uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IO uint32_t ECCDR; /*!< FLASH ECC data register, Address offset: 0x108 */ + uint32_t RESERVED8[37]; /*!< Reserved8, Address offset: 0x10C-0x19C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0x1A0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0x1A4 */ + uint32_t RESERVED9[6]; /*!< Reserved9, Address offset: 0x1A8-0x1BC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0x1C0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0x1C4 */ + uint32_t RESERVED10[6]; /*!< Reserved10, Address offset: 0x1C8-0x1DC */ + __IO uint32_t SECWM2R_CUR; /*!< FLASH secure watermark 2 current register, Address offset: 0x1E0 */ + __IO uint32_t SECWM2R_PRG; /*!< FLASH secure watermark 2 to program register, Address offset: 0x1E4 */ + __IO uint32_t WRP2R_CUR; /*!< FLASH write sector group protection current register for bank2, Address offset: 0x1E8 */ + __IO uint32_t WRP2R_PRG; /*!< FLASH write sector group protection to program register for bank2, Address offset: 0x1EC */ + __IO uint32_t EDATA2R_CUR; /*!< FLASH data sectors configuration current register for bank2, Address offset: 0x1F0 */ + __IO uint32_t EDATA2R_PRG; /*!< FLASH data sectors configuration to program register for bank2, Address offset: 0x1F4 */ + __IO uint32_t HDP2R_CUR; /*!< FLASH HDP configuration current register for bank2, Address offset: 0x1F8 */ + __IO uint32_t HDP2R_PRG; /*!< FLASH HDP configuration to program register for bank2, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + __IO uint32_t MPCWM3BCFGR; /*!< TZSC memory 3 sub-region B watermark configuration register, Address offset: 0x68 */ + __IO uint32_t MPCWM3BR; /*!< TZSC memory 3 sub-region B watermark register, Address offset: 0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + __IO uint32_t MPCWM4BCFGR; /*!< TZSC memory 4 sub-region B watermark configuration register, Address offset: 0x78 */ + __IO uint32_t MPCWM4BR; /*!< TZSC memory 4 sub-region B watermark register, Address offset: 0x7c */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x17C */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x1FC */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ +} COMPOPT_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR1; /*!< Comparator configuration register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR1_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CFGR1_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + + +/** + * @brief Programmable Logic Array (PLAY) + */ +typedef struct +{ + __IO uint32_t CFGCR; /*!< PLAY Configuration Control Register, Address offset: 0x00 */ + __IO uint32_t SECCFGR; /*!< PLAY Security attributes Configuration Register, Address offset: 0x04 */ + __IO uint32_t PRIVCFGR; /*!< PLAY Privilege attributes Configuration Register, Address offset: 0x08 */ + uint32_t reserved1[5]; /*!< Reserved Address offset: 0x0C-0x18 */ + __IO uint32_t FILTCFG[16]; /*!< PLAY Filter Configuration Registers, Address offset: 0x20 */ + __IO uint32_t LECFG1[16]; /*!< PLAY Logic Element Configuration Registers 1, Address offset: 0x60 */ + __IO uint32_t LECFG2[16]; /*!< PLAY Logic Element Configuration Registers 2, Address offset: 0xA0 */ + uint32_t reserved2[8]; /*!< Reserved Address offset: 0xE0-0xFC */ + __IO uint32_t OUTCFG[16]; /*!< PLAY Output Configuration Registers, Address offset: 0x0100 */ + uint32_t reserved3[48]; /*!< Reserved Address offset: 0x0140-0x01FC */ + __IO uint32_t SWIN; /*!< PLAY Software Input Status Register, Address offset: 0x0200 */ + __IO uint32_t SWINSET; /*!< PLAY Software Input Set Register, Address offset: 0x0204 */ + __IO uint32_t SWINCLR; /*!< PLAY Software Input Clear Register, Address offset: 0x0208 */ + uint32_t reserved4; /*!< Reserved Address offset: 0x020C */ + __IO uint32_t OSR; /*!< PLAY Output Status Register, Address offset: 0x0210 */ + uint32_t reserved5[3]; /*!< Reserved Address offset: 0x0214-0x021C */ + __IO uint32_t FLSTAT; /*!< PLAY Flag Status Register, Address offset: 0x0220 */ + __IO uint32_t FLSET; /*!< PLAY Flag Set Register, Address offset: 0x0224 */ + __IO uint32_t FLCLR; /*!< PLAY Flag Clear Register, Address offset: 0x0228 */ + __IO uint32_t FLIER; /*!< PLAY Flag Interrupt Enable Register, Address offset: 0x022C */ + __IO uint32_t FLCTL; /*!< PLAY Flag Control Register, Address offset: 0x0230 */ + __IO uint32_t MSR; /*!< PLAY Miscellaneous Status Register, Address offset: 0x0234 */ + __IO uint32_t ISR; /*!< PLAY Interrupt Status Register, Address offset: 0x0238 */ + __IO uint32_t ICR; /*!< PLAY Interrupt Clear Register, Address offset: 0x023C */ + __IO uint32_t IER; /*!< PLAY Interrupt Enable Register, Address offset: 0x0240 */ +} PLAY_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t PMCR; /*!< Power mode control register , Address offset: 0x00 */ + __IO uint32_t PMSR; /*!< Power mode status register , Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t VOSCR; /*!< Voltage scaling control register , Address offset: 0x10 */ + __IO uint32_t VOSSR; /*!< Voltage sacling status register , Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t BDCR; /*!< BacKup domain control register , Address offset: 0x20 */ + __IO uint32_t DBPCR; /*!< DBP control register, Address offset: 0x24 */ + __IO uint32_t BDSR; /*!< BacKup domain status register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Usb typeC and Power Delivery Register, Address offset: 0x2C */ + __IO uint32_t SCCR; /*!< Supply configuration control register, Address offset: 0x30 */ + __IO uint32_t VMCR; /*!< Voltage Monitor Control Register, Address offset: 0x34 */ + __IO uint32_t USBSCR; /*!< USB Supply Control Register Address offset: 0x38 */ + __IO uint32_t VMSR; /*!< Status Register Voltage Monitoring, Address offset: 0x3C */ + __IO uint32_t WUSCR; /*!< WakeUP status clear register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< WakeUP status Register, Address offset: 0x44 */ + __IO uint32_t WUCR; /*!< WakeUP configuration register, Address offset: 0x48 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t IORETR; /*!< IO RETention Register, Address offset: 0x50 */ + uint32_t RESERVED4[43];/*!< Reserved, Address offset: 0x54-0xFC */ + __IO uint32_t SECCFGR; /*!< Security configuration register, Address offset: 0x100 */ + __IO uint32_t PRIVCFGR; /*!< Privilege configuration register, Address offset: 0x104 */ +}PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + __IO uint32_t WPR3; /*!< SRAM Write Protection Register 3, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t HSICFGR; /*!< RCC HSI Clock Calibration Register, Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x14 */ + __IO uint32_t CSICFGR; /*!< RCC CSI Clock Calibration Register, Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register Address offset: 0x2C */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x44 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 Peripherals Reset Register Address offset: 0x64 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x68 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 Peripherals reset Low Word register Address offset: 0x74 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 Peripherals reset High Word register Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED10; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 Peripherals Clock Enable Register Address offset: 0x8C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x90 */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 Peripherals clock Enable Low Word register Address offset: 0x9C */ + __IO uint32_t APB1HENR; /*!< RCC APB1 Peripherals clock Enable High Word register Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 Peripheral sleep clock Register Address offset: 0xB0 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 Peripheral sleep clock Register Address offset: 0xB4 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0xB8 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 Peripherals sleep clock Register Address offset: 0xBC */ + uint32_t RESERVED17; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 Peripherals sleep clock Low Word Register Address offset: 0xC4 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 Peripherals sleep clock High Word Register Address offset: 0xC8 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 Peripherals sleep clock Register Address offset: 0xCC */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 Peripherals Clock Low Power Enable Register Address offset: 0xD0 */ + uint32_t RESERVED18; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t CCIPR1; /*!< RCC IPs Clocks Configuration Register 1 Address offset: 0xD8 */ + __IO uint32_t CCIPR2; /*!< RCC IPs Clocks Configuration Register 2 Address offset: 0xDC */ + __IO uint32_t CCIPR3; /*!< RCC IPs Clocks Configuration Register 3 Address offset: 0xE0 */ + __IO uint32_t CCIPR4; /*!< RCC IPs Clocks Configuration Register 4 Address offset: 0xE4 */ + __IO uint32_t CCIPR5; /*!< RCC IPs Clocks Configuration Register 5 Address offset: 0xE8 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< RCC VSW Backup Domain & V33 Domain Control Register Address offset: 0xF0 */ + __IO uint32_t RSR; /*!< RCC Reset status Register Address offset: 0xF4 */ + uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC Secure mode configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x64 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */ + __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; +/** + * @brief System configuration, Boot and Security + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */ + __IO uint32_t HDPLCR; /*!< SBS HDPL Control Register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS HDPL Status Register, Address offset: 0x14 */ + __IO uint32_t NEXTHDPLCR; /*!< NEXT HDPL Control Register, Address offset: 0x18 */ + __IO uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control Register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock Register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */ + __IO uint32_t RSSCMDR; /*!< SBS RSS Command Register, Address offset: 0x34 */ + uint32_t RESERVED4[26]; /*!< RESERVED4, Address offset: 0x38 - 0x9C */ + __IO uint32_t EPOCHSELCR; /*!< EPOCH Selection Register, Address offset: 0xA0 */ + uint32_t RESERVED5[7]; /*!< RESERVED5, Address offset: 0xA4 - 0xBC */ + __IO uint32_t SECCFGR; /*!< SBS Security Mode Configuration, Address offset: 0xC0 */ + uint32_t RESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config Register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask Register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status Register, Address offset: 0x108 */ + uint32_t RESERVED7; /*!< RESERVED7, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS Compensation Cell Control & Status Register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS Compensation Cell Value Register, Address offset: 0x114 */ + __IO uint32_t CCSWCR; /*!< SBS Compensation Cell for I/Os sw code Register, Address offset: 0x118 */ + __IO uint32_t RESERVED8; /*!< RESERVED8, Address offset: 0x11C */ + __IO uint32_t CFGR2; /*!< SBS Class B Register, Address offset: 0x120 */ + uint32_t RESERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */ + __IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset: 0x144 */ + __IO uint32_t CSLCKR; /*!< SBS CPU Secure Lock Register, Address offset: 0x148 */ + __IO uint32_t ECCNMIR; /*!< SBS FLITF ECC NMI MASK Register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ + + +#define SRAM1_SIZE (0x20000UL) /*!< SRAM1=128k */ +#define SRAM2_SIZE (0x14000UL) /*!< SRAM2=80k */ +#define SRAM3_SIZE (0x18000UL) /*!< SRAM3=96k */ +#define BKPSRAM_SIZE (0x00800UL) /*!< BKPSRAM=2k */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 1 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (128 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20020000UL) /*!< SRAM2 (80 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x20034000UL) /*!< SRAM3 (96 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) /*!< FMC Memory Bank1 for SRAM, NOR and PSRAM */ +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< FMC Memory Bank3 for NAND */ +#define FMC_SDRAM_BANK_1 (FMC_BASE + 0x60000000UL) /*!< FMC Memory SDRAM Bank1 */ +#define FMC_SDRAM_BANK_2 (FMC_BASE + 0x70000000UL) /*!< FMC Memory SDRAM Bank2 */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) +#define COMP12_BASE_NS (APB1PERIPH_BASE_NS + 0x4000UL) +#define COMP1_BASE_NS (COMP12_BASE_NS + 0x0CUL) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x10UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define CEC_BASE_NS (APB1PERIPH_BASE_NS + 0x7000UL) +#define UART7_BASE_NS (APB1PERIPH_BASE_NS + 0x7800UL) +#define UART8_BASE_NS (APB1PERIPH_BASE_NS + 0x7C00UL) +#define DTS_BASE_NS (APB1PERIPH_BASE_NS + 0x8C00UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x6000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x6400UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define GPDMA2_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03800UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ETH_BASE_NS (AHB1PERIPH_BASE_NS + 0x8000UL) +#define ETH_MAC_BASE_NS (ETH_BASE) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA2_Channel0_BASE_NS (GPDMA2_BASE_NS + 0x0050UL) +#define GPDMA2_Channel1_BASE_NS (GPDMA2_BASE_NS + 0x00D0UL) +#define GPDMA2_Channel2_BASE_NS (GPDMA2_BASE_NS + 0x0150UL) +#define GPDMA2_Channel3_BASE_NS (GPDMA2_BASE_NS + 0x01D0UL) +#define GPDMA2_Channel4_BASE_NS (GPDMA2_BASE_NS + 0x0250UL) +#define GPDMA2_Channel5_BASE_NS (GPDMA2_BASE_NS + 0x02D0UL) +#define GPDMA2_Channel6_BASE_NS (GPDMA2_BASE_NS + 0x0350UL) +#define GPDMA2_Channel7_BASE_NS (GPDMA2_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define ADC3_BASE_NS (AHB2PERIPH_BASE_NS + 0x0D800UL) +#define ADC3_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x0DB00UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) + +/*!< APB3 Non secure peripherals */ +#define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define I3C2_BASE_NS (APB3PERIPH_BASE_NS + 0x3000UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) +#define PLAY1_BASE_NS (APB3PERIPH_BASE_NS + 0x8000UL) + +/*!< AHB3 Non secure peripherals */ +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define DEBUG_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) + +/*!< AHB4 Non secure peripherals */ +#define SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8400UL) +#define FMC_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_NS (AHB4PERIPH_BASE_NS + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define FMC_Bank5_6_R_BASE_NS (FMC_R_BASE_NS + 0x0140UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 1 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (128 KB) secure base address */ +#define SRAM2_BASE_S (0x30020000UL) /*!< SRAM2 (80 KB) secure base address */ +#define SRAM3_BASE_S (0x30034000UL) /*!< SRAM3 (96 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) + +/*!< APB1 secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) +#define COMP12_BASE_S (APB1PERIPH_BASE_S + 0x4000UL) +#define COMP1_BASE_S (COMP12_BASE_S + 0x0CUL) +#define COMP2_BASE_S (COMP12_BASE_S + 0x10UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define CEC_BASE_S (APB1PERIPH_BASE_S + 0x7000UL) +#define UART7_BASE_S (APB1PERIPH_BASE_S + 0x7800UL) +#define UART8_BASE_S (APB1PERIPH_BASE_S + 0x7C00UL) +#define DTS_BASE_S (APB1PERIPH_BASE_S + 0x8C00UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA800UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x6000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x6400UL) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_BASE_S AHB1PERIPH_BASE_S +#define GPDMA2_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x03800UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define ETH_BASE_S (AHB1PERIPH_BASE_S + 0x8000UL) +#define ETH_MAC_BASE_S (ETH_BASE_S) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA2_Channel0_BASE_S (GPDMA2_BASE_S + 0x0050UL) +#define GPDMA2_Channel1_BASE_S (GPDMA2_BASE_S + 0x00D0UL) +#define GPDMA2_Channel2_BASE_S (GPDMA2_BASE_S + 0x0150UL) +#define GPDMA2_Channel3_BASE_S (GPDMA2_BASE_S + 0x01D0UL) +#define GPDMA2_Channel4_BASE_S (GPDMA2_BASE_S + 0x0250UL) +#define GPDMA2_Channel5_BASE_S (GPDMA2_BASE_S + 0x02D0UL) +#define GPDMA2_Channel6_BASE_S (GPDMA2_BASE_S + 0x0350UL) +#define GPDMA2_Channel7_BASE_S (GPDMA2_BASE_S + 0x03D0UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) + +/*!< AHB2 secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x08400UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define ADC3_BASE_S (AHB2PERIPH_BASE_S + 0x0D800UL) +#define ADC3_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x0DB00UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) + +/*!< APB3 secure peripherals */ +#define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define I3C2_BASE_S (APB3PERIPH_BASE_S + 0x3000UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) +#define PLAY1_BASE_S (APB3PERIPH_BASE_S + 0x8000UL) + +/*!< AHB3 secure peripherals */ +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define DEBUG_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) + +/*!< AHB4 secure peripherals */ +#define SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) +#define DLYB_SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8400UL) +#define FMC_R_BASE_S (AHB4PERIPH_BASE_S + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_S (AHB4PERIPH_BASE_S + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_S (AHB4PERIPH_BASE_S + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define FMC_Bank5_6_R_BASE_S (FMC_R_BASE_S + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x44024000UL) +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ +#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */ + +/* Flash system Area */ +#define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */ +#define FLASH_SYSTEM_BASE_S (0x0FF80000UL) /*!< FLASH System secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes system Flash */ + +/* Internal Flash EDATA Area */ +#define FLASH_EDATA_BASE_NS (0x09000000UL) /*!< FLASH high-cycle data non-secure base address */ +#define FLASH_EDATA_BASE_S (0x0D000000UL) /*!< FLASH high-cycle data secure base address */ +#define FLASH_EDATA_SIZE (0x18000U) /*!< 96 KB of Flash high-cycle data */ + +/* Internal Flash OBK Area */ +#define FLASH_OBK_BASE_NS (0x0BFD0000UL) /*!< FLASH OBK (option byte keys) non-secure base address */ +#define FLASH_OBK_BASE_S (0x0FFD0000UL) /*!< FLASH OBK (option byte keys) secure base address */ +#define FLASH_OBK_SIZE (0x2000U) /*!< 8 KB of option byte keys */ +#define FLASH_OBK_HDPL0_SIZE (0x100U) /*!< 256 Bytes of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL1_BASE_NS (FLASH_OBK_BASE_NS + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 non-secure base address */ +#define FLASH_OBK_HDPL1_BASE_S (FLASH_OBK_BASE_S + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 secure base address */ +#define FLASH_OBK_HDPL1_SIZE (0x800U) /*!< 2 KB of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL2_BASE_NS (FLASH_OBK_HDPL1_BASE_NS + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 non-secure base address */ +#define FLASH_OBK_HDPL2_BASE_S (FLASH_OBK_HDPL1_BASE_S + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 secure base address */ +#define FLASH_OBK_HDPL2_SIZE (0x300U) /*!< 768 Bytes of HDPL2 option byte keys */ + +#define FLASH_OBK_HDPL3_BASE_NS (FLASH_OBK_HDPL2_BASE_NS + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3_BASE_S (FLASH_OBK_HDPL2_BASE_S + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3_SIZE (0x13F0U) /*!< 5104 Bytes HDPL3 option byte keys */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_OBK_HDPL3S_BASE_NS (FLASH_OBK_HDPL3_BASE_NS) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3S_BASE_S (FLASH_OBK_HDPL3_BASE_S) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3S_SIZE (0x0C00U) /*!< 3072 Bytes of secure HDPL3 option byte keys */ + +#define FLASH_OBK_HDPL3NS_BASE_NS (FLASH_OBK_HDPL3_BASE_NS + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3NS_BASE_S (FLASH_OBK_HDPL3_BASE_S + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */ +#endif /* CMSE */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BFAE068UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BFAE084UL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0x0BFAE068UL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it jumps to the non-secure reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3NS_TypeDef)(uint32_t VectorTableAddr); + +/** + * @brief Input parameter definition of RSSLIB_DataProvisioning + */ +typedef struct +{ + uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ + uint32_t *pDestination; /*!< Address in OBKeys sections where to provision Data */ + uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ + uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ + uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ +} RSSLIB_DataProvisioningConf_t; + +/** + * @brief Prototype of RSSLIB Data Provisioning Function + * @detail This function write Data within OBKeys sections. + * @param pointer on the structure defining Data to be provisioned and where to + * provision them within OBKeys sections. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_NSC_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); + + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM RSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; + __IM RSSLIB_S_JumpHDPlvl3NS_TypeDef JumpHDPLvl3NS; +} S_pFuncTypeDef; + +/** + * @brief RSSLib Non-secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_NSC_DataProvisioning_TypeDef DataProvisioning; +} NSC_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + uint32_t RESERVED1[3]; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/*!< Non Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define NSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BFAE06CUL) +#define NSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BFAE074UL) + +/************ RSSLIB function return constants ********************************/ +#define NSSLIB_ERROR (0xF5F5F5F5UL) +#define NSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define NSSLIB_PFUNC_BASE (0x0BFAE06CUL) +#define NSSLIB_PFUNC ((NSSLIB_pFunc_TypeDef *)NSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM NSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; +} NSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *)TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *)TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *)TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *)TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *)TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *)TIM7_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *)TIM12_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *)WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *)IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *)SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *)SPI3_BASE_NS) +#define COMP12_NS ((COMPOPT_TypeDef *)COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *)COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *)COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define USART2_NS ((USART_TypeDef *)USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *)USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *)UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *)UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *)I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *)I2C2_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *)I3C1_BASE_NS) +#define CRS_NS ((CRS_TypeDef *)CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *)USART6_BASE_NS) +#define CEC_NS ((CEC_TypeDef *)CEC_BASE_NS) +#define UART7_NS ((USART_TypeDef *)UART7_BASE_NS) +#define UART8_NS ((USART_TypeDef *)UART8_BASE_NS) +#define DTS_NS ((DTS_TypeDef *)DTS_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *)LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_NS) +#define FDCAN2_NS ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *)UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA2_NS ((DMA_TypeDef *) GPDMA2_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define ETH_NS ((ETH_TypeDef *) ETH_BASE_NS) +#define ETH_MAC_NS ((ETH_TypeDef *) ETH_MAC_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA2_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_NS) +#define GPDMA2_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_NS) +#define GPDMA2_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_NS) +#define GPDMA2_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_NS) +#define GPDMA2_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_NS) +#define GPDMA2_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_NS) +#define GPDMA2_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_NS) +#define GPDMA2_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define ADC3_NS ((ADC_TypeDef *) ADC3_BASE_NS) +#define ADC3_COMMON_NS ((ADC_Common_TypeDef *) ADC3_COMMON_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) + + +/*!< APB3 Non secure peripherals */ +#define SBS_NS ((SBS_TypeDef *) SBS_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) +#define PLAY1_NS ((PLAY_TypeDef *) PLAY1_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) + +/*!< AHB4 Non secure peripherals */ +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) + +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define FMC_Bank5_6_R_NS ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *)TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *)TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *)TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *)TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *)TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *)TIM7_BASE_S) +#define TIM12_S ((TIM_TypeDef *)TIM12_BASE_S) +#define WWDG_S ((WWDG_TypeDef *)WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *)IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *)SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *)SPI3_BASE_S) +#define COMP12_S ((COMPOPT_TypeDef *)COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *)COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *)COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define USART2_S ((USART_TypeDef *)USART2_BASE_S) +#define USART3_S ((USART_TypeDef *)USART3_BASE_S) +#define UART4_S ((USART_TypeDef *)UART4_BASE_S) +#define UART5_S ((USART_TypeDef *)UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *)I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *)I2C2_BASE_S) +#define I3C1_S ((I3C_TypeDef *)I3C1_BASE_S) +#define CRS_S ((CRS_TypeDef *)CRS_BASE_S) +#define USART6_S ((USART_TypeDef *)USART6_BASE_S) +#define CEC_S ((CEC_TypeDef *)CEC_BASE_S) +#define UART7_S ((USART_TypeDef *)UART7_BASE_S) +#define UART8_S ((USART_TypeDef *)UART8_BASE_S) +#define DTS_S ((DTS_TypeDef *)DTS_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *)LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_S) +#define FDCAN2_S ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *)UCPD1_BASE_S) + +/*!< APB2 secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *)USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA2_S ((DMA_TypeDef *) GPDMA2_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define ETH_S ((ETH_TypeDef *) ETH_BASE_S) +#define ETH_MAC_S ((ETH_TypeDef *) ETH_MAC_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA2_Channel0_S ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_S) +#define GPDMA2_Channel1_S ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_S) +#define GPDMA2_Channel2_S ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_S) +#define GPDMA2_Channel3_S ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_S) +#define GPDMA2_Channel4_S ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_S) +#define GPDMA2_Channel5_S ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_S) +#define GPDMA2_Channel6_S ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_S) +#define GPDMA2_Channel7_S ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_S) + + +/*!< AHB2 secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define ADC3_S ((ADC_TypeDef *) ADC3_BASE_S) +#define ADC3_COMMON_S ((ADC_Common_TypeDef *) ADC3_COMMON_BASE_S) + +/*!< APB3 secure peripherals */ +#define SBS_S ((SBS_TypeDef *) SBS_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) +#define PLAY1_S ((PLAY_TypeDef *) PLAY1_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) + +/*!< AHB4 secure peripherals */ +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) + +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define FMC_Bank5_6_R_S ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S) + +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define FLASH_OBK_BASE FLASH_OBK_BASE_S +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_S +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define APB3PERIPH_BASE APB3PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_S +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + + +#define DTS DTS_S +#define DTS_BASE DTS_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA2 GPDMA2_S +#define GPDMA2_BASE GPDMA2_BASE_S + +#define GPDMA2_Channel0 GPDMA2_Channel0_S +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_S + +#define GPDMA2_Channel1 GPDMA2_Channel1_S +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_S + +#define GPDMA2_Channel2 GPDMA2_Channel2_S +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_S + +#define GPDMA2_Channel3 GPDMA2_Channel3_S +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_S + +#define GPDMA2_Channel4 GPDMA2_Channel4_S +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_S + +#define GPDMA2_Channel5 GPDMA2_Channel5_S +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_S + +#define GPDMA2_Channel6 GPDMA2_Channel6_S +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_S + +#define GPDMA2_Channel7 GPDMA2_Channel7_S +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define SPI4 SPI4_S +#define SPI4_BASE SPI4_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define UART7 UART7_S +#define UART7_BASE UART7_BASE_S + +#define UART8 UART8_S +#define UART8_BASE UART8_BASE_S + +#define CEC CEC_S +#define CEC_BASE CEC_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S + +#define I3C2 I3C2_S +#define I3C2_BASE I3C2_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define FDCAN2 FDCAN2_S +#define FDCAN2_BASE FDCAN2_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SBS SBS_S +#define SBS_BASE SBS_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + +#define ADC3 ADC3_S +#define ADC3_BASE ADC3_BASE_S + +#define ADC3_COMMON ADC3_COMMON_S +#define ADC3_COMMON_BASE ADC3_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define ETH ETH_S +#define ETH_BASE ETH_BASE_S +#define ETH_MAC ETH_MAC_S +#define ETH_MAC_BASE ETH_MAC_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define FMC_Bank5_6_R FMC_Bank5_6_R_S +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S + +#define PLAY1 PLAY1_S +#define PLAY1_BASE PLAY1_BASE_S + +#else + +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define FLASH_OBK_BASE FLASH_OBK_BASE_NS +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_NS +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_NS + +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS + +#define SRAM3_BASE SRAM3_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS + +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define APB3PERIPH_BASE APB3PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_NS +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + + +#define DTS DTS_NS +#define DTS_BASE DTS_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA2 GPDMA2_NS +#define GPDMA2_BASE GPDMA2_BASE_NS + +#define GPDMA2_Channel0 GPDMA2_Channel0_NS +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_NS + +#define GPDMA2_Channel1 GPDMA2_Channel1_NS +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_NS + +#define GPDMA2_Channel2 GPDMA2_Channel2_NS +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_NS + +#define GPDMA2_Channel3 GPDMA2_Channel3_NS +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_NS + +#define GPDMA2_Channel4 GPDMA2_Channel4_NS +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_NS + +#define GPDMA2_Channel5 GPDMA2_Channel5_NS +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_NS + +#define GPDMA2_Channel6 GPDMA2_Channel6_NS +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_NS + +#define GPDMA2_Channel7 GPDMA2_Channel7_NS +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define SPI4 SPI4_NS +#define SPI4_BASE SPI4_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define UART7 UART7_NS +#define UART7_BASE UART7_BASE_NS + +#define UART8 UART8_NS +#define UART8_BASE UART8_BASE_NS + +#define CEC CEC_NS +#define CEC_BASE CEC_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS + +#define I3C2 I3C2_NS +#define I3C2_BASE I3C2_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define FDCAN2 FDCAN2_NS +#define FDCAN2_BASE FDCAN2_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SBS SBS_NS +#define SBS_BASE SBS_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + + +#define ETH ETH_NS +#define ETH_BASE ETH_BASE_NS +#define ETH_MAC ETH_MAC_NS +#define ETH_MAC_BASE ETH_MAC_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define FMC_Bank5_6_R FMC_Bank5_6_R_NS +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define ADC3 ADC3_NS +#define ADC3_BASE ADC3_BASE_NS + +#define ADC3_COMMON ADC3_COMMON_NS +#define ADC3_COMMON_BASE ADC3_COMMON_BASE_NS + +#define PLAY1 PLAY1_NS +#define PLAY1_BASE PLAY1_BASE_NS +#endif + + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP18_Msk /*!< ADC channel 19 sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register *****************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x01UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC Option bit 0 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/**********************************************************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/**********************************************************************************************************************/ +#define COMP_WINDOW_MODE_SUPPORT /*!< COMP feature available only on specific devices */ + + +/********************************** Bit definition for COMP_SR register *****************************************/ +#define COMP_SR_C1VAL_Pos (0U) +#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */ +#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk + +#define COMP_SR_C2VAL_Pos (1U) +#define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos) /*!< 0x00000002 */ +#define COMP_SR_C2VAL COMP_SR_C2VAL_Msk + +#define COMP_SR_C1IF_Pos (16U) +#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */ +#define COMP_SR_C1IF COMP_SR_C1IF_Msk + +#define COMP_SR_C2IF_Pos (17U) +#define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos) /*!< 0x00020000 */ +#define COMP_SR_C2IF COMP_SR_C2IF_Msk + +/********************************** Bit definition for COMP_ICFR register *****************************************/ +#define COMP_ICFR_CC1IF_Pos (16U) +#define COMP_ICFR_CC1IF_Msk (0x1UL << COMP_ICFR_CC1IF_Pos) /*!< 0x00010000 */ +#define COMP_ICFR_CC1IF COMP_ICFR_CC1IF_Msk + +#define COMP_ICFR_CC2IF_Pos (17U) +#define COMP_ICFR_CC2IF_Msk (0x1UL << COMP_ICFR_CC2IF_Pos) /*!< 0x00020000 */ +#define COMP_ICFR_CC2IF COMP_ICFR_CC2IF_Msk + +/********************************** Bit definition for COMP_CFGR1 register **************************************/ +#define COMP_CFGR1_EN_Pos (0U) +#define COMP_CFGR1_EN_Msk (0x1UL << COMP_CFGR1_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR1_EN COMP_CFGR1_EN_Msk /*!< COMP1 enable bit */ + +#define COMP_CFGR1_BRGEN_Pos (1U) +#define COMP_CFGR1_BRGEN_Msk (0x1UL << COMP_CFGR1_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR1_BRGEN COMP_CFGR1_BRGEN_Msk /*!< COMP1 Scaler bridge enable */ + +#define COMP_CFGR1_SCALEN_Pos (2U) +#define COMP_CFGR1_SCALEN_Msk (0x1UL << COMP_CFGR1_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR1_SCALEN COMP_CFGR1_SCALEN_Msk /*!< COMP1 Voltage scaler enable bit */ + +#define COMP_CFGR1_POLARITY_Pos (3U) +#define COMP_CFGR1_POLARITY_Msk (0x1UL << COMP_CFGR1_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR1_POLARITY COMP_CFGR1_POLARITY_Msk /*!< COMP1 polarity selection bit */ + +#define COMP_CFGR1_WINMODE_Pos (4U) +#define COMP_CFGR1_WINMODE_Msk (0x1UL << COMP_CFGR1_WINMODE_Pos) /*!< 0x00000010 */ +#define COMP_CFGR1_WINMODE COMP_CFGR1_WINMODE_Msk /*!< COMP1 window mode selection bit */ + +#define COMP_CFGR1_ITEN_Pos (6U) +#define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< COMP1 interrupt enable */ + +#define COMP_CFGR1_HYST_Pos (8U) +#define COMP_CFGR1_HYST_Msk (0x3UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR1_HYST COMP_CFGR1_HYST_Msk /*!< COMP1 hysteresis selection bits */ +#define COMP_CFGR1_HYST_0 (0x1UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR1_HYST_1 (0x2UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR1_PWRMODE_Pos (12U) +#define COMP_CFGR1_PWRMODE_Msk (0x3UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR1_PWRMODE COMP_CFGR1_PWRMODE_Msk /*!< COMP1 Power Mode of the comparator */ +#define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR1_WINOUT_Pos (14U) +#define COMP_CFGR1_WINOUT_Msk (0x1UL << COMP_CFGR1_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CFGR1_WINOUT COMP_CFGR1_WINOUT_Msk /*!< COMP1 window output selection bit */ + +#define COMP_CFGR1_INMSEL_Pos (16U) +#define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< COMP1 input minus selection bit */ +#define COMP_CFGR1_INMSEL_0 (0x1UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR1_INMSEL_1 (0x2UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR1_INMSEL_2 (0x4UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR1_INMSEL_3 (0x8UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR1_INPSEL_Pos (20U) +#define COMP_CFGR1_INPSEL_Msk (0x5UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00500000 */ +#define COMP_CFGR1_INPSEL COMP_CFGR1_INPSEL_Msk /*!< COMP1 input plus 0 selection bit */ + +#define COMP_CFGR1_INPSEL0_Pos (20U) +#define COMP_CFGR1_INPSEL0_Msk (0x1UL << COMP_CFGR1_INPSEL0_Pos) /*!< 0x00100000 */ +#define COMP_CFGR1_INPSEL0 COMP_CFGR1_INPSEL0_Msk /*!< COMP1 input plus 0 selection bit */ + +#define COMP_CFGR1_INPSEL1_Pos (22U) +#define COMP_CFGR1_INPSEL1_Msk (0x1UL << COMP_CFGR1_INPSEL1_Pos) /*!< 0x00400000 */ +#define COMP_CFGR1_INPSEL1 COMP_CFGR1_INPSEL1_Msk /*!< COMP1 input plus 1 selection bit */ + +#define COMP_CFGR1_BLANKING_Pos (24U) +#define COMP_CFGR1_BLANKING_Msk (0xFUL << COMP_CFGR1_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR1_BLANKING COMP_CFGR1_BLANKING_Msk /*!< COMP1 blanking source selection bits */ +#define COMP_CFGR1_BLANKING_0 (0x1UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR1_BLANKING_1 (0x2UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR1_BLANKING_2 (0x4UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR1_BLANKING_3 (0x8UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR1_LOCK_Pos (31U) +#define COMP_CFGR1_LOCK_Msk (0x1UL << COMP_CFGR1_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR1_LOCK COMP_CFGR1_LOCK_Msk /*!< COMP1 Lock Bit */ + +/********************************* Bit definition for COMP_CFGR2 register *******************************************/ +#define COMP_CFGR2_EN_Pos (0U) +#define COMP_CFGR2_EN_Msk (0x1UL << COMP_CFGR2_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR2_EN COMP_CFGR2_EN_Msk /*!< COMP1 enable bit */ + +#define COMP_CFGR2_BRGEN_Pos (1U) +#define COMP_CFGR2_BRGEN_Msk (0x1UL << COMP_CFGR2_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR2_BRGEN COMP_CFGR2_BRGEN_Msk /*!< COMP1 Scaler bridge enable */ + +#define COMP_CFGR2_SCALEN_Pos (2U) +#define COMP_CFGR2_SCALEN_Msk (0x1UL << COMP_CFGR2_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR2_SCALEN COMP_CFGR2_SCALEN_Msk /*!< COMP1 Voltage scaler enable bit */ + +#define COMP_CFGR2_POLARITY_Pos (3U) +#define COMP_CFGR2_POLARITY_Msk (0x1UL << COMP_CFGR2_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR2_POLARITY COMP_CFGR2_POLARITY_Msk /*!< COMP1 polarity selection bit */ +#define COMP_CFGR2_WINMODE_Pos (4U) +#define COMP_CFGR2_WINMODE_Msk (0x1UL << COMP_CFGR2_WINMODE_Pos) /*!< 0x00000010 */ +#define COMP_CFGR2_WINMODE COMP_CFGR2_WINMODE_Msk /*!< COMP1 window mode selection bit */ + + +#define COMP_CFGR2_ITEN_Pos (6U) +#define COMP_CFGR2_ITEN_Msk (0x1UL << COMP_CFGR2_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR2_ITEN COMP_CFGR2_ITEN_Msk /*!< COMP1 interrupt enable */ + +#define COMP_CFGR2_HYST_Pos (8U) +#define COMP_CFGR2_HYST_Msk (0x3UL << COMP_CFGR2_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR2_HYST COMP_CFGR2_HYST_Msk /*!< COMP1 hysteresis selection bits */ +#define COMP_CFGR2_HYST_0 (0x1UL << COMP_CFGR2_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR2_HYST_1 (0x2UL << COMP_CFGR2_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR2_PWRMODE_Pos (12U) +#define COMP_CFGR2_PWRMODE_Msk (0x3UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR2_PWRMODE COMP_CFGR2_PWRMODE_Msk /*!< COMP1 Power Mode of the comparator */ +#define COMP_CFGR2_PWRMODE_0 (0x1UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR2_PWRMODE_1 (0x2UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR2_WINOUT_Pos (14U) +#define COMP_CFGR2_WINOUT_Msk (0x1UL << COMP_CFGR2_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CFGR2_WINOUT COMP_CFGR2_WINOUT_Msk /*!< COMP1 window output selection bit */ + +#define COMP_CFGR2_INMSEL_Pos (16U) +#define COMP_CFGR2_INMSEL_Msk (0xFUL << COMP_CFGR2_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR2_INMSEL COMP_CFGR2_INMSEL_Msk /*!< COMP1 input minus selection bit */ +#define COMP_CFGR2_INMSEL_0 (0x1UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR2_INMSEL_1 (0x2UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR2_INMSEL_2 (0x4UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR2_INMSEL_3 (0x8UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR2_INPSEL0_Pos (20U) +#define COMP_CFGR2_INPSEL0_Msk (0x1UL << COMP_CFGR2_INPSEL0_Pos) /*!< 0x00100000 */ +#define COMP_CFGR2_INPSEL0 COMP_CFGR2_INPSEL0_Msk /*!< COMP1 input plus 0 selection bit */ + +#define COMP_CFGR2_INPSEL1_Pos (22U) +#define COMP_CFGR2_INPSEL1_Msk (0x1UL << COMP_CFGR2_INPSEL1_Pos) /*!< 0x00400000 */ +#define COMP_CFGR2_INPSEL1 COMP_CFGR2_INPSEL1_Msk /*!< COMP1 input plus 1 selection bit */ + +#define COMP_CFGR2_BLANKING_Pos (24U) +#define COMP_CFGR2_BLANKING_Msk (0xFUL << COMP_CFGR2_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR2_BLANKING COMP_CFGR2_BLANKING_Msk /*!< COMP1 blanking source selection bits */ +#define COMP_CFGR2_BLANKING_0 (0x1UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR2_BLANKING_1 (0x2UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR2_BLANKING_2 (0x4UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR2_BLANKING_3 (0x8UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR2_LOCK_Pos (31U) +#define COMP_CFGR2_LOCK_Msk (0x1UL << COMP_CFGR2_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR2_LOCK COMP_CFGR2_LOCK_Msk /*!< COMP1 Lock Bit */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) +#define CRC_CR_RTYPE_IN_Pos (9U) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< RTYPE_IN Reverse type Input bits */ +#define CRC_CR_RTYPE_OUT_Pos (10U) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< RTYPE_OUT Reverse type Output bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_BUSY_Pos (4U) +#define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9U) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12U) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15U) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR0 register *******************/ +#define RNG_HTCR0_HTCFG_Pos (0U) +#define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR0_HTCFG RNG_HTCR0_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR1 register *******************/ +#define RNG_HTCR1_HTCFG_Pos (0U) +#define RNG_HTCR1_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR1_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR1_HTCFG RNG_HTCR1_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR2 register *******************/ +#define RNG_HTCR2_HTCFG_Pos (0U) +#define RNG_HTCR2_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR2_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR2_HTCFG RNG_HTCR2_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR3 register *******************/ +#define RNG_HTCR3_HTCFG_Pos (0U) +#define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk + +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************** RNG Nist Compliance Values ******************************/ +#define RNG_HTCRx_VALUE 0x0003FFFF +#define RNG_CR_NIST_VALUE (0x00200F00U) +#define RNG_HTCR_NIST_VALUE (0xA2B0U) + +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 + + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) /*!< FLASH Bank Size */ +#define FLASH_SECTOR_SIZE 0x2000U /*!< Flash Sector Size: 8 KB */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Operation in Flash high-cycle data area interrupted */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (23U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00800000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< Operation in OTP area interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTCR register *******************/ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ +#define FLASH_OPTCR_OPTSTART_Pos (1U) +#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ + +/******************* Bits definition for FLASH_SR register ***********************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< Data buffer not empty flag */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ +#define FLASH_SR_OBKERR_Pos (21U) +#define FLASH_SR_OBKERR_Msk (0x1UL << FLASH_SR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_SR_OBKERR FLASH_SR_OBKERR_Msk /*!< OBK general error flag */ +#define FLASH_SR_OBKWERR_Pos (22U) +#define FLASH_SR_OBKWERR_Msk (0x1UL << FLASH_SR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_SR_OBKWERR FLASH_SR_OBKWERR_Msk /*!< OBK write error flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ + +/******************* Bits definition for FLASH_CR register ***********************/ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming control bit */ +#define FLASH_CR_SER_Pos (2U) +#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ +#define FLASH_CR_START_Pos (5U) +#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000020 */ +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ +#define FLASH_CR_SNB_Pos (6U) +#define FLASH_CR_SNB_Msk (0x3FUL << FLASH_CR_SNB_Pos) /*!< 0x00000FC0 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ +#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ +#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos) /*!< 0x00000800 */ +#define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos) /*!< 0x00001000 */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-operation interrupt control bit */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ +#define FLASH_CR_OBKERRIE_Pos (21U) +#define FLASH_CR_OBKERRIE_Msk (0x1UL << FLASH_CR_OBKERRIE_Pos) /*!< 0x00200000 */ +#define FLASH_CR_OBKERRIE FLASH_CR_OBKERRIE_Msk /*!< OBK general error interrupt enable bitt */ +#define FLASH_CR_OBKWERRIE_Pos (22U) +#define FLASH_CR_OBKWERRIE_Msk (0x1UL << FLASH_CR_OBKWERRIE_Pos) /*!< 0x00400000 */ +#define FLASH_CR_OBKWERRIE FLASH_CR_OBKWERRIE_Msk /*!< OBK write error interrupt enable bit */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ +#define FLASH_CR_INV_Pos (29U) +#define FLASH_CR_INV_Msk (0x1UL << FLASH_CR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_CR_INV FLASH_CR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x10000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector */ + +/******************* Bits definition for FLASH_CCR register *******************/ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ +#define FLASH_CCR_CLR_OBKERR_Pos (21U) +#define FLASH_CCR_CLR_OBKERR_Msk (0x1UL << FLASH_CCR_CLR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_CCR_CLR_OBKERR FLASH_CCR_CLR_OBKERR_Msk /*!< OBKERR flag clear bit */ +#define FLASH_CCR_CLR_OBKWERR_Pos (22U) +#define FLASH_CCR_CLR_OBKWERR_Msk (0x1UL << FLASH_CCR_CLR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_CCR_CLR_OBKWERR FLASH_CCR_CLR_OBKWERR_Msk /*!< OBKWERR flag clear bit */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Option byte change error clear bit */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/****************** Bits definition for FLASH_OBKCFGR register *****************/ +#define FLASH_OBKCFGR_LOCK_Pos (0U) +#define FLASH_OBKCFGR_LOCK_Msk (0x1UL << FLASH_OBKCFGR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OBKCFGR_LOCK FLASH_OBKCFGR_LOCK_Msk /*!< OBKCFGR lock */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Pos (1U) +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Msk (0x1UL << FLASH_OBKCFGR_SWAP_SECT_REQ_Pos) /*!< 0x00000002 */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ FLASH_OBKCFGR_SWAP_SECT_REQ_Msk /*!< OBK swap sector request */ +#define FLASH_OBKCFGR_ALT_SECT_Pos (2U) +#define FLASH_OBKCFGR_ALT_SECT_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_Pos) /*!< 0x00000004 */ +#define FLASH_OBKCFGR_ALT_SECT FLASH_OBKCFGR_ALT_SECT_Msk /*!< Alternate sector */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Pos (3U) +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_ERASE_Pos) /*!< 0x00000008 */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE FLASH_OBKCFGR_ALT_SECT_ERASE_Msk /*!< Alternate sector erase */ +#define FLASH_OBKCFGR_SWAP_OFFSET_Pos (16U) +#define FLASH_OBKCFGR_SWAP_OFFSET_Msk (0x1FFUL << FLASH_OBKCFGR_SWAP_OFFSET_Pos) /*!< 0x01FF0000 */ +#define FLASH_OBKCFGR_SWAP_OFFSET FLASH_OBKCFGR_SWAP_OFFSET_Msk /*!< Swap offset */ + +/****************** Bits definition for FLASH_HDPEXTR register *****************/ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000007F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 1 */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x007F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 2 */ + +/******************* Bits definition for FLASH_OPTSR register ***************/ +#define FLASH_OPTSR_BOR_LEV_Pos (0U) +#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000003 */ +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option bit */ +#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR_BORH_EN_Pos (2U) +#define FLASH_OPTSR_BORH_EN_Msk (0x1UL << FLASH_OPTSR_BORH_EN_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR_BORH_EN FLASH_OPTSR_BORH_EN_Msk /*!< Brownout high enable configuration bit */ +#define FLASH_OPTSR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_IWDG_SW FLASH_OPTSR_IWDG_SW_Msk /*!< IWDG control mode option bit */ +#define FLASH_OPTSR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_WWDG_SW FLASH_OPTSR_WWDG_SW_Msk /*!< WWDG control mode option bit */ +#define FLASH_OPTSR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_NRST_STOP FLASH_OPTSR_NRST_STOP_Msk /*!< Stop mode entry reset option bit */ +#define FLASH_OPTSR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_NRST_STDBY FLASH_OPTSR_NRST_STDBY_Msk /*!< Standby mode entry reset option bit */ +#define FLASH_OPTSR_PRODUCT_STATE_Pos (8U) +#define FLASH_OPTSR_PRODUCT_STATE_Msk (0xFFUL << FLASH_OPTSR_PRODUCT_STATE_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRODUCT_STATE FLASH_OPTSR_PRODUCT_STATE_Msk /*!< Life state code option byte */ +#define FLASH_OPTSR_IO_VDD_HSLV_Pos (16U) +#define FLASH_OPTSR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDD_HSLV_Pos) /*!< 0x00010000 */ +#define FLASH_OPTSR_IO_VDD_HSLV FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Pos (17U) +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDDIO2_HSLV_Pos) /*!< 0x00020000 */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_IWDG_STOP FLASH_OPTSR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTSR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_IWDG_STDBY FLASH_OPTSR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTSR_BOOT_UBE_Pos (22U) +#define FLASH_OPTSR_BOOT_UBE_Msk (0xFFUL << FLASH_OPTSR_BOOT_UBE_Pos) /*!< 0x3FC00000 */ +#define FLASH_OPTSR_BOOT_UBE FLASH_OPTSR_BOOT_UBE_Msk /*!< Unique boot entry option byte */ +#define FLASH_OPTSR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_SWAP_BANK FLASH_OPTSR_SWAP_BANK_Msk /*!< Bank swapping option bit */ + +/******************* Bits definition for FLASH_EPOCHR register ***************/ +#define FLASH_EPOCHR_EPOCH_Pos (0U) +#define FLASH_EPOCHR_EPOCH_Msk (0xFFFFFFUL << FLASH_EPOCHR_EPOCH_Pos) /*!< 0x00FFFFFF */ +#define FLASH_EPOCHR_EPOCH FLASH_EPOCHR_EPOCH_Msk /*!< EPOCH counter */ + +/******************* Bits definition for FLASH_OPTSR2 register ***************/ +#define FLASH_OPTSR2_SRAM1_3_RST_Pos (2U) +#define FLASH_OPTSR2_SRAM1_3_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM1_3_RST_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR2_SRAM1_3_RST FLASH_OPTSR2_SRAM1_3_RST_Msk /*!< SRAM1 and SRAM3 erased when a system reset occurs */ +#define FLASH_OPTSR2_SRAM2_RST_Pos (3U) +#define FLASH_OPTSR2_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM2_RST_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR2_SRAM2_RST FLASH_OPTSR2_SRAM2_RST_Msk /*!< SRAM2 erased when a system reset occurs*/ +#define FLASH_OPTSR2_BKPRAM_ECC_Pos (4U) +#define FLASH_OPTSR2_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTSR2_BKPRAM_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_BKPRAM_ECC FLASH_OPTSR2_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTSR2_SRAM3_ECC_Pos (5U) +#define FLASH_OPTSR2_SRAM3_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM3_ECC_Pos) /*!< 0x00000020 */ +#define FLASH_OPTSR2_SRAM3_ECC FLASH_OPTSR2_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTSR2_SRAM2_ECC_Pos (6U) +#define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */ +#define FLASH_OPTSR2_USBPD_DIS_Pos (8U) +#define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */ +#define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */ +#define FLASH_OPTSR2_TZEN_Pos (24U) +#define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */ +#define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */ + +/**************** Bits definition for FLASH_BOOTR register **********************/ +#define FLASH_BOOTR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_BOOT_LOCK FLASH_BOOTR_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_BOOTR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_BOOTADD FLASH_BOOTR_BOOTADD_Msk /*!< Boot address */ + +/**************** Bits definition for FLASH_PRIVBBR register *******************/ +#define FLASH_PRIVBBR_PRIVBB_Pos (0U) +#define FLASH_PRIVBBR_PRIVBB_Msk (0xFFFFFFFFUL << FLASH_PRIVBBR_PRIVBB_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PRIVBBR_PRIVBB FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector attribute */ + +/***************** Bits definition for FLASH_SECWMR register ********************/ +#define FLASH_SECWMR_SECWM_STRT_Pos (0U) +#define FLASH_SECWMR_SECWM_STRT_Msk (0x3FUL << FLASH_SECWMR_SECWM_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_SECWMR_SECWM_STRT FLASH_SECWMR_SECWM_STRT_Msk /*!< Start sector of secure area */ +#define FLASH_SECWMR_SECWM_END_Pos (16U) +#define FLASH_SECWMR_SECWM_END_Msk (0x3FUL << FLASH_SECWMR_SECWM_END_Pos) /*!< 0x003F0000 */ +#define FLASH_SECWMR_SECWM_END FLASH_SECWMR_SECWM_END_Msk /*!< End sector of secure area */ + +/***************** Bits definition for FLASH_WRPR register *********************/ +#define FLASH_WRPR_WRPSG_Pos (0U) +#define FLASH_WRPR_WRPSG_Msk (0x0000FFFFUL << FLASH_WRPR_WRPSG_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRPR_WRPSG FLASH_WRPR_WRPSG_Msk /*!< Sector group protection option status */ + +/***************** Bits definition for FLASH_EDATA register ********************/ +#define FLASH_EDATAR_EDATA_STRT_Pos (0U) +#define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */ +#define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */ +#define FLASH_EDATAR_EDATA_EN_Pos (15U) +#define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */ +#define FLASH_EDATAR_EDATA_EN FLASH_EDATAR_EDATA_EN_Msk /*!< Flash high-cycle data enable */ + +/***************** Bits definition for FLASH_HDPR register ********************/ +#define FLASH_HDPR_HDP_STRT_Pos (0U) +#define FLASH_HDPR_HDP_STRT_Msk (0x7FUL << FLASH_HDPR_HDP_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_HDPR_HDP_STRT FLASH_HDPR_HDP_STRT_Msk /*!< Start sector of hide protection area */ +#define FLASH_HDPR_HDP_END_Pos (16U) +#define FLASH_HDPR_HDP_END_Msk (0x7FUL << FLASH_HDPR_HDP_END_Pos) /*!< 0x007F0000 */ +#define FLASH_HDPR_HDP_END FLASH_HDPR_HDP_END_Msk /*!< End sector of hide protection area */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_OBK_ECC_Pos (20U) +#define FLASH_ECCR_OBK_ECC_Msk (0x1UL << FLASH_ECCR_OBK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_OBK_ECC FLASH_ECCR_OBK_ECC_Msk /*!< Flash OB Keys storage area ECC fail */ +#define FLASH_ECCR_DATA_ECC_Pos (21U) +#define FLASH_ECCR_DATA_ECC_Msk (0x1UL << FLASH_ECCR_DATA_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_DATA_ECC FLASH_ECCR_DATA_ECC_Msk /*!< Flash high-cycle data ECC fail */ +#define FLASH_ECCR_BK_ECC_Pos (22U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (23U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_OTP_ECC_Pos (24U) +#define FLASH_ECCR_OTP_ECC_Msk (0x1UL << FLASH_ECCR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (25U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_ECCDR register ***************/ +#define FLASH_ECCDR_FAIL_DATA_Pos (0U) +#define FLASH_ECCDR_FAIL_DATA_Msk (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_OR register ******************/ +#define RTC_OR_OUT2_RMP_Pos (0U) +#define RTC_OR_OUT2_RMP_Msk (0x1UL << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x08000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk +#define TAMP_CR1_ITAMP15E_Pos (30U) +#define TAMP_CR1_ITAMP15E_Msk (0x1UL << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ +#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP4NOER_Pos (3U) +#define TAMP_CR3_ITAMP4NOER_Msk (0x1UL << TAMP_CR3_ITAMP4NOER_Pos) /*!< 0x00000008 */ +#define TAMP_CR3_ITAMP4NOER TAMP_CR3_ITAMP4NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000080 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000400 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00001000 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk +#define TAMP_CR3_ITAMP15NOER_Pos (14U) +#define TAMP_CR3_ITAMP15NOER_Msk (0x1UL << TAMP_CR3_ITAMP15NOER_Pos) /*!< 0x00004000 */ +#define TAMP_CR3_ITAMP15NOER TAMP_CR3_ITAMP15NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk +#define TAMP_IER_ITAMP15IE_Pos (30U) +#define TAMP_IER_ITAMP15IE_Msk (0x1UL << TAMP_IER_ITAMP15IE_Pos) /*!< 0x40000000 */ +#define TAMP_IER_ITAMP15IE TAMP_IER_ITAMP15IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk +#define TAMP_SR_ITAMP15F_Pos (30U) +#define TAMP_SR_ITAMP15F_Msk (0x1UL << TAMP_SR_ITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SR_ITAMP15F TAMP_SR_ITAMP15F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk +#define TAMP_MISR_ITAMP15MF_Pos (30U) +#define TAMP_MISR_ITAMP15MF_Msk (0x1UL << TAMP_MISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_MISR_ITAMP15MF TAMP_MISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP4MF_Pos (19U) +#define TAMP_SMISR_ITAMP4MF_Msk (0x1UL << TAMP_SMISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_SMISR_ITAMP4MF TAMP_SMISR_ITAMP4MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk +#define TAMP_SMISR_ITAMP15MF_Pos (30U) +#define TAMP_SMISR_ITAMP15MF_Msk (0x1UL << TAMP_SMISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_SMISR_ITAMP15MF TAMP_SMISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk +#define TAMP_SCR_CITAMP15F_Pos (30U) +#define TAMP_SCR_CITAMP15F_Msk (0x1UL << TAMP_SCR_CITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SCR_CITAMP15F TAMP_SCR_CITAMP15F_Msk +/******************** Bits definition for TAMP_COUNT1R register ***************/ +#define TAMP_COUNT1R_COUNT_Pos (0U) +#define TAMP_COUNT1R_COUNT_Msk (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */ +#define TAMP_COUNT1R_COUNT TAMP_COUNT1R_COUNT_Msk + +/******************** Bits definition for TAMP_OR register ***************/ +#define TAMP_OR_OUT3_RMP_Pos (1U) +#define TAMP_OR_OUT3_RMP_Msk (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00000006 */ +#define TAMP_OR_OUT3_RMP TAMP_OR_OUT3_RMP_Msk +#define TAMP_OR_OUT3_RMP_0 (0x1UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00100000 */ +#define TAMP_OR_OUT3_RMP_1 (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00200000 */ +#define TAMP_OR_OUT5_RMP_Pos (3U) +#define TAMP_OR_OUT5_RMP_Msk (0x1UL << TAMP_OR_OUT5_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_OUT5_RMP TAMP_OR_OUT5_RMP_Msk +#define TAMP_OR_IN2_RMP_Pos (8U) +#define TAMP_OR_IN2_RMP_Msk (0x1UL << TAMP_OR_IN2_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN2_RMP TAMP_OR_IN2_RMP_Msk +#define TAMP_OR_IN3_RMP_Pos (9U) +#define TAMP_OR_IN3_RMP_Msk (0x1UL << TAMP_OR_IN3_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN3_RMP TAMP_OR_IN3_RMP_Msk +#define TAMP_OR_IN4_RMP_Pos (10U) +#define TAMP_OR_IN4_RMP_Msk (0x1UL << TAMP_OR_IN4_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN4_RMP TAMP_OR_IN4_RMP_Msk + +/******************** Bits definition for TAMP_ERCFG register ***************/ +#define TAMP_ERCFGR_ERCFG0_Pos (0U) +#define TAMP_ERCFGR_ERCFG0_Msk (0x1UL << TAMP_ERCFGR_ERCFG0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR_ERCFG0 TAMP_ERCFGR_ERCFG0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* SBS */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SBS_HDPLCR register *****************/ +#define SBS_HDPLCR_INCR_HDPL_Pos (0U) +#define SBS_HDPLCR_INCR_HDPL_Msk (0xFFUL << SBS_HDPLCR_INCR_HDPL_Pos) /*!< 0x000000FF */ +#define SBS_HDPLCR_INCR_HDPL SBS_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL value. */ + +/******************** Bit definition for SBS_HDPLSR register *****************/ +#define SBS_HDPLSR_HDPL_Pos (0U) +#define SBS_HDPLSR_HDPL_Msk (0xFFUL << SBS_HDPLSR_HDPL_Pos) /*!< 0x000000FF */ +#define SBS_HDPLSR_HDPL SBS_HDPLSR_HDPL_Msk /*!< HDPL value. */ + +/******************** Bit definition for SBS_NEXTHDPLCR register *****************/ +#define SBS_NEXTHDPLCR_NEXTHDPL_Pos (0U) +#define SBS_NEXTHDPLCR_NEXTHDPL_Msk (0x3UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000003 */ +#define SBS_NEXTHDPLCR_NEXTHDPL SBS_NEXTHDPLCR_NEXTHDPL_Msk /*!< NEXTHDPL value. */ +#define SBS_NEXTHDPLCR_NEXTHDPL_0 (0x1UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000001 */ +#define SBS_NEXTHDPLCR_NEXTHDPL_1 (0x2UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000002 */ + +/******************** Bit definition for SBS_DBGCR register *****************/ +#define SBS_DBGCR_AP_UNLOCK_Pos (0U) +#define SBS_DBGCR_AP_UNLOCK_Msk (0xFFUL << SBS_DBGCR_AP_UNLOCK_Pos) /*!< 0x000000FF */ +#define SBS_DBGCR_AP_UNLOCK SBS_DBGCR_AP_UNLOCK_Msk /*!< Open the Access Port. */ + +#define SBS_DBGCR_DBG_UNLOCK_Pos (8U) +#define SBS_DBGCR_DBG_UNLOCK_Msk (0xFFUL << SBS_DBGCR_DBG_UNLOCK_Pos) /*!< 0x0000FF00 */ +#define SBS_DBGCR_DBG_UNLOCK SBS_DBGCR_DBG_UNLOCK_Msk /*!< Open the debug when DBG_AUTH_HDPL is reached. */ + +#define SBS_DBGCR_DBG_AUTH_HDPL_Pos (16U) +#define SBS_DBGCR_DBG_AUTH_HDPL_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_HDPL_Pos) /*!< 0x00FF0000 */ +#define SBS_DBGCR_DBG_AUTH_HDPL SBS_DBGCR_DBG_AUTH_HDPL_Msk /*!< HDPL value when the debug should be effectively opened. */ + +#define SBS_DBGCR_DBG_AUTH_SEC_Pos (24U) +#define SBS_DBGCR_DBG_AUTH_SEC_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_SEC_Pos) /*!< 0xFF000000 */ +#define SBS_DBGCR_DBG_AUTH_SEC SBS_DBGCR_DBG_AUTH_SEC_Msk /*!< Open the non-secured and secured debugs. */ + +/******************** Bit definition for SBS_DBGLCKR register *****************/ +#define SBS_DBGLOCKR_DBGCFG_LOCK_Pos (0U) +#define SBS_DBGLOCKR_DBGCFG_LOCK_Msk (0xFFUL << SBS_DBGLOCKR_DBGCFG_LOCK_Pos) /*!< 0x000000FF */ +#define SBS_DBGLOCKR_DBGCFG_LOCK SBS_DBGLOCKR_DBGCFG_LOCK_Msk /*!< SBS_DBGLOCKR_DBGCFG_LOCK value. */ + +/******************** Bit definition for SBS_RSSCMDR register ***************/ +#define SBS_RSSCMDR_RSSCMD_Pos (0U) +#define SBS_RSSCMDR_RSSCMD_Msk (0xFFFFUL << SBS_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */ +#define SBS_RSSCMDR_RSSCMD SBS_RSSCMDR_RSSCMD_Msk /*!< command to be executed by the RSS. */ + +/******************** Bit definition for SBS_EPOCHSELCR register ************/ +#define SBS_EPOCHSELCR_EPOCH_SEL_Pos (0U) +#define SBS_EPOCHSELCR_EPOCH_SEL_Msk (0x3UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000003 */ +#define SBS_EPOCHSELCR_EPOCH_SEL SBS_EPOCHSELCR_EPOCH_SEL_Msk /*!< Select EPOCH sent to SAES IP to encrypt/decrypt keys */ +#define SBS_EPOCHSELCR_EPOCH_SEL_0 (0x1UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000001 */ +#define SBS_EPOCHSELCR_EPOCH_SEL_1 (0x2UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000002 */ + +/****************** Bit definition for SBS_PMCR register ****************/ +#define SBS_PMCR_PB6_FMP_Pos (16U) +#define SBS_PMCR_PB6_FMP_Msk (0x1UL << SBS_PMCR_PB6_FMP_Pos) /*!< 0x00010000 */ +#define SBS_PMCR_PB6_FMP SBS_PMCR_PB6_FMP_Msk /*!< Fast-mode Plus command on PB(6) */ +#define SBS_PMCR_PB7_FMP_Pos (17U) +#define SBS_PMCR_PB7_FMP_Msk (0x1UL << SBS_PMCR_PB7_FMP_Pos) /*!< 0x00020000 */ +#define SBS_PMCR_PB7_FMP SBS_PMCR_PB7_FMP_Msk /*!< Fast-mode Plus command on PB(7) */ +#define SBS_PMCR_PB8_FMP_Pos (18U) +#define SBS_PMCR_PB8_FMP_Msk (0x1UL << SBS_PMCR_PB8_FMP_Pos) /*!< 0x00040000 */ +#define SBS_PMCR_PB8_FMP SBS_PMCR_PB8_FMP_Msk /*!< Fast-mode Plus command on PB(8) */ +#define SBS_PMCR_PB9_FMP_Pos (19U) +#define SBS_PMCR_PB9_FMP_Msk (0x1UL << SBS_PMCR_PB9_FMP_Pos) /*!< 0x00080000 */ +#define SBS_PMCR_PB9_FMP SBS_PMCR_PB9_FMP_Msk /*!< Fast-mode Plus command on PB(9) */ +#define SBS_PMCR_ETH_SEL_PHY_Pos (21U) +#define SBS_PMCR_ETH_SEL_PHY_Msk (0x7UL << SBS_PMCR_ETH_SEL_PHY_Pos) /*!< 0x00E00000 */ +#define SBS_PMCR_ETH_SEL_PHY SBS_PMCR_ETH_SEL_PHY_Msk /*!< Ethernet PHY Interface Selection */ +#define SBS_PMCR_ETH_SEL_PHY_0 (0x1UL << SBS_PMCR_ETH_SEL_PHY_Pos) /*!< 0x00200000 */ +#define SBS_PMCR_ETH_SEL_PHY_1 (0x2UL << SBS_PMCR_ETH_SEL_PHY_Pos) /*!< 0x00400000 */ +#define SBS_PMCR_ETH_SEL_PHY_2 (0x4UL << SBS_PMCR_ETH_SEL_PHY_Pos) /*!< 0x00800000 */ +#define SBS_PMCR_ETHINTPOL_Pos (25U) +#define SBS_PMCR_ETHINTPOL_Msk (0x1UL << SBS_PMCR_ETHINTPOL_Pos) /*!< 0x0200000 */ +#define SBS_PMCR_ETHINTPOL SBS_PMCR_ETHINTPOL_Msk /*!< ETH external PHY interrupt polarity configuration */ +#define SBS_PMCR_ETHPDACK_Pos (26U) +#define SBS_PMCR_ETHPDACK_Msk (0x1UL << SBS_PMCR_ETHPDACK_Pos) /*!< 0x0400000 */ +#define SBS_PMCR_ETHPDACK SBS_PMCR_ETHPDACK_Msk /*!< ETH power-down acknowledge */ +#define SBS_PMCR_ETHTXLPI_Pos (27U) +#define SBS_PMCR_ETHTXLPI_Msk (0x1UL << SBS_PMCR_ETHTXLPI_Pos) /*!< 0x0400000 */ +#define SBS_PMCR_ETHTXLPI SBS_PMCR_ETHTXLPI_Msk /*!< ETH TxLPI status */ + +/****************** Bit definition for SBS_FPUIMR register ***************/ +#define SBS_FPUIMR_FPU_IE_Pos (0U) +#define SBS_FPUIMR_FPU_IE_Msk (0x3FUL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F - */ +#define SBS_FPUIMR_FPU_IE SBS_FPUIMR_FPU_IE_Msk /*!< All FPU interrupts enable */ +#define SBS_FPUIMR_FPU_IE_0 (0x1UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000001 - Invalid operation Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_1 (0x2UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000002 - Divide-by-zero Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_2 (0x4UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000004 - Underflow Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_3 (0x8UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000008 - Overflow Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_4 (0x10UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000010 - Input denormal Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_5 (0x20UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000020 - Inexact Interrupt enable (interrupt disabled at reset) */ + +/****************** Bit definition for SBS_MESR register ****************/ +#define SBS_MESR_MCLR_Pos (0U) +#define SBS_MESR_MCLR_Msk (0x1UL << SBS_MESR_MCLR_Pos) /*!< 0x00000001 */ +#define SBS_MESR_MCLR SBS_MESR_MCLR_Msk /*!< Status of Erase after Reset */ +#define SBS_MESR_IPMEE_Pos (16U) +#define SBS_MESR_IPMEE_Msk (0x1UL << SBS_MESR_IPMEE_Pos) /*!< 0x00010000 */ +#define SBS_MESR_IPMEE SBS_MESR_IPMEE_Msk /*!< Status of End of Erase for ICache and PKA RAMs */ + +/****************** Bit definition for SBS_CCCSR register ****************/ +#define SBS_CCCSR_EN1_Pos (0U) +#define SBS_CCCSR_EN1_Msk (0x1UL << SBS_CCCSR_EN1_Pos) /*!< 0x00000001 */ +#define SBS_CCCSR_EN1 SBS_CCCSR_EN1_Msk /*!< Enable compensation cell for VDD power rail */ +#define SBS_CCCSR_CS1_Pos (1U) +#define SBS_CCCSR_CS1_Msk (0x1UL << SBS_CCCSR_CS1_Pos) /*!< 0x00000002 */ +#define SBS_CCCSR_CS1 SBS_CCCSR_CS1_Msk /*!< Code selection for VDD power rail */ +#define SBS_CCCSR_EN2_Pos (2U) +#define SBS_CCCSR_EN2_Msk (0x1UL << SBS_CCCSR_EN2_Pos) /*!< 0x00000004 */ +#define SBS_CCCSR_EN2 SBS_CCCSR_EN2_Msk /*!< Enable compensation cell for VDDIO power rail */ +#define SBS_CCCSR_CS2_Pos (3U) +#define SBS_CCCSR_CS2_Msk (0x1UL << SBS_CCCSR_CS2_Pos) /*!< 0x00000008 */ +#define SBS_CCCSR_CS2 SBS_CCCSR_CS2_Msk /*!< Code selection for VDDIO power rail */ +#define SBS_CCCSR_RDY1_Pos (8U) +#define SBS_CCCSR_RDY1_Msk (0x1UL << SBS_CCCSR_RDY1_Pos) /*!< 0x00000100 */ +#define SBS_CCCSR_RDY1 SBS_CCCSR_RDY1_Msk /*!< VDD compensation cell ready flag */ +#define SBS_CCCSR_RDY2_Pos (9U) +#define SBS_CCCSR_RDY2_Msk (0x1UL << SBS_CCCSR_RDY2_Pos) /*!< 0x00000200 */ +#define SBS_CCCSR_RDY2 SBS_CCCSR_RDY2_Msk /*!< VDDIO compensation cell ready flag */ + +/****************** Bit definition for SBS_CCVALR register ****************/ +#define SBS_CCVALR_ANSRC1_Pos (0U) +#define SBS_CCVALR_ANSRC1_Msk (0xFUL << SBS_CCVALR_ANSRC1_Pos) /*!< 0x0000000F */ +#define SBS_CCVALR_ANSRC1 SBS_CCVALR_ANSRC1_Msk /*!< NMOS compensation value */ +#define SBS_CCVALR_APSRC1_Pos (4U) +#define SBS_CCVALR_APSRC1_Msk (0xFUL << SBS_CCVALR_APSRC1_Pos) /*!< 0x000000F0 */ +#define SBS_CCVALR_APSRC1 SBS_CCVALR_APSRC1_Msk /*!< PMOS compensation value */ +#define SBS_CCVALR_ANSRC2_Pos (8U) +#define SBS_CCVALR_ANSRC2_Msk (0xFUL << SBS_CCVALR_ANSRC2_Pos) /*!< 0x00000F00 */ +#define SBS_CCVALR_ANSRC2 SBS_CCVALR_ANSRC2_Msk /*!< NMOS compensation value */ +#define SBS_CCVALR_APSRC2_Pos (12U) +#define SBS_CCVALR_APSRC2_Msk (0xFUL << SBS_CCVALR_APSRC2_Pos) /*!< 0x0000F000 */ +#define SBS_CCVALR_APSRC2 SBS_CCVALR_APSRC2_Msk /*!< PMOS compensation value */ + +/****************** Bit definition for SBS_CCSWCR register ****************/ +#define SBS_CCSWCR_SW_ANSRC1_Pos (0U) +#define SBS_CCSWCR_SW_ANSRC1_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC1_Pos) /*!< 0x0000000F */ +#define SBS_CCSWCR_SW_ANSRC1 SBS_CCSWCR_SW_ANSRC1_Msk /*!< NMOS compensation code for VDD Power Rail */ +#define SBS_CCSWCR_SW_APSRC1_Pos (4U) +#define SBS_CCSWCR_SW_APSRC1_Msk (0xFUL << SBS_CCSWCR_SW_APSRC1_Pos) /*!< 0x000000F0 */ +#define SBS_CCSWCR_SW_APSRC1 SBS_CCSWCR_SW_APSRC1_Msk /*!< PMOS compensation code for VDD Power Rail */ +#define SBS_CCSWCR_SW_ANSRC2_Pos (8U) +#define SBS_CCSWCR_SW_ANSRC2_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC2_Pos) /*!< 0x00000F00 */ +#define SBS_CCSWCR_SW_ANSRC2 SBS_CCSWCR_SW_ANSRC2_Msk /*!< NMOS compensation code for VDDIO Power Rail */ +#define SBS_CCSWCR_SW_APSRC2_Pos (12U) +#define SBS_CCSWCR_SW_APSRC2_Msk (0xFUL << SBS_CCSWCR_SW_APSRC2_Pos) /*!< 0x0000F000 */ +#define SBS_CCSWCR_SW_APSRC2 SBS_CCSWCR_SW_APSRC2_Msk /*!< PMOS compensation code for VDDIO Power Rail */ + +/****************** Bit definition for SBS_CFGR2 register ****************/ +#define SBS_CFGR2_CLL_Pos (0U) +#define SBS_CFGR2_CLL_Msk (0x1UL << SBS_CFGR2_CLL_Pos) /*!< 0x00000001 */ +#define SBS_CFGR2_CLL SBS_CFGR2_CLL_Msk /*!< Core Lockup Lock */ +#define SBS_CFGR2_SEL_Pos (1U) +#define SBS_CFGR2_SEL_Msk (0x1UL << SBS_CFGR2_SEL_Pos) /*!< 0x00000002 */ +#define SBS_CFGR2_SEL SBS_CFGR2_SEL_Msk /*!< SRAM ECC Lock */ +#define SBS_CFGR2_PVDL_Pos (2U) +#define SBS_CFGR2_PVDL_Msk (0x1UL << SBS_CFGR2_PVDL_Pos) /*!< 0x00000004 */ +#define SBS_CFGR2_PVDL SBS_CFGR2_PVDL_Msk /*!< PVD Lock */ +#define SBS_CFGR2_ECCL_Pos (3U) +#define SBS_CFGR2_ECCL_Msk (0x1UL << SBS_CFGR2_ECCL_Pos) /*!< 0x00000008 */ +#define SBS_CFGR2_ECCL SBS_CFGR2_ECCL_Msk /*!< Flash ECC Lock*/ + +/******************** Bit definition for SBS_SECCFGR register ***************/ +#define SBS_SECCFGR_SBSSEC_Pos (0U) +#define SBS_SECCFGR_SBSSEC_Msk (0x1UL << SBS_SECCFGR_SBSSEC_Pos) /*!< 0x00000001 */ +#define SBS_SECCFGR_SBSSEC SBS_SECCFGR_SBSSEC_Msk /*!< SBS clock control security enable */ +#define SBS_SECCFGR_CLASSBSEC_Pos (1U) +#define SBS_SECCFGR_CLASSBSEC_Msk (0x1UL << SBS_SECCFGR_CLASSBSEC_Pos) /*!< 0x00000002 */ +#define SBS_SECCFGR_CLASSBSEC SBS_SECCFGR_CLASSBSEC_Msk /*!< ClassB SBS security enable */ +#define SBS_SECCFGR_FPUSEC_Pos (3U) +#define SBS_SECCFGR_FPUSEC_Msk (0x1UL << SBS_SECCFGR_FPUSEC_Pos) /*!< 0x00000008 */ +#define SBS_SECCFGR_FPUSEC SBS_SECCFGR_FPUSEC_Msk /*!< FPU SBS security enable */ + +/****************** Bit definition for SBS_CNSLCKR register **************/ +#define SBS_CNSLCKR_LOCKNSVTOR_Pos (0U) +#define SBS_CNSLCKR_LOCKNSVTOR_Msk (0x1UL << SBS_CNSLCKR_LOCKNSVTOR_Pos) /*!< 0x00000001 */ +#define SBS_CNSLCKR_LOCKNSVTOR SBS_CNSLCKR_LOCKNSVTOR_Msk /*!< Disable VTOR_NS register writes by SW or debug agent */ +#define SBS_CNSLCKR_LOCKNSMPU_Pos (1U) +#define SBS_CNSLCKR_LOCKNSMPU_Msk (0x1UL << SBS_CNSLCKR_LOCKNSMPU_Pos) /*!< 0x00000002 */ +#define SBS_CNSLCKR_LOCKNSMPU SBS_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Secure MPU registers writes by SW or debug agent */ + +/****************** Bit definition for SBS_CSLCKR register ***************/ +#define SBS_CSLCKR_LOCKSVTAIRCR_Pos (0U) +#define SBS_CSLCKR_LOCKSVTAIRCR_Msk (0x1UL << SBS_CSLCKR_LOCKSVTAIRCR_Pos) /*!< 0x00000001 */ +#define SBS_CSLCKR_LOCKSVTAIRCR SBS_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vector table address, handling of system faults */ +#define SBS_CSLCKR_LOCKSMPU_Pos (1U) +#define SBS_CSLCKR_LOCKSMPU_Msk (0x1UL << SBS_CSLCKR_LOCKSMPU_Pos) /*!< 0x00000002 */ +#define SBS_CSLCKR_LOCKSMPU SBS_CSLCKR_LOCKSMPU_Msk /*!< Disable changes to the secure MPU registers writes by SW or debug agent */ +#define SBS_CSLCKR_LOCKSAU_Pos (2U) +#define SBS_CSLCKR_LOCKSAU_Msk (0x1UL << SBS_CSLCKR_LOCKSAU_Pos) /*!< 0x00000004 */ +#define SBS_CSLCKR_LOCKSAU SBS_CSLCKR_LOCKSAU_Msk /*!< Disable changes to SAU registers */ + +/****************** Bit definition for SBS_ECCNMIR register ***************/ +#define SBS_ECCNMIR_ECCNMI_MASK_EN_Pos (0U) +#define SBS_ECCNMIR_ECCNMI_MASK_EN_Msk (0x1UL << SBS_ECCNMIR_ECCNMI_MASK_EN_Pos) /*!< 0x00000001 */ +#define SBS_ECCNMIR_ECCNMI_MASK_EN SBS_ECCNMIR_ECCNMI_MASK_EN_Msk /*!< Disable NMI in case of double ECC error in flash interface */ + +/*****************************************************************************/ +/* */ +/* Global TrustZone Control */ +/* */ +/*****************************************************************************/ +/******************* Bits definition for GTZC_TZSC_CR register ******************/ +#define GTZC_TZSC_CR_LCK_Pos (0U) +#define GTZC_TZSC_CR_LCK_Msk (0x01UL << GTZC_TZSC_CR_LCK_Pos) /*!< 0x00000001 */ + +/******************* Bits definition for GTZC_TZSC_MPCWM_CFGR register **********/ +#define GTZC_TZSC_MPCWM_CFGR_SREN_Pos (0U) +#define GTZC_TZSC_MPCWM_CFGR_SREN_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SREN_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SREN GTZC_TZSC_MPCWM_CFGR_SREN_Msk +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos (1U) +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk +#define GTZC_TZSC_MPCWM_CFGR_SEC_Pos (8U) +#define GTZC_TZSC_MPCWM_CFGR_SEC_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SEC GTZC_TZSC_MPCWM_CFGR_SEC_Msk +#define GTZC_TZSC_MPCWM_CFGR_PRIV_Pos (9U) +#define GTZC_TZSC_MPCWM_CFGR_PRIV_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_PRIV_Pos) +#define GTZC_TZSC_MPCWM_CFGR_PRIV GTZC_TZSC_MPCWM_CFGR_PRIV_Msk + +/******************* Bits definition for GTZC_TZSC_MPCWMR register **************/ +#define GTZC_TZSC_MPCWMR_SUBZ_START_Pos (0U) +#define GTZC_TZSC_MPCWMR_SUBZ_START_Msk (0x7FFUL << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) +#define GTZC_TZSC_MPCWMR_SUBZ_START GTZC_TZSC_MPCWMR_SUBZ_START_Msk +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos (16U) +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk (0xFFFUL << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk + +/******* Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers *****/ +/******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers *****/ + +/*************** Bits definition for register x=1 (TZSC1) *************/ +#define GTZC_CFGR1_TIM2_Pos (0U) +#define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) +#define GTZC_CFGR1_TIM3_Pos (1U) +#define GTZC_CFGR1_TIM3_Msk (0x01UL << GTZC_CFGR1_TIM3_Pos) +#define GTZC_CFGR1_TIM4_Pos (2U) +#define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) +#define GTZC_CFGR1_TIM5_Pos (3U) +#define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos) +#define GTZC_CFGR1_TIM6_Pos (4U) +#define GTZC_CFGR1_TIM6_Msk (0x01UL << GTZC_CFGR1_TIM6_Pos) +#define GTZC_CFGR1_TIM7_Pos (5U) +#define GTZC_CFGR1_TIM7_Msk (0x01UL << GTZC_CFGR1_TIM7_Pos) +#define GTZC_CFGR1_TIM12_Pos (6U) +#define GTZC_CFGR1_TIM12_Msk (0x01UL << GTZC_CFGR1_TIM12_Pos) +#define GTZC_CFGR1_WWDG_Pos (9U) +#define GTZC_CFGR1_WWDG_Msk (0x01UL << GTZC_CFGR1_WWDG_Pos) +#define GTZC_CFGR1_IWDG_Pos (10U) +#define GTZC_CFGR1_IWDG_Msk (0x01UL << GTZC_CFGR1_IWDG_Pos) +#define GTZC_CFGR1_SPI2_Pos (11U) +#define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos) +#define GTZC_CFGR1_SPI3_Pos (12U) +#define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos) +#define GTZC_CFGR1_USART2_Pos (13U) +#define GTZC_CFGR1_USART2_Msk (0x01UL << GTZC_CFGR1_USART2_Pos) +#define GTZC_CFGR1_USART3_Pos (14U) +#define GTZC_CFGR1_USART3_Msk (0x01UL << GTZC_CFGR1_USART3_Pos) +#define GTZC_CFGR1_UART4_Pos (15U) +#define GTZC_CFGR1_UART4_Msk (0x01UL << GTZC_CFGR1_UART4_Pos) +#define GTZC_CFGR1_UART5_Pos (16U) +#define GTZC_CFGR1_UART5_Msk (0x01UL << GTZC_CFGR1_UART5_Pos) +#define GTZC_CFGR1_I2C1_Pos (17U) +#define GTZC_CFGR1_I2C1_Msk (0x01UL << GTZC_CFGR1_I2C1_Pos) +#define GTZC_CFGR1_I2C2_Pos (18U) +#define GTZC_CFGR1_I2C2_Msk (0x01UL << GTZC_CFGR1_I2C2_Pos) +#define GTZC_CFGR1_I3C1_Pos (19U) +#define GTZC_CFGR1_I3C1_Msk (0x01UL << GTZC_CFGR1_I3C1_Pos) +#define GTZC_CFGR1_CRS_Pos (20U) +#define GTZC_CFGR1_CRS_Msk (0x01UL << GTZC_CFGR1_CRS_Pos) +#define GTZC_CFGR1_USART6_Pos (21U) +#define GTZC_CFGR1_USART6_Msk (0x01UL << GTZC_CFGR1_USART6_Pos) +#define GTZC_CFGR1_HDMICEC_Pos (24U) +#define GTZC_CFGR1_HDMICEC_Msk (0x01UL << GTZC_CFGR1_HDMICEC_Pos) +#define GTZC_CFGR1_DAC1_Pos (25U) +#define GTZC_CFGR1_DAC1_Msk (0x01UL << GTZC_CFGR1_DAC1_Pos) +#define GTZC_CFGR1_UART7_Pos (26U) +#define GTZC_CFGR1_UART7_Msk (0x01UL << GTZC_CFGR1_UART7_Pos) +#define GTZC_CFGR1_UART8_Pos (27U) +#define GTZC_CFGR1_UART8_Msk (0x01UL << GTZC_CFGR1_UART8_Pos) +#define GTZC_CFGR1_DTS_Pos (30U) +#define GTZC_CFGR1_DTS_Msk (0x01UL << GTZC_CFGR1_DTS_Pos) +#define GTZC_CFGR1_LPTIM2_Pos (31U) +#define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) + +/*************** Bits definition for register x=2 (TZSC1) *************/ +#define GTZC_CFGR2_FDCAN1_Pos (0U) +#define GTZC_CFGR2_FDCAN1_Msk (0x01UL << GTZC_CFGR2_FDCAN1_Pos) +#define GTZC_CFGR2_FDCAN2_Pos (1U) +#define GTZC_CFGR2_FDCAN2_Msk (0x01UL << GTZC_CFGR2_FDCAN2_Pos) +#define GTZC_CFGR2_UCPD1_Pos (2U) +#define GTZC_CFGR2_UCPD1_Msk (0x01UL << GTZC_CFGR2_UCPD1_Pos) +#define GTZC_CFGR2_COMP_Pos (4U) +#define GTZC_CFGR2_COMP_Msk (0x01UL << GTZC_CFGR2_COMP_Pos) +#define GTZC_CFGR2_TIM1_Pos (8U) +#define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) +#define GTZC_CFGR2_SPI1_Pos (9U) +#define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) +#define GTZC_CFGR2_TIM8_Pos (10U) +#define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos) +#define GTZC_CFGR2_USART1_Pos (11U) +#define GTZC_CFGR2_USART1_Msk (0x01UL << GTZC_CFGR2_USART1_Pos) +#define GTZC_CFGR2_TIM15_Pos (12U) +#define GTZC_CFGR2_TIM15_Msk (0x01UL << GTZC_CFGR2_TIM15_Pos) +#define GTZC_CFGR2_SPI4_Pos (15U) +#define GTZC_CFGR2_SPI4_Msk (0x01UL << GTZC_CFGR2_SPI4_Pos) +#define GTZC_CFGR2_USB_Pos (19U) +#define GTZC_CFGR2_USB_Msk (0x01UL << GTZC_CFGR2_USB_Pos) +#define GTZC_CFGR2_LPUART1_Pos (25U) +#define GTZC_CFGR2_LPUART1_Msk (0x01UL << GTZC_CFGR2_LPUART1_Pos) +#define GTZC_CFGR2_I2C3_Pos (26U) +#define GTZC_CFGR2_I2C3_Msk (0x01UL << GTZC_CFGR2_I2C3_Pos) +#define GTZC_CFGR2_LPTIM1_Pos (28U) +#define GTZC_CFGR2_LPTIM1_Msk (0x01UL << GTZC_CFGR2_LPTIM1_Pos) + +/*************** Bits definition for register x=3 (TZSC1) *************/ +#define GTZC_CFGR3_VREFBUF_Pos (1U) +#define GTZC_CFGR3_VREFBUF_Msk (0x01UL << GTZC_CFGR3_VREFBUF_Pos) +#define GTZC_CFGR3_I3C2_Pos (2U) +#define GTZC_CFGR3_I3C2_Msk (0x01UL << GTZC_CFGR3_I3C2_Pos) +#define GTZC_CFGR3_ADC3_Pos (6U) +#define GTZC_CFGR3_ADC3_Msk (0x01UL << GTZC_CFGR3_ADC3_Pos) +#define GTZC_CFGR3_CRC_Pos (8U) +#define GTZC_CFGR3_CRC_Msk (0x01UL << GTZC_CFGR3_CRC_Pos) +#define GTZC_CFGR3_CORDIC_Pos (9U) +#define GTZC_CFGR3_CORDIC_Msk (0x01UL << GTZC_CFGR3_CORDIC_Pos) +#define GTZC_CFGR3_ETHERNET_Pos (11U) +#define GTZC_CFGR3_ETHERNET_Msk (0x01UL << GTZC_CFGR3_ETHERNET_Pos) +#define GTZC_CFGR3_ICACHE_REG_Pos (12U) +#define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) +#define GTZC_CFGR3_DCACHE1_REG_Pos (13U) +#define GTZC_CFGR3_DCACHE1_REG_Msk (0x01UL << GTZC_CFGR3_DCACHE1_REG_Pos) +#define GTZC_CFGR3_ADC_Pos (14U) +#define GTZC_CFGR3_ADC_Msk (0x01UL << GTZC_CFGR3_ADC_Pos) +#define GTZC_CFGR3_HASH_Pos (17U) +#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) +#define GTZC_CFGR3_RNG_Pos (18U) +#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos) +#define GTZC_CFGR3_PKA_Pos (20U) +#define GTZC_CFGR3_PKA_Msk (0x01UL << GTZC_CFGR3_PKA_Pos) +#define GTZC_CFGR3_SDMMC1_Pos (21U) +#define GTZC_CFGR3_SDMMC1_Msk (0x01UL << GTZC_CFGR3_SDMMC1_Pos) +#define GTZC_CFGR3_FMC_REG_Pos (23U) +#define GTZC_CFGR3_FMC_REG_Msk (0x01UL << GTZC_CFGR3_FMC_REG_Pos) +#define GTZC_CFGR3_OCTOSPI1_Pos (24U) +#define GTZC_CFGR3_OCTOSPI1_Msk (0x01UL << GTZC_CFGR3_OCTOSPI1_Pos) +#define GTZC_CFGR3_RAMCFG_Pos (26U) +#define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) + +/*************** Bits definition for register x=4 (TZSC1) *************/ +#define GTZC_CFGR4_GPDMA1_Pos (0U) +#define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) +#define GTZC_CFGR4_GPDMA2_Pos (1U) +#define GTZC_CFGR4_GPDMA2_Msk (0x01UL << GTZC_CFGR4_GPDMA2_Pos) +#define GTZC_CFGR4_FLASH_Pos (2U) +#define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos) +#define GTZC_CFGR4_FLASH_REG_Pos (3U) +#define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos) + +#define GTZC_CFGR4_SBS_Pos (6U) +#define GTZC_CFGR4_SBS_Msk (0x01UL << GTZC_CFGR4_SBS_Pos) +#define GTZC_CFGR4_RTC_Pos (7U) +#define GTZC_CFGR4_RTC_Msk (0x01UL << GTZC_CFGR4_RTC_Pos) +#define GTZC_CFGR4_TAMP_Pos (8U) +#define GTZC_CFGR4_TAMP_Msk (0x01UL << GTZC_CFGR4_TAMP_Pos) +#define GTZC_CFGR4_PWR_Pos (9U) +#define GTZC_CFGR4_PWR_Msk (0x01UL << GTZC_CFGR4_PWR_Pos) +#define GTZC_CFGR4_RCC_Pos (10U) +#define GTZC_CFGR4_RCC_Msk (0x01UL << GTZC_CFGR4_RCC_Pos) +#define GTZC_CFGR4_EXTI_Pos (11U) +#define GTZC_CFGR4_EXTI_Msk (0x01UL << GTZC_CFGR4_EXTI_Pos) +#define GTZC_CFGR4_PLAY1_Pos (12U) +#define GTZC_CFGR4_PLAY1_Msk (0x01UL << GTZC_CFGR4_PLAY1_Pos) +#define GTZC_CFGR4_TZSC_Pos (16U) +#define GTZC_CFGR4_TZSC_Msk (0x01UL << GTZC_CFGR4_TZSC_Pos) +#define GTZC_CFGR4_TZIC_Pos (17U) +#define GTZC_CFGR4_TZIC_Msk (0x01UL << GTZC_CFGR4_TZIC_Pos) +#define GTZC_CFGR4_OCTOSPI1_MEM_Pos (18U) +#define GTZC_CFGR4_OCTOSPI1_MEM_Msk (0x01UL << GTZC_CFGR4_OCTOSPI1_MEM_Pos) +#define GTZC_CFGR4_FMC_MEM_Pos (19U) +#define GTZC_CFGR4_FMC_MEM_Msk (0x01UL << GTZC_CFGR4_FMC_MEM_Pos) +#define GTZC_CFGR4_BKPSRAM_Pos (20U) +#define GTZC_CFGR4_BKPSRAM_Msk (0x01UL << GTZC_CFGR4_BKPSRAM_Pos) +#define GTZC_CFGR4_SRAM1_Pos (24U) +#define GTZC_CFGR4_SRAM1_Msk (0x01UL << GTZC_CFGR4_SRAM1_Pos) +#define GTZC_CFGR4_MPCBB1_REG_Pos (25U) +#define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos) +#define GTZC_CFGR4_SRAM2_Pos (26U) +#define GTZC_CFGR4_SRAM2_Msk (0x01UL << GTZC_CFGR4_SRAM2_Pos) +#define GTZC_CFGR4_MPCBB2_REG_Pos (27U) +#define GTZC_CFGR4_MPCBB2_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos) +#define GTZC_CFGR4_SRAM3_Pos (28U) +#define GTZC_CFGR4_SRAM3_Msk (0x01UL << GTZC_CFGR4_SRAM3_Pos) +#define GTZC_CFGR4_MPCBB3_REG_Pos (29U) +#define GTZC_CFGR4_MPCBB3_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB3_REG_Pos) + +/******************* Bits definition for GTZC_TZSC1_SECCFGR1 register ***************/ +#define GTZC_TZSC1_SECCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZSC1_SECCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZSC1_SECCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZSC1_SECCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZSC1_SECCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZSC1_SECCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZSC1_SECCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZSC1_SECCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZSC1_SECCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZSC1_SECCFGR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZSC1_SECCFGR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZSC1_SECCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZSC1_SECCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZSC1_SECCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZSC1_SECCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZSC1_SECCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZSC1_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZSC1_SECCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZSC1_SECCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZSC1_SECCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZSC1_SECCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZSC1_SECCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZSC1_SECCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZSC1_SECCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZSC1_SECCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZSC1_SECCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZSC1_SECCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZSC1_SECCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZSC1_SECCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZSC1_SECCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZSC1_SECCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZSC1_SECCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZSC1_SECCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZSC1_SECCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZSC1_SECCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZSC1_SECCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZSC1_SECCFGR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZSC1_SECCFGR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZSC1_SECCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZSC1_SECCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZSC1_SECCFGR1_UART7_Pos GTZC_CFGR1_UART7_Pos +#define GTZC_TZSC1_SECCFGR1_UART7_Msk GTZC_CFGR1_UART7_Msk +#define GTZC_TZSC1_SECCFGR1_UART8_Pos GTZC_CFGR1_UART8_Pos +#define GTZC_TZSC1_SECCFGR1_UART8_Msk GTZC_CFGR1_UART8_Msk +#define GTZC_TZSC1_SECCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZSC1_SECCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZSC1_SECCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/ +#define GTZC_TZSC1_SECCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZSC1_SECCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZSC1_SECCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZSC1_SECCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZSC1_SECCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZSC1_SECCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZSC1_SECCFGR2_COMP_Pos GTZC_CFGR2_COMP_Pos +#define GTZC_TZSC1_SECCFGR2_COMP_Msk GTZC_CFGR2_COMP_Msk +#define GTZC_TZSC1_SECCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZSC1_SECCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZSC1_SECCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZSC1_SECCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZSC1_SECCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZSC1_SECCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZSC1_SECCFGR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZSC1_SECCFGR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZSC1_SECCFGR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZSC1_SECCFGR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZSC1_SECCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZSC1_SECCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZSC1_SECCFGR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZSC1_SECCFGR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZSC1_SECCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZSC1_SECCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZSC_SECCFGR3 register ***************/ +#define GTZC_TZSC1_SECCFGR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZSC1_SECCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZSC1_SECCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZSC1_SECCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZSC1_SECCFGR3_ADC3_Pos GTZC_CFGR3_ADC3_Pos +#define GTZC_TZSC1_SECCFGR3_ADC3_Msk GTZC_CFGR3_ADC3_Msk +#define GTZC_TZSC1_SECCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZSC1_SECCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZSC1_SECCFGR3_CORDIC_Pos GTZC_CFGR3_CORDIC_Pos +#define GTZC_TZSC1_SECCFGR3_CORDIC_Msk GTZC_CFGR3_CORDIC_Msk +#define GTZC_TZSC1_SECCFGR3_ETHERNET_Pos GTZC_CFGR3_ETHERNET_Pos +#define GTZC_TZSC1_SECCFGR3_ETHERNET_Msk GTZC_CFGR3_ETHERNET_Msk +#define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZSC1_SECCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZSC1_SECCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZSC1_SECCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZSC1_SECCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZSC1_SECCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZSC1_SECCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZSC1_SECCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZSC1_SECCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZSC1_SECCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZSC1_SECCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZSC1_SECCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZSC1_SECCFGR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZSC1_SECCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZSC1_SECCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/ +#define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZSC1_PRIVCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZSC1_PRIVCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZSC1_PRIVCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZSC1_PRIVCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZSC1_PRIVCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZSC1_PRIVCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZSC1_PRIVCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZSC1_PRIVCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZSC1_PRIVCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZSC1_PRIVCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZSC1_PRIVCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZSC1_PRIVCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZSC1_PRIVCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZSC1_PRIVCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZSC1_PRIVCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZSC1_PRIVCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART7_Pos GTZC_CFGR1_UART7_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART7_Msk GTZC_CFGR1_UART7_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART8_Pos GTZC_CFGR1_UART8_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART8_Msk GTZC_CFGR1_UART8_Msk +#define GTZC_TZSC1_PRIVCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZSC1_PRIVCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/ +#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZSC1_PRIVCFGR2_COMP_Pos GTZC_CFGR2_COMP_Pos +#define GTZC_TZSC1_PRIVCFGR2_COMP_Msk GTZC_CFGR2_COMP_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZSC1_PRIVCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZSC1_PRIVCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZSC1_PRIVCFGR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZSC1_PRIVCFGR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZSC1_PRIVCFGR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZSC1_PRIVCFGR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZSC1_PRIVCFGR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZSC1_PRIVCFGR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR3 register ***************/ +#define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZSC1_PRIVCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZSC1_PRIVCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZSC1_PRIVCFGR3_ADC3_Pos GTZC_CFGR3_ADC3_Pos +#define GTZC_TZSC1_PRIVCFGR3_ADC3_Msk GTZC_CFGR3_ADC3_Msk +#define GTZC_TZSC1_PRIVCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZSC1_PRIVCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZSC1_PRIVCFGR3_CORDIC_Pos GTZC_CFGR3_CORDIC_Pos +#define GTZC_TZSC1_PRIVCFGR3_CORDIC_Msk GTZC_CFGR3_CORDIC_Msk +#define GTZC_TZSC1_PRIVCFGR3_ETHERNET_Pos GTZC_CFGR3_ETHERNET_Pos +#define GTZC_TZSC1_PRIVCFGR3_ETHERNET_Msk GTZC_CFGR3_ETHERNET_Msk +#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZSC1_PRIVCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZSC1_PRIVCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZSC1_PRIVCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZSC1_PRIVCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZSC1_PRIVCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZSC1_PRIVCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZSC1_PRIVCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_IER1 register ***************/ +#define GTZC_TZIC1_IER1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_IER1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_IER1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_IER1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_IER1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_IER1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_IER1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_IER1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_IER1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_IER1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_IER1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_IER1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_IER1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_IER1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_IER1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_IER1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_IER1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_IER1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_IER1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_IER1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_IER1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_IER1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_IER1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_IER1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_IER1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_IER1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_IER1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_IER1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_IER1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_IER1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_IER1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_IER1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_IER1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_IER1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_IER1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_IER1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_IER1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_IER1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_IER1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_IER1_UART7_Pos GTZC_CFGR1_UART7_Pos +#define GTZC_TZIC1_IER1_UART7_Msk GTZC_CFGR1_UART7_Msk +#define GTZC_TZIC1_IER1_UART8_Pos GTZC_CFGR1_UART8_Pos +#define GTZC_TZIC1_IER1_UART8_Msk GTZC_CFGR1_UART8_Msk +#define GTZC_TZIC1_IER1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_IER1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_IER1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_IER2 register ***************/ +#define GTZC_TZIC1_IER2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_IER2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_IER2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_IER2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_IER2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_IER2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_IER2_COMP_Pos GTZC_CFGR2_COMP_Pos +#define GTZC_TZIC1_IER2_COMP_Msk GTZC_CFGR2_COMP_Msk +#define GTZC_TZIC1_IER2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_IER2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_IER2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_IER2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_IER2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_IER2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_IER2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_IER2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_IER2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_IER2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_IER2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_IER2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_IER2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_IER2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_IER2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_IER2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_IER2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZIC_IER3 register ***************/ +#define GTZC_TZIC1_IER3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_IER3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_IER3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_IER3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_IER3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_IER3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_IER3_ADC3_Pos GTZC_CFGR3_ADC3_Pos +#define GTZC_TZIC1_IER3_ADC3_Msk GTZC_CFGR3_ADC3_Msk +#define GTZC_TZIC1_IER3_CORDIC_Pos GTZC_CFGR3_CORDIC_Pos +#define GTZC_TZIC1_IER3_CORDIC_Msk GTZC_CFGR3_CORDIC_Msk +#define GTZC_TZIC1_IER3_ETHERNET_Pos GTZC_CFGR3_ETHERNET_Pos +#define GTZC_TZIC1_IER3_ETHERNET_Msk GTZC_CFGR3_ETHERNET_Msk +#define GTZC_TZIC1_IER3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_IER3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_IER3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_IER3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_IER3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_IER3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_IER3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_IER3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_IER3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_IER3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_IER3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_IER3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_IER3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_IER3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_IER3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_IER3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_IER3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_IER3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_IER3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_IER3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_IER3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_IER3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_TZIC1_IER4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_IER4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_IER4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_IER4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_IER4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_IER4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_IER4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_IER4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_IER4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_IER4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_IER4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_IER4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_IER4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_IER4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_IER4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_IER4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_IER4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_IER4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_IER4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_IER4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_IER4_PLAY1_Pos GTZC_CFGR4_PLAY1_Pos +#define GTZC_TZIC1_IER4_PLAY1_Msk GTZC_CFGR4_PLAY1_Msk +#define GTZC_TZIC1_IER4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_IER4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_IER4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_IER4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_IER4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_IER4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_IER4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_IER4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_IER4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_IER4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_IER4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_IER4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_IER4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_IER4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_IER4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_IER4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/******************* Bits definition for GTZC_TZIC_SR1 register **************/ +#define GTZC_TZIC1_SR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_SR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_SR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_SR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_SR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_SR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_SR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_SR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_SR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_SR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_SR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_SR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_SR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_SR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_SR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_SR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_SR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_SR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_SR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_SR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_SR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_SR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_SR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_SR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_SR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_SR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_SR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_SR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_SR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_SR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_SR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_SR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_SR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_SR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_SR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_SR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_SR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_SR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_SR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_SR1_UART7_Pos GTZC_CFGR1_UART7_Pos +#define GTZC_TZIC1_SR1_UART7_Msk GTZC_CFGR1_UART7_Msk +#define GTZC_TZIC1_SR1_UART8_Pos GTZC_CFGR1_UART8_Pos +#define GTZC_TZIC1_SR1_UART8_Msk GTZC_CFGR1_UART8_Msk +#define GTZC_TZIC1_SR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_SR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_SR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_SR2 register **************/ +#define GTZC_TZIC1_SR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_SR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_SR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_SR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_SR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_SR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_SR2_COMP_Pos GTZC_CFGR2_COMP_Pos +#define GTZC_TZIC1_SR2_COMP_Msk GTZC_CFGR2_COMP_Msk +#define GTZC_TZIC1_SR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_SR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_SR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_SR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_SR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_SR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_SR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_SR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_SR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_SR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_SR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_SR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_SR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_SR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_SR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_SR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_SR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZIC_SR3 register **************/ +#define GTZC_TZIC1_SR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_SR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_SR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_SR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_SR3_ADC3_Pos GTZC_CFGR3_ADC3_Pos +#define GTZC_TZIC1_SR3_ADC3_Msk GTZC_CFGR3_ADC3_Msk +#define GTZC_TZIC1_SR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_SR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_SR3_CORDIC_Pos GTZC_CFGR3_CORDIC_Pos +#define GTZC_TZIC1_SR3_CORDIC_Msk GTZC_CFGR3_CORDIC_Msk +#define GTZC_TZIC1_SR3_ETHERNET_Pos GTZC_CFGR3_ETHERNET_Pos +#define GTZC_TZIC1_SR3_ETHERNET_Msk GTZC_CFGR3_ETHERNET_Msk +#define GTZC_TZIC1_SR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_SR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_SR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_SR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_SR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_SR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_SR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_SR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_SR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_SR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_SR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_SR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_SR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_SR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_SR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_SR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_SR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_SR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_SR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_SR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_SR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_SR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_SR4 register ***************/ +#define GTZC_TZIC1_SR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_SR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_SR4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_SR4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_SR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_SR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_SR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_SR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_SR4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_SR4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_SR4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_SR4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_SR4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_SR4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_SR4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_SR4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_SR4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_SR4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_SR4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_SR4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_SR4_PLAY1_Pos GTZC_CFGR4_PLAY1_Pos +#define GTZC_TZIC1_SR4_PLAY1_Msk GTZC_CFGR4_PLAY1_Msk +#define GTZC_TZIC1_SR4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_SR4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_SR4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_SR4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_SR4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_SR4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_SR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_SR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_SR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_SR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_SR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_SR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_SR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_SR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_SR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_SR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/****************** Bits definition for GTZC_TZIC_FCR1 register ****************/ +#define GTZC_TZIC1_FCR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_FCR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_FCR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_FCR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_FCR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_FCR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_FCR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_FCR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_FCR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_FCR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_FCR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_FCR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_FCR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_FCR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_FCR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_FCR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_FCR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_FCR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_FCR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_FCR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_FCR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_FCR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_FCR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_FCR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_FCR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_FCR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_FCR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_FCR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_FCR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_FCR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_FCR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_FCR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_FCR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_FCR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_FCR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_FCR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_FCR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_FCR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_FCR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_FCR1_UART7_Pos GTZC_CFGR1_UART7_Pos +#define GTZC_TZIC1_FCR1_UART7_Msk GTZC_CFGR1_UART7_Msk +#define GTZC_TZIC1_FCR1_UART8_Pos GTZC_CFGR1_UART8_Pos +#define GTZC_TZIC1_FCR1_UART8_Msk GTZC_CFGR1_UART8_Msk +#define GTZC_TZIC1_FCR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_FCR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_FCR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_FCR2 register **************/ +#define GTZC_TZIC1_FCR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_FCR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_FCR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_FCR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_FCR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_FCR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_FCR2_COMP_Pos GTZC_CFGR2_COMP_Pos +#define GTZC_TZIC1_FCR2_COMP_Msk GTZC_CFGR2_COMP_Msk +#define GTZC_TZIC1_FCR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_FCR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_FCR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_FCR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_FCR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_FCR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_FCR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_FCR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_FCR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_FCR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_FCR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_FCR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_FCR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_FCR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_FCR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_FCR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_FCR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/****************** Bits definition for GTZC_TZIC_FCR3 register ****************/ +#define GTZC_TZIC1_FCR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_FCR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_FCR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_FCR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_FCR3_ADC3_Pos GTZC_CFGR3_ADC3_Pos +#define GTZC_TZIC1_FCR3_ADC3_Msk GTZC_CFGR3_ADC3_Msk +#define GTZC_TZIC1_FCR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_FCR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_FCR3_CORDIC_Pos GTZC_CFGR3_CORDIC_Pos +#define GTZC_TZIC1_FCR3_CORDIC_Msk GTZC_CFGR3_CORDIC_Msk +#define GTZC_TZIC1_FCR3_ETHERNET_Pos GTZC_CFGR3_ETHERNET_Pos +#define GTZC_TZIC1_FCR3_ETHERNET_Msk GTZC_CFGR3_ETHERNET_Msk +#define GTZC_TZIC1_FCR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_FCR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_FCR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_FCR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_FCR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_FCR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_FCR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_FCR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_FCR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_FCR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_FCR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_FCR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_FCR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_FCR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_FCR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_FCR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_FCR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_FCR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_FCR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_FCR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_FCR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_FCR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_FCR4 register ***************/ +#define GTZC_TZIC1_FCR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_FCR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_FCR4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_FCR4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_FCR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_FCR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_FCR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_FCR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_FCR4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_FCR4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_FCR4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_FCR4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_FCR4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_FCR4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_FCR4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_FCR4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_FCR4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_FCR4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_FCR4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_FCR4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_FCR4_PLAY1_Pos GTZC_CFGR4_PLAY1_Pos +#define GTZC_TZIC1_FCR4_PLAY1_Msk GTZC_CFGR4_PLAY1_Msk +#define GTZC_TZIC1_FCR4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_FCR4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_FCR4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_FCR4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_FCR4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_FCR4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_FCR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_FCR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_FCR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_FCR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_FCR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_FCR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_FCR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_FCR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_FCR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_FCR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/******************* Bits definition for GTZC_MPCBB_CR register *****************/ +#define GTZC_MPCBB_CR_GLOCK_Pos (0U) +#define GTZC_MPCBB_CR_GLOCK_Msk (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CR_INVSECSTATE_Pos (30U) +#define GTZC_MPCBB_CR_INVSECSTATE_Msk (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CR_SRWILADIS_Pos (31U) +#define GTZC_MPCBB_CR_SRWILADIS_Msk (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for GTZC_MPCBB_CFGLOCKR1 register ************/ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos (0U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos (1U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos (2U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos (3U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos (4U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos (5U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos (6U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos (7U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos (8U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos (9U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos (10U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos (11U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos (12U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos (13U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos (14U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos (15U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos (16U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos (17U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos (18U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos (19U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos (20U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos (21U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos (22U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos (23U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos (24U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos (25U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos (26U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos (27U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos (28U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos (29U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos (30U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos (31U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos) /*!< 0x80000000 */ + + +/******************************************************************************/ +/* */ +/* UCPD */ +/* */ +/******************************************************************************/ +/******************** Bits definition for UCPD_CFG1 register *******************/ +#define UCPD_CFG1_HBITCLKDIV_Pos (0U) +#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */ +#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */ +#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */ +#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */ +#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */ +#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */ +#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */ +#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */ +#define UCPD_CFG1_IFRGAP_Pos (6U) +#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */ +#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */ +#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */ +#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */ +#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */ +#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */ +#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */ +#define UCPD_CFG1_TRANSWIN_Pos (11U) +#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */ +#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */ +#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */ +#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */ +#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */ +#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */ +#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */ +#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U) +#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */ +#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */ +#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */ +#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */ +#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */ +#define UCPD_CFG1_RXORDSETEN_Pos (20U) +#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x1FF00000 */ +#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */ +#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00100000 */ +#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00200000 */ +#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00400000 */ +#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00800000 */ +#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x01000000 */ +#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x02000000 */ +#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x04000000 */ +#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x08000000 */ +#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x10000000 */ +#define UCPD_CFG1_TXDMAEN_Pos (29U) +#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */ +#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define UCPD_CFG1_RXDMAEN_Pos (30U) +#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */ +#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define UCPD_CFG1_UCPDEN_Pos (31U) +#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */ +#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */ + +/******************** Bits definition for UCPD_CFG2 register *******************/ +#define UCPD_CFG2_RXFILTDIS_Pos (0U) +#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */ +#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */ +#define UCPD_CFG2_RXFILT2N3_Pos (1U) +#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */ +#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */ +#define UCPD_CFG2_FORCECLK_Pos (2U) +#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */ +#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */ +#define UCPD_CFG2_WUPEN_Pos (3U) +#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */ +#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define UCPD_CFG2_RXAFILTEN_Pos (8U) +#define UCPD_CFG2_RXAFILTEN_Msk (0x1UL << UCPD_CFG2_RXAFILTEN_Pos) /*!< 0x00000100 */ +#define UCPD_CFG2_RXAFILTEN UCPD_CFG2_RXAFILTEN_Msk /*!< Rx analog filter enable */ + +/******************** Bits definition for UCPD_CFG3 register *******************/ +#define UCPD_CFG3_TRIM_CC1_RD_Pos (0U) +#define UCPD_CFG3_TRIM_CC1_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RD_Pos) /*!< 0x0000000F */ +#define UCPD_CFG3_TRIM_CC1_RD UCPD_CFG3_TRIM_CC1_RD_Msk /*!< SW trim value for RD resistor (CC1) */ +#define UCPD_CFG3_TRIM_CC1_RP_Pos (9U) +#define UCPD_CFG3_TRIM_CC1_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RP_Pos) /*!< 0x00001E00 */ +#define UCPD_CFG3_TRIM_CC1_RP UCPD_CFG3_TRIM_CC1_RP_Msk /*!< SW trim value for RP current sources (CC1) */ +#define UCPD_CFG3_TRIM_CC2_RD_Pos (16U) +#define UCPD_CFG3_TRIM_CC2_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RD_Pos) /*!< 0x000F0000 */ +#define UCPD_CFG3_TRIM_CC2_RD UCPD_CFG3_TRIM_CC2_RD_Msk /*!< SW trim value for RD resistor (CC2) */ +#define UCPD_CFG3_TRIM_CC2_RP_Pos (25U) +#define UCPD_CFG3_TRIM_CC2_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RP_Pos) /*!< 0x1E000000 */ +#define UCPD_CFG3_TRIM_CC2_RP UCPD_CFG3_TRIM_CC2_RP_Msk /*!< SW trim value for RP current sources (CC2) */ + +/******************** Bits definition for UCPD_CR register ********************/ +#define UCPD_CR_TXMODE_Pos (0U) +#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */ +#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */ +#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */ +#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */ +#define UCPD_CR_TXSEND_Pos (2U) +#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */ +#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */ +#define UCPD_CR_TXHRST_Pos (3U) +#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */ +#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */ +#define UCPD_CR_RXMODE_Pos (4U) +#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */ +#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */ +#define UCPD_CR_PHYRXEN_Pos (5U) +#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */ +#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */ +#define UCPD_CR_PHYCCSEL_Pos (6U) +#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */ +#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */ +#define UCPD_CR_ANASUBMODE_Pos (7U) +#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */ +#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */ +#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */ +#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */ +#define UCPD_CR_ANAMODE_Pos (9U) +#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */ +#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */ +#define UCPD_CR_CCENABLE_Pos (10U) +#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */ +#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */ +#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */ +#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */ +#define UCPD_CR_FRSRXEN_Pos (16U) +#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */ +#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */ +#define UCPD_CR_FRSTX_Pos (17U) +#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */ +#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */ +#define UCPD_CR_RDCH_Pos (18U) +#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */ +#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */ +#define UCPD_CR_CC1TCDIS_Pos (20U) +#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */ +#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */ +#define UCPD_CR_CC2TCDIS_Pos (21U) +#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */ +#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */ + +/******************** Bits definition for UCPD_IMR register *******************/ +#define UCPD_IMR_TXISIE_Pos (0U) +#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */ +#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */ +#define UCPD_IMR_TXMSGDISCIE_Pos (1U) +#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */ +#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */ +#define UCPD_IMR_TXMSGSENTIE_Pos (2U) +#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */ +#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */ +#define UCPD_IMR_TXMSGABTIE_Pos (3U) +#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */ +#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */ +#define UCPD_IMR_HRSTDISCIE_Pos (4U) +#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */ +#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */ +#define UCPD_IMR_HRSTSENTIE_Pos (5U) +#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */ +#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */ +#define UCPD_IMR_TXUNDIE_Pos (6U) +#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */ +#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */ +#define UCPD_IMR_RXNEIE_Pos (8U) +#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */ +#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */ +#define UCPD_IMR_RXORDDETIE_Pos (9U) +#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */ +#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */ +#define UCPD_IMR_RXHRSTDETIE_Pos (10U) +#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */ +#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */ +#define UCPD_IMR_RXOVRIE_Pos (11U) +#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */ +#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */ +#define UCPD_IMR_RXMSGENDIE_Pos (12U) +#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */ +#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */ +#define UCPD_IMR_TYPECEVT1IE_Pos (14U) +#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */ +#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */ +#define UCPD_IMR_TYPECEVT2IE_Pos (15U) +#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */ +#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */ +#define UCPD_IMR_FRSEVTIE_Pos (20U) +#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */ +#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */ + +/******************** Bits definition for UCPD_SR register ********************/ +#define UCPD_SR_TXIS_Pos (0U) +#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */ +#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */ +#define UCPD_SR_TXMSGDISC_Pos (1U) +#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */ +#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */ +#define UCPD_SR_TXMSGSENT_Pos (2U) +#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */ +#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */ +#define UCPD_SR_TXMSGABT_Pos (3U) +#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */ +#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */ +#define UCPD_SR_HRSTDISC_Pos (4U) +#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */ +#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */ +#define UCPD_SR_HRSTSENT_Pos (5U) +#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */ +#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */ +#define UCPD_SR_TXUND_Pos (6U) +#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */ +#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */ +#define UCPD_SR_RXNE_Pos (8U) +#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */ +#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */ +#define UCPD_SR_RXORDDET_Pos (9U) +#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */ +#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */ +#define UCPD_SR_RXHRSTDET_Pos (10U) +#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */ +#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */ +#define UCPD_SR_RXOVR_Pos (11U) +#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */ +#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */ +#define UCPD_SR_RXMSGEND_Pos (12U) +#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */ +#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */ +#define UCPD_SR_RXERR_Pos (13U) +#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */ +#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */ +#define UCPD_SR_TYPECEVT1_Pos (14U) +#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */ +#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */ +#define UCPD_SR_TYPECEVT2_Pos (15U) +#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */ +#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */ +#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U) +#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00030000 */ +#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */ +#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00010000 */ +#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00020000 */ +#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U) +#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x000C0000 */ +#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/** @addtogroup STM32H5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || ((INSTANCE) == ADC1_S) || \ + ((INSTANCE) == ADC2_NS) || ((INSTANCE) == ADC2_S) || \ + ((INSTANCE) == ADC3_NS) || ((INSTANCE) == ADC3_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || ((INSTANCE) == ADC1_S)) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || ((INSTANCE) == ADC12_COMMON_S) || \ + ((INSTANCE) == ADC3_COMMON_NS) || ((INSTANCE) == ADC3_COMMON_S)) +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************* CORDIC Instances *****************************/ +#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) + + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S )) +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel1_NS) || ((INSTANCE) == GPDMA2_Channel1_S) || \ + ((INSTANCE) == GPDMA2_Channel2_NS) || ((INSTANCE) == GPDMA2_Channel2_S) || \ + ((INSTANCE) == GPDMA2_Channel3_NS) || ((INSTANCE) == GPDMA2_Channel3_S) || \ + ((INSTANCE) == GPDMA2_Channel4_NS) || ((INSTANCE) == GPDMA2_Channel4_S) || \ + ((INSTANCE) == GPDMA2_Channel5_NS) || ((INSTANCE) == GPDMA2_Channel5_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) IS_DMA_ALL_INSTANCE(INSTANCE) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + + + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* PLAY Instances *******************************/ +#define IS_PLAY_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PLAY1_NS) || ((__INSTANCE__) == PLAY1_S)) + +#define PLAY_INPUT_MUX_NBR(INSTANCE) \ + ((((INSTANCE) == PLAY1_NS) || ((INSTANCE) == PLAY1_S))?16U:0U) + +#define PLAY_LUT_NBR(INSTANCE) \ + ((((INSTANCE) == PLAY1_NS) || ((INSTANCE) == PLAY1_S))?16U:0U) + +#define PLAY_OUTPUT_MUX_NBR(INSTANCE) \ + ((((INSTANCE) == PLAY1_NS) || ((INSTANCE) == PLAY1_S))?16U:0U) + +#define PLAY_SWTRIGGER_NBR(INSTANCE) \ + ((((INSTANCE) == PLAY1_NS) || ((INSTANCE) == PLAY1_S))?16U:0U) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* DTS Instances *******************************/ +#define IS_DTS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DTS_NS) || ((__INSTANCE__) == DTS_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On H5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On H5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************************** I3C Instances *******************************/ +#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || ((INSTANCE) == I3C1_S) || \ + ((INSTANCE) == I3C2_NS) || ((INSTANCE) == I3C2_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \ + ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \ + ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S)) + +/****************************** FDCAN Instances *******************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S) || \ + ((INSTANCE) == FDCAN2_NS) || ((INSTANCE) == FDCAN2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S) || \ + ((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) ) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) +#define IS_TIM_OCXREF_COMP_CLEARINPUT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************************** I2S Instances *******************************/ +#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** CEC Instance *****************************************/ +#define IS_CEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CEC_NS) || ((INSTANCE) == CEC_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* USB DRD FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************* USB DRD FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************** COMP Instances with window mode capability **************/ +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) +/** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32H543xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H543xx_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h553xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h553xx.h new file mode 100644 index 0000000000..675fa1a5ce --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h553xx.h @@ -0,0 +1,25428 @@ +/** + ****************************************************************************** + * @file stm32h553xx.h + * @author MCD Application Team + * @brief CMSIS STM32H553xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32H553xx_H +#define STM32H553xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32H553xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32H553xx Specific Interrupt Numbers ====================================== */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + GPDMA1_Channel0_IRQn = 27, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 28, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 29, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 30, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 31, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 32, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 33, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 34, /*!< GPDMA1 Channel 7 global interrupt */ + IWDG_IRQn = 35, /*!< IWDG global interrupt */ + SAES_IRQn = 36, /*!< Secure AES global interrupt */ + ADC1_IRQn = 37, /*!< ADC1 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + I2C1_EV_IRQn = 51, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 52, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 53, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 54, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 55, /*!< SPI1 global interrupt */ + SPI2_IRQn = 56, /*!< SPI2 global interrupt */ + SPI3_IRQn = 57, /*!< SPI3 global interrupt */ + USART1_IRQn = 58, /*!< USART1 global interrupt */ + USART2_IRQn = 59, /*!< USART2 global interrupt */ + USART3_IRQn = 60, /*!< USART3 global interrupt */ + UART4_IRQn = 61, /*!< UART4 global interrupt */ + UART5_IRQn = 62, /*!< UART5 global interrupt */ + LPUART1_IRQn = 63, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 64, /*!< LPTIM1 global interrupt */ + TIM8_BRK_IRQn = 65, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 66, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 67, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 68, /*!< TIM8 Capture Compare interrupt */ + ADC2_IRQn = 69, /*!< ADC2 global interrupt */ + LPTIM2_IRQn = 70, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 71, /*!< TIM15 global interrupt */ + USB_DRD_FS_IRQn = 74, /*!< USB FS global interrupt */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + UCPD1_IRQn = 76, /*!< UCPD1 global interrupt */ + FMC_IRQn = 77, /*!< FMC global interrupt */ + OCTOSPI1_IRQn = 78, /*!< OctoSPI1 global interrupt */ + SDMMC1_IRQn = 79, /*!< SDMMC1 global interrupt */ + I2C3_EV_IRQn = 80, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 81, /*!< I2C3 error interrupt */ + SPI4_IRQn = 82, /*!< SPI4 global interrupt */ + USART6_IRQn = 85, /*!< USART6 global interrupt */ + GPDMA2_Channel0_IRQn = 90, /*!< GPDMA2 Channel 0 global interrupt */ + GPDMA2_Channel1_IRQn = 91, /*!< GPDMA2 Channel 1 global interrupt */ + GPDMA2_Channel2_IRQn = 92, /*!< GPDMA2 Channel 2 global interrupt */ + GPDMA2_Channel3_IRQn = 93, /*!< GPDMA2 Channel 3 global interrupt */ + GPDMA2_Channel4_IRQn = 94, /*!< GPDMA2 Channel 4 global interrupt */ + GPDMA2_Channel5_IRQn = 95, /*!< GPDMA2 Channel 5 global interrupt */ + GPDMA2_Channel6_IRQn = 96, /*!< GPDMA2 Channel 6 global interrupt */ + GPDMA2_Channel7_IRQn = 97, /*!< GPDMA2 Channel 7 global interrupt */ + UART7_IRQn = 98, /*!< UART7 global interrupt */ + UART8_IRQn = 99, /*!< UART8 global interrupt */ + FPU_IRQn = 103, /*!< FPU global interrupt */ + ICACHE_IRQn = 104, /*!< Instruction cache global interrupt */ + DCACHE1_IRQn = 105, /*!< Data cache global interrupt */ + ETH_IRQn = 106, /*!< Ethernet global interrupt */ + ETH_WKUP_IRQn = 107, /*!< Ethernet Wakeup global interrupt */ + FDCAN2_IT0_IRQn = 109, /*!< FDCAN2 interrupt 0 */ + FDCAN2_IT1_IRQn = 110, /*!< FDCAN2 interrupt 1 */ + CORDIC_IRQn = 111, /*!< CORDIC global interrupt */ + DTS_IRQn = 113, /*!< DTS global interrupt */ + RNG_IRQn = 114, /*!< RNG global interrupt */ + OTFDEC1_IRQn = 115, /*!< OTFDEC1 global interrupt */ + AES_IRQn = 116, /*!< AES global interrupt */ + HASH_IRQn = 117, /*!< HASH global interrupt */ + PKA_IRQn = 118, /*!< PKA global interrupt */ + CEC_IRQn = 119, /*!< CEC-HDMI global interrupt */ + TIM12_IRQn = 120, /*!< TIM12 global interrupt */ + I3C1_EV_IRQn = 123, /*!< I3C1 event interrupt */ + I3C1_ER_IRQn = 124, /*!< I3C1 error interrupt */ + I3C2_EV_IRQn = 131, /*!< I3C2 Event interrupt */ + I3C2_ER_IRQn = 132, /*!< I3C2 Error interrupt */ + COMP_IRQn = 133, /*!< COMP1 COMP2 global interrupt */ + PLAY1_IRQn = 147, /*!< PLAY1 global non-secure interrupt */ + PLAY1_S_IRQn = 148, /*!< PLAY1 global secure interrupt */ + ADC3_IRQn = 149, /*!< ADC3 global interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + __IO uint32_t MISR; /*!< masked interrupt status register, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HRA[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[42]; /*!< HASH digest registers, Address offset: 0x310-0x3B4 */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2[23]; /*!< Reserved, 0x24 - 0x7C */ + __IO uint32_t EDBGRQ; /*!< Debug MCU EDBGRQ register, Address offset: 0x80 */ + uint32_t RESERVED3[30]; /*!< Reserved, 0x84 - 0xF8 */ + __IO uint32_t SR; /*!< Debug MCU SR register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug DBG_AUTH_HOST register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug DBG_AUTH_DEV register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug DBG_AUTH_ACK register, Address offset: 0x108 */ + uint32_t RESERVED4[945]; /*!< Reserved, 0x10C - 0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU Peripheral ID register 4, Address offset: 0xFD0 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xFD4 - 0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU Peripheral ID register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU Peripheral ID register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU Peripheral ID register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU Peripheral ID register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU Component ID register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU Component ID register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU Component ID register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU Component ID register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWJBTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + __IO uint32_t MACHWF3R; + uint32_t RESERVED11[53]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[4]; + uint32_t RESERVED14[3]; + __IO uint32_t MACCSRSWCR; + uint32_t RESERVED15[3]; + __IO uint32_t MACPRSTIMR; + __IO uint32_t MACPRSTIMUR; + uint32_t RESERVED16[46]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED17[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED18[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED19[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED20[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED21[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED22[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED23[41]; + __IO uint32_t MMCFPETISR; + __IO uint32_t MMCFPETIMR; + __IO uint32_t MMCFPETFCR; + __IO uint32_t MMCTHRCR; + uint32_t RESERVED24[4]; + __IO uint32_t MMCFPERISR; + __IO uint32_t MMCFPERIMR; + __IO uint32_t MMCRPAER; + __IO uint32_t MMCRPSMDER; + __IO uint32_t MMCRPAOKR; + __IO uint32_t MMCFPERFCR; + uint32_t RESERVED25[10]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED26[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED27[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED28[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED29[72]; + __IO uint32_t MACIACR; + __IO uint32_t MACTMRQR; + uint32_t RESERVED30[34]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED31; + __IO uint32_t MACTSSR; + __IO uint32_t MACRXDTI; + __IO uint32_t MACTXDTI; + uint32_t RESERVED32; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED33[2]; + __IO uint32_t MACACR; + uint32_t RESERVED34; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED35[2]; + __IO uint32_t MACTSILR; + __IO uint32_t MACTSELR; + __IO uint32_t MACPPSCR; + uint32_t RESERVED36[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED37[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED38[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED39[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED40[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED41[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED42[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED43[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED44[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED45; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED46; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; + uint32_t RESERVED47[2]; + __IO uint32_t DMACCATDR; + uint32_t RESERVED48; + __IO uint32_t DMACCARDR; + uint32_t RESERVED49; + __IO uint32_t DMACCATBR; + uint32_t RESERVED50; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; + __IO uint32_t DMACMFCR; +}ETH_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ + __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */ + __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x3C */ + __IO uint32_t RTSR3; /*!< EXTI Rising Trigger Selection Register 3, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling Trigger Selection Register 3, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software Interrupt event Register 3, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Pending Register 3, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Pending Register 3, Address offset: 0x50 */ + __IO uint32_t SECCFGR3; /*!< EXTI Security Configuration Register 3, Address offset: 0x54 */ + __IO uint32_t PRIVCFGR3; /*!< EXTI Privilege Configuration Register 3, Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved 3, Address offset: 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED4[3]; /*!< Reserved 4, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED5[2]; /*!< Reserved 5, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ + uint32_t RESERVED6[2]; /*!< Reserved 6, 0x98 -- 0x9C */ + __IO uint32_t IMR3; /*!< EXTI Interrupt Mask Register 3, Address offset: 0xA0 */ + __IO uint32_t EMR3; /*!< EXTI Event Mask Register 3, Address offset: 0xA4 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x04 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t NSOBKKEYR; /*!< FLASH non-secure option bytes keys key register, Address offset: 0x10 */ + __IO uint32_t SECOBKKEYR; /*!< FLASH secure option bytes keys key register, Address offset: 0x14 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x18 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, Address offset: 0x30 */ + __IO uint32_t SECCCR; /*!< FLASH secure clear control register, Address offset: 0x34 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x38 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x3C */ + __IO uint32_t NSOBKCFGR; /*!< FLASH non-secure option byte key configuration register, Address offset: 0x40 */ + __IO uint32_t SECOBKCFGR; /*!< FLASH secure option byte key configuration register, Address offset: 0x44 */ + __IO uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x4C */ + __IO uint32_t OPTSR_CUR; /*!< FLASH option status current register, Address offset: 0x50 */ + __IO uint32_t OPTSR_PRG; /*!< FLASH option status to program register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x58-0x5C */ + __IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, Address offset: 0x60 */ + __IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, Address offset: 0x64 */ + __IO uint32_t SECEPOCHR_CUR; /*!< FLASH secure epoch current register, Address offset: 0x68 */ + __IO uint32_t SECEPOCHR_PRG; /*!< FLASH secure epoch to program register, Address offset: 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< FLASH option status current register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< FLASH option status to program register 2, Address offset: 0x74 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x78-0x7C */ + __IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, Address offset: 0x80 */ + __IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, Address offset: 0x84 */ + __IO uint32_t SECBOOTR_CUR; /*!< FLASH secure unique boot entry current register, Address offset: 0x88 */ + __IO uint32_t SECBOOTR_PRG; /*!< FLASH secure unique boot entry to program register, Address offset: 0x8C */ + __IO uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock current register, Address offset: 0x90 */ + __IO uint32_t OTPBLR_PRG; /*!< FLASH OTP block Lock to program register, Address offset: 0x94 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x98-0x9C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0xA4 */ + uint32_t RESERVED6[6]; /*!< Reserved6, Address offset: 0xA8-0xBC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xC0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xC4 */ + uint32_t RESERVED7[6]; /*!< Reserved7, Address offset: 0xC8-0xDC */ + __IO uint32_t SECWM1R_CUR; /*!< FLASH secure watermark 1 current register, Address offset: 0xE0 */ + __IO uint32_t SECWM1R_PRG; /*!< FLASH secure watermark 1 to program register, Address offset: 0xE4 */ + __IO uint32_t WRP1R_CUR; /*!< FLASH write sector group protection current register for bank1, Address offset: 0xE8 */ + __IO uint32_t WRP1R_PRG; /*!< FLASH write sector group protection to program register for bank1, Address offset: 0xEC */ + __IO uint32_t EDATA1R_CUR; /*!< FLASH data sectors configuration current register for bank1, Address offset: 0xF0 */ + __IO uint32_t EDATA1R_PRG; /*!< FLASH data sectors configuration to program register for bank1, Address offset: 0xF4 */ + __IO uint32_t HDP1R_CUR; /*!< FLASH HDP configuration current register for bank1, Address offset: 0xF8 */ + __IO uint32_t HDP1R_PRG; /*!< FLASH HDP configuration to program register for bank1, Address offset: 0xFC */ + __IO uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IO uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IO uint32_t ECCDR; /*!< FLASH ECC data register, Address offset: 0x108 */ + uint32_t RESERVED8[37]; /*!< Reserved8, Address offset: 0x10C-0x19C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0x1A0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0x1A4 */ + uint32_t RESERVED9[6]; /*!< Reserved9, Address offset: 0x1A8-0x1BC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0x1C0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0x1C4 */ + uint32_t RESERVED10[6]; /*!< Reserved10, Address offset: 0x1C8-0x1DC */ + __IO uint32_t SECWM2R_CUR; /*!< FLASH secure watermark 2 current register, Address offset: 0x1E0 */ + __IO uint32_t SECWM2R_PRG; /*!< FLASH secure watermark 2 to program register, Address offset: 0x1E4 */ + __IO uint32_t WRP2R_CUR; /*!< FLASH write sector group protection current register for bank2, Address offset: 0x1E8 */ + __IO uint32_t WRP2R_PRG; /*!< FLASH write sector group protection to program register for bank2, Address offset: 0x1EC */ + __IO uint32_t EDATA2R_CUR; /*!< FLASH data sectors configuration current register for bank2, Address offset: 0x1F0 */ + __IO uint32_t EDATA2R_PRG; /*!< FLASH data sectors configuration to program register for bank2, Address offset: 0x1F4 */ + __IO uint32_t HDP2R_CUR; /*!< FLASH HDP configuration current register for bank2, Address offset: 0x1F8 */ + __IO uint32_t HDP2R_PRG; /*!< FLASH HDP configuration to program register for bank2, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + __IO uint32_t MPCWM3BCFGR; /*!< TZSC memory 3 sub-region B watermark configuration register, Address offset: 0x68 */ + __IO uint32_t MPCWM3BR; /*!< TZSC memory 3 sub-region B watermark register, Address offset: 0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + __IO uint32_t MPCWM4BCFGR; /*!< TZSC memory 4 sub-region B watermark configuration register, Address offset: 0x78 */ + __IO uint32_t MPCWM4BR; /*!< TZSC memory 4 sub-region B watermark register, Address offset: 0x7c */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x17C */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x1FC */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ +} COMPOPT_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR1; /*!< Comparator configuration register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR1_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CFGR1_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; +/** + * @brief OTFDEC register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ +} OTFDEC_Region_TypeDef; + + +typedef struct +{ + __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ + __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ + uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ + __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ + __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ + __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ +} OTFDEC_TypeDef; + + +/** + * @brief Coupling and chaining bridge (CCB) + */ +typedef struct +{ + __IO uint32_t CR; /*!< CCB ccontrol register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CCB status register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t REFTAGR[4]; /*!< CCB reference tag register, Address offset: 0x10 */ +} CCB_TypeDef; + +/** + * @brief Programmable Logic Array (PLAY) + */ +typedef struct +{ + __IO uint32_t CFGCR; /*!< PLAY Configuration Control Register, Address offset: 0x00 */ + __IO uint32_t SECCFGR; /*!< PLAY Security attributes Configuration Register, Address offset: 0x04 */ + __IO uint32_t PRIVCFGR; /*!< PLAY Privilege attributes Configuration Register, Address offset: 0x08 */ + uint32_t reserved1[5]; /*!< Reserved Address offset: 0x0C-0x18 */ + __IO uint32_t FILTCFG[16]; /*!< PLAY Filter Configuration Registers, Address offset: 0x20 */ + __IO uint32_t LECFG1[16]; /*!< PLAY Logic Element Configuration Registers 1, Address offset: 0x60 */ + __IO uint32_t LECFG2[16]; /*!< PLAY Logic Element Configuration Registers 2, Address offset: 0xA0 */ + uint32_t reserved2[8]; /*!< Reserved Address offset: 0xE0-0xFC */ + __IO uint32_t OUTCFG[16]; /*!< PLAY Output Configuration Registers, Address offset: 0x0100 */ + uint32_t reserved3[48]; /*!< Reserved Address offset: 0x0140-0x01FC */ + __IO uint32_t SWIN; /*!< PLAY Software Input Status Register, Address offset: 0x0200 */ + __IO uint32_t SWINSET; /*!< PLAY Software Input Set Register, Address offset: 0x0204 */ + __IO uint32_t SWINCLR; /*!< PLAY Software Input Clear Register, Address offset: 0x0208 */ + uint32_t reserved4; /*!< Reserved Address offset: 0x020C */ + __IO uint32_t OSR; /*!< PLAY Output Status Register, Address offset: 0x0210 */ + uint32_t reserved5[3]; /*!< Reserved Address offset: 0x0214-0x021C */ + __IO uint32_t FLSTAT; /*!< PLAY Flag Status Register, Address offset: 0x0220 */ + __IO uint32_t FLSET; /*!< PLAY Flag Set Register, Address offset: 0x0224 */ + __IO uint32_t FLCLR; /*!< PLAY Flag Clear Register, Address offset: 0x0228 */ + __IO uint32_t FLIER; /*!< PLAY Flag Interrupt Enable Register, Address offset: 0x022C */ + __IO uint32_t FLCTL; /*!< PLAY Flag Control Register, Address offset: 0x0230 */ + __IO uint32_t MSR; /*!< PLAY Miscellaneous Status Register, Address offset: 0x0234 */ + __IO uint32_t ISR; /*!< PLAY Interrupt Status Register, Address offset: 0x0238 */ + __IO uint32_t ICR; /*!< PLAY Interrupt Clear Register, Address offset: 0x023C */ + __IO uint32_t IER; /*!< PLAY Interrupt Enable Register, Address offset: 0x0240 */ +} PLAY_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t PMCR; /*!< Power mode control register , Address offset: 0x00 */ + __IO uint32_t PMSR; /*!< Power mode status register , Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t VOSCR; /*!< Voltage scaling control register , Address offset: 0x10 */ + __IO uint32_t VOSSR; /*!< Voltage sacling status register , Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t BDCR; /*!< BacKup domain control register , Address offset: 0x20 */ + __IO uint32_t DBPCR; /*!< DBP control register, Address offset: 0x24 */ + __IO uint32_t BDSR; /*!< BacKup domain status register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Usb typeC and Power Delivery Register, Address offset: 0x2C */ + __IO uint32_t SCCR; /*!< Supply configuration control register, Address offset: 0x30 */ + __IO uint32_t VMCR; /*!< Voltage Monitor Control Register, Address offset: 0x34 */ + __IO uint32_t USBSCR; /*!< USB Supply Control Register Address offset: 0x38 */ + __IO uint32_t VMSR; /*!< Status Register Voltage Monitoring, Address offset: 0x3C */ + __IO uint32_t WUSCR; /*!< WakeUP status clear register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< WakeUP status Register, Address offset: 0x44 */ + __IO uint32_t WUCR; /*!< WakeUP configuration register, Address offset: 0x48 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t IORETR; /*!< IO RETention Register, Address offset: 0x50 */ + uint32_t RESERVED4[43];/*!< Reserved, Address offset: 0x54-0xFC */ + __IO uint32_t SECCFGR; /*!< Security configuration register, Address offset: 0x100 */ + __IO uint32_t PRIVCFGR; /*!< Privilege configuration register, Address offset: 0x104 */ +}PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + __IO uint32_t WPR3; /*!< SRAM Write Protection Register 3, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t HSICFGR; /*!< RCC HSI Clock Calibration Register, Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x14 */ + __IO uint32_t CSICFGR; /*!< RCC CSI Clock Calibration Register, Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register Address offset: 0x2C */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x44 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 Peripherals Reset Register Address offset: 0x64 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x68 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 Peripherals reset Low Word register Address offset: 0x74 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 Peripherals reset High Word register Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED10; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 Peripherals Clock Enable Register Address offset: 0x8C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x90 */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 Peripherals clock Enable Low Word register Address offset: 0x9C */ + __IO uint32_t APB1HENR; /*!< RCC APB1 Peripherals clock Enable High Word register Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 Peripheral sleep clock Register Address offset: 0xB0 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 Peripheral sleep clock Register Address offset: 0xB4 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0xB8 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 Peripherals sleep clock Register Address offset: 0xBC */ + uint32_t RESERVED17; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 Peripherals sleep clock Low Word Register Address offset: 0xC4 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 Peripherals sleep clock High Word Register Address offset: 0xC8 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 Peripherals sleep clock Register Address offset: 0xCC */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 Peripherals Clock Low Power Enable Register Address offset: 0xD0 */ + uint32_t RESERVED18; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t CCIPR1; /*!< RCC IPs Clocks Configuration Register 1 Address offset: 0xD8 */ + __IO uint32_t CCIPR2; /*!< RCC IPs Clocks Configuration Register 2 Address offset: 0xDC */ + __IO uint32_t CCIPR3; /*!< RCC IPs Clocks Configuration Register 3 Address offset: 0xE0 */ + __IO uint32_t CCIPR4; /*!< RCC IPs Clocks Configuration Register 4 Address offset: 0xE4 */ + __IO uint32_t CCIPR5; /*!< RCC IPs Clocks Configuration Register 5 Address offset: 0xE8 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< RCC VSW Backup Domain & V33 Domain Control Register Address offset: 0xF0 */ + __IO uint32_t RSR; /*!< RCC Reset status Register Address offset: 0xF4 */ + uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC Secure mode configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x64 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */ + __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; +/** + * @brief System configuration, Boot and Security + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */ + __IO uint32_t HDPLCR; /*!< SBS HDPL Control Register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS HDPL Status Register, Address offset: 0x14 */ + __IO uint32_t NEXTHDPLCR; /*!< NEXT HDPL Control Register, Address offset: 0x18 */ + __IO uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control Register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock Register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */ + __IO uint32_t RSSCMDR; /*!< SBS RSS Command Register, Address offset: 0x34 */ + uint32_t RESERVED4[26]; /*!< RESERVED4, Address offset: 0x38 - 0x9C */ + __IO uint32_t EPOCHSELCR; /*!< EPOCH Selection Register, Address offset: 0xA0 */ + uint32_t RESERVED5[7]; /*!< RESERVED5, Address offset: 0xA4 - 0xBC */ + __IO uint32_t SECCFGR; /*!< SBS Security Mode Configuration, Address offset: 0xC0 */ + uint32_t RESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config Register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask Register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status Register, Address offset: 0x108 */ + uint32_t RESERVED7; /*!< RESERVED7, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS Compensation Cell Control & Status Register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS Compensation Cell Value Register, Address offset: 0x114 */ + __IO uint32_t CCSWCR; /*!< SBS Compensation Cell for I/Os sw code Register, Address offset: 0x118 */ + __IO uint32_t RESERVED8; /*!< RESERVED8, Address offset: 0x11C */ + __IO uint32_t CFGR2; /*!< SBS Class B Register, Address offset: 0x120 */ + uint32_t RESERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */ + __IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset: 0x144 */ + __IO uint32_t CSLCKR; /*!< SBS CPU Secure Lock Register, Address offset: 0x148 */ + __IO uint32_t ECCNMIR; /*!< SBS FLITF ECC NMI MASK Register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ + + +#define SRAM1_SIZE (0x20000UL) /*!< SRAM1=128k */ +#define SRAM2_SIZE (0x14000UL) /*!< SRAM2=80k */ +#define SRAM3_SIZE (0x18000UL) /*!< SRAM3=96k */ +#define BKPSRAM_SIZE (0x00800UL) /*!< BKPSRAM=2k */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 1 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (128 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20020000UL) /*!< SRAM2 (80 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x20034000UL) /*!< SRAM3 (96 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) /*!< FMC Memory Bank1 for SRAM, NOR and PSRAM */ +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< FMC Memory Bank3 for NAND */ +#define FMC_SDRAM_BANK_1 (FMC_BASE + 0x60000000UL) /*!< FMC Memory SDRAM Bank1 */ +#define FMC_SDRAM_BANK_2 (FMC_BASE + 0x70000000UL) /*!< FMC Memory SDRAM Bank2 */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) +#define COMP12_BASE_NS (APB1PERIPH_BASE_NS + 0x4000UL) +#define COMP1_BASE_NS (COMP12_BASE_NS + 0x0CUL) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x10UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define CEC_BASE_NS (APB1PERIPH_BASE_NS + 0x7000UL) +#define UART7_BASE_NS (APB1PERIPH_BASE_NS + 0x7800UL) +#define UART8_BASE_NS (APB1PERIPH_BASE_NS + 0x7C00UL) +#define DTS_BASE_NS (APB1PERIPH_BASE_NS + 0x8C00UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x6000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x6400UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define GPDMA2_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03800UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ETH_BASE_NS (AHB1PERIPH_BASE_NS + 0x8000UL) +#define ETH_MAC_BASE_NS (ETH_BASE) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA2_Channel0_BASE_NS (GPDMA2_BASE_NS + 0x0050UL) +#define GPDMA2_Channel1_BASE_NS (GPDMA2_BASE_NS + 0x00D0UL) +#define GPDMA2_Channel2_BASE_NS (GPDMA2_BASE_NS + 0x0150UL) +#define GPDMA2_Channel3_BASE_NS (GPDMA2_BASE_NS + 0x01D0UL) +#define GPDMA2_Channel4_BASE_NS (GPDMA2_BASE_NS + 0x0250UL) +#define GPDMA2_Channel5_BASE_NS (GPDMA2_BASE_NS + 0x02D0UL) +#define GPDMA2_Channel6_BASE_NS (GPDMA2_BASE_NS + 0x0350UL) +#define GPDMA2_Channel7_BASE_NS (GPDMA2_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define ADC3_BASE_NS (AHB2PERIPH_BASE_NS + 0x0D800UL) +#define ADC3_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x0DB00UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) +#define CCB_BASE_NS (AHB2PERIPH_BASE_NS + 0xA7C00UL) + +/*!< APB3 Non secure peripherals */ +#define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define I3C2_BASE_NS (APB3PERIPH_BASE_NS + 0x3000UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) +#define PLAY1_BASE_NS (APB3PERIPH_BASE_NS + 0x8000UL) + +/*!< AHB3 Non secure peripherals */ +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define DEBUG_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) + +/*!< AHB4 Non secure peripherals */ +#define OTFDEC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x5000UL) +#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) +#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) +#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) +#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) +#define SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8400UL) +#define FMC_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_NS (AHB4PERIPH_BASE_NS + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define FMC_Bank5_6_R_BASE_NS (FMC_R_BASE_NS + 0x0140UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 1 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (128 KB) secure base address */ +#define SRAM2_BASE_S (0x30020000UL) /*!< SRAM2 (80 KB) secure base address */ +#define SRAM3_BASE_S (0x30034000UL) /*!< SRAM3 (96 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) + +/*!< APB1 secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) +#define COMP12_BASE_S (APB1PERIPH_BASE_S + 0x4000UL) +#define COMP1_BASE_S (COMP12_BASE_S + 0x0CUL) +#define COMP2_BASE_S (COMP12_BASE_S + 0x10UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define CEC_BASE_S (APB1PERIPH_BASE_S + 0x7000UL) +#define UART7_BASE_S (APB1PERIPH_BASE_S + 0x7800UL) +#define UART8_BASE_S (APB1PERIPH_BASE_S + 0x7C00UL) +#define DTS_BASE_S (APB1PERIPH_BASE_S + 0x8C00UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA800UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x6000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x6400UL) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_BASE_S AHB1PERIPH_BASE_S +#define GPDMA2_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x03800UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define ETH_BASE_S (AHB1PERIPH_BASE_S + 0x8000UL) +#define ETH_MAC_BASE_S (ETH_BASE_S) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA2_Channel0_BASE_S (GPDMA2_BASE_S + 0x0050UL) +#define GPDMA2_Channel1_BASE_S (GPDMA2_BASE_S + 0x00D0UL) +#define GPDMA2_Channel2_BASE_S (GPDMA2_BASE_S + 0x0150UL) +#define GPDMA2_Channel3_BASE_S (GPDMA2_BASE_S + 0x01D0UL) +#define GPDMA2_Channel4_BASE_S (GPDMA2_BASE_S + 0x0250UL) +#define GPDMA2_Channel5_BASE_S (GPDMA2_BASE_S + 0x02D0UL) +#define GPDMA2_Channel6_BASE_S (GPDMA2_BASE_S + 0x0350UL) +#define GPDMA2_Channel7_BASE_S (GPDMA2_BASE_S + 0x03D0UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) + +/*!< AHB2 secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x08400UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define ADC3_BASE_S (AHB2PERIPH_BASE_S + 0x0D800UL) +#define ADC3_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x0DB00UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) +#define CCB_BASE_S (AHB2PERIPH_BASE_S + 0xA7C00UL) + +/*!< APB3 secure peripherals */ +#define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define I3C2_BASE_S (APB3PERIPH_BASE_S + 0x3000UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) +#define PLAY1_BASE_S (APB3PERIPH_BASE_S + 0x8000UL) + +/*!< AHB3 secure peripherals */ +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define DEBUG_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) + +/*!< AHB4 secure peripherals */ +#define OTFDEC1_BASE_S (AHB4PERIPH_BASE_S + 0x5000UL) +#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) +#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) +#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) +#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) +#define SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) +#define DLYB_SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8400UL) +#define FMC_R_BASE_S (AHB4PERIPH_BASE_S + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_S (AHB4PERIPH_BASE_S + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_S (AHB4PERIPH_BASE_S + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define FMC_Bank5_6_R_BASE_S (FMC_R_BASE_S + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x44024000UL) +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ +#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */ + +/* Flash system Area */ +#define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */ +#define FLASH_SYSTEM_BASE_S (0x0FF80000UL) /*!< FLASH System secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes system Flash */ + +/* Internal Flash EDATA Area */ +#define FLASH_EDATA_BASE_NS (0x09000000UL) /*!< FLASH high-cycle data non-secure base address */ +#define FLASH_EDATA_BASE_S (0x0D000000UL) /*!< FLASH high-cycle data secure base address */ +#define FLASH_EDATA_SIZE (0x18000U) /*!< 96 KB of Flash high-cycle data */ + +/* Internal Flash OBK Area */ +#define FLASH_OBK_BASE_NS (0x0BFD0000UL) /*!< FLASH OBK (option byte keys) non-secure base address */ +#define FLASH_OBK_BASE_S (0x0FFD0000UL) /*!< FLASH OBK (option byte keys) secure base address */ +#define FLASH_OBK_SIZE (0x2000U) /*!< 8 KB of option byte keys */ +#define FLASH_OBK_HDPL0_SIZE (0x100U) /*!< 256 Bytes of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL1_BASE_NS (FLASH_OBK_BASE_NS + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 non-secure base address */ +#define FLASH_OBK_HDPL1_BASE_S (FLASH_OBK_BASE_S + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 secure base address */ +#define FLASH_OBK_HDPL1_SIZE (0x800U) /*!< 2 KB of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL2_BASE_NS (FLASH_OBK_HDPL1_BASE_NS + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 non-secure base address */ +#define FLASH_OBK_HDPL2_BASE_S (FLASH_OBK_HDPL1_BASE_S + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 secure base address */ +#define FLASH_OBK_HDPL2_SIZE (0x300U) /*!< 768 Bytes of HDPL2 option byte keys */ + +#define FLASH_OBK_HDPL3_BASE_NS (FLASH_OBK_HDPL2_BASE_NS + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3_BASE_S (FLASH_OBK_HDPL2_BASE_S + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3_SIZE (0x13F0U) /*!< 5104 Bytes HDPL3 option byte keys */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_OBK_HDPL3S_BASE_NS (FLASH_OBK_HDPL3_BASE_NS) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3S_BASE_S (FLASH_OBK_HDPL3_BASE_S) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3S_SIZE (0x0C00U) /*!< 3072 Bytes of secure HDPL3 option byte keys */ + +#define FLASH_OBK_HDPL3NS_BASE_NS (FLASH_OBK_HDPL3_BASE_NS + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3NS_BASE_S (FLASH_OBK_HDPL3_BASE_S + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */ +#endif /* CMSE */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BFAE068UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BFAE084UL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0x0BFAE068UL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it jumps to the non-secure reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3NS_TypeDef)(uint32_t VectorTableAddr); + +/** + * @brief Input parameter definition of RSSLIB_DataProvisioning + */ +typedef struct +{ + uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ + uint32_t *pDestination; /*!< Address in OBKeys sections where to provision Data */ + uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ + uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ + uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ +} RSSLIB_DataProvisioningConf_t; + +/** + * @brief Prototype of RSSLIB Data Provisioning Function + * @detail This function write Data within OBKeys sections. + * @param pointer on the structure defining Data to be provisioned and where to + * provision them within OBKeys sections. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_NSC_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); + + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM RSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; + __IM RSSLIB_S_JumpHDPlvl3NS_TypeDef JumpHDPLvl3NS; +} S_pFuncTypeDef; + +/** + * @brief RSSLib Non-secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_NSC_DataProvisioning_TypeDef DataProvisioning; +} NSC_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + uint32_t RESERVED1[3]; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/*!< Non Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define NSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BFAE06CUL) +#define NSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BFAE074UL) + +/************ RSSLIB function return constants ********************************/ +#define NSSLIB_ERROR (0xF5F5F5F5UL) +#define NSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define NSSLIB_PFUNC_BASE (0x0BFAE06CUL) +#define NSSLIB_PFUNC ((NSSLIB_pFunc_TypeDef *)NSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM NSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; +} NSSLIB_pFunc_TypeDef; + +/* + * Certificate address description + */ +#define CERT_CHIP_PACK1_ADDR (0x0BFAFE00U) +#define CERT_CHIP_PACK1_SIZE (0x200U) +#define CERT_CHIP_PACK2_ADDR (0x0BFAFC00U) +#define CERT_CHIP_PACK2_SIZE (0x200U) + +#define CERT_CHIP_PACK_ADDR (CERT_CHIP_PACK2_ADDR) +#define CERT_CHIP_PACK_SIZE (CERT_CHIP_PACK1_SIZE + CERT_CHIP_PACK2_SIZE) + +#define CERT_ST_DUA_INIT_ATTEST_PUB_KEY_OFFSET (152U) +#define CERT_ST_DUA_INIT_ATTEST_PUB_KEY_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_PUB_KEY_OFFSET) +#define CERT_ST_DUA_INIT_ATTEST_SIGN_OFFSET (216U) +#define CERT_ST_DUA_INIT_ATTEST_SIGN_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_SIGN_OFFSET) +#define CERT_ST_DUA_INIT_ATTEST_SERIAL_OFFSET (484U) +#define CERT_ST_DUA_INIT_ATTEST_SERIAL_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_SERIAL_OFFSET) + +#define CERT_ST_DUA_USER_PUB_KEY_OFFSET (12U) +#define CERT_ST_DUA_USER_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_PUB_KEY_OFFSET) +#define CERT_ST_DUA_USER_SIGN_OFFSET (76U) +#define CERT_ST_DUA_USER_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_SIGN_OFFSET) +#define CERT_ST_DUA_USER_SERIAL_OFFSET (140U) +#define CERT_ST_DUA_USER_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_SERIAL_OFFSET) + +/** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *)TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *)TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *)TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *)TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *)TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *)TIM7_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *)TIM12_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *)WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *)IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *)SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *)SPI3_BASE_NS) +#define COMP12_NS ((COMPOPT_TypeDef *)COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *)COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *)COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define USART2_NS ((USART_TypeDef *)USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *)USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *)UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *)UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *)I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *)I2C2_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *)I3C1_BASE_NS) +#define CRS_NS ((CRS_TypeDef *)CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *)USART6_BASE_NS) +#define CEC_NS ((CEC_TypeDef *)CEC_BASE_NS) +#define UART7_NS ((USART_TypeDef *)UART7_BASE_NS) +#define UART8_NS ((USART_TypeDef *)UART8_BASE_NS) +#define DTS_NS ((DTS_TypeDef *)DTS_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *)LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_NS) +#define FDCAN2_NS ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *)UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA2_NS ((DMA_TypeDef *) GPDMA2_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define ETH_NS ((ETH_TypeDef *) ETH_BASE_NS) +#define ETH_MAC_NS ((ETH_TypeDef *) ETH_MAC_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA2_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_NS) +#define GPDMA2_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_NS) +#define GPDMA2_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_NS) +#define GPDMA2_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_NS) +#define GPDMA2_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_NS) +#define GPDMA2_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_NS) +#define GPDMA2_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_NS) +#define GPDMA2_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define ADC3_NS ((ADC_TypeDef *) ADC3_BASE_NS) +#define ADC3_COMMON_NS ((ADC_Common_TypeDef *) ADC3_COMMON_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define CCB_NS ((CCB_TypeDef *) CCB_BASE_NS) + + +/*!< APB3 Non secure peripherals */ +#define SBS_NS ((SBS_TypeDef *) SBS_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) +#define PLAY1_NS ((PLAY_TypeDef *) PLAY1_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) + +/*!< AHB4 Non secure peripherals */ +#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) +#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) +#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) +#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) +#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) + +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define FMC_Bank5_6_R_NS ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *)TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *)TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *)TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *)TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *)TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *)TIM7_BASE_S) +#define TIM12_S ((TIM_TypeDef *)TIM12_BASE_S) +#define WWDG_S ((WWDG_TypeDef *)WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *)IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *)SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *)SPI3_BASE_S) +#define COMP12_S ((COMPOPT_TypeDef *)COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *)COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *)COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define USART2_S ((USART_TypeDef *)USART2_BASE_S) +#define USART3_S ((USART_TypeDef *)USART3_BASE_S) +#define UART4_S ((USART_TypeDef *)UART4_BASE_S) +#define UART5_S ((USART_TypeDef *)UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *)I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *)I2C2_BASE_S) +#define I3C1_S ((I3C_TypeDef *)I3C1_BASE_S) +#define CRS_S ((CRS_TypeDef *)CRS_BASE_S) +#define USART6_S ((USART_TypeDef *)USART6_BASE_S) +#define CEC_S ((CEC_TypeDef *)CEC_BASE_S) +#define UART7_S ((USART_TypeDef *)UART7_BASE_S) +#define UART8_S ((USART_TypeDef *)UART8_BASE_S) +#define DTS_S ((DTS_TypeDef *)DTS_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *)LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_S) +#define FDCAN2_S ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *)UCPD1_BASE_S) + +/*!< APB2 secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *)USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA2_S ((DMA_TypeDef *) GPDMA2_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define ETH_S ((ETH_TypeDef *) ETH_BASE_S) +#define ETH_MAC_S ((ETH_TypeDef *) ETH_MAC_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA2_Channel0_S ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_S) +#define GPDMA2_Channel1_S ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_S) +#define GPDMA2_Channel2_S ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_S) +#define GPDMA2_Channel3_S ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_S) +#define GPDMA2_Channel4_S ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_S) +#define GPDMA2_Channel5_S ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_S) +#define GPDMA2_Channel6_S ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_S) +#define GPDMA2_Channel7_S ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_S) + + +/*!< AHB2 secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define CCB_S ((CCB_TypeDef *) CCB_BASE_S) +#define ADC3_S ((ADC_TypeDef *) ADC3_BASE_S) +#define ADC3_COMMON_S ((ADC_Common_TypeDef *) ADC3_COMMON_BASE_S) + +/*!< APB3 secure peripherals */ +#define SBS_S ((SBS_TypeDef *) SBS_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) +#define PLAY1_S ((PLAY_TypeDef *) PLAY1_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) + +/*!< AHB4 secure peripherals */ +#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) +#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) +#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) +#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) +#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) + +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define FMC_Bank5_6_R_S ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S) + +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define FLASH_OBK_BASE FLASH_OBK_BASE_S +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_S +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define APB3PERIPH_BASE APB3PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_S +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + + +#define DTS DTS_S +#define DTS_BASE DTS_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA2 GPDMA2_S +#define GPDMA2_BASE GPDMA2_BASE_S + +#define GPDMA2_Channel0 GPDMA2_Channel0_S +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_S + +#define GPDMA2_Channel1 GPDMA2_Channel1_S +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_S + +#define GPDMA2_Channel2 GPDMA2_Channel2_S +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_S + +#define GPDMA2_Channel3 GPDMA2_Channel3_S +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_S + +#define GPDMA2_Channel4 GPDMA2_Channel4_S +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_S + +#define GPDMA2_Channel5 GPDMA2_Channel5_S +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_S + +#define GPDMA2_Channel6 GPDMA2_Channel6_S +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_S + +#define GPDMA2_Channel7 GPDMA2_Channel7_S +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define SPI4 SPI4_S +#define SPI4_BASE SPI4_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define UART7 UART7_S +#define UART7_BASE UART7_BASE_S + +#define UART8 UART8_S +#define UART8_BASE UART8_BASE_S + +#define CEC CEC_S +#define CEC_BASE CEC_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S + +#define I3C2 I3C2_S +#define I3C2_BASE I3C2_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define FDCAN2 FDCAN2_S +#define FDCAN2_BASE FDCAN2_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SBS SBS_S +#define SBS_BASE SBS_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + +#define ADC3 ADC3_S +#define ADC3_BASE ADC3_BASE_S + +#define ADC3_COMMON ADC3_COMMON_S +#define ADC3_COMMON_BASE ADC3_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define AES AES_S +#define AES_BASE AES_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S +#define CCB CCB_S +#define CCB_BASE CCB_BASE_S + +#define OTFDEC1 OTFDEC1_S +#define OTFDEC1_BASE OTFDEC1_BASE_S + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_S +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_S +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_S +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_S +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S + + +#define ETH ETH_S +#define ETH_BASE ETH_BASE_S +#define ETH_MAC ETH_MAC_S +#define ETH_MAC_BASE ETH_MAC_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define FMC_Bank5_6_R FMC_Bank5_6_R_S +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S + +#define PLAY1 PLAY1_S +#define PLAY1_BASE PLAY1_BASE_S + +#else + +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define FLASH_OBK_BASE FLASH_OBK_BASE_NS +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_NS +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_NS + +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS + +#define SRAM3_BASE SRAM3_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS + +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define APB3PERIPH_BASE APB3PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_NS +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + + +#define DTS DTS_NS +#define DTS_BASE DTS_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA2 GPDMA2_NS +#define GPDMA2_BASE GPDMA2_BASE_NS + +#define GPDMA2_Channel0 GPDMA2_Channel0_NS +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_NS + +#define GPDMA2_Channel1 GPDMA2_Channel1_NS +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_NS + +#define GPDMA2_Channel2 GPDMA2_Channel2_NS +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_NS + +#define GPDMA2_Channel3 GPDMA2_Channel3_NS +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_NS + +#define GPDMA2_Channel4 GPDMA2_Channel4_NS +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_NS + +#define GPDMA2_Channel5 GPDMA2_Channel5_NS +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_NS + +#define GPDMA2_Channel6 GPDMA2_Channel6_NS +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_NS + +#define GPDMA2_Channel7 GPDMA2_Channel7_NS +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define SPI4 SPI4_NS +#define SPI4_BASE SPI4_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define UART7 UART7_NS +#define UART7_BASE UART7_BASE_NS + +#define UART8 UART8_NS +#define UART8_BASE UART8_BASE_NS + +#define CEC CEC_NS +#define CEC_BASE CEC_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS + +#define I3C2 I3C2_NS +#define I3C2_BASE I3C2_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define FDCAN2 FDCAN2_NS +#define FDCAN2_BASE FDCAN2_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SBS SBS_NS +#define SBS_BASE SBS_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define AES AES_NS +#define AES_BASE AES_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + +#define CCB CCB_NS +#define CCB_BASE CCB_BASE_NS + +#define OTFDEC1 OTFDEC1_NS +#define OTFDEC1_BASE OTFDEC1_BASE_NS + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS + + +#define ETH ETH_NS +#define ETH_BASE ETH_BASE_NS +#define ETH_MAC ETH_MAC_NS +#define ETH_MAC_BASE ETH_MAC_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define FMC_Bank5_6_R FMC_Bank5_6_R_NS +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define ADC3 ADC3_NS +#define ADC3_BASE ADC3_BASE_NS + +#define ADC3_COMMON ADC3_COMMON_NS +#define ADC3_COMMON_BASE ADC3_COMMON_BASE_NS + +#define PLAY1 PLAY1_NS +#define PLAY1_BASE PLAY1_BASE_NS +#endif + + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP18_Msk /*!< ADC channel 19 sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register *****************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x01UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC Option bit 0 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/**********************************************************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/**********************************************************************************************************************/ +#define COMP_WINDOW_MODE_SUPPORT /*!< COMP feature available only on specific devices */ + + +/********************************** Bit definition for COMP_SR register *****************************************/ +#define COMP_SR_C1VAL_Pos (0U) +#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */ +#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk + +#define COMP_SR_C2VAL_Pos (1U) +#define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos) /*!< 0x00000002 */ +#define COMP_SR_C2VAL COMP_SR_C2VAL_Msk + +#define COMP_SR_C1IF_Pos (16U) +#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */ +#define COMP_SR_C1IF COMP_SR_C1IF_Msk + +#define COMP_SR_C2IF_Pos (17U) +#define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos) /*!< 0x00020000 */ +#define COMP_SR_C2IF COMP_SR_C2IF_Msk + +/********************************** Bit definition for COMP_ICFR register *****************************************/ +#define COMP_ICFR_CC1IF_Pos (16U) +#define COMP_ICFR_CC1IF_Msk (0x1UL << COMP_ICFR_CC1IF_Pos) /*!< 0x00010000 */ +#define COMP_ICFR_CC1IF COMP_ICFR_CC1IF_Msk + +#define COMP_ICFR_CC2IF_Pos (17U) +#define COMP_ICFR_CC2IF_Msk (0x1UL << COMP_ICFR_CC2IF_Pos) /*!< 0x00020000 */ +#define COMP_ICFR_CC2IF COMP_ICFR_CC2IF_Msk + +/********************************** Bit definition for COMP_CFGR1 register **************************************/ +#define COMP_CFGR1_EN_Pos (0U) +#define COMP_CFGR1_EN_Msk (0x1UL << COMP_CFGR1_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR1_EN COMP_CFGR1_EN_Msk /*!< COMP1 enable bit */ + +#define COMP_CFGR1_BRGEN_Pos (1U) +#define COMP_CFGR1_BRGEN_Msk (0x1UL << COMP_CFGR1_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR1_BRGEN COMP_CFGR1_BRGEN_Msk /*!< COMP1 Scaler bridge enable */ + +#define COMP_CFGR1_SCALEN_Pos (2U) +#define COMP_CFGR1_SCALEN_Msk (0x1UL << COMP_CFGR1_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR1_SCALEN COMP_CFGR1_SCALEN_Msk /*!< COMP1 Voltage scaler enable bit */ + +#define COMP_CFGR1_POLARITY_Pos (3U) +#define COMP_CFGR1_POLARITY_Msk (0x1UL << COMP_CFGR1_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR1_POLARITY COMP_CFGR1_POLARITY_Msk /*!< COMP1 polarity selection bit */ + +#define COMP_CFGR1_WINMODE_Pos (4U) +#define COMP_CFGR1_WINMODE_Msk (0x1UL << COMP_CFGR1_WINMODE_Pos) /*!< 0x00000010 */ +#define COMP_CFGR1_WINMODE COMP_CFGR1_WINMODE_Msk /*!< COMP1 window mode selection bit */ + +#define COMP_CFGR1_ITEN_Pos (6U) +#define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< COMP1 interrupt enable */ + +#define COMP_CFGR1_HYST_Pos (8U) +#define COMP_CFGR1_HYST_Msk (0x3UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR1_HYST COMP_CFGR1_HYST_Msk /*!< COMP1 hysteresis selection bits */ +#define COMP_CFGR1_HYST_0 (0x1UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR1_HYST_1 (0x2UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR1_PWRMODE_Pos (12U) +#define COMP_CFGR1_PWRMODE_Msk (0x3UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR1_PWRMODE COMP_CFGR1_PWRMODE_Msk /*!< COMP1 Power Mode of the comparator */ +#define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR1_WINOUT_Pos (14U) +#define COMP_CFGR1_WINOUT_Msk (0x1UL << COMP_CFGR1_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CFGR1_WINOUT COMP_CFGR1_WINOUT_Msk /*!< COMP1 window output selection bit */ + +#define COMP_CFGR1_INMSEL_Pos (16U) +#define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< COMP1 input minus selection bit */ +#define COMP_CFGR1_INMSEL_0 (0x1UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR1_INMSEL_1 (0x2UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR1_INMSEL_2 (0x4UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR1_INMSEL_3 (0x8UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR1_INPSEL_Pos (20U) +#define COMP_CFGR1_INPSEL_Msk (0x5UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00500000 */ +#define COMP_CFGR1_INPSEL COMP_CFGR1_INPSEL_Msk /*!< COMP1 input plus 0 selection bit */ + +#define COMP_CFGR1_INPSEL0_Pos (20U) +#define COMP_CFGR1_INPSEL0_Msk (0x1UL << COMP_CFGR1_INPSEL0_Pos) /*!< 0x00100000 */ +#define COMP_CFGR1_INPSEL0 COMP_CFGR1_INPSEL0_Msk /*!< COMP1 input plus 0 selection bit */ + +#define COMP_CFGR1_INPSEL1_Pos (22U) +#define COMP_CFGR1_INPSEL1_Msk (0x1UL << COMP_CFGR1_INPSEL1_Pos) /*!< 0x00400000 */ +#define COMP_CFGR1_INPSEL1 COMP_CFGR1_INPSEL1_Msk /*!< COMP1 input plus 1 selection bit */ + +#define COMP_CFGR1_BLANKING_Pos (24U) +#define COMP_CFGR1_BLANKING_Msk (0xFUL << COMP_CFGR1_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR1_BLANKING COMP_CFGR1_BLANKING_Msk /*!< COMP1 blanking source selection bits */ +#define COMP_CFGR1_BLANKING_0 (0x1UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR1_BLANKING_1 (0x2UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR1_BLANKING_2 (0x4UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR1_BLANKING_3 (0x8UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR1_LOCK_Pos (31U) +#define COMP_CFGR1_LOCK_Msk (0x1UL << COMP_CFGR1_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR1_LOCK COMP_CFGR1_LOCK_Msk /*!< COMP1 Lock Bit */ + +/********************************* Bit definition for COMP_CFGR2 register *******************************************/ +#define COMP_CFGR2_EN_Pos (0U) +#define COMP_CFGR2_EN_Msk (0x1UL << COMP_CFGR2_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR2_EN COMP_CFGR2_EN_Msk /*!< COMP1 enable bit */ + +#define COMP_CFGR2_BRGEN_Pos (1U) +#define COMP_CFGR2_BRGEN_Msk (0x1UL << COMP_CFGR2_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR2_BRGEN COMP_CFGR2_BRGEN_Msk /*!< COMP1 Scaler bridge enable */ + +#define COMP_CFGR2_SCALEN_Pos (2U) +#define COMP_CFGR2_SCALEN_Msk (0x1UL << COMP_CFGR2_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR2_SCALEN COMP_CFGR2_SCALEN_Msk /*!< COMP1 Voltage scaler enable bit */ + +#define COMP_CFGR2_POLARITY_Pos (3U) +#define COMP_CFGR2_POLARITY_Msk (0x1UL << COMP_CFGR2_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR2_POLARITY COMP_CFGR2_POLARITY_Msk /*!< COMP1 polarity selection bit */ +#define COMP_CFGR2_WINMODE_Pos (4U) +#define COMP_CFGR2_WINMODE_Msk (0x1UL << COMP_CFGR2_WINMODE_Pos) /*!< 0x00000010 */ +#define COMP_CFGR2_WINMODE COMP_CFGR2_WINMODE_Msk /*!< COMP1 window mode selection bit */ + + +#define COMP_CFGR2_ITEN_Pos (6U) +#define COMP_CFGR2_ITEN_Msk (0x1UL << COMP_CFGR2_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR2_ITEN COMP_CFGR2_ITEN_Msk /*!< COMP1 interrupt enable */ + +#define COMP_CFGR2_HYST_Pos (8U) +#define COMP_CFGR2_HYST_Msk (0x3UL << COMP_CFGR2_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR2_HYST COMP_CFGR2_HYST_Msk /*!< COMP1 hysteresis selection bits */ +#define COMP_CFGR2_HYST_0 (0x1UL << COMP_CFGR2_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR2_HYST_1 (0x2UL << COMP_CFGR2_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR2_PWRMODE_Pos (12U) +#define COMP_CFGR2_PWRMODE_Msk (0x3UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR2_PWRMODE COMP_CFGR2_PWRMODE_Msk /*!< COMP1 Power Mode of the comparator */ +#define COMP_CFGR2_PWRMODE_0 (0x1UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR2_PWRMODE_1 (0x2UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR2_WINOUT_Pos (14U) +#define COMP_CFGR2_WINOUT_Msk (0x1UL << COMP_CFGR2_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CFGR2_WINOUT COMP_CFGR2_WINOUT_Msk /*!< COMP1 window output selection bit */ + +#define COMP_CFGR2_INMSEL_Pos (16U) +#define COMP_CFGR2_INMSEL_Msk (0xFUL << COMP_CFGR2_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR2_INMSEL COMP_CFGR2_INMSEL_Msk /*!< COMP1 input minus selection bit */ +#define COMP_CFGR2_INMSEL_0 (0x1UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR2_INMSEL_1 (0x2UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR2_INMSEL_2 (0x4UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR2_INMSEL_3 (0x8UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR2_INPSEL0_Pos (20U) +#define COMP_CFGR2_INPSEL0_Msk (0x1UL << COMP_CFGR2_INPSEL0_Pos) /*!< 0x00100000 */ +#define COMP_CFGR2_INPSEL0 COMP_CFGR2_INPSEL0_Msk /*!< COMP1 input plus 0 selection bit */ + +#define COMP_CFGR2_INPSEL1_Pos (22U) +#define COMP_CFGR2_INPSEL1_Msk (0x1UL << COMP_CFGR2_INPSEL1_Pos) /*!< 0x00400000 */ +#define COMP_CFGR2_INPSEL1 COMP_CFGR2_INPSEL1_Msk /*!< COMP1 input plus 1 selection bit */ + +#define COMP_CFGR2_BLANKING_Pos (24U) +#define COMP_CFGR2_BLANKING_Msk (0xFUL << COMP_CFGR2_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR2_BLANKING COMP_CFGR2_BLANKING_Msk /*!< COMP1 blanking source selection bits */ +#define COMP_CFGR2_BLANKING_0 (0x1UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR2_BLANKING_1 (0x2UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR2_BLANKING_2 (0x4UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR2_BLANKING_3 (0x8UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR2_LOCK_Pos (31U) +#define COMP_CFGR2_LOCK_Msk (0x1UL << COMP_CFGR2_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR2_LOCK COMP_CFGR2_LOCK_Msk /*!< COMP1 Lock Bit */ + +/******************************************************************************/ +/* */ +/* Coupling and chaining bridge (CCB) */ +/* */ +/******************************************************************************/ +/* Specific device feature definitions */ +#define HW_SANITY_CHECK_SUPPORT /*!< CCB feature available only on specific devices: HW Sanity check is available on H5 1M devices */ +/******************* Bit definition for CCB_CR register ******************/ +#define CCB_CR_CCOP_Pos (0U) +#define CCB_CR_CCOP_Msk (0xFFUL << CCB_CR_CCOP_Pos) /*!< 0x000000FF */ +#define CCB_CR_CCOP CCB_CR_CCOP_Msk /*!< Coupling and chaining operation */ +#define CCB_CR_IPRST_Pos (31U) +#define CCB_CR_IPRST_Msk (0x1UL << CCB_CR_IPRST_Pos) /*!< 0x80000000 */ +#define CCB_CR_IPRST CCB_CR_IPRST_Msk /*!< CCB reset */ + +/******************* Bit definition for CCB_SR register ******************/ +#define CCB_SR_OPSTEP_Pos (0U) +#define CCB_SR_OPSTEP_Msk (0x1FUL << CCB_SR_OPSTEP_Pos) /*!< 0x0000001F */ +#define CCB_SR_OPSTEP CCB_SR_OPSTEP_Msk /*!< Operation step */ +#define CCB_SR_OPERR_Pos (8U) +#define CCB_SR_OPERR_Msk (0x3FUL << CCB_SR_OPERR_Pos) /*!< 0x00003F00 */ +#define CCB_SR_OPERR CCB_SR_OPERR_Msk /*!< Operation error */ +#define CCB_SR_BUSY_Pos (16U) +#define CCB_SR_BUSY_Msk (0x1UL << CCB_SR_BUSY_Pos) /*!< 0x00010000 */ +#define CCB_SR_BUSY CCB_SR_BUSY_Msk /*!< CCB busy */ +#define CCB_SR_TAMP_EVT0_Pos (24U) +#define CCB_SR_TAMP_EVT0_Msk (0x1UL << CCB_SR_TAMP_EVT0_Pos) /*!< 0x01000000 */ +#define CCB_SR_TAMP_EVT0 CCB_SR_TAMP_EVT0_Msk /*!< Tamper event 0 flag */ +#define CCB_SR_TAMP_EVT1_Pos (25U) +#define CCB_SR_TAMP_EVT1_Msk (0x1UL << CCB_SR_TAMP_EVT1_Pos) /*!< 0x02000000 */ +#define CCB_SR_TAMP_EVT1 CCB_SR_TAMP_EVT1_Msk /*!< Tamper event 1 flag */ +#define CCB_SR_TAMP_EVT2_Pos (26U) +#define CCB_SR_TAMP_EVT2_Msk (0x1UL << CCB_SR_TAMP_EVT2_Pos) /*!< 0x04000000 */ +#define CCB_SR_TAMP_EVT2 CCB_SR_TAMP_EVT2_Msk /*!< Tamper event 2 flag */ +#define CCB_SR_TAMP_EVT3_Pos (27U) +#define CCB_SR_TAMP_EVT3_Msk (0x1UL << CCB_SR_TAMP_EVT3_Pos) /*!< 0x08000000 */ +#define CCB_SR_TAMP_EVT3 CCB_SR_TAMP_EVT3_Msk /*!< Tamper event 3 flag */ +#define CCB_SR_TAMP_EVT4_Pos (28U) +#define CCB_SR_TAMP_EVT4_Msk (0x1UL << CCB_SR_TAMP_EVT4_Pos) /*!< 0x10000000 */ +#define CCB_SR_TAMP_EVT4 CCB_SR_TAMP_EVT4_Msk /*!< Tamper event 4 flag */ + +#define CCB_SR_TAMP_EVT5_Pos (29U) +#define CCB_SR_TAMP_EVT5_Msk (0x1UL << CCB_SR_TAMP_EVT5_Pos) /*!< 0x20000000 */ +#define CCB_SR_TAMP_EVT5 CCB_SR_TAMP_EVT5_Msk /*!< Tamper event 5 flag */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) +#define CRC_CR_RTYPE_IN_Pos (9U) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< RTYPE_IN Reverse type Input bits */ +#define CRC_CR_RTYPE_OUT_Pos (10U) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< RTYPE_OUT Reverse type Output bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_BUSY_Pos (4U) +#define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9U) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12U) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15U) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR0 register *******************/ +#define RNG_HTCR0_HTCFG_Pos (0U) +#define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR0_HTCFG RNG_HTCR0_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR1 register *******************/ +#define RNG_HTCR1_HTCFG_Pos (0U) +#define RNG_HTCR1_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR1_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR1_HTCFG RNG_HTCR1_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR2 register *******************/ +#define RNG_HTCR2_HTCFG_Pos (0U) +#define RNG_HTCR2_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR2_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR2_HTCFG RNG_HTCR2_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR3 register *******************/ +#define RNG_HTCR3_HTCFG_Pos (0U) +#define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk + +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************** RNG Nist Compliance Values ******************************/ +#define RNG_HTCRx_VALUE 0x0003FFFF +#define RNG_CR_NIST_VALUE (0x00200F00U) +#define RNG_HTCR_NIST_VALUE (0xA2B0U) + +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 + + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) /*!< FLASH Bank Size */ +#define FLASH_SECTOR_SIZE 0x2000U /*!< Flash Sector Size: 8 KB */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Operation in Flash high-cycle data area interrupted */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (23U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00800000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< Operation in OTP area interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTCR register *******************/ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ +#define FLASH_OPTCR_OPTSTART_Pos (1U) +#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ + +/******************* Bits definition for FLASH_SR register ***********************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< Data buffer not empty flag */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ +#define FLASH_SR_OBKERR_Pos (21U) +#define FLASH_SR_OBKERR_Msk (0x1UL << FLASH_SR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_SR_OBKERR FLASH_SR_OBKERR_Msk /*!< OBK general error flag */ +#define FLASH_SR_OBKWERR_Pos (22U) +#define FLASH_SR_OBKWERR_Msk (0x1UL << FLASH_SR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_SR_OBKWERR FLASH_SR_OBKWERR_Msk /*!< OBK write error flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ + +/******************* Bits definition for FLASH_CR register ***********************/ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming control bit */ +#define FLASH_CR_SER_Pos (2U) +#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ +#define FLASH_CR_START_Pos (5U) +#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000020 */ +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ +#define FLASH_CR_SNB_Pos (6U) +#define FLASH_CR_SNB_Msk (0x3FUL << FLASH_CR_SNB_Pos) /*!< 0x00000FC0 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ +#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ +#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos) /*!< 0x00000800 */ +#define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos) /*!< 0x00001000 */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-operation interrupt control bit */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ +#define FLASH_CR_OBKERRIE_Pos (21U) +#define FLASH_CR_OBKERRIE_Msk (0x1UL << FLASH_CR_OBKERRIE_Pos) /*!< 0x00200000 */ +#define FLASH_CR_OBKERRIE FLASH_CR_OBKERRIE_Msk /*!< OBK general error interrupt enable bitt */ +#define FLASH_CR_OBKWERRIE_Pos (22U) +#define FLASH_CR_OBKWERRIE_Msk (0x1UL << FLASH_CR_OBKWERRIE_Pos) /*!< 0x00400000 */ +#define FLASH_CR_OBKWERRIE FLASH_CR_OBKWERRIE_Msk /*!< OBK write error interrupt enable bit */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ +#define FLASH_CR_INV_Pos (29U) +#define FLASH_CR_INV_Msk (0x1UL << FLASH_CR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_CR_INV FLASH_CR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x10000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector */ + +/******************* Bits definition for FLASH_CCR register *******************/ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ +#define FLASH_CCR_CLR_OBKERR_Pos (21U) +#define FLASH_CCR_CLR_OBKERR_Msk (0x1UL << FLASH_CCR_CLR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_CCR_CLR_OBKERR FLASH_CCR_CLR_OBKERR_Msk /*!< OBKERR flag clear bit */ +#define FLASH_CCR_CLR_OBKWERR_Pos (22U) +#define FLASH_CCR_CLR_OBKWERR_Msk (0x1UL << FLASH_CCR_CLR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_CCR_CLR_OBKWERR FLASH_CCR_CLR_OBKWERR_Msk /*!< OBKWERR flag clear bit */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Option byte change error clear bit */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/****************** Bits definition for FLASH_OBKCFGR register *****************/ +#define FLASH_OBKCFGR_LOCK_Pos (0U) +#define FLASH_OBKCFGR_LOCK_Msk (0x1UL << FLASH_OBKCFGR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OBKCFGR_LOCK FLASH_OBKCFGR_LOCK_Msk /*!< OBKCFGR lock */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Pos (1U) +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Msk (0x1UL << FLASH_OBKCFGR_SWAP_SECT_REQ_Pos) /*!< 0x00000002 */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ FLASH_OBKCFGR_SWAP_SECT_REQ_Msk /*!< OBK swap sector request */ +#define FLASH_OBKCFGR_ALT_SECT_Pos (2U) +#define FLASH_OBKCFGR_ALT_SECT_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_Pos) /*!< 0x00000004 */ +#define FLASH_OBKCFGR_ALT_SECT FLASH_OBKCFGR_ALT_SECT_Msk /*!< Alternate sector */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Pos (3U) +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_ERASE_Pos) /*!< 0x00000008 */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE FLASH_OBKCFGR_ALT_SECT_ERASE_Msk /*!< Alternate sector erase */ +#define FLASH_OBKCFGR_SWAP_OFFSET_Pos (16U) +#define FLASH_OBKCFGR_SWAP_OFFSET_Msk (0x1FFUL << FLASH_OBKCFGR_SWAP_OFFSET_Pos) /*!< 0x01FF0000 */ +#define FLASH_OBKCFGR_SWAP_OFFSET FLASH_OBKCFGR_SWAP_OFFSET_Msk /*!< Swap offset */ + +/****************** Bits definition for FLASH_HDPEXTR register *****************/ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000007F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 1 */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x007F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 2 */ + +/******************* Bits definition for FLASH_OPTSR register ***************/ +#define FLASH_OPTSR_BOR_LEV_Pos (0U) +#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000003 */ +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option bit */ +#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR_BORH_EN_Pos (2U) +#define FLASH_OPTSR_BORH_EN_Msk (0x1UL << FLASH_OPTSR_BORH_EN_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR_BORH_EN FLASH_OPTSR_BORH_EN_Msk /*!< Brownout high enable configuration bit */ +#define FLASH_OPTSR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_IWDG_SW FLASH_OPTSR_IWDG_SW_Msk /*!< IWDG control mode option bit */ +#define FLASH_OPTSR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_WWDG_SW FLASH_OPTSR_WWDG_SW_Msk /*!< WWDG control mode option bit */ +#define FLASH_OPTSR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_NRST_STOP FLASH_OPTSR_NRST_STOP_Msk /*!< Stop mode entry reset option bit */ +#define FLASH_OPTSR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_NRST_STDBY FLASH_OPTSR_NRST_STDBY_Msk /*!< Standby mode entry reset option bit */ +#define FLASH_OPTSR_PRODUCT_STATE_Pos (8U) +#define FLASH_OPTSR_PRODUCT_STATE_Msk (0xFFUL << FLASH_OPTSR_PRODUCT_STATE_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRODUCT_STATE FLASH_OPTSR_PRODUCT_STATE_Msk /*!< Life state code option byte */ +#define FLASH_OPTSR_IO_VDD_HSLV_Pos (16U) +#define FLASH_OPTSR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDD_HSLV_Pos) /*!< 0x00010000 */ +#define FLASH_OPTSR_IO_VDD_HSLV FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Pos (17U) +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDDIO2_HSLV_Pos) /*!< 0x00020000 */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_IWDG_STOP FLASH_OPTSR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTSR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_IWDG_STDBY FLASH_OPTSR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTSR_BOOT_UBE_Pos (22U) +#define FLASH_OPTSR_BOOT_UBE_Msk (0xFFUL << FLASH_OPTSR_BOOT_UBE_Pos) /*!< 0x3FC00000 */ +#define FLASH_OPTSR_BOOT_UBE FLASH_OPTSR_BOOT_UBE_Msk /*!< Unique boot entry option byte */ +#define FLASH_OPTSR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_SWAP_BANK FLASH_OPTSR_SWAP_BANK_Msk /*!< Bank swapping option bit */ + +/******************* Bits definition for FLASH_EPOCHR register ***************/ +#define FLASH_EPOCHR_EPOCH_Pos (0U) +#define FLASH_EPOCHR_EPOCH_Msk (0xFFFFFFUL << FLASH_EPOCHR_EPOCH_Pos) /*!< 0x00FFFFFF */ +#define FLASH_EPOCHR_EPOCH FLASH_EPOCHR_EPOCH_Msk /*!< EPOCH counter */ + +/******************* Bits definition for FLASH_OPTSR2 register ***************/ +#define FLASH_OPTSR2_SRAM1_3_RST_Pos (2U) +#define FLASH_OPTSR2_SRAM1_3_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM1_3_RST_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR2_SRAM1_3_RST FLASH_OPTSR2_SRAM1_3_RST_Msk /*!< SRAM1 and SRAM3 erased when a system reset occurs */ +#define FLASH_OPTSR2_SRAM2_RST_Pos (3U) +#define FLASH_OPTSR2_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM2_RST_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR2_SRAM2_RST FLASH_OPTSR2_SRAM2_RST_Msk /*!< SRAM2 erased when a system reset occurs*/ +#define FLASH_OPTSR2_BKPRAM_ECC_Pos (4U) +#define FLASH_OPTSR2_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTSR2_BKPRAM_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_BKPRAM_ECC FLASH_OPTSR2_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTSR2_SRAM3_ECC_Pos (5U) +#define FLASH_OPTSR2_SRAM3_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM3_ECC_Pos) /*!< 0x00000020 */ +#define FLASH_OPTSR2_SRAM3_ECC FLASH_OPTSR2_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTSR2_SRAM2_ECC_Pos (6U) +#define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */ +#define FLASH_OPTSR2_USBPD_DIS_Pos (8U) +#define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */ +#define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */ +#define FLASH_OPTSR2_TZEN_Pos (24U) +#define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */ +#define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */ + +/**************** Bits definition for FLASH_BOOTR register **********************/ +#define FLASH_BOOTR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_BOOT_LOCK FLASH_BOOTR_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_BOOTR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_BOOTADD FLASH_BOOTR_BOOTADD_Msk /*!< Boot address */ + +/**************** Bits definition for FLASH_PRIVBBR register *******************/ +#define FLASH_PRIVBBR_PRIVBB_Pos (0U) +#define FLASH_PRIVBBR_PRIVBB_Msk (0xFFFFFFFFUL << FLASH_PRIVBBR_PRIVBB_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PRIVBBR_PRIVBB FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector attribute */ + +/***************** Bits definition for FLASH_SECWMR register ********************/ +#define FLASH_SECWMR_SECWM_STRT_Pos (0U) +#define FLASH_SECWMR_SECWM_STRT_Msk (0x3FUL << FLASH_SECWMR_SECWM_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_SECWMR_SECWM_STRT FLASH_SECWMR_SECWM_STRT_Msk /*!< Start sector of secure area */ +#define FLASH_SECWMR_SECWM_END_Pos (16U) +#define FLASH_SECWMR_SECWM_END_Msk (0x3FUL << FLASH_SECWMR_SECWM_END_Pos) /*!< 0x003F0000 */ +#define FLASH_SECWMR_SECWM_END FLASH_SECWMR_SECWM_END_Msk /*!< End sector of secure area */ + +/***************** Bits definition for FLASH_WRPR register *********************/ +#define FLASH_WRPR_WRPSG_Pos (0U) +#define FLASH_WRPR_WRPSG_Msk (0x0000FFFFUL << FLASH_WRPR_WRPSG_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRPR_WRPSG FLASH_WRPR_WRPSG_Msk /*!< Sector group protection option status */ + +/***************** Bits definition for FLASH_EDATA register ********************/ +#define FLASH_EDATAR_EDATA_STRT_Pos (0U) +#define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */ +#define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */ +#define FLASH_EDATAR_EDATA_EN_Pos (15U) +#define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */ +#define FLASH_EDATAR_EDATA_EN FLASH_EDATAR_EDATA_EN_Msk /*!< Flash high-cycle data enable */ + +/***************** Bits definition for FLASH_HDPR register ********************/ +#define FLASH_HDPR_HDP_STRT_Pos (0U) +#define FLASH_HDPR_HDP_STRT_Msk (0x7FUL << FLASH_HDPR_HDP_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_HDPR_HDP_STRT FLASH_HDPR_HDP_STRT_Msk /*!< Start sector of hide protection area */ +#define FLASH_HDPR_HDP_END_Pos (16U) +#define FLASH_HDPR_HDP_END_Msk (0x7FUL << FLASH_HDPR_HDP_END_Pos) /*!< 0x007F0000 */ +#define FLASH_HDPR_HDP_END FLASH_HDPR_HDP_END_Msk /*!< End sector of hide protection area */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_OBK_ECC_Pos (20U) +#define FLASH_ECCR_OBK_ECC_Msk (0x1UL << FLASH_ECCR_OBK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_OBK_ECC FLASH_ECCR_OBK_ECC_Msk /*!< Flash OB Keys storage area ECC fail */ +#define FLASH_ECCR_DATA_ECC_Pos (21U) +#define FLASH_ECCR_DATA_ECC_Msk (0x1UL << FLASH_ECCR_DATA_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_DATA_ECC FLASH_ECCR_DATA_ECC_Msk /*!< Flash high-cycle data ECC fail */ +#define FLASH_ECCR_BK_ECC_Pos (22U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (23U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_OTP_ECC_Pos (24U) +#define FLASH_ECCR_OTP_ECC_Msk (0x1UL << FLASH_ECCR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (25U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_ECCDR register ***************/ +#define FLASH_ECCDR_FAIL_DATA_Pos (0U) +#define FLASH_ECCDR_FAIL_DATA_Msk (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_OR register ******************/ +#define RTC_OR_OUT2_RMP_Pos (0U) +#define RTC_OR_OUT2_RMP_Msk (0x1UL << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x08000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk +#define TAMP_CR1_ITAMP15E_Pos (30U) +#define TAMP_CR1_ITAMP15E_Msk (0x1UL << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ +#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP4NOER_Pos (3U) +#define TAMP_CR3_ITAMP4NOER_Msk (0x1UL << TAMP_CR3_ITAMP4NOER_Pos) /*!< 0x00000008 */ +#define TAMP_CR3_ITAMP4NOER TAMP_CR3_ITAMP4NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000080 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000400 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00001000 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk +#define TAMP_CR3_ITAMP15NOER_Pos (14U) +#define TAMP_CR3_ITAMP15NOER_Msk (0x1UL << TAMP_CR3_ITAMP15NOER_Pos) /*!< 0x00004000 */ +#define TAMP_CR3_ITAMP15NOER TAMP_CR3_ITAMP15NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk +#define TAMP_IER_ITAMP15IE_Pos (30U) +#define TAMP_IER_ITAMP15IE_Msk (0x1UL << TAMP_IER_ITAMP15IE_Pos) /*!< 0x40000000 */ +#define TAMP_IER_ITAMP15IE TAMP_IER_ITAMP15IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk +#define TAMP_SR_ITAMP15F_Pos (30U) +#define TAMP_SR_ITAMP15F_Msk (0x1UL << TAMP_SR_ITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SR_ITAMP15F TAMP_SR_ITAMP15F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk +#define TAMP_MISR_ITAMP15MF_Pos (30U) +#define TAMP_MISR_ITAMP15MF_Msk (0x1UL << TAMP_MISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_MISR_ITAMP15MF TAMP_MISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP4MF_Pos (19U) +#define TAMP_SMISR_ITAMP4MF_Msk (0x1UL << TAMP_SMISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_SMISR_ITAMP4MF TAMP_SMISR_ITAMP4MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk +#define TAMP_SMISR_ITAMP15MF_Pos (30U) +#define TAMP_SMISR_ITAMP15MF_Msk (0x1UL << TAMP_SMISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_SMISR_ITAMP15MF TAMP_SMISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk +#define TAMP_SCR_CITAMP15F_Pos (30U) +#define TAMP_SCR_CITAMP15F_Msk (0x1UL << TAMP_SCR_CITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SCR_CITAMP15F TAMP_SCR_CITAMP15F_Msk +/******************** Bits definition for TAMP_COUNT1R register ***************/ +#define TAMP_COUNT1R_COUNT_Pos (0U) +#define TAMP_COUNT1R_COUNT_Msk (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */ +#define TAMP_COUNT1R_COUNT TAMP_COUNT1R_COUNT_Msk + +/******************** Bits definition for TAMP_OR register ***************/ +#define TAMP_OR_OUT3_RMP_Pos (1U) +#define TAMP_OR_OUT3_RMP_Msk (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00000006 */ +#define TAMP_OR_OUT3_RMP TAMP_OR_OUT3_RMP_Msk +#define TAMP_OR_OUT3_RMP_0 (0x1UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00100000 */ +#define TAMP_OR_OUT3_RMP_1 (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00200000 */ +#define TAMP_OR_OUT5_RMP_Pos (3U) +#define TAMP_OR_OUT5_RMP_Msk (0x1UL << TAMP_OR_OUT5_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_OUT5_RMP TAMP_OR_OUT5_RMP_Msk +#define TAMP_OR_IN2_RMP_Pos (8U) +#define TAMP_OR_IN2_RMP_Msk (0x1UL << TAMP_OR_IN2_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN2_RMP TAMP_OR_IN2_RMP_Msk +#define TAMP_OR_IN3_RMP_Pos (9U) +#define TAMP_OR_IN3_RMP_Msk (0x1UL << TAMP_OR_IN3_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN3_RMP TAMP_OR_IN3_RMP_Msk +#define TAMP_OR_IN4_RMP_Pos (10U) +#define TAMP_OR_IN4_RMP_Msk (0x1UL << TAMP_OR_IN4_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN4_RMP TAMP_OR_IN4_RMP_Msk + +/******************** Bits definition for TAMP_ERCFG register ***************/ +#define TAMP_ERCFGR_ERCFG0_Pos (0U) +#define TAMP_ERCFGR_ERCFG0_Msk (0x1UL << TAMP_ERCFGR_ERCFG0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR_ERCFG0 TAMP_ERCFGR_ERCFG0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* SBS */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SBS_HDPLCR register *****************/ +#define SBS_HDPLCR_INCR_HDPL_Pos (0U) +#define SBS_HDPLCR_INCR_HDPL_Msk (0xFFUL << SBS_HDPLCR_INCR_HDPL_Pos) /*!< 0x000000FF */ +#define SBS_HDPLCR_INCR_HDPL SBS_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL value. */ + +/******************** Bit definition for SBS_HDPLSR register *****************/ +#define SBS_HDPLSR_HDPL_Pos (0U) +#define SBS_HDPLSR_HDPL_Msk (0xFFUL << SBS_HDPLSR_HDPL_Pos) /*!< 0x000000FF */ +#define SBS_HDPLSR_HDPL SBS_HDPLSR_HDPL_Msk /*!< HDPL value. */ + +/******************** Bit definition for SBS_NEXTHDPLCR register *****************/ +#define SBS_NEXTHDPLCR_NEXTHDPL_Pos (0U) +#define SBS_NEXTHDPLCR_NEXTHDPL_Msk (0x3UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000003 */ +#define SBS_NEXTHDPLCR_NEXTHDPL SBS_NEXTHDPLCR_NEXTHDPL_Msk /*!< NEXTHDPL value. */ +#define SBS_NEXTHDPLCR_NEXTHDPL_0 (0x1UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000001 */ +#define SBS_NEXTHDPLCR_NEXTHDPL_1 (0x2UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000002 */ + +/******************** Bit definition for SBS_DBGCR register *****************/ +#define SBS_DBGCR_AP_UNLOCK_Pos (0U) +#define SBS_DBGCR_AP_UNLOCK_Msk (0xFFUL << SBS_DBGCR_AP_UNLOCK_Pos) /*!< 0x000000FF */ +#define SBS_DBGCR_AP_UNLOCK SBS_DBGCR_AP_UNLOCK_Msk /*!< Open the Access Port. */ + +#define SBS_DBGCR_DBG_UNLOCK_Pos (8U) +#define SBS_DBGCR_DBG_UNLOCK_Msk (0xFFUL << SBS_DBGCR_DBG_UNLOCK_Pos) /*!< 0x0000FF00 */ +#define SBS_DBGCR_DBG_UNLOCK SBS_DBGCR_DBG_UNLOCK_Msk /*!< Open the debug when DBG_AUTH_HDPL is reached. */ + +#define SBS_DBGCR_DBG_AUTH_HDPL_Pos (16U) +#define SBS_DBGCR_DBG_AUTH_HDPL_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_HDPL_Pos) /*!< 0x00FF0000 */ +#define SBS_DBGCR_DBG_AUTH_HDPL SBS_DBGCR_DBG_AUTH_HDPL_Msk /*!< HDPL value when the debug should be effectively opened. */ + +#define SBS_DBGCR_DBG_AUTH_SEC_Pos (24U) +#define SBS_DBGCR_DBG_AUTH_SEC_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_SEC_Pos) /*!< 0xFF000000 */ +#define SBS_DBGCR_DBG_AUTH_SEC SBS_DBGCR_DBG_AUTH_SEC_Msk /*!< Open the non-secured and secured debugs. */ + +/******************** Bit definition for SBS_DBGLCKR register *****************/ +#define SBS_DBGLOCKR_DBGCFG_LOCK_Pos (0U) +#define SBS_DBGLOCKR_DBGCFG_LOCK_Msk (0xFFUL << SBS_DBGLOCKR_DBGCFG_LOCK_Pos) /*!< 0x000000FF */ +#define SBS_DBGLOCKR_DBGCFG_LOCK SBS_DBGLOCKR_DBGCFG_LOCK_Msk /*!< SBS_DBGLOCKR_DBGCFG_LOCK value. */ + +/******************** Bit definition for SBS_RSSCMDR register ***************/ +#define SBS_RSSCMDR_RSSCMD_Pos (0U) +#define SBS_RSSCMDR_RSSCMD_Msk (0xFFFFUL << SBS_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */ +#define SBS_RSSCMDR_RSSCMD SBS_RSSCMDR_RSSCMD_Msk /*!< command to be executed by the RSS. */ + +/******************** Bit definition for SBS_EPOCHSELCR register ************/ +#define SBS_EPOCHSELCR_EPOCH_SEL_Pos (0U) +#define SBS_EPOCHSELCR_EPOCH_SEL_Msk (0x3UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000003 */ +#define SBS_EPOCHSELCR_EPOCH_SEL SBS_EPOCHSELCR_EPOCH_SEL_Msk /*!< Select EPOCH sent to SAES IP to encrypt/decrypt keys */ +#define SBS_EPOCHSELCR_EPOCH_SEL_0 (0x1UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000001 */ +#define SBS_EPOCHSELCR_EPOCH_SEL_1 (0x2UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000002 */ + +/****************** Bit definition for SBS_PMCR register ****************/ +#define SBS_PMCR_PB6_FMP_Pos (16U) +#define SBS_PMCR_PB6_FMP_Msk (0x1UL << SBS_PMCR_PB6_FMP_Pos) /*!< 0x00010000 */ +#define SBS_PMCR_PB6_FMP SBS_PMCR_PB6_FMP_Msk /*!< Fast-mode Plus command on PB(6) */ +#define SBS_PMCR_PB7_FMP_Pos (17U) +#define SBS_PMCR_PB7_FMP_Msk (0x1UL << SBS_PMCR_PB7_FMP_Pos) /*!< 0x00020000 */ +#define SBS_PMCR_PB7_FMP SBS_PMCR_PB7_FMP_Msk /*!< Fast-mode Plus command on PB(7) */ +#define SBS_PMCR_PB8_FMP_Pos (18U) +#define SBS_PMCR_PB8_FMP_Msk (0x1UL << SBS_PMCR_PB8_FMP_Pos) /*!< 0x00040000 */ +#define SBS_PMCR_PB8_FMP SBS_PMCR_PB8_FMP_Msk /*!< Fast-mode Plus command on PB(8) */ +#define SBS_PMCR_PB9_FMP_Pos (19U) +#define SBS_PMCR_PB9_FMP_Msk (0x1UL << SBS_PMCR_PB9_FMP_Pos) /*!< 0x00080000 */ +#define SBS_PMCR_PB9_FMP SBS_PMCR_PB9_FMP_Msk /*!< Fast-mode Plus command on PB(9) */ +#define SBS_PMCR_ETH_SEL_PHY_Pos (21U) +#define SBS_PMCR_ETH_SEL_PHY_Msk (0x7UL << SBS_PMCR_ETH_SEL_PHY_Pos) /*!< 0x00E00000 */ +#define SBS_PMCR_ETH_SEL_PHY SBS_PMCR_ETH_SEL_PHY_Msk /*!< Ethernet PHY Interface Selection */ +#define SBS_PMCR_ETH_SEL_PHY_0 (0x1UL << SBS_PMCR_ETH_SEL_PHY_Pos) /*!< 0x00200000 */ +#define SBS_PMCR_ETH_SEL_PHY_1 (0x2UL << SBS_PMCR_ETH_SEL_PHY_Pos) /*!< 0x00400000 */ +#define SBS_PMCR_ETH_SEL_PHY_2 (0x4UL << SBS_PMCR_ETH_SEL_PHY_Pos) /*!< 0x00800000 */ +#define SBS_PMCR_ETHINTPOL_Pos (25U) +#define SBS_PMCR_ETHINTPOL_Msk (0x1UL << SBS_PMCR_ETHINTPOL_Pos) /*!< 0x0200000 */ +#define SBS_PMCR_ETHINTPOL SBS_PMCR_ETHINTPOL_Msk /*!< ETH external PHY interrupt polarity configuration */ +#define SBS_PMCR_ETHPDACK_Pos (26U) +#define SBS_PMCR_ETHPDACK_Msk (0x1UL << SBS_PMCR_ETHPDACK_Pos) /*!< 0x0400000 */ +#define SBS_PMCR_ETHPDACK SBS_PMCR_ETHPDACK_Msk /*!< ETH power-down acknowledge */ +#define SBS_PMCR_ETHTXLPI_Pos (27U) +#define SBS_PMCR_ETHTXLPI_Msk (0x1UL << SBS_PMCR_ETHTXLPI_Pos) /*!< 0x0400000 */ +#define SBS_PMCR_ETHTXLPI SBS_PMCR_ETHTXLPI_Msk /*!< ETH TxLPI status */ + +/****************** Bit definition for SBS_FPUIMR register ***************/ +#define SBS_FPUIMR_FPU_IE_Pos (0U) +#define SBS_FPUIMR_FPU_IE_Msk (0x3FUL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F - */ +#define SBS_FPUIMR_FPU_IE SBS_FPUIMR_FPU_IE_Msk /*!< All FPU interrupts enable */ +#define SBS_FPUIMR_FPU_IE_0 (0x1UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000001 - Invalid operation Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_1 (0x2UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000002 - Divide-by-zero Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_2 (0x4UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000004 - Underflow Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_3 (0x8UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000008 - Overflow Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_4 (0x10UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000010 - Input denormal Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_5 (0x20UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000020 - Inexact Interrupt enable (interrupt disabled at reset) */ + +/****************** Bit definition for SBS_MESR register ****************/ +#define SBS_MESR_MCLR_Pos (0U) +#define SBS_MESR_MCLR_Msk (0x1UL << SBS_MESR_MCLR_Pos) /*!< 0x00000001 */ +#define SBS_MESR_MCLR SBS_MESR_MCLR_Msk /*!< Status of Erase after Reset */ +#define SBS_MESR_IPMEE_Pos (16U) +#define SBS_MESR_IPMEE_Msk (0x1UL << SBS_MESR_IPMEE_Pos) /*!< 0x00010000 */ +#define SBS_MESR_IPMEE SBS_MESR_IPMEE_Msk /*!< Status of End of Erase for ICache and PKA RAMs */ + +/****************** Bit definition for SBS_CCCSR register ****************/ +#define SBS_CCCSR_EN1_Pos (0U) +#define SBS_CCCSR_EN1_Msk (0x1UL << SBS_CCCSR_EN1_Pos) /*!< 0x00000001 */ +#define SBS_CCCSR_EN1 SBS_CCCSR_EN1_Msk /*!< Enable compensation cell for VDD power rail */ +#define SBS_CCCSR_CS1_Pos (1U) +#define SBS_CCCSR_CS1_Msk (0x1UL << SBS_CCCSR_CS1_Pos) /*!< 0x00000002 */ +#define SBS_CCCSR_CS1 SBS_CCCSR_CS1_Msk /*!< Code selection for VDD power rail */ +#define SBS_CCCSR_EN2_Pos (2U) +#define SBS_CCCSR_EN2_Msk (0x1UL << SBS_CCCSR_EN2_Pos) /*!< 0x00000004 */ +#define SBS_CCCSR_EN2 SBS_CCCSR_EN2_Msk /*!< Enable compensation cell for VDDIO power rail */ +#define SBS_CCCSR_CS2_Pos (3U) +#define SBS_CCCSR_CS2_Msk (0x1UL << SBS_CCCSR_CS2_Pos) /*!< 0x00000008 */ +#define SBS_CCCSR_CS2 SBS_CCCSR_CS2_Msk /*!< Code selection for VDDIO power rail */ +#define SBS_CCCSR_RDY1_Pos (8U) +#define SBS_CCCSR_RDY1_Msk (0x1UL << SBS_CCCSR_RDY1_Pos) /*!< 0x00000100 */ +#define SBS_CCCSR_RDY1 SBS_CCCSR_RDY1_Msk /*!< VDD compensation cell ready flag */ +#define SBS_CCCSR_RDY2_Pos (9U) +#define SBS_CCCSR_RDY2_Msk (0x1UL << SBS_CCCSR_RDY2_Pos) /*!< 0x00000200 */ +#define SBS_CCCSR_RDY2 SBS_CCCSR_RDY2_Msk /*!< VDDIO compensation cell ready flag */ + +/****************** Bit definition for SBS_CCVALR register ****************/ +#define SBS_CCVALR_ANSRC1_Pos (0U) +#define SBS_CCVALR_ANSRC1_Msk (0xFUL << SBS_CCVALR_ANSRC1_Pos) /*!< 0x0000000F */ +#define SBS_CCVALR_ANSRC1 SBS_CCVALR_ANSRC1_Msk /*!< NMOS compensation value */ +#define SBS_CCVALR_APSRC1_Pos (4U) +#define SBS_CCVALR_APSRC1_Msk (0xFUL << SBS_CCVALR_APSRC1_Pos) /*!< 0x000000F0 */ +#define SBS_CCVALR_APSRC1 SBS_CCVALR_APSRC1_Msk /*!< PMOS compensation value */ +#define SBS_CCVALR_ANSRC2_Pos (8U) +#define SBS_CCVALR_ANSRC2_Msk (0xFUL << SBS_CCVALR_ANSRC2_Pos) /*!< 0x00000F00 */ +#define SBS_CCVALR_ANSRC2 SBS_CCVALR_ANSRC2_Msk /*!< NMOS compensation value */ +#define SBS_CCVALR_APSRC2_Pos (12U) +#define SBS_CCVALR_APSRC2_Msk (0xFUL << SBS_CCVALR_APSRC2_Pos) /*!< 0x0000F000 */ +#define SBS_CCVALR_APSRC2 SBS_CCVALR_APSRC2_Msk /*!< PMOS compensation value */ + +/****************** Bit definition for SBS_CCSWCR register ****************/ +#define SBS_CCSWCR_SW_ANSRC1_Pos (0U) +#define SBS_CCSWCR_SW_ANSRC1_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC1_Pos) /*!< 0x0000000F */ +#define SBS_CCSWCR_SW_ANSRC1 SBS_CCSWCR_SW_ANSRC1_Msk /*!< NMOS compensation code for VDD Power Rail */ +#define SBS_CCSWCR_SW_APSRC1_Pos (4U) +#define SBS_CCSWCR_SW_APSRC1_Msk (0xFUL << SBS_CCSWCR_SW_APSRC1_Pos) /*!< 0x000000F0 */ +#define SBS_CCSWCR_SW_APSRC1 SBS_CCSWCR_SW_APSRC1_Msk /*!< PMOS compensation code for VDD Power Rail */ +#define SBS_CCSWCR_SW_ANSRC2_Pos (8U) +#define SBS_CCSWCR_SW_ANSRC2_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC2_Pos) /*!< 0x00000F00 */ +#define SBS_CCSWCR_SW_ANSRC2 SBS_CCSWCR_SW_ANSRC2_Msk /*!< NMOS compensation code for VDDIO Power Rail */ +#define SBS_CCSWCR_SW_APSRC2_Pos (12U) +#define SBS_CCSWCR_SW_APSRC2_Msk (0xFUL << SBS_CCSWCR_SW_APSRC2_Pos) /*!< 0x0000F000 */ +#define SBS_CCSWCR_SW_APSRC2 SBS_CCSWCR_SW_APSRC2_Msk /*!< PMOS compensation code for VDDIO Power Rail */ + +/****************** Bit definition for SBS_CFGR2 register ****************/ +#define SBS_CFGR2_CLL_Pos (0U) +#define SBS_CFGR2_CLL_Msk (0x1UL << SBS_CFGR2_CLL_Pos) /*!< 0x00000001 */ +#define SBS_CFGR2_CLL SBS_CFGR2_CLL_Msk /*!< Core Lockup Lock */ +#define SBS_CFGR2_SEL_Pos (1U) +#define SBS_CFGR2_SEL_Msk (0x1UL << SBS_CFGR2_SEL_Pos) /*!< 0x00000002 */ +#define SBS_CFGR2_SEL SBS_CFGR2_SEL_Msk /*!< SRAM ECC Lock */ +#define SBS_CFGR2_PVDL_Pos (2U) +#define SBS_CFGR2_PVDL_Msk (0x1UL << SBS_CFGR2_PVDL_Pos) /*!< 0x00000004 */ +#define SBS_CFGR2_PVDL SBS_CFGR2_PVDL_Msk /*!< PVD Lock */ +#define SBS_CFGR2_ECCL_Pos (3U) +#define SBS_CFGR2_ECCL_Msk (0x1UL << SBS_CFGR2_ECCL_Pos) /*!< 0x00000008 */ +#define SBS_CFGR2_ECCL SBS_CFGR2_ECCL_Msk /*!< Flash ECC Lock*/ + +/******************** Bit definition for SBS_SECCFGR register ***************/ +#define SBS_SECCFGR_SBSSEC_Pos (0U) +#define SBS_SECCFGR_SBSSEC_Msk (0x1UL << SBS_SECCFGR_SBSSEC_Pos) /*!< 0x00000001 */ +#define SBS_SECCFGR_SBSSEC SBS_SECCFGR_SBSSEC_Msk /*!< SBS clock control security enable */ +#define SBS_SECCFGR_CLASSBSEC_Pos (1U) +#define SBS_SECCFGR_CLASSBSEC_Msk (0x1UL << SBS_SECCFGR_CLASSBSEC_Pos) /*!< 0x00000002 */ +#define SBS_SECCFGR_CLASSBSEC SBS_SECCFGR_CLASSBSEC_Msk /*!< ClassB SBS security enable */ +#define SBS_SECCFGR_FPUSEC_Pos (3U) +#define SBS_SECCFGR_FPUSEC_Msk (0x1UL << SBS_SECCFGR_FPUSEC_Pos) /*!< 0x00000008 */ +#define SBS_SECCFGR_FPUSEC SBS_SECCFGR_FPUSEC_Msk /*!< FPU SBS security enable */ + +/****************** Bit definition for SBS_CNSLCKR register **************/ +#define SBS_CNSLCKR_LOCKNSVTOR_Pos (0U) +#define SBS_CNSLCKR_LOCKNSVTOR_Msk (0x1UL << SBS_CNSLCKR_LOCKNSVTOR_Pos) /*!< 0x00000001 */ +#define SBS_CNSLCKR_LOCKNSVTOR SBS_CNSLCKR_LOCKNSVTOR_Msk /*!< Disable VTOR_NS register writes by SW or debug agent */ +#define SBS_CNSLCKR_LOCKNSMPU_Pos (1U) +#define SBS_CNSLCKR_LOCKNSMPU_Msk (0x1UL << SBS_CNSLCKR_LOCKNSMPU_Pos) /*!< 0x00000002 */ +#define SBS_CNSLCKR_LOCKNSMPU SBS_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Secure MPU registers writes by SW or debug agent */ + +/****************** Bit definition for SBS_CSLCKR register ***************/ +#define SBS_CSLCKR_LOCKSVTAIRCR_Pos (0U) +#define SBS_CSLCKR_LOCKSVTAIRCR_Msk (0x1UL << SBS_CSLCKR_LOCKSVTAIRCR_Pos) /*!< 0x00000001 */ +#define SBS_CSLCKR_LOCKSVTAIRCR SBS_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vector table address, handling of system faults */ +#define SBS_CSLCKR_LOCKSMPU_Pos (1U) +#define SBS_CSLCKR_LOCKSMPU_Msk (0x1UL << SBS_CSLCKR_LOCKSMPU_Pos) /*!< 0x00000002 */ +#define SBS_CSLCKR_LOCKSMPU SBS_CSLCKR_LOCKSMPU_Msk /*!< Disable changes to the secure MPU registers writes by SW or debug agent */ +#define SBS_CSLCKR_LOCKSAU_Pos (2U) +#define SBS_CSLCKR_LOCKSAU_Msk (0x1UL << SBS_CSLCKR_LOCKSAU_Pos) /*!< 0x00000004 */ +#define SBS_CSLCKR_LOCKSAU SBS_CSLCKR_LOCKSAU_Msk /*!< Disable changes to SAU registers */ + +/****************** Bit definition for SBS_ECCNMIR register ***************/ +#define SBS_ECCNMIR_ECCNMI_MASK_EN_Pos (0U) +#define SBS_ECCNMIR_ECCNMI_MASK_EN_Msk (0x1UL << SBS_ECCNMIR_ECCNMI_MASK_EN_Pos) /*!< 0x00000001 */ +#define SBS_ECCNMIR_ECCNMI_MASK_EN SBS_ECCNMIR_ECCNMI_MASK_EN_Msk /*!< Disable NMI in case of double ECC error in flash interface */ + +/*****************************************************************************/ +/* */ +/* Global TrustZone Control */ +/* */ +/*****************************************************************************/ +/******************* Bits definition for GTZC_TZSC_CR register ******************/ +#define GTZC_TZSC_CR_LCK_Pos (0U) +#define GTZC_TZSC_CR_LCK_Msk (0x01UL << GTZC_TZSC_CR_LCK_Pos) /*!< 0x00000001 */ + +/******************* Bits definition for GTZC_TZSC_MPCWM_CFGR register **********/ +#define GTZC_TZSC_MPCWM_CFGR_SREN_Pos (0U) +#define GTZC_TZSC_MPCWM_CFGR_SREN_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SREN_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SREN GTZC_TZSC_MPCWM_CFGR_SREN_Msk +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos (1U) +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk +#define GTZC_TZSC_MPCWM_CFGR_SEC_Pos (8U) +#define GTZC_TZSC_MPCWM_CFGR_SEC_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SEC GTZC_TZSC_MPCWM_CFGR_SEC_Msk +#define GTZC_TZSC_MPCWM_CFGR_PRIV_Pos (9U) +#define GTZC_TZSC_MPCWM_CFGR_PRIV_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_PRIV_Pos) +#define GTZC_TZSC_MPCWM_CFGR_PRIV GTZC_TZSC_MPCWM_CFGR_PRIV_Msk + +/******************* Bits definition for GTZC_TZSC_MPCWMR register **************/ +#define GTZC_TZSC_MPCWMR_SUBZ_START_Pos (0U) +#define GTZC_TZSC_MPCWMR_SUBZ_START_Msk (0x7FFUL << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) +#define GTZC_TZSC_MPCWMR_SUBZ_START GTZC_TZSC_MPCWMR_SUBZ_START_Msk +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos (16U) +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk (0xFFFUL << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk + +/******* Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers *****/ +/******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers *****/ + +/*************** Bits definition for register x=1 (TZSC1) *************/ +#define GTZC_CFGR1_TIM2_Pos (0U) +#define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) +#define GTZC_CFGR1_TIM3_Pos (1U) +#define GTZC_CFGR1_TIM3_Msk (0x01UL << GTZC_CFGR1_TIM3_Pos) +#define GTZC_CFGR1_TIM4_Pos (2U) +#define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) +#define GTZC_CFGR1_TIM5_Pos (3U) +#define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos) +#define GTZC_CFGR1_TIM6_Pos (4U) +#define GTZC_CFGR1_TIM6_Msk (0x01UL << GTZC_CFGR1_TIM6_Pos) +#define GTZC_CFGR1_TIM7_Pos (5U) +#define GTZC_CFGR1_TIM7_Msk (0x01UL << GTZC_CFGR1_TIM7_Pos) +#define GTZC_CFGR1_TIM12_Pos (6U) +#define GTZC_CFGR1_TIM12_Msk (0x01UL << GTZC_CFGR1_TIM12_Pos) +#define GTZC_CFGR1_WWDG_Pos (9U) +#define GTZC_CFGR1_WWDG_Msk (0x01UL << GTZC_CFGR1_WWDG_Pos) +#define GTZC_CFGR1_IWDG_Pos (10U) +#define GTZC_CFGR1_IWDG_Msk (0x01UL << GTZC_CFGR1_IWDG_Pos) +#define GTZC_CFGR1_SPI2_Pos (11U) +#define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos) +#define GTZC_CFGR1_SPI3_Pos (12U) +#define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos) +#define GTZC_CFGR1_USART2_Pos (13U) +#define GTZC_CFGR1_USART2_Msk (0x01UL << GTZC_CFGR1_USART2_Pos) +#define GTZC_CFGR1_USART3_Pos (14U) +#define GTZC_CFGR1_USART3_Msk (0x01UL << GTZC_CFGR1_USART3_Pos) +#define GTZC_CFGR1_UART4_Pos (15U) +#define GTZC_CFGR1_UART4_Msk (0x01UL << GTZC_CFGR1_UART4_Pos) +#define GTZC_CFGR1_UART5_Pos (16U) +#define GTZC_CFGR1_UART5_Msk (0x01UL << GTZC_CFGR1_UART5_Pos) +#define GTZC_CFGR1_I2C1_Pos (17U) +#define GTZC_CFGR1_I2C1_Msk (0x01UL << GTZC_CFGR1_I2C1_Pos) +#define GTZC_CFGR1_I2C2_Pos (18U) +#define GTZC_CFGR1_I2C2_Msk (0x01UL << GTZC_CFGR1_I2C2_Pos) +#define GTZC_CFGR1_I3C1_Pos (19U) +#define GTZC_CFGR1_I3C1_Msk (0x01UL << GTZC_CFGR1_I3C1_Pos) +#define GTZC_CFGR1_CRS_Pos (20U) +#define GTZC_CFGR1_CRS_Msk (0x01UL << GTZC_CFGR1_CRS_Pos) +#define GTZC_CFGR1_USART6_Pos (21U) +#define GTZC_CFGR1_USART6_Msk (0x01UL << GTZC_CFGR1_USART6_Pos) +#define GTZC_CFGR1_HDMICEC_Pos (24U) +#define GTZC_CFGR1_HDMICEC_Msk (0x01UL << GTZC_CFGR1_HDMICEC_Pos) +#define GTZC_CFGR1_DAC1_Pos (25U) +#define GTZC_CFGR1_DAC1_Msk (0x01UL << GTZC_CFGR1_DAC1_Pos) +#define GTZC_CFGR1_UART7_Pos (26U) +#define GTZC_CFGR1_UART7_Msk (0x01UL << GTZC_CFGR1_UART7_Pos) +#define GTZC_CFGR1_UART8_Pos (27U) +#define GTZC_CFGR1_UART8_Msk (0x01UL << GTZC_CFGR1_UART8_Pos) +#define GTZC_CFGR1_DTS_Pos (30U) +#define GTZC_CFGR1_DTS_Msk (0x01UL << GTZC_CFGR1_DTS_Pos) +#define GTZC_CFGR1_LPTIM2_Pos (31U) +#define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) + +/*************** Bits definition for register x=2 (TZSC1) *************/ +#define GTZC_CFGR2_FDCAN1_Pos (0U) +#define GTZC_CFGR2_FDCAN1_Msk (0x01UL << GTZC_CFGR2_FDCAN1_Pos) +#define GTZC_CFGR2_FDCAN2_Pos (1U) +#define GTZC_CFGR2_FDCAN2_Msk (0x01UL << GTZC_CFGR2_FDCAN2_Pos) +#define GTZC_CFGR2_UCPD1_Pos (2U) +#define GTZC_CFGR2_UCPD1_Msk (0x01UL << GTZC_CFGR2_UCPD1_Pos) +#define GTZC_CFGR2_COMP_Pos (4U) +#define GTZC_CFGR2_COMP_Msk (0x01UL << GTZC_CFGR2_COMP_Pos) +#define GTZC_CFGR2_TIM1_Pos (8U) +#define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) +#define GTZC_CFGR2_SPI1_Pos (9U) +#define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) +#define GTZC_CFGR2_TIM8_Pos (10U) +#define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos) +#define GTZC_CFGR2_USART1_Pos (11U) +#define GTZC_CFGR2_USART1_Msk (0x01UL << GTZC_CFGR2_USART1_Pos) +#define GTZC_CFGR2_TIM15_Pos (12U) +#define GTZC_CFGR2_TIM15_Msk (0x01UL << GTZC_CFGR2_TIM15_Pos) +#define GTZC_CFGR2_SPI4_Pos (15U) +#define GTZC_CFGR2_SPI4_Msk (0x01UL << GTZC_CFGR2_SPI4_Pos) +#define GTZC_CFGR2_USB_Pos (19U) +#define GTZC_CFGR2_USB_Msk (0x01UL << GTZC_CFGR2_USB_Pos) +#define GTZC_CFGR2_LPUART1_Pos (25U) +#define GTZC_CFGR2_LPUART1_Msk (0x01UL << GTZC_CFGR2_LPUART1_Pos) +#define GTZC_CFGR2_I2C3_Pos (26U) +#define GTZC_CFGR2_I2C3_Msk (0x01UL << GTZC_CFGR2_I2C3_Pos) +#define GTZC_CFGR2_LPTIM1_Pos (28U) +#define GTZC_CFGR2_LPTIM1_Msk (0x01UL << GTZC_CFGR2_LPTIM1_Pos) + +/*************** Bits definition for register x=3 (TZSC1) *************/ +#define GTZC_CFGR3_VREFBUF_Pos (1U) +#define GTZC_CFGR3_VREFBUF_Msk (0x01UL << GTZC_CFGR3_VREFBUF_Pos) +#define GTZC_CFGR3_I3C2_Pos (2U) +#define GTZC_CFGR3_I3C2_Msk (0x01UL << GTZC_CFGR3_I3C2_Pos) +#define GTZC_CFGR3_CCB_Pos (4U) +#define GTZC_CFGR3_CCB_Msk (0x01UL << GTZC_CFGR3_CCB_Pos) +#define GTZC_CFGR3_ADC3_Pos (6U) +#define GTZC_CFGR3_ADC3_Msk (0x01UL << GTZC_CFGR3_ADC3_Pos) +#define GTZC_CFGR3_CRC_Pos (8U) +#define GTZC_CFGR3_CRC_Msk (0x01UL << GTZC_CFGR3_CRC_Pos) +#define GTZC_CFGR3_CORDIC_Pos (9U) +#define GTZC_CFGR3_CORDIC_Msk (0x01UL << GTZC_CFGR3_CORDIC_Pos) +#define GTZC_CFGR3_ETHERNET_Pos (11U) +#define GTZC_CFGR3_ETHERNET_Msk (0x01UL << GTZC_CFGR3_ETHERNET_Pos) +#define GTZC_CFGR3_ICACHE_REG_Pos (12U) +#define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) +#define GTZC_CFGR3_DCACHE1_REG_Pos (13U) +#define GTZC_CFGR3_DCACHE1_REG_Msk (0x01UL << GTZC_CFGR3_DCACHE1_REG_Pos) +#define GTZC_CFGR3_ADC_Pos (14U) +#define GTZC_CFGR3_ADC_Msk (0x01UL << GTZC_CFGR3_ADC_Pos) +#define GTZC_CFGR3_AES_Pos (16U) +#define GTZC_CFGR3_AES_Msk (0x01UL << GTZC_CFGR3_AES_Pos) +#define GTZC_CFGR3_HASH_Pos (17U) +#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) +#define GTZC_CFGR3_RNG_Pos (18U) +#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos) +#define GTZC_CFGR3_SAES_Pos (19U) +#define GTZC_CFGR3_SAES_Msk (0x01UL << GTZC_CFGR3_SAES_Pos) +#define GTZC_CFGR3_PKA_Pos (20U) +#define GTZC_CFGR3_PKA_Msk (0x01UL << GTZC_CFGR3_PKA_Pos) +#define GTZC_CFGR3_SDMMC1_Pos (21U) +#define GTZC_CFGR3_SDMMC1_Msk (0x01UL << GTZC_CFGR3_SDMMC1_Pos) +#define GTZC_CFGR3_FMC_REG_Pos (23U) +#define GTZC_CFGR3_FMC_REG_Msk (0x01UL << GTZC_CFGR3_FMC_REG_Pos) +#define GTZC_CFGR3_OCTOSPI1_Pos (24U) +#define GTZC_CFGR3_OCTOSPI1_Msk (0x01UL << GTZC_CFGR3_OCTOSPI1_Pos) +#define GTZC_CFGR3_RAMCFG_Pos (26U) +#define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) + +/*************** Bits definition for register x=4 (TZSC1) *************/ +#define GTZC_CFGR4_GPDMA1_Pos (0U) +#define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) +#define GTZC_CFGR4_GPDMA2_Pos (1U) +#define GTZC_CFGR4_GPDMA2_Msk (0x01UL << GTZC_CFGR4_GPDMA2_Pos) +#define GTZC_CFGR4_FLASH_Pos (2U) +#define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos) +#define GTZC_CFGR4_FLASH_REG_Pos (3U) +#define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos) + +#define GTZC_CFGR4_OTFDEC1_Pos (4U) +#define GTZC_CFGR4_OTFDEC1_Msk (0x01UL << GTZC_CFGR4_OTFDEC1_Pos) +#define GTZC_CFGR4_SBS_Pos (6U) +#define GTZC_CFGR4_SBS_Msk (0x01UL << GTZC_CFGR4_SBS_Pos) +#define GTZC_CFGR4_RTC_Pos (7U) +#define GTZC_CFGR4_RTC_Msk (0x01UL << GTZC_CFGR4_RTC_Pos) +#define GTZC_CFGR4_TAMP_Pos (8U) +#define GTZC_CFGR4_TAMP_Msk (0x01UL << GTZC_CFGR4_TAMP_Pos) +#define GTZC_CFGR4_PWR_Pos (9U) +#define GTZC_CFGR4_PWR_Msk (0x01UL << GTZC_CFGR4_PWR_Pos) +#define GTZC_CFGR4_RCC_Pos (10U) +#define GTZC_CFGR4_RCC_Msk (0x01UL << GTZC_CFGR4_RCC_Pos) +#define GTZC_CFGR4_EXTI_Pos (11U) +#define GTZC_CFGR4_EXTI_Msk (0x01UL << GTZC_CFGR4_EXTI_Pos) +#define GTZC_CFGR4_PLAY1_Pos (12U) +#define GTZC_CFGR4_PLAY1_Msk (0x01UL << GTZC_CFGR4_PLAY1_Pos) +#define GTZC_CFGR4_TZSC_Pos (16U) +#define GTZC_CFGR4_TZSC_Msk (0x01UL << GTZC_CFGR4_TZSC_Pos) +#define GTZC_CFGR4_TZIC_Pos (17U) +#define GTZC_CFGR4_TZIC_Msk (0x01UL << GTZC_CFGR4_TZIC_Pos) +#define GTZC_CFGR4_OCTOSPI1_MEM_Pos (18U) +#define GTZC_CFGR4_OCTOSPI1_MEM_Msk (0x01UL << GTZC_CFGR4_OCTOSPI1_MEM_Pos) +#define GTZC_CFGR4_FMC_MEM_Pos (19U) +#define GTZC_CFGR4_FMC_MEM_Msk (0x01UL << GTZC_CFGR4_FMC_MEM_Pos) +#define GTZC_CFGR4_BKPSRAM_Pos (20U) +#define GTZC_CFGR4_BKPSRAM_Msk (0x01UL << GTZC_CFGR4_BKPSRAM_Pos) +#define GTZC_CFGR4_SRAM1_Pos (24U) +#define GTZC_CFGR4_SRAM1_Msk (0x01UL << GTZC_CFGR4_SRAM1_Pos) +#define GTZC_CFGR4_MPCBB1_REG_Pos (25U) +#define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos) +#define GTZC_CFGR4_SRAM2_Pos (26U) +#define GTZC_CFGR4_SRAM2_Msk (0x01UL << GTZC_CFGR4_SRAM2_Pos) +#define GTZC_CFGR4_MPCBB2_REG_Pos (27U) +#define GTZC_CFGR4_MPCBB2_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos) +#define GTZC_CFGR4_SRAM3_Pos (28U) +#define GTZC_CFGR4_SRAM3_Msk (0x01UL << GTZC_CFGR4_SRAM3_Pos) +#define GTZC_CFGR4_MPCBB3_REG_Pos (29U) +#define GTZC_CFGR4_MPCBB3_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB3_REG_Pos) + +/******************* Bits definition for GTZC_TZSC1_SECCFGR1 register ***************/ +#define GTZC_TZSC1_SECCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZSC1_SECCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZSC1_SECCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZSC1_SECCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZSC1_SECCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZSC1_SECCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZSC1_SECCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZSC1_SECCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZSC1_SECCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZSC1_SECCFGR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZSC1_SECCFGR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZSC1_SECCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZSC1_SECCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZSC1_SECCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZSC1_SECCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZSC1_SECCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZSC1_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZSC1_SECCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZSC1_SECCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZSC1_SECCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZSC1_SECCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZSC1_SECCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZSC1_SECCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZSC1_SECCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZSC1_SECCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZSC1_SECCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZSC1_SECCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZSC1_SECCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZSC1_SECCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZSC1_SECCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZSC1_SECCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZSC1_SECCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZSC1_SECCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZSC1_SECCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZSC1_SECCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZSC1_SECCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZSC1_SECCFGR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZSC1_SECCFGR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZSC1_SECCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZSC1_SECCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZSC1_SECCFGR1_UART7_Pos GTZC_CFGR1_UART7_Pos +#define GTZC_TZSC1_SECCFGR1_UART7_Msk GTZC_CFGR1_UART7_Msk +#define GTZC_TZSC1_SECCFGR1_UART8_Pos GTZC_CFGR1_UART8_Pos +#define GTZC_TZSC1_SECCFGR1_UART8_Msk GTZC_CFGR1_UART8_Msk +#define GTZC_TZSC1_SECCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZSC1_SECCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZSC1_SECCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/ +#define GTZC_TZSC1_SECCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZSC1_SECCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZSC1_SECCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZSC1_SECCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZSC1_SECCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZSC1_SECCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZSC1_SECCFGR2_COMP_Pos GTZC_CFGR2_COMP_Pos +#define GTZC_TZSC1_SECCFGR2_COMP_Msk GTZC_CFGR2_COMP_Msk +#define GTZC_TZSC1_SECCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZSC1_SECCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZSC1_SECCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZSC1_SECCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZSC1_SECCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZSC1_SECCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZSC1_SECCFGR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZSC1_SECCFGR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZSC1_SECCFGR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZSC1_SECCFGR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZSC1_SECCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZSC1_SECCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZSC1_SECCFGR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZSC1_SECCFGR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZSC1_SECCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZSC1_SECCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZSC_SECCFGR3 register ***************/ +#define GTZC_TZSC1_SECCFGR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZSC1_SECCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZSC1_SECCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZSC1_SECCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZSC1_SECCFGR3_CCB_Pos GTZC_CFGR3_CCB_Pos +#define GTZC_TZSC1_SECCFGR3_CCB_Msk GTZC_CFGR3_CCB_Msk +#define GTZC_TZSC1_SECCFGR3_ADC3_Pos GTZC_CFGR3_ADC3_Pos +#define GTZC_TZSC1_SECCFGR3_ADC3_Msk GTZC_CFGR3_ADC3_Msk +#define GTZC_TZSC1_SECCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZSC1_SECCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZSC1_SECCFGR3_CORDIC_Pos GTZC_CFGR3_CORDIC_Pos +#define GTZC_TZSC1_SECCFGR3_CORDIC_Msk GTZC_CFGR3_CORDIC_Msk +#define GTZC_TZSC1_SECCFGR3_ETHERNET_Pos GTZC_CFGR3_ETHERNET_Pos +#define GTZC_TZSC1_SECCFGR3_ETHERNET_Msk GTZC_CFGR3_ETHERNET_Msk +#define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZSC1_SECCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZSC1_SECCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZSC1_SECCFGR3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZSC1_SECCFGR3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZSC1_SECCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZSC1_SECCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZSC1_SECCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZSC1_SECCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZSC1_SECCFGR3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZSC1_SECCFGR3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZSC1_SECCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZSC1_SECCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZSC1_SECCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZSC1_SECCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZSC1_SECCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZSC1_SECCFGR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZSC1_SECCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZSC1_SECCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/ +#define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZSC1_PRIVCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZSC1_PRIVCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZSC1_PRIVCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZSC1_PRIVCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZSC1_PRIVCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZSC1_PRIVCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZSC1_PRIVCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZSC1_PRIVCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZSC1_PRIVCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZSC1_PRIVCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZSC1_PRIVCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZSC1_PRIVCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZSC1_PRIVCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZSC1_PRIVCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZSC1_PRIVCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZSC1_PRIVCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART7_Pos GTZC_CFGR1_UART7_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART7_Msk GTZC_CFGR1_UART7_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART8_Pos GTZC_CFGR1_UART8_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART8_Msk GTZC_CFGR1_UART8_Msk +#define GTZC_TZSC1_PRIVCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZSC1_PRIVCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/ +#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZSC1_PRIVCFGR2_COMP_Pos GTZC_CFGR2_COMP_Pos +#define GTZC_TZSC1_PRIVCFGR2_COMP_Msk GTZC_CFGR2_COMP_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZSC1_PRIVCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZSC1_PRIVCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZSC1_PRIVCFGR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZSC1_PRIVCFGR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZSC1_PRIVCFGR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZSC1_PRIVCFGR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZSC1_PRIVCFGR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZSC1_PRIVCFGR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR3 register ***************/ +#define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZSC1_PRIVCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZSC1_PRIVCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZSC1_PRIVCFGR3_CCB_Pos GTZC_CFGR3_CCB_Pos +#define GTZC_TZSC1_PRIVCFGR3_CCB_Msk GTZC_CFGR3_CCB_Msk +#define GTZC_TZSC1_PRIVCFGR3_ADC3_Pos GTZC_CFGR3_ADC3_Pos +#define GTZC_TZSC1_PRIVCFGR3_ADC3_Msk GTZC_CFGR3_ADC3_Msk +#define GTZC_TZSC1_PRIVCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZSC1_PRIVCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZSC1_PRIVCFGR3_CORDIC_Pos GTZC_CFGR3_CORDIC_Pos +#define GTZC_TZSC1_PRIVCFGR3_CORDIC_Msk GTZC_CFGR3_CORDIC_Msk +#define GTZC_TZSC1_PRIVCFGR3_ETHERNET_Pos GTZC_CFGR3_ETHERNET_Pos +#define GTZC_TZSC1_PRIVCFGR3_ETHERNET_Msk GTZC_CFGR3_ETHERNET_Msk +#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZSC1_PRIVCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZSC1_PRIVCFGR3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZSC1_PRIVCFGR3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZSC1_PRIVCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZSC1_PRIVCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZSC1_PRIVCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZSC1_PRIVCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZSC1_PRIVCFGR3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZSC1_PRIVCFGR3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZSC1_PRIVCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZSC1_PRIVCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_IER1 register ***************/ +#define GTZC_TZIC1_IER1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_IER1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_IER1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_IER1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_IER1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_IER1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_IER1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_IER1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_IER1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_IER1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_IER1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_IER1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_IER1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_IER1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_IER1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_IER1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_IER1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_IER1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_IER1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_IER1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_IER1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_IER1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_IER1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_IER1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_IER1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_IER1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_IER1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_IER1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_IER1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_IER1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_IER1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_IER1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_IER1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_IER1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_IER1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_IER1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_IER1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_IER1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_IER1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_IER1_UART7_Pos GTZC_CFGR1_UART7_Pos +#define GTZC_TZIC1_IER1_UART7_Msk GTZC_CFGR1_UART7_Msk +#define GTZC_TZIC1_IER1_UART8_Pos GTZC_CFGR1_UART8_Pos +#define GTZC_TZIC1_IER1_UART8_Msk GTZC_CFGR1_UART8_Msk +#define GTZC_TZIC1_IER1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_IER1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_IER1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_IER2 register ***************/ +#define GTZC_TZIC1_IER2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_IER2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_IER2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_IER2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_IER2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_IER2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_IER2_COMP_Pos GTZC_CFGR2_COMP_Pos +#define GTZC_TZIC1_IER2_COMP_Msk GTZC_CFGR2_COMP_Msk +#define GTZC_TZIC1_IER2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_IER2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_IER2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_IER2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_IER2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_IER2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_IER2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_IER2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_IER2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_IER2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_IER2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_IER2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_IER2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_IER2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_IER2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_IER2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_IER2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZIC_IER3 register ***************/ +#define GTZC_TZIC1_IER3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_IER3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_IER3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_IER3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_IER3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_IER3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_IER3_CCB_Pos GTZC_CFGR3_CCB_Pos +#define GTZC_TZIC1_IER3_CCB_Msk GTZC_CFGR3_CCB_Msk +#define GTZC_TZIC1_IER3_ADC3_Pos GTZC_CFGR3_ADC3_Pos +#define GTZC_TZIC1_IER3_ADC3_Msk GTZC_CFGR3_ADC3_Msk +#define GTZC_TZIC1_IER3_CORDIC_Pos GTZC_CFGR3_CORDIC_Pos +#define GTZC_TZIC1_IER3_CORDIC_Msk GTZC_CFGR3_CORDIC_Msk +#define GTZC_TZIC1_IER3_ETHERNET_Pos GTZC_CFGR3_ETHERNET_Pos +#define GTZC_TZIC1_IER3_ETHERNET_Msk GTZC_CFGR3_ETHERNET_Msk +#define GTZC_TZIC1_IER3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_IER3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_IER3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_IER3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_IER3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_IER3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_IER3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_IER3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_IER3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZIC1_IER3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZIC1_IER3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_IER3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_IER3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_IER3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_IER3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZIC1_IER3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZIC1_IER3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_IER3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_IER3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_IER3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_IER3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_IER3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_IER3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_IER3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_IER3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_IER3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_TZIC1_IER4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_IER4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_IER4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_IER4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_IER4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_IER4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_IER4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_IER4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_IER4_OTFDEC1_Pos GTZC_CFGR4_OTFDEC1_Pos +#define GTZC_TZIC1_IER4_OTFDEC1_Msk GTZC_CFGR4_OTFDEC1_Msk +#define GTZC_TZIC1_IER4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_IER4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_IER4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_IER4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_IER4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_IER4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_IER4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_IER4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_IER4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_IER4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_IER4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_IER4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_IER4_PLAY1_Pos GTZC_CFGR4_PLAY1_Pos +#define GTZC_TZIC1_IER4_PLAY1_Msk GTZC_CFGR4_PLAY1_Msk +#define GTZC_TZIC1_IER4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_IER4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_IER4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_IER4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_IER4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_IER4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_IER4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_IER4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_IER4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_IER4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_IER4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_IER4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_IER4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_IER4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_IER4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_IER4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/******************* Bits definition for GTZC_TZIC_SR1 register **************/ +#define GTZC_TZIC1_SR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_SR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_SR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_SR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_SR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_SR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_SR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_SR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_SR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_SR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_SR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_SR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_SR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_SR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_SR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_SR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_SR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_SR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_SR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_SR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_SR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_SR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_SR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_SR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_SR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_SR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_SR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_SR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_SR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_SR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_SR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_SR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_SR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_SR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_SR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_SR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_SR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_SR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_SR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_SR1_UART7_Pos GTZC_CFGR1_UART7_Pos +#define GTZC_TZIC1_SR1_UART7_Msk GTZC_CFGR1_UART7_Msk +#define GTZC_TZIC1_SR1_UART8_Pos GTZC_CFGR1_UART8_Pos +#define GTZC_TZIC1_SR1_UART8_Msk GTZC_CFGR1_UART8_Msk +#define GTZC_TZIC1_SR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_SR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_SR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_SR2 register **************/ +#define GTZC_TZIC1_SR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_SR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_SR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_SR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_SR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_SR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_SR2_COMP_Pos GTZC_CFGR2_COMP_Pos +#define GTZC_TZIC1_SR2_COMP_Msk GTZC_CFGR2_COMP_Msk +#define GTZC_TZIC1_SR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_SR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_SR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_SR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_SR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_SR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_SR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_SR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_SR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_SR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_SR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_SR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_SR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_SR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_SR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_SR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_SR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZIC_SR3 register **************/ +#define GTZC_TZIC1_SR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_SR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_SR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_SR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_SR3_CCB_Pos GTZC_CFGR3_CCB_Pos +#define GTZC_TZIC1_SR3_CCB_Msk GTZC_CFGR3_CCB_Msk +#define GTZC_TZIC1_SR3_ADC3_Pos GTZC_CFGR3_ADC3_Pos +#define GTZC_TZIC1_SR3_ADC3_Msk GTZC_CFGR3_ADC3_Msk +#define GTZC_TZIC1_SR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_SR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_SR3_CORDIC_Pos GTZC_CFGR3_CORDIC_Pos +#define GTZC_TZIC1_SR3_CORDIC_Msk GTZC_CFGR3_CORDIC_Msk +#define GTZC_TZIC1_SR3_ETHERNET_Pos GTZC_CFGR3_ETHERNET_Pos +#define GTZC_TZIC1_SR3_ETHERNET_Msk GTZC_CFGR3_ETHERNET_Msk +#define GTZC_TZIC1_SR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_SR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_SR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_SR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_SR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_SR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_SR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_SR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_SR3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZIC1_SR3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZIC1_SR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_SR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_SR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_SR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_SR3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZIC1_SR3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZIC1_SR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_SR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_SR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_SR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_SR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_SR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_SR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_SR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_SR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_SR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_SR4 register ***************/ +#define GTZC_TZIC1_SR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_SR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_SR4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_SR4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_SR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_SR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_SR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_SR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_SR4_OTFDEC1_Pos GTZC_CFGR4_OTFDEC1_Pos +#define GTZC_TZIC1_SR4_OTFDEC1_Msk GTZC_CFGR4_OTFDEC1_Msk +#define GTZC_TZIC1_SR4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_SR4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_SR4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_SR4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_SR4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_SR4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_SR4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_SR4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_SR4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_SR4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_SR4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_SR4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_SR4_PLAY1_Pos GTZC_CFGR4_PLAY1_Pos +#define GTZC_TZIC1_SR4_PLAY1_Msk GTZC_CFGR4_PLAY1_Msk +#define GTZC_TZIC1_SR4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_SR4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_SR4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_SR4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_SR4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_SR4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_SR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_SR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_SR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_SR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_SR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_SR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_SR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_SR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_SR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_SR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/****************** Bits definition for GTZC_TZIC_FCR1 register ****************/ +#define GTZC_TZIC1_FCR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_FCR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_FCR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_FCR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_FCR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_FCR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_FCR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_FCR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_FCR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_FCR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_FCR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_FCR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_FCR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_FCR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_FCR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_FCR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_FCR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_FCR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_FCR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_FCR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_FCR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_FCR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_FCR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_FCR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_FCR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_FCR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_FCR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_FCR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_FCR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_FCR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_FCR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_FCR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_FCR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_FCR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_FCR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_FCR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_FCR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_FCR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_FCR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_FCR1_UART7_Pos GTZC_CFGR1_UART7_Pos +#define GTZC_TZIC1_FCR1_UART7_Msk GTZC_CFGR1_UART7_Msk +#define GTZC_TZIC1_FCR1_UART8_Pos GTZC_CFGR1_UART8_Pos +#define GTZC_TZIC1_FCR1_UART8_Msk GTZC_CFGR1_UART8_Msk +#define GTZC_TZIC1_FCR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_FCR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_FCR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_FCR2 register **************/ +#define GTZC_TZIC1_FCR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_FCR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_FCR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_FCR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_FCR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_FCR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_FCR2_COMP_Pos GTZC_CFGR2_COMP_Pos +#define GTZC_TZIC1_FCR2_COMP_Msk GTZC_CFGR2_COMP_Msk +#define GTZC_TZIC1_FCR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_FCR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_FCR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_FCR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_FCR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_FCR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_FCR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_FCR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_FCR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_FCR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_FCR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_FCR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_FCR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_FCR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_FCR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_FCR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_FCR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/****************** Bits definition for GTZC_TZIC_FCR3 register ****************/ +#define GTZC_TZIC1_FCR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_FCR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_FCR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_FCR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_FCR3_CCB_Pos GTZC_CFGR3_CCB_Pos +#define GTZC_TZIC1_FCR3_CCB_Msk GTZC_CFGR3_CCB_Msk +#define GTZC_TZIC1_FCR3_ADC3_Pos GTZC_CFGR3_ADC3_Pos +#define GTZC_TZIC1_FCR3_ADC3_Msk GTZC_CFGR3_ADC3_Msk +#define GTZC_TZIC1_FCR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_FCR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_FCR3_CORDIC_Pos GTZC_CFGR3_CORDIC_Pos +#define GTZC_TZIC1_FCR3_CORDIC_Msk GTZC_CFGR3_CORDIC_Msk +#define GTZC_TZIC1_FCR3_ETHERNET_Pos GTZC_CFGR3_ETHERNET_Pos +#define GTZC_TZIC1_FCR3_ETHERNET_Msk GTZC_CFGR3_ETHERNET_Msk +#define GTZC_TZIC1_FCR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_FCR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_FCR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_FCR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_FCR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_FCR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_FCR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_FCR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_FCR3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZIC1_FCR3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZIC1_FCR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_FCR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_FCR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_FCR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_FCR3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZIC1_FCR3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZIC1_FCR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_FCR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_FCR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_FCR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_FCR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_FCR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_FCR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_FCR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_FCR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_FCR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_FCR4 register ***************/ +#define GTZC_TZIC1_FCR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_FCR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_FCR4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_FCR4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_FCR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_FCR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_FCR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_FCR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_FCR4_OTFDEC1_Pos GTZC_CFGR4_OTFDEC1_Pos +#define GTZC_TZIC1_FCR4_OTFDEC1_Msk GTZC_CFGR4_OTFDEC1_Msk +#define GTZC_TZIC1_FCR4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_FCR4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_FCR4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_FCR4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_FCR4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_FCR4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_FCR4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_FCR4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_FCR4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_FCR4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_FCR4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_FCR4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_FCR4_PLAY1_Pos GTZC_CFGR4_PLAY1_Pos +#define GTZC_TZIC1_FCR4_PLAY1_Msk GTZC_CFGR4_PLAY1_Msk +#define GTZC_TZIC1_FCR4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_FCR4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_FCR4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_FCR4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_FCR4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_FCR4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_FCR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_FCR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_FCR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_FCR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_FCR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_FCR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_FCR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_FCR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_FCR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_FCR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/******************* Bits definition for GTZC_MPCBB_CR register *****************/ +#define GTZC_MPCBB_CR_GLOCK_Pos (0U) +#define GTZC_MPCBB_CR_GLOCK_Msk (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CR_INVSECSTATE_Pos (30U) +#define GTZC_MPCBB_CR_INVSECSTATE_Msk (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CR_SRWILADIS_Pos (31U) +#define GTZC_MPCBB_CR_SRWILADIS_Msk (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for GTZC_MPCBB_CFGLOCKR1 register ************/ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos (0U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos (1U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos (2U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos (3U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos (4U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos (5U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos (6U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos (7U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos (8U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos (9U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos (10U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos (11U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos (12U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos (13U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos (14U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos (15U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos (16U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos (17U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos (18U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos (19U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos (20U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos (21U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos (22U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos (23U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos (24U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos (25U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos (26U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos (27U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos (28U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos (29U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos (30U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos (31U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos) /*!< 0x80000000 */ + + +/******************************************************************************/ +/* */ +/* UCPD */ +/* */ +/******************************************************************************/ +/******************** Bits definition for UCPD_CFG1 register *******************/ +#define UCPD_CFG1_HBITCLKDIV_Pos (0U) +#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */ +#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */ +#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */ +#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */ +#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */ +#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */ +#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */ +#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */ +#define UCPD_CFG1_IFRGAP_Pos (6U) +#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */ +#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */ +#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */ +#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */ +#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */ +#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */ +#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */ +#define UCPD_CFG1_TRANSWIN_Pos (11U) +#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */ +#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */ +#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */ +#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */ +#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */ +#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */ +#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */ +#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U) +#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */ +#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */ +#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */ +#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */ +#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */ +#define UCPD_CFG1_RXORDSETEN_Pos (20U) +#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x1FF00000 */ +#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */ +#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00100000 */ +#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00200000 */ +#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00400000 */ +#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00800000 */ +#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x01000000 */ +#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x02000000 */ +#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x04000000 */ +#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x08000000 */ +#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x10000000 */ +#define UCPD_CFG1_TXDMAEN_Pos (29U) +#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */ +#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define UCPD_CFG1_RXDMAEN_Pos (30U) +#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */ +#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define UCPD_CFG1_UCPDEN_Pos (31U) +#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */ +#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */ + +/******************** Bits definition for UCPD_CFG2 register *******************/ +#define UCPD_CFG2_RXFILTDIS_Pos (0U) +#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */ +#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */ +#define UCPD_CFG2_RXFILT2N3_Pos (1U) +#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */ +#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */ +#define UCPD_CFG2_FORCECLK_Pos (2U) +#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */ +#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */ +#define UCPD_CFG2_WUPEN_Pos (3U) +#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */ +#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define UCPD_CFG2_RXAFILTEN_Pos (8U) +#define UCPD_CFG2_RXAFILTEN_Msk (0x1UL << UCPD_CFG2_RXAFILTEN_Pos) /*!< 0x00000100 */ +#define UCPD_CFG2_RXAFILTEN UCPD_CFG2_RXAFILTEN_Msk /*!< Rx analog filter enable */ + +/******************** Bits definition for UCPD_CFG3 register *******************/ +#define UCPD_CFG3_TRIM_CC1_RD_Pos (0U) +#define UCPD_CFG3_TRIM_CC1_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RD_Pos) /*!< 0x0000000F */ +#define UCPD_CFG3_TRIM_CC1_RD UCPD_CFG3_TRIM_CC1_RD_Msk /*!< SW trim value for RD resistor (CC1) */ +#define UCPD_CFG3_TRIM_CC1_RP_Pos (9U) +#define UCPD_CFG3_TRIM_CC1_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RP_Pos) /*!< 0x00001E00 */ +#define UCPD_CFG3_TRIM_CC1_RP UCPD_CFG3_TRIM_CC1_RP_Msk /*!< SW trim value for RP current sources (CC1) */ +#define UCPD_CFG3_TRIM_CC2_RD_Pos (16U) +#define UCPD_CFG3_TRIM_CC2_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RD_Pos) /*!< 0x000F0000 */ +#define UCPD_CFG3_TRIM_CC2_RD UCPD_CFG3_TRIM_CC2_RD_Msk /*!< SW trim value for RD resistor (CC2) */ +#define UCPD_CFG3_TRIM_CC2_RP_Pos (25U) +#define UCPD_CFG3_TRIM_CC2_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RP_Pos) /*!< 0x1E000000 */ +#define UCPD_CFG3_TRIM_CC2_RP UCPD_CFG3_TRIM_CC2_RP_Msk /*!< SW trim value for RP current sources (CC2) */ + +/******************** Bits definition for UCPD_CR register ********************/ +#define UCPD_CR_TXMODE_Pos (0U) +#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */ +#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */ +#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */ +#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */ +#define UCPD_CR_TXSEND_Pos (2U) +#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */ +#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */ +#define UCPD_CR_TXHRST_Pos (3U) +#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */ +#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */ +#define UCPD_CR_RXMODE_Pos (4U) +#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */ +#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */ +#define UCPD_CR_PHYRXEN_Pos (5U) +#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */ +#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */ +#define UCPD_CR_PHYCCSEL_Pos (6U) +#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */ +#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */ +#define UCPD_CR_ANASUBMODE_Pos (7U) +#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */ +#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */ +#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */ +#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */ +#define UCPD_CR_ANAMODE_Pos (9U) +#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */ +#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */ +#define UCPD_CR_CCENABLE_Pos (10U) +#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */ +#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */ +#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */ +#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */ +#define UCPD_CR_FRSRXEN_Pos (16U) +#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */ +#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */ +#define UCPD_CR_FRSTX_Pos (17U) +#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */ +#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */ +#define UCPD_CR_RDCH_Pos (18U) +#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */ +#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */ +#define UCPD_CR_CC1TCDIS_Pos (20U) +#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */ +#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */ +#define UCPD_CR_CC2TCDIS_Pos (21U) +#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */ +#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */ + +/******************** Bits definition for UCPD_IMR register *******************/ +#define UCPD_IMR_TXISIE_Pos (0U) +#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */ +#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */ +#define UCPD_IMR_TXMSGDISCIE_Pos (1U) +#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */ +#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */ +#define UCPD_IMR_TXMSGSENTIE_Pos (2U) +#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */ +#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */ +#define UCPD_IMR_TXMSGABTIE_Pos (3U) +#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */ +#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */ +#define UCPD_IMR_HRSTDISCIE_Pos (4U) +#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */ +#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */ +#define UCPD_IMR_HRSTSENTIE_Pos (5U) +#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */ +#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */ +#define UCPD_IMR_TXUNDIE_Pos (6U) +#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */ +#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */ +#define UCPD_IMR_RXNEIE_Pos (8U) +#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */ +#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */ +#define UCPD_IMR_RXORDDETIE_Pos (9U) +#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */ +#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */ +#define UCPD_IMR_RXHRSTDETIE_Pos (10U) +#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */ +#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */ +#define UCPD_IMR_RXOVRIE_Pos (11U) +#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */ +#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */ +#define UCPD_IMR_RXMSGENDIE_Pos (12U) +#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */ +#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */ +#define UCPD_IMR_TYPECEVT1IE_Pos (14U) +#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */ +#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */ +#define UCPD_IMR_TYPECEVT2IE_Pos (15U) +#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */ +#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */ +#define UCPD_IMR_FRSEVTIE_Pos (20U) +#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */ +#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */ + +/******************** Bits definition for UCPD_SR register ********************/ +#define UCPD_SR_TXIS_Pos (0U) +#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */ +#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */ +#define UCPD_SR_TXMSGDISC_Pos (1U) +#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */ +#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */ +#define UCPD_SR_TXMSGSENT_Pos (2U) +#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */ +#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */ +#define UCPD_SR_TXMSGABT_Pos (3U) +#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */ +#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */ +#define UCPD_SR_HRSTDISC_Pos (4U) +#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */ +#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */ +#define UCPD_SR_HRSTSENT_Pos (5U) +#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */ +#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */ +#define UCPD_SR_TXUND_Pos (6U) +#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */ +#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */ +#define UCPD_SR_RXNE_Pos (8U) +#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */ +#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */ +#define UCPD_SR_RXORDDET_Pos (9U) +#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */ +#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */ +#define UCPD_SR_RXHRSTDET_Pos (10U) +#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */ +#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */ +#define UCPD_SR_RXOVR_Pos (11U) +#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */ +#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */ +#define UCPD_SR_RXMSGEND_Pos (12U) +#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */ +#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */ +#define UCPD_SR_RXERR_Pos (13U) +#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */ +#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */ +#define UCPD_SR_TYPECEVT1_Pos (14U) +#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */ +#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */ +#define UCPD_SR_TYPECEVT2_Pos (15U) +#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */ +#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */ +#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U) +#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00030000 */ +#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */ +#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00010000 */ +#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00020000 */ +#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U) +#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x000C0000 */ +#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/** @addtogroup STM32H5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || ((INSTANCE) == ADC1_S) || \ + ((INSTANCE) == ADC2_NS) || ((INSTANCE) == ADC2_S) || \ + ((INSTANCE) == ADC3_NS) || ((INSTANCE) == ADC3_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || ((INSTANCE) == ADC1_S)) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || ((INSTANCE) == ADC12_COMMON_S) || \ + ((INSTANCE) == ADC3_COMMON_NS) || ((INSTANCE) == ADC3_COMMON_S)) +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) + +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************* CORDIC Instances *****************************/ +#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) + +/******************************* CCB Instances ********************************/ +#define IS_CCB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CCB_NS) || ((INSTANCE) == CCB_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S )) +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel1_NS) || ((INSTANCE) == GPDMA2_Channel1_S) || \ + ((INSTANCE) == GPDMA2_Channel2_NS) || ((INSTANCE) == GPDMA2_Channel2_S) || \ + ((INSTANCE) == GPDMA2_Channel3_NS) || ((INSTANCE) == GPDMA2_Channel3_S) || \ + ((INSTANCE) == GPDMA2_Channel4_NS) || ((INSTANCE) == GPDMA2_Channel4_S) || \ + ((INSTANCE) == GPDMA2_Channel5_NS) || ((INSTANCE) == GPDMA2_Channel5_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) IS_DMA_ALL_INSTANCE(INSTANCE) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +/****************************** OTFDEC Instances ********************************/ +#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + + + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* PLAY Instances *******************************/ +#define IS_PLAY_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PLAY1_NS) || ((__INSTANCE__) == PLAY1_S)) + +#define PLAY_INPUT_MUX_NBR(INSTANCE) \ + ((((INSTANCE) == PLAY1_NS) || ((INSTANCE) == PLAY1_S))?16U:0U) + +#define PLAY_LUT_NBR(INSTANCE) \ + ((((INSTANCE) == PLAY1_NS) || ((INSTANCE) == PLAY1_S))?16U:0U) + +#define PLAY_OUTPUT_MUX_NBR(INSTANCE) \ + ((((INSTANCE) == PLAY1_NS) || ((INSTANCE) == PLAY1_S))?16U:0U) + +#define PLAY_SWTRIGGER_NBR(INSTANCE) \ + ((((INSTANCE) == PLAY1_NS) || ((INSTANCE) == PLAY1_S))?16U:0U) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* DTS Instances *******************************/ +#define IS_DTS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DTS_NS) || ((__INSTANCE__) == DTS_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On H5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On H5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************************** I3C Instances *******************************/ +#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || ((INSTANCE) == I3C1_S) || \ + ((INSTANCE) == I3C2_NS) || ((INSTANCE) == I3C2_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \ + ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \ + ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S)) + +/****************************** FDCAN Instances *******************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S) || \ + ((INSTANCE) == FDCAN2_NS) || ((INSTANCE) == FDCAN2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S) || \ + ((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) ) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) +#define IS_TIM_OCXREF_COMP_CLEARINPUT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************************** I2S Instances *******************************/ +#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** CEC Instance *****************************************/ +#define IS_CEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CEC_NS) || ((INSTANCE) == CEC_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* USB DRD FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************* USB DRD FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************** COMP Instances with window mode capability **************/ +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) +/** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32H553xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H553xx_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h index 0833025985..acff23c693 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h @@ -387,11 +387,11 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /** @@ -4432,42 +4432,42 @@ typedef struct /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2U) -#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3U) -#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5U) -#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7U) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8U) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12U) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13U) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16U) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30U) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31U) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0U) @@ -11558,7 +11558,7 @@ typedef struct /**************** Bit definition for XSPI_DCR3 register ******************/ #define XSPI_DCR3_CSBOUND_Pos (16U) #define XSPI_DCR3_CSBOUND_Msk (0x1FUL << XSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */ -#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< Maximum transfer */ +#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< NCS boundary */ /**************** Bit definition for XSPI_DCR4 register ******************/ #define XSPI_DCR4_REFRESH_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h index ab687a3cd3..6b9f4ee628 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h @@ -392,11 +392,11 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /** @@ -4653,42 +4653,42 @@ typedef struct /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2U) -#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3U) -#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5U) -#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7U) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8U) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12U) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13U) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16U) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30U) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31U) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0U) @@ -13643,7 +13643,7 @@ typedef struct /**************** Bit definition for XSPI_DCR3 register ******************/ #define XSPI_DCR3_CSBOUND_Pos (16U) #define XSPI_DCR3_CSBOUND_Msk (0x1FUL << XSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */ -#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< Maximum transfer */ +#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< NCS boundary */ /**************** Bit definition for XSPI_DCR4 register ******************/ #define XSPI_DCR4_REFRESH_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h index a480b61a0d..116e97783d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h @@ -429,11 +429,11 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /** @@ -4812,42 +4812,42 @@ typedef struct /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2U) -#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3U) -#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5U) -#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7U) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8U) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12U) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13U) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16U) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30U) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31U) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0U) @@ -14035,7 +14035,7 @@ typedef struct /**************** Bit definition for XSPI_DCR3 register ******************/ #define XSPI_DCR3_CSBOUND_Pos (16U) #define XSPI_DCR3_CSBOUND_Msk (0x1FUL << XSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */ -#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< Maximum transfer */ +#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< NCS boundary */ /**************** Bit definition for XSPI_DCR4 register ******************/ #define XSPI_DCR4_REFRESH_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5e4xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5e4xx.h index 4a13b04e71..2ee444acdd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5e4xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5e4xx.h @@ -336,7 +336,7 @@ typedef struct __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ - uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t MISR; /*!< masked interrupt status register, Address offset: 0x5C */ __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ @@ -422,10 +422,14 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ } RNG_TypeDef; /** @@ -2407,7 +2411,6 @@ typedef struct #define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) #define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) #define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) -#define CCB_BASE_NS (AHB2PERIPH_BASE_NS + 0xA7C00UL) /*!< APB3 Non secure peripherals */ #define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) @@ -2620,7 +2623,6 @@ typedef struct #define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) #define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) #define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) -#define CCB_BASE_S (AHB2PERIPH_BASE_S + 0xA7C00UL) /*!< APB3 secure peripherals */ #define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) @@ -3033,7 +3035,6 @@ typedef struct #define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) #define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) #define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) -#define CCB_NS ((CCB_TypeDef *) CCB_BASE_NS) /*!< APB3 Non secure peripherals */ @@ -3223,7 +3224,6 @@ typedef struct #define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) #define RNG_S ((RNG_TypeDef *) RNG_BASE_S) #define PKA_S ((PKA_TypeDef *) PKA_BASE_S) -#define CCB_S ((CCB_TypeDef *) CCB_BASE_S) #define ADC3_S ((ADC_TypeDef *) ADC3_BASE_S) #define ADC3_COMMON_S ((ADC_Common_TypeDef *) ADC3_COMMON_BASE_S) #define USB_OTG_FS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_S) @@ -3705,8 +3705,6 @@ typedef struct #define PKA PKA_S #define PKA_BASE PKA_BASE_S #define PKA_RAM_BASE PKA_RAM_BASE_S -#define CCB CCB_S -#define CCB_BASE CCB_BASE_S #define ETH ETH_S #define ETH_BASE ETH_BASE_S @@ -4240,9 +4238,6 @@ typedef struct #define PKA_BASE PKA_BASE_NS #define PKA_RAM_BASE PKA_RAM_BASE_NS -#define CCB CCB_NS -#define CCB_BASE CCB_BASE_NS - #define ETH ETH_NS #define ETH_BASE ETH_BASE_NS @@ -5403,10 +5398,6 @@ typedef struct #define COMP_CFGR1_WINMODE_Msk (0x1UL << COMP_CFGR1_WINMODE_Pos) /*!< 0x00000010 */ #define COMP_CFGR1_WINMODE COMP_CFGR1_WINMODE_Msk /*!< COMP1 window mode selection bit */ -#define COMP_CFGR1_WINOUT_Pos (5U) -#define COMP_CFGR1_WINOUT_Msk (0x1UL << COMP_CFGR1_WINOUT_Pos) /*!< 0x00000020 */ -#define COMP_CFGR1_WINOUT COMP_CFGR1_WINOUT_Msk /*!< COMP1 window output selection bit */ - #define COMP_CFGR1_ITEN_Pos (6U) #define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ #define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< COMP1 interrupt enable */ @@ -5423,6 +5414,10 @@ typedef struct #define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ #define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ +#define COMP_CFGR1_WINOUT_Pos (14U) +#define COMP_CFGR1_WINOUT_Msk (0x1UL << COMP_CFGR1_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CFGR1_WINOUT COMP_CFGR1_WINOUT_Msk /*!< COMP1 window output selection bit */ + #define COMP_CFGR1_INMSEL_Pos (16U) #define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ #define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< COMP1 input minus selection bit */ @@ -5495,6 +5490,7 @@ typedef struct #define COMP_CFGR2_PWRMODE_0 (0x1UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00001000 */ #define COMP_CFGR2_PWRMODE_1 (0x2UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00002000 */ + #define COMP_CFGR2_INMSEL_Pos (16U) #define COMP_CFGR2_INMSEL_Msk (0xFUL << COMP_CFGR2_INMSEL_Pos) /*!< 0x000F0000 */ #define COMP_CFGR2_INMSEL COMP_CFGR2_INMSEL_Msk /*!< COMP1 input minus selection bit */ @@ -5601,50 +5597,6 @@ typedef struct #define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U) #define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */ #define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS pairs */ -/******************************************************************************/ -/* */ -/* Coupling and chaining bridge (CCB) */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CCB_CR register ******************/ -#define CCB_CR_CCOP_Pos (0U) -#define CCB_CR_CCOP_Msk (0xFFUL << CCB_CR_CCOP_Pos) /*!< 0x000000FF */ -#define CCB_CR_CCOP CCB_CR_CCOP_Msk /*!< Coupling and chaining operation */ -#define CCB_CR_IPRST_Pos (31U) -#define CCB_CR_IPRST_Msk (0x1UL << CCB_CR_IPRST_Pos) /*!< 0x80000000 */ -#define CCB_CR_IPRST CCB_CR_IPRST_Msk /*!< CCB reset */ - -/******************* Bit definition for CCB_SR register ******************/ -#define CCB_SR_OPSTEP_Pos (0U) -#define CCB_SR_OPSTEP_Msk (0x1FUL << CCB_SR_OPSTEP_Pos) /*!< 0x0000001F */ -#define CCB_SR_OPSTEP CCB_SR_OPSTEP_Msk /*!< Operation step */ -#define CCB_SR_OPERR_Pos (8U) -#define CCB_SR_OPERR_Msk (0x3FUL << CCB_SR_OPERR_Pos) /*!< 0x00003F00 */ -#define CCB_SR_OPERR CCB_SR_OPERR_Msk /*!< Operation error */ -#define CCB_SR_BUSY_Pos (16U) -#define CCB_SR_BUSY_Msk (0x1UL << CCB_SR_BUSY_Pos) /*!< 0x00010000 */ -#define CCB_SR_BUSY CCB_SR_BUSY_Msk /*!< CCB busy */ -#define CCB_SR_TAMP_EVT0_Pos (24U) -#define CCB_SR_TAMP_EVT0_Msk (0x1UL << CCB_SR_TAMP_EVT0_Pos) /*!< 0x01000000 */ -#define CCB_SR_TAMP_EVT0 CCB_SR_TAMP_EVT0_Msk /*!< Tamper event 0 flag */ -#define CCB_SR_TAMP_EVT1_Pos (25U) -#define CCB_SR_TAMP_EVT1_Msk (0x1UL << CCB_SR_TAMP_EVT1_Pos) /*!< 0x02000000 */ -#define CCB_SR_TAMP_EVT1 CCB_SR_TAMP_EVT1_Msk /*!< Tamper event 1 flag */ -#define CCB_SR_TAMP_EVT2_Pos (26U) -#define CCB_SR_TAMP_EVT2_Msk (0x1UL << CCB_SR_TAMP_EVT2_Pos) /*!< 0x04000000 */ -#define CCB_SR_TAMP_EVT2 CCB_SR_TAMP_EVT2_Msk /*!< Tamper event 2 flag */ -#define CCB_SR_TAMP_EVT3_Pos (27U) -#define CCB_SR_TAMP_EVT3_Msk (0x1UL << CCB_SR_TAMP_EVT3_Pos) /*!< 0x08000000 */ -#define CCB_SR_TAMP_EVT3 CCB_SR_TAMP_EVT3_Msk /*!< Tamper event 3 flag */ -#define CCB_SR_TAMP_EVT4_Pos (28U) -#define CCB_SR_TAMP_EVT4_Msk (0x1UL << CCB_SR_TAMP_EVT4_Pos) /*!< 0x10000000 */ -#define CCB_SR_TAMP_EVT4 CCB_SR_TAMP_EVT4_Msk /*!< Tamper event 4 flag */ - -#define CCB_SR_TAMP_EVT5_Pos (29U) -#define CCB_SR_TAMP_EVT5_Msk (0x1UL << CCB_SR_TAMP_EVT5_Pos) /*!< 0x20000000 */ -#define CCB_SR_TAMP_EVT5 CCB_SR_TAMP_EVT5_Msk /*!< Tamper event 5 flag */ - /******************************************************************************/ /* */ /* CORDIC calculation unit */ @@ -5861,42 +5813,42 @@ typedef struct /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2U) -#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3U) -#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5U) -#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7U) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8U) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12U) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13U) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16U) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30U) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31U) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0U) @@ -5908,6 +5860,9 @@ typedef struct #define RNG_SR_SECS_Pos (2U) #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ #define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_BUSY_Pos (4U) +#define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ #define RNG_SR_CEIS_Pos (5U) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk @@ -5926,14 +5881,134 @@ typedef struct #define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk -/******************** Bits definition for RNG_HTCR register *******************/ -#define RNG_HTCR_HTCFG_Pos (0U) -#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ -#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** Bits definition for RNG_HTCR0 register *******************/ +#define RNG_HTCR0_HTCFG_Pos (0U) +#define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR0_HTCFG RNG_HTCR0_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR1 register *******************/ +#define RNG_HTCR1_HTCFG_Pos (0U) +#define RNG_HTCR1_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR1_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR1_HTCFG RNG_HTCR1_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR2 register *******************/ +#define RNG_HTCR2_HTCFG_Pos (0U) +#define RNG_HTCR2_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR2_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR2_HTCFG RNG_HTCR2_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR3 register *******************/ +#define RNG_HTCR3_HTCFG_Pos (0U) +#define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk + +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ /******************** RNG Nist Compliance Values ******************************/ -#define RNG_CR_NIST_VALUE (0x00200F00U) -#define RNG_HTCR_NIST_VALUE (0xA2B0U) +#define RNG_HTCRx_VALUE 0x0003FFFF +#define RNG_CR_NIST_VALUE (0x08451F00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) + +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 /******************************************************************************/ /* */ @@ -18394,6 +18469,9 @@ typedef struct #define XSPI_CR_TCEN_Pos (3U) #define XSPI_CR_TCEN_Msk (0x1UL << XSPI_CR_TCEN_Pos) /*!< 0x00000008 */ #define XSPI_CR_TCEN XSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */ +#define XSPI_CR_ADOFFEN_Pos (4U) +#define XSPI_CR_ADOFFEN_Msk (0x1UL << XSPI_CR_ADOFFEN_Pos) /*!< 0x00000010 */ +#define XSPI_CR_ADOFFEN XSPI_CR_ADOFFEN_Msk /*!< Address offset enable */ #define XSPI_CR_DMM_Pos (6U) #define XSPI_CR_DMM_Msk (0x1UL << XSPI_CR_DMM_Pos) /*!< 0x00000040 */ #define XSPI_CR_DMM XSPI_CR_DMM_Msk /*!< Dual-memory configuration */ @@ -18415,6 +18493,9 @@ typedef struct #define XSPI_CR_TOIE_Pos (20U) #define XSPI_CR_TOIE_Msk (0x1UL << XSPI_CR_TOIE_Pos) /*!< 0x00100000 */ #define XSPI_CR_TOIE XSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */ +#define XSPI_CR_BERRIE_Pos (21U) +#define XSPI_CR_BERRIE_Msk (0x1UL << XSPI_CR_BERRIE_Pos) /*!< 0x00200000 */ +#define XSPI_CR_BERRIE XSPI_CR_BERRIE_Msk /*!< Bus error interrupt enable */ #define XSPI_CR_APMS_Pos (22U) #define XSPI_CR_APMS_Msk (0x1UL << XSPI_CR_APMS_Pos) /*!< 0x00400000 */ #define XSPI_CR_APMS XSPI_CR_APMS_Msk /*!< Automatic Poll Mode Stop */ @@ -18461,6 +18542,9 @@ typedef struct #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */ #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */ #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */ +#define XSPI_DCR1_ADOFF_Pos (27U) +#define XSPI_DCR1_ADOFF_Msk (0x1FUL << XSPI_DCR1_ADOFF_Pos) /*!< 0xF8000000 */ +#define XSPI_DCR1_ADOFF XSPI_DCR1_ADOFF_Msk /*!< Address offset */ /**************** Bit definition for XSPI_DCR2 register ******************/ #define XSPI_DCR2_PRESCALER_Pos (0U) @@ -18474,12 +18558,12 @@ typedef struct #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */ /**************** Bit definition for XSPI_DCR3 register ******************/ -#define XSPI_DCR3_MAXTRAN_Pos (0U) -#define XSPI_DCR3_MAXTRAN_Msk (0xFFUL << XSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */ -#define XSPI_DCR3_MAXTRAN XSPI_DCR3_MAXTRAN_Msk /*!< Maximum transfer */ +#define XSPI_DCR3_MAXTRAN_Pos (0U) +#define XSPI_DCR3_MAXTRAN_Msk (0xFFUL << XSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */ +#define XSPI_DCR3_MAXTRAN XSPI_DCR3_MAXTRAN_Msk /*!< Maximum transfer */ #define XSPI_DCR3_CSBOUND_Pos (16U) #define XSPI_DCR3_CSBOUND_Msk (0x1FUL << XSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */ -#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< Maximum transfer */ +#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< NCS boundary */ /**************** Bit definition for XSPI_DCR4 register ******************/ #define XSPI_DCR4_REFRESH_Pos (0U) @@ -18505,6 +18589,9 @@ typedef struct #define XSPI_SR_BUSY_Pos (5U) #define XSPI_SR_BUSY_Msk (0x1UL << XSPI_SR_BUSY_Pos) /*!< 0x00000020 */ #define XSPI_SR_BUSY XSPI_SR_BUSY_Msk /*!< Busy */ +#define XSPI_SR_BERRF_Pos (6U) +#define XSPI_SR_BERRF_Msk (0x1UL << XSPI_SR_BERRF_Pos) /*!< 0x00000040 */ +#define XSPI_SR_BERRF XSPI_SR_BERRF_Msk /*!< Bus error flag */ #define XSPI_SR_FLEVEL_Pos (8U) #define XSPI_SR_FLEVEL_Msk (0x3FUL << XSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */ #define XSPI_SR_FLEVEL XSPI_SR_FLEVEL_Msk /*!< FIFO Level */ @@ -18522,6 +18609,9 @@ typedef struct #define XSPI_FCR_CTOF_Pos (4U) #define XSPI_FCR_CTOF_Msk (0x1UL << XSPI_FCR_CTOF_Pos) /*!< 0x00000010 */ #define XSPI_FCR_CTOF XSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */ +#define XSPI_FCR_CBERRF_Pos (6U) +#define XSPI_FCR_CBERRF_Msk (0x1UL << XSPI_FCR_CBERRF_Pos) /*!< 0x00000040 */ +#define XSPI_FCR_CBERRF XSPI_FCR_CBERRF_Msk /*!< Clear bus error flag */ /**************** Bit definition for XSPI_DLR register *******************/ #define XSPI_DLR_DL_Pos (0U) @@ -18815,6 +18905,9 @@ typedef struct #define OCTOSPI_CR_TCEN_Pos XSPI_CR_TCEN_Pos #define OCTOSPI_CR_TCEN_Msk XSPI_CR_TCEN_Msk /*!< 0x00000008 */ #define OCTOSPI_CR_TCEN XSPI_CR_TCEN /*!< Timeout Counter Enable */ +#define OCTOSPI_CR_ADOFFEN_Pos XSPI_CR_ADOFFEN_Pos +#define OCTOSPI_CR_ADOFFEN_Msk XSPI_CR_ADOFFEN_Msk /*!< 0x00000010 */ +#define OCTOSPI_CR_ADOFFEN XSPI_CR_ADOFFEN /*!< Address offset enable */ #define OCTOSPI_CR_DMM_Pos XSPI_CR_DMM_Pos #define OCTOSPI_CR_DMM_Msk XSPI_CR_DMM_Msk /*!< 0x00000040 */ #define OCTOSPI_CR_DMM XSPI_CR_DMM /*!< Dual Memory Mode */ @@ -18836,6 +18929,9 @@ typedef struct #define OCTOSPI_CR_TOIE_Pos XSPI_CR_TOIE_Pos #define OCTOSPI_CR_TOIE_Msk XSPI_CR_TOIE_Msk /*!< 0x00100000 */ #define OCTOSPI_CR_TOIE XSPI_CR_TOIE /*!< TimeOut Interrupt Enable */ +#define OCTOSPI_CR_BERRIE_Pos XSPI_CR_BERRIE_Pos +#define OCTOSPI_CR_BERRIE_Msk XSPI_CR_BERRIE_Msk /*!< 0x00200000 */ +#define OCTOSPI_CR_BERRIE XSPI_CR_BERRIE /*!< Bus error interrupt enable */ #define OCTOSPI_CR_APMS_Pos XSPI_CR_APMS_Pos #define OCTOSPI_CR_APMS_Msk XSPI_CR_APMS_Msk /*!< 0x00400000 */ #define OCTOSPI_CR_APMS XSPI_CR_APMS /*!< Automatic Poll Mode Stop */ @@ -18882,6 +18978,9 @@ typedef struct #define OCTOSPI_DCR1_MTYP_0 XSPI_DCR1_MTYP_0 /*!< 0x01000000 */ #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02000000 */ #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04000000 */ +#define OCTOSPI_DCR1_ADOFF_Pos XSPI_DCR1_ADOFF_Pos +#define OCTOSPI_DCR1_ADOFF_Msk XSPI_DCR1_ADOFF_Msk /*!< 0xF8000000 */ +#define OCTOSPI_DCR1_ADOFF XSPI_DCR1_ADOFF /*!< Address offset */ /**************** Bit definition for OCTOSPI_DCR2 register ******************/ #define OCTOSPI_DCR2_PRESCALER_Pos XSPI_DCR2_PRESCALER_Pos @@ -18923,6 +19022,9 @@ typedef struct #define OCTOSPI_SR_BUSY_Pos XSPI_SR_BUSY_Pos #define OCTOSPI_SR_BUSY_Msk XSPI_SR_BUSY_Msk /*!< 0x00000020 */ #define OCTOSPI_SR_BUSY XSPI_SR_BUSY /*!< Busy */ +#define OCTOSPI_SR_BERRF_Pos XSPI_SR_BERRF_Pos +#define OCTOSPI_SR_BERRF_Msk XSPI_SR_BERRF_Msk /*!< 0x00000040 */ +#define OCTOSPI_SR_BERRF XSPI_SR_BERRF /*!< Bus error flag */ #define OCTOSPI_SR_FLEVEL_Pos XSPI_SR_FLEVEL_Pos #define OCTOSPI_SR_FLEVEL_Msk (0x3FUL << OCTOSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */ #define OCTOSPI_SR_FLEVEL XSPI_SR_FLEVEL /*!< FIFO Level */ @@ -18940,6 +19042,9 @@ typedef struct #define OCTOSPI_FCR_CTOF_Pos XSPI_FCR_CTOF_Pos #define OCTOSPI_FCR_CTOF_Msk XSPI_FCR_CTOF_Msk /*!< 0x00000010 */ #define OCTOSPI_FCR_CTOF XSPI_FCR_CTOF /*!< Clear Timeout Flag */ +#define OCTOSPI_FCR_CBERRF_Pos XSPI_FCR_CBERRF_Pos +#define OCTOSPI_FCR_CBERRF_Msk XSPI_FCR_CBERRF_Msk /*!< 0x00000040 */ +#define OCTOSPI_FCR_CBERRF XSPI_FCR_CBERRF /*!< Clear bus error flag */ /**************** Bit definition for OCTOSPI_DLR register *******************/ #define OCTOSPI_DLR_DL_Pos XSPI_DLR_DL_Pos @@ -24541,8 +24646,6 @@ typedef struct #define GTZC_CFGR3_VREFBUF_Msk (0x01UL << GTZC_CFGR3_VREFBUF_Pos) #define GTZC_CFGR3_I3C2_Pos (2U) #define GTZC_CFGR3_I3C2_Msk (0x01UL << GTZC_CFGR3_I3C2_Pos) -#define GTZC_CFGR3_CCB_Pos (4U) -#define GTZC_CFGR3_CCB_Msk (0x01UL << GTZC_CFGR3_CCB_Pos) #define GTZC_CFGR3_OCTOSPIM_Pos (5U) #define GTZC_CFGR3_OCTOSPIM_Msk (0x01UL << GTZC_CFGR3_OCTOSPIM_Pos) #define GTZC_CFGR3_ADC3_Pos (6U) @@ -24778,8 +24881,6 @@ typedef struct #define GTZC_TZSC1_SECCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk #define GTZC_TZSC1_SECCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos #define GTZC_TZSC1_SECCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk -#define GTZC_TZSC1_SECCFGR3_CCB_Pos GTZC_CFGR3_CCB_Pos -#define GTZC_TZSC1_SECCFGR3_CCB_Msk GTZC_CFGR3_CCB_Msk #define GTZC_TZSC1_SECCFGR3_OCTOSPIM_Pos GTZC_CFGR3_OCTOSPIM_Pos #define GTZC_TZSC1_SECCFGR3_OCTOSPIM_Msk GTZC_CFGR3_OCTOSPIM_Msk #define GTZC_TZSC1_SECCFGR3_ADC3_Pos GTZC_CFGR3_ADC3_Pos @@ -24959,8 +25060,6 @@ typedef struct #define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk #define GTZC_TZSC1_PRIVCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos #define GTZC_TZSC1_PRIVCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk -#define GTZC_TZSC1_PRIVCFGR3_CCB_Pos GTZC_CFGR3_CCB_Pos -#define GTZC_TZSC1_PRIVCFGR3_CCB_Msk GTZC_CFGR3_CCB_Msk #define GTZC_TZSC1_PRIVCFGR3_OCTOSPIM_Pos GTZC_CFGR3_OCTOSPIM_Pos #define GTZC_TZSC1_PRIVCFGR3_OCTOSPIM_Msk GTZC_CFGR3_OCTOSPIM_Msk #define GTZC_TZSC1_PRIVCFGR3_ADC3_Pos GTZC_CFGR3_ADC3_Pos @@ -25141,8 +25240,6 @@ typedef struct #define GTZC_TZIC1_IER3_I3C2_Msk GTZC_CFGR3_I3C2_Msk #define GTZC_TZIC1_IER3_CRC_Pos GTZC_CFGR3_CRC_Pos #define GTZC_TZIC1_IER3_CRC_Msk GTZC_CFGR3_CRC_Msk -#define GTZC_TZIC1_IER3_CCB_Pos GTZC_CFGR3_CCB_Pos -#define GTZC_TZIC1_IER3_CCB_Msk GTZC_CFGR3_CCB_Msk #define GTZC_TZIC1_IER3_OCTOSPIM_Pos GTZC_CFGR3_OCTOSPIM_Pos #define GTZC_TZIC1_IER3_OCTOSPIM_Msk GTZC_CFGR3_OCTOSPIM_Msk #define GTZC_TZIC1_IER3_ADC3_Pos GTZC_CFGR3_ADC3_Pos @@ -25375,8 +25472,6 @@ typedef struct #define GTZC_TZIC1_SR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk #define GTZC_TZIC1_SR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos #define GTZC_TZIC1_SR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk -#define GTZC_TZIC1_SR3_CCB_Pos GTZC_CFGR3_CCB_Pos -#define GTZC_TZIC1_SR3_CCB_Msk GTZC_CFGR3_CCB_Msk #define GTZC_TZIC1_SR3_OCTOSPIM_Pos GTZC_CFGR3_OCTOSPIM_Pos #define GTZC_TZIC1_SR3_OCTOSPIM_Msk GTZC_CFGR3_OCTOSPIM_Msk #define GTZC_TZIC1_SR3_ADC3_Pos GTZC_CFGR3_ADC3_Pos @@ -25611,8 +25706,6 @@ typedef struct #define GTZC_TZIC1_FCR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk #define GTZC_TZIC1_FCR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos #define GTZC_TZIC1_FCR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk -#define GTZC_TZIC1_FCR3_CCB_Pos GTZC_CFGR3_CCB_Pos -#define GTZC_TZIC1_FCR3_CCB_Msk GTZC_CFGR3_CCB_Msk #define GTZC_TZIC1_FCR3_OCTOSPIM_Pos GTZC_CFGR3_OCTOSPIM_Pos #define GTZC_TZIC1_FCR3_OCTOSPIM_Msk GTZC_CFGR3_OCTOSPIM_Msk #define GTZC_TZIC1_FCR3_ADC3_Pos GTZC_CFGR3_ADC3_Pos @@ -27377,9 +27470,9 @@ typedef struct #define I3C_MISR_IBIMIS_Pos (15U) #define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ #define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Interrupt status */ -#define I3C_MISR_BIENDMIS_Pos (16U) -#define I3C_MISR_BIENDMIS_Msk (0x1UL << I3C_MISR_BIENDMIS_Pos) /*!< 0x00010000 */ -#define I3C_MISR_BIENDMIS I3C_MISR_BIENDMIS_Msk /*!< IBI End Interrupt status */ +#define I3C_MISR_IBIENDMIS_Pos (16U) +#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ +#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Interrupt status */ #define I3C_MISR_CRMIS_Pos (17U) #define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ #define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Interrupt status */ @@ -30259,8 +30352,6 @@ typedef struct /******************************* CORDIC Instances *****************************/ #define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) -/******************************* CCB Instances ********************************/ -#define IS_CCB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CCB_NS) || ((INSTANCE) == CCB_S)) /******************************* CRC Instances ********************************/ #define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5e5xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5e5xx.h index 46f8bbf5b1..f766344199 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5e5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5e5xx.h @@ -337,7 +337,7 @@ typedef struct __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ - uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t MISR; /*!< masked interrupt status register, Address offset: 0x5C */ __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ @@ -423,10 +423,14 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ } RNG_TypeDef; /** @@ -2411,7 +2415,6 @@ typedef struct #define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) #define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) #define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) -#define CCB_BASE_NS (AHB2PERIPH_BASE_NS + 0xA7C00UL) /*!< APB3 Non secure peripherals */ #define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) @@ -2625,7 +2628,6 @@ typedef struct #define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) #define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) #define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) -#define CCB_BASE_S (AHB2PERIPH_BASE_S + 0xA7C00UL) /*!< APB3 secure peripherals */ #define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) @@ -3039,7 +3041,6 @@ typedef struct #define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) #define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) #define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) -#define CCB_NS ((CCB_TypeDef *) CCB_BASE_NS) /*!< APB3 Non secure peripherals */ @@ -3229,7 +3230,6 @@ typedef struct #define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) #define RNG_S ((RNG_TypeDef *) RNG_BASE_S) #define PKA_S ((PKA_TypeDef *) PKA_BASE_S) -#define CCB_S ((CCB_TypeDef *) CCB_BASE_S) #define ADC3_S ((ADC_TypeDef *) ADC3_BASE_S) #define ADC3_COMMON_S ((ADC_Common_TypeDef *) ADC3_COMMON_BASE_S) #define USB_OTG_FS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_S) @@ -3714,8 +3714,6 @@ typedef struct #define PKA PKA_S #define PKA_BASE PKA_BASE_S #define PKA_RAM_BASE PKA_RAM_BASE_S -#define CCB CCB_S -#define CCB_BASE CCB_BASE_S #define ETH ETH_S #define ETH_BASE ETH_BASE_S @@ -4251,9 +4249,6 @@ typedef struct #define PKA_BASE PKA_BASE_NS #define PKA_RAM_BASE PKA_RAM_BASE_NS -#define CCB CCB_NS -#define CCB_BASE CCB_BASE_NS - #define ETH ETH_NS #define ETH_BASE ETH_BASE_NS @@ -5414,10 +5409,6 @@ typedef struct #define COMP_CFGR1_WINMODE_Msk (0x1UL << COMP_CFGR1_WINMODE_Pos) /*!< 0x00000010 */ #define COMP_CFGR1_WINMODE COMP_CFGR1_WINMODE_Msk /*!< COMP1 window mode selection bit */ -#define COMP_CFGR1_WINOUT_Pos (5U) -#define COMP_CFGR1_WINOUT_Msk (0x1UL << COMP_CFGR1_WINOUT_Pos) /*!< 0x00000020 */ -#define COMP_CFGR1_WINOUT COMP_CFGR1_WINOUT_Msk /*!< COMP1 window output selection bit */ - #define COMP_CFGR1_ITEN_Pos (6U) #define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ #define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< COMP1 interrupt enable */ @@ -5434,6 +5425,10 @@ typedef struct #define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ #define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ +#define COMP_CFGR1_WINOUT_Pos (14U) +#define COMP_CFGR1_WINOUT_Msk (0x1UL << COMP_CFGR1_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CFGR1_WINOUT COMP_CFGR1_WINOUT_Msk /*!< COMP1 window output selection bit */ + #define COMP_CFGR1_INMSEL_Pos (16U) #define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ #define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< COMP1 input minus selection bit */ @@ -5506,6 +5501,7 @@ typedef struct #define COMP_CFGR2_PWRMODE_0 (0x1UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00001000 */ #define COMP_CFGR2_PWRMODE_1 (0x2UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00002000 */ + #define COMP_CFGR2_INMSEL_Pos (16U) #define COMP_CFGR2_INMSEL_Msk (0xFUL << COMP_CFGR2_INMSEL_Pos) /*!< 0x000F0000 */ #define COMP_CFGR2_INMSEL COMP_CFGR2_INMSEL_Msk /*!< COMP1 input minus selection bit */ @@ -5612,50 +5608,6 @@ typedef struct #define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U) #define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */ #define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS pairs */ -/******************************************************************************/ -/* */ -/* Coupling and chaining bridge (CCB) */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CCB_CR register ******************/ -#define CCB_CR_CCOP_Pos (0U) -#define CCB_CR_CCOP_Msk (0xFFUL << CCB_CR_CCOP_Pos) /*!< 0x000000FF */ -#define CCB_CR_CCOP CCB_CR_CCOP_Msk /*!< Coupling and chaining operation */ -#define CCB_CR_IPRST_Pos (31U) -#define CCB_CR_IPRST_Msk (0x1UL << CCB_CR_IPRST_Pos) /*!< 0x80000000 */ -#define CCB_CR_IPRST CCB_CR_IPRST_Msk /*!< CCB reset */ - -/******************* Bit definition for CCB_SR register ******************/ -#define CCB_SR_OPSTEP_Pos (0U) -#define CCB_SR_OPSTEP_Msk (0x1FUL << CCB_SR_OPSTEP_Pos) /*!< 0x0000001F */ -#define CCB_SR_OPSTEP CCB_SR_OPSTEP_Msk /*!< Operation step */ -#define CCB_SR_OPERR_Pos (8U) -#define CCB_SR_OPERR_Msk (0x3FUL << CCB_SR_OPERR_Pos) /*!< 0x00003F00 */ -#define CCB_SR_OPERR CCB_SR_OPERR_Msk /*!< Operation error */ -#define CCB_SR_BUSY_Pos (16U) -#define CCB_SR_BUSY_Msk (0x1UL << CCB_SR_BUSY_Pos) /*!< 0x00010000 */ -#define CCB_SR_BUSY CCB_SR_BUSY_Msk /*!< CCB busy */ -#define CCB_SR_TAMP_EVT0_Pos (24U) -#define CCB_SR_TAMP_EVT0_Msk (0x1UL << CCB_SR_TAMP_EVT0_Pos) /*!< 0x01000000 */ -#define CCB_SR_TAMP_EVT0 CCB_SR_TAMP_EVT0_Msk /*!< Tamper event 0 flag */ -#define CCB_SR_TAMP_EVT1_Pos (25U) -#define CCB_SR_TAMP_EVT1_Msk (0x1UL << CCB_SR_TAMP_EVT1_Pos) /*!< 0x02000000 */ -#define CCB_SR_TAMP_EVT1 CCB_SR_TAMP_EVT1_Msk /*!< Tamper event 1 flag */ -#define CCB_SR_TAMP_EVT2_Pos (26U) -#define CCB_SR_TAMP_EVT2_Msk (0x1UL << CCB_SR_TAMP_EVT2_Pos) /*!< 0x04000000 */ -#define CCB_SR_TAMP_EVT2 CCB_SR_TAMP_EVT2_Msk /*!< Tamper event 2 flag */ -#define CCB_SR_TAMP_EVT3_Pos (27U) -#define CCB_SR_TAMP_EVT3_Msk (0x1UL << CCB_SR_TAMP_EVT3_Pos) /*!< 0x08000000 */ -#define CCB_SR_TAMP_EVT3 CCB_SR_TAMP_EVT3_Msk /*!< Tamper event 3 flag */ -#define CCB_SR_TAMP_EVT4_Pos (28U) -#define CCB_SR_TAMP_EVT4_Msk (0x1UL << CCB_SR_TAMP_EVT4_Pos) /*!< 0x10000000 */ -#define CCB_SR_TAMP_EVT4 CCB_SR_TAMP_EVT4_Msk /*!< Tamper event 4 flag */ - -#define CCB_SR_TAMP_EVT5_Pos (29U) -#define CCB_SR_TAMP_EVT5_Msk (0x1UL << CCB_SR_TAMP_EVT5_Pos) /*!< 0x20000000 */ -#define CCB_SR_TAMP_EVT5 CCB_SR_TAMP_EVT5_Msk /*!< Tamper event 5 flag */ - /******************************************************************************/ /* */ /* CORDIC calculation unit */ @@ -5872,42 +5824,42 @@ typedef struct /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2U) -#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3U) -#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5U) -#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7U) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8U) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12U) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13U) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16U) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30U) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31U) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0U) @@ -5919,6 +5871,9 @@ typedef struct #define RNG_SR_SECS_Pos (2U) #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ #define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_BUSY_Pos (4U) +#define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ #define RNG_SR_CEIS_Pos (5U) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk @@ -5937,14 +5892,134 @@ typedef struct #define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk -/******************** Bits definition for RNG_HTCR register *******************/ -#define RNG_HTCR_HTCFG_Pos (0U) -#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ -#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** Bits definition for RNG_HTCR0 register *******************/ +#define RNG_HTCR0_HTCFG_Pos (0U) +#define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR0_HTCFG RNG_HTCR0_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR1 register *******************/ +#define RNG_HTCR1_HTCFG_Pos (0U) +#define RNG_HTCR1_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR1_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR1_HTCFG RNG_HTCR1_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR2 register *******************/ +#define RNG_HTCR2_HTCFG_Pos (0U) +#define RNG_HTCR2_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR2_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR2_HTCFG RNG_HTCR2_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR3 register *******************/ +#define RNG_HTCR3_HTCFG_Pos (0U) +#define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk + +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ /******************** RNG Nist Compliance Values ******************************/ -#define RNG_CR_NIST_VALUE (0x00200F00U) -#define RNG_HTCR_NIST_VALUE (0xA2B0U) +#define RNG_HTCRx_VALUE 0x0003FFFF +#define RNG_CR_NIST_VALUE (0x08451F00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) + +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 /******************************************************************************/ /* */ @@ -18405,6 +18480,9 @@ typedef struct #define XSPI_CR_TCEN_Pos (3U) #define XSPI_CR_TCEN_Msk (0x1UL << XSPI_CR_TCEN_Pos) /*!< 0x00000008 */ #define XSPI_CR_TCEN XSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */ +#define XSPI_CR_ADOFFEN_Pos (4U) +#define XSPI_CR_ADOFFEN_Msk (0x1UL << XSPI_CR_ADOFFEN_Pos) /*!< 0x00000010 */ +#define XSPI_CR_ADOFFEN XSPI_CR_ADOFFEN_Msk /*!< Address offset enable */ #define XSPI_CR_DMM_Pos (6U) #define XSPI_CR_DMM_Msk (0x1UL << XSPI_CR_DMM_Pos) /*!< 0x00000040 */ #define XSPI_CR_DMM XSPI_CR_DMM_Msk /*!< Dual-memory configuration */ @@ -18426,6 +18504,9 @@ typedef struct #define XSPI_CR_TOIE_Pos (20U) #define XSPI_CR_TOIE_Msk (0x1UL << XSPI_CR_TOIE_Pos) /*!< 0x00100000 */ #define XSPI_CR_TOIE XSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */ +#define XSPI_CR_BERRIE_Pos (21U) +#define XSPI_CR_BERRIE_Msk (0x1UL << XSPI_CR_BERRIE_Pos) /*!< 0x00200000 */ +#define XSPI_CR_BERRIE XSPI_CR_BERRIE_Msk /*!< Bus error interrupt enable */ #define XSPI_CR_APMS_Pos (22U) #define XSPI_CR_APMS_Msk (0x1UL << XSPI_CR_APMS_Pos) /*!< 0x00400000 */ #define XSPI_CR_APMS XSPI_CR_APMS_Msk /*!< Automatic Poll Mode Stop */ @@ -18472,6 +18553,9 @@ typedef struct #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */ #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */ #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */ +#define XSPI_DCR1_ADOFF_Pos (27U) +#define XSPI_DCR1_ADOFF_Msk (0x1FUL << XSPI_DCR1_ADOFF_Pos) /*!< 0xF8000000 */ +#define XSPI_DCR1_ADOFF XSPI_DCR1_ADOFF_Msk /*!< Address offset */ /**************** Bit definition for XSPI_DCR2 register ******************/ #define XSPI_DCR2_PRESCALER_Pos (0U) @@ -18485,12 +18569,12 @@ typedef struct #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */ /**************** Bit definition for XSPI_DCR3 register ******************/ -#define XSPI_DCR3_MAXTRAN_Pos (0U) -#define XSPI_DCR3_MAXTRAN_Msk (0xFFUL << XSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */ -#define XSPI_DCR3_MAXTRAN XSPI_DCR3_MAXTRAN_Msk /*!< Maximum transfer */ +#define XSPI_DCR3_MAXTRAN_Pos (0U) +#define XSPI_DCR3_MAXTRAN_Msk (0xFFUL << XSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */ +#define XSPI_DCR3_MAXTRAN XSPI_DCR3_MAXTRAN_Msk /*!< Maximum transfer */ #define XSPI_DCR3_CSBOUND_Pos (16U) #define XSPI_DCR3_CSBOUND_Msk (0x1FUL << XSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */ -#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< Maximum transfer */ +#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< NCS boundary */ /**************** Bit definition for XSPI_DCR4 register ******************/ #define XSPI_DCR4_REFRESH_Pos (0U) @@ -18516,6 +18600,9 @@ typedef struct #define XSPI_SR_BUSY_Pos (5U) #define XSPI_SR_BUSY_Msk (0x1UL << XSPI_SR_BUSY_Pos) /*!< 0x00000020 */ #define XSPI_SR_BUSY XSPI_SR_BUSY_Msk /*!< Busy */ +#define XSPI_SR_BERRF_Pos (6U) +#define XSPI_SR_BERRF_Msk (0x1UL << XSPI_SR_BERRF_Pos) /*!< 0x00000040 */ +#define XSPI_SR_BERRF XSPI_SR_BERRF_Msk /*!< Bus error flag */ #define XSPI_SR_FLEVEL_Pos (8U) #define XSPI_SR_FLEVEL_Msk (0x3FUL << XSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */ #define XSPI_SR_FLEVEL XSPI_SR_FLEVEL_Msk /*!< FIFO Level */ @@ -18533,6 +18620,9 @@ typedef struct #define XSPI_FCR_CTOF_Pos (4U) #define XSPI_FCR_CTOF_Msk (0x1UL << XSPI_FCR_CTOF_Pos) /*!< 0x00000010 */ #define XSPI_FCR_CTOF XSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */ +#define XSPI_FCR_CBERRF_Pos (6U) +#define XSPI_FCR_CBERRF_Msk (0x1UL << XSPI_FCR_CBERRF_Pos) /*!< 0x00000040 */ +#define XSPI_FCR_CBERRF XSPI_FCR_CBERRF_Msk /*!< Clear bus error flag */ /**************** Bit definition for XSPI_DLR register *******************/ #define XSPI_DLR_DL_Pos (0U) @@ -18826,6 +18916,9 @@ typedef struct #define OCTOSPI_CR_TCEN_Pos XSPI_CR_TCEN_Pos #define OCTOSPI_CR_TCEN_Msk XSPI_CR_TCEN_Msk /*!< 0x00000008 */ #define OCTOSPI_CR_TCEN XSPI_CR_TCEN /*!< Timeout Counter Enable */ +#define OCTOSPI_CR_ADOFFEN_Pos XSPI_CR_ADOFFEN_Pos +#define OCTOSPI_CR_ADOFFEN_Msk XSPI_CR_ADOFFEN_Msk /*!< 0x00000010 */ +#define OCTOSPI_CR_ADOFFEN XSPI_CR_ADOFFEN /*!< Address offset enable */ #define OCTOSPI_CR_DMM_Pos XSPI_CR_DMM_Pos #define OCTOSPI_CR_DMM_Msk XSPI_CR_DMM_Msk /*!< 0x00000040 */ #define OCTOSPI_CR_DMM XSPI_CR_DMM /*!< Dual Memory Mode */ @@ -18847,6 +18940,9 @@ typedef struct #define OCTOSPI_CR_TOIE_Pos XSPI_CR_TOIE_Pos #define OCTOSPI_CR_TOIE_Msk XSPI_CR_TOIE_Msk /*!< 0x00100000 */ #define OCTOSPI_CR_TOIE XSPI_CR_TOIE /*!< TimeOut Interrupt Enable */ +#define OCTOSPI_CR_BERRIE_Pos XSPI_CR_BERRIE_Pos +#define OCTOSPI_CR_BERRIE_Msk XSPI_CR_BERRIE_Msk /*!< 0x00200000 */ +#define OCTOSPI_CR_BERRIE XSPI_CR_BERRIE /*!< Bus error interrupt enable */ #define OCTOSPI_CR_APMS_Pos XSPI_CR_APMS_Pos #define OCTOSPI_CR_APMS_Msk XSPI_CR_APMS_Msk /*!< 0x00400000 */ #define OCTOSPI_CR_APMS XSPI_CR_APMS /*!< Automatic Poll Mode Stop */ @@ -18893,6 +18989,9 @@ typedef struct #define OCTOSPI_DCR1_MTYP_0 XSPI_DCR1_MTYP_0 /*!< 0x01000000 */ #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02000000 */ #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04000000 */ +#define OCTOSPI_DCR1_ADOFF_Pos XSPI_DCR1_ADOFF_Pos +#define OCTOSPI_DCR1_ADOFF_Msk XSPI_DCR1_ADOFF_Msk /*!< 0xF8000000 */ +#define OCTOSPI_DCR1_ADOFF XSPI_DCR1_ADOFF /*!< Address offset */ /**************** Bit definition for OCTOSPI_DCR2 register ******************/ #define OCTOSPI_DCR2_PRESCALER_Pos XSPI_DCR2_PRESCALER_Pos @@ -18934,6 +19033,9 @@ typedef struct #define OCTOSPI_SR_BUSY_Pos XSPI_SR_BUSY_Pos #define OCTOSPI_SR_BUSY_Msk XSPI_SR_BUSY_Msk /*!< 0x00000020 */ #define OCTOSPI_SR_BUSY XSPI_SR_BUSY /*!< Busy */ +#define OCTOSPI_SR_BERRF_Pos XSPI_SR_BERRF_Pos +#define OCTOSPI_SR_BERRF_Msk XSPI_SR_BERRF_Msk /*!< 0x00000040 */ +#define OCTOSPI_SR_BERRF XSPI_SR_BERRF /*!< Bus error flag */ #define OCTOSPI_SR_FLEVEL_Pos XSPI_SR_FLEVEL_Pos #define OCTOSPI_SR_FLEVEL_Msk (0x3FUL << OCTOSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */ #define OCTOSPI_SR_FLEVEL XSPI_SR_FLEVEL /*!< FIFO Level */ @@ -18951,6 +19053,9 @@ typedef struct #define OCTOSPI_FCR_CTOF_Pos XSPI_FCR_CTOF_Pos #define OCTOSPI_FCR_CTOF_Msk XSPI_FCR_CTOF_Msk /*!< 0x00000010 */ #define OCTOSPI_FCR_CTOF XSPI_FCR_CTOF /*!< Clear Timeout Flag */ +#define OCTOSPI_FCR_CBERRF_Pos XSPI_FCR_CBERRF_Pos +#define OCTOSPI_FCR_CBERRF_Msk XSPI_FCR_CBERRF_Msk /*!< 0x00000040 */ +#define OCTOSPI_FCR_CBERRF XSPI_FCR_CBERRF /*!< Clear bus error flag */ /**************** Bit definition for OCTOSPI_DLR register *******************/ #define OCTOSPI_DLR_DL_Pos XSPI_DLR_DL_Pos @@ -24597,8 +24702,6 @@ typedef struct #define GTZC_CFGR3_VREFBUF_Msk (0x01UL << GTZC_CFGR3_VREFBUF_Pos) #define GTZC_CFGR3_I3C2_Pos (2U) #define GTZC_CFGR3_I3C2_Msk (0x01UL << GTZC_CFGR3_I3C2_Pos) -#define GTZC_CFGR3_CCB_Pos (4U) -#define GTZC_CFGR3_CCB_Msk (0x01UL << GTZC_CFGR3_CCB_Pos) #define GTZC_CFGR3_OCTOSPIM_Pos (5U) #define GTZC_CFGR3_OCTOSPIM_Msk (0x01UL << GTZC_CFGR3_OCTOSPIM_Pos) #define GTZC_CFGR3_ADC3_Pos (6U) @@ -24836,8 +24939,6 @@ typedef struct #define GTZC_TZSC1_SECCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk #define GTZC_TZSC1_SECCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos #define GTZC_TZSC1_SECCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk -#define GTZC_TZSC1_SECCFGR3_CCB_Pos GTZC_CFGR3_CCB_Pos -#define GTZC_TZSC1_SECCFGR3_CCB_Msk GTZC_CFGR3_CCB_Msk #define GTZC_TZSC1_SECCFGR3_OCTOSPIM_Pos GTZC_CFGR3_OCTOSPIM_Pos #define GTZC_TZSC1_SECCFGR3_OCTOSPIM_Msk GTZC_CFGR3_OCTOSPIM_Msk #define GTZC_TZSC1_SECCFGR3_ADC3_Pos GTZC_CFGR3_ADC3_Pos @@ -25019,8 +25120,6 @@ typedef struct #define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk #define GTZC_TZSC1_PRIVCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos #define GTZC_TZSC1_PRIVCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk -#define GTZC_TZSC1_PRIVCFGR3_CCB_Pos GTZC_CFGR3_CCB_Pos -#define GTZC_TZSC1_PRIVCFGR3_CCB_Msk GTZC_CFGR3_CCB_Msk #define GTZC_TZSC1_PRIVCFGR3_OCTOSPIM_Pos GTZC_CFGR3_OCTOSPIM_Pos #define GTZC_TZSC1_PRIVCFGR3_OCTOSPIM_Msk GTZC_CFGR3_OCTOSPIM_Msk #define GTZC_TZSC1_PRIVCFGR3_ADC3_Pos GTZC_CFGR3_ADC3_Pos @@ -25203,8 +25302,6 @@ typedef struct #define GTZC_TZIC1_IER3_I3C2_Msk GTZC_CFGR3_I3C2_Msk #define GTZC_TZIC1_IER3_CRC_Pos GTZC_CFGR3_CRC_Pos #define GTZC_TZIC1_IER3_CRC_Msk GTZC_CFGR3_CRC_Msk -#define GTZC_TZIC1_IER3_CCB_Pos GTZC_CFGR3_CCB_Pos -#define GTZC_TZIC1_IER3_CCB_Msk GTZC_CFGR3_CCB_Msk #define GTZC_TZIC1_IER3_OCTOSPIM_Pos GTZC_CFGR3_OCTOSPIM_Pos #define GTZC_TZIC1_IER3_OCTOSPIM_Msk GTZC_CFGR3_OCTOSPIM_Msk #define GTZC_TZIC1_IER3_ADC3_Pos GTZC_CFGR3_ADC3_Pos @@ -25439,8 +25536,6 @@ typedef struct #define GTZC_TZIC1_SR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk #define GTZC_TZIC1_SR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos #define GTZC_TZIC1_SR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk -#define GTZC_TZIC1_SR3_CCB_Pos GTZC_CFGR3_CCB_Pos -#define GTZC_TZIC1_SR3_CCB_Msk GTZC_CFGR3_CCB_Msk #define GTZC_TZIC1_SR3_OCTOSPIM_Pos GTZC_CFGR3_OCTOSPIM_Pos #define GTZC_TZIC1_SR3_OCTOSPIM_Msk GTZC_CFGR3_OCTOSPIM_Msk #define GTZC_TZIC1_SR3_ADC3_Pos GTZC_CFGR3_ADC3_Pos @@ -25677,8 +25772,6 @@ typedef struct #define GTZC_TZIC1_FCR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk #define GTZC_TZIC1_FCR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos #define GTZC_TZIC1_FCR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk -#define GTZC_TZIC1_FCR3_CCB_Pos GTZC_CFGR3_CCB_Pos -#define GTZC_TZIC1_FCR3_CCB_Msk GTZC_CFGR3_CCB_Msk #define GTZC_TZIC1_FCR3_OCTOSPIM_Pos GTZC_CFGR3_OCTOSPIM_Pos #define GTZC_TZIC1_FCR3_OCTOSPIM_Msk GTZC_CFGR3_OCTOSPIM_Msk #define GTZC_TZIC1_FCR3_ADC3_Pos GTZC_CFGR3_ADC3_Pos @@ -27445,9 +27538,9 @@ typedef struct #define I3C_MISR_IBIMIS_Pos (15U) #define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ #define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Interrupt status */ -#define I3C_MISR_BIENDMIS_Pos (16U) -#define I3C_MISR_BIENDMIS_Msk (0x1UL << I3C_MISR_BIENDMIS_Pos) /*!< 0x00010000 */ -#define I3C_MISR_BIENDMIS I3C_MISR_BIENDMIS_Msk /*!< IBI End Interrupt status */ +#define I3C_MISR_IBIENDMIS_Pos (16U) +#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ +#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Interrupt status */ #define I3C_MISR_CRMIS_Pos (17U) #define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ #define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Interrupt status */ @@ -30369,8 +30462,6 @@ typedef struct /******************************* CORDIC Instances *****************************/ #define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) -/******************************* CCB Instances ********************************/ -#define IS_CCB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CCB_NS) || ((INSTANCE) == CCB_S)) /******************************* CRC Instances ********************************/ #define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5f4xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5f4xx.h index cf63a43620..2e65d86eb3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5f4xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5f4xx.h @@ -339,7 +339,7 @@ typedef struct __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ - uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t MISR; /*!< masked interrupt status register, Address offset: 0x5C */ __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ @@ -459,10 +459,14 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ } RNG_TypeDef; /** @@ -5581,10 +5585,6 @@ typedef struct #define COMP_CFGR1_WINMODE_Msk (0x1UL << COMP_CFGR1_WINMODE_Pos) /*!< 0x00000010 */ #define COMP_CFGR1_WINMODE COMP_CFGR1_WINMODE_Msk /*!< COMP1 window mode selection bit */ -#define COMP_CFGR1_WINOUT_Pos (5U) -#define COMP_CFGR1_WINOUT_Msk (0x1UL << COMP_CFGR1_WINOUT_Pos) /*!< 0x00000020 */ -#define COMP_CFGR1_WINOUT COMP_CFGR1_WINOUT_Msk /*!< COMP1 window output selection bit */ - #define COMP_CFGR1_ITEN_Pos (6U) #define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ #define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< COMP1 interrupt enable */ @@ -5601,6 +5601,10 @@ typedef struct #define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ #define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ +#define COMP_CFGR1_WINOUT_Pos (14U) +#define COMP_CFGR1_WINOUT_Msk (0x1UL << COMP_CFGR1_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CFGR1_WINOUT COMP_CFGR1_WINOUT_Msk /*!< COMP1 window output selection bit */ + #define COMP_CFGR1_INMSEL_Pos (16U) #define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ #define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< COMP1 input minus selection bit */ @@ -5673,6 +5677,7 @@ typedef struct #define COMP_CFGR2_PWRMODE_0 (0x1UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00001000 */ #define COMP_CFGR2_PWRMODE_1 (0x2UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00002000 */ + #define COMP_CFGR2_INMSEL_Pos (16U) #define COMP_CFGR2_INMSEL_Msk (0xFUL << COMP_CFGR2_INMSEL_Pos) /*!< 0x000F0000 */ #define COMP_CFGR2_INMSEL COMP_CFGR2_INMSEL_Msk /*!< COMP1 input minus selection bit */ @@ -5784,7 +5789,8 @@ typedef struct /* Coupling and chaining bridge (CCB) */ /* */ /******************************************************************************/ - +/* Specific device feature definitions */ +#define SW_SANITY_CHECK_SUPPORT /*!< CCB feature available only on specific devices: SW Sanity check is available on H5 4M devices */ /******************* Bit definition for CCB_CR register ******************/ #define CCB_CR_CCOP_Pos (0U) #define CCB_CR_CCOP_Msk (0xFFUL << CCB_CR_CCOP_Pos) /*!< 0x000000FF */ @@ -6039,42 +6045,42 @@ typedef struct /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2U) -#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3U) -#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5U) -#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7U) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8U) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12U) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13U) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16U) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30U) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31U) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0U) @@ -6086,6 +6092,9 @@ typedef struct #define RNG_SR_SECS_Pos (2U) #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ #define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_BUSY_Pos (4U) +#define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ #define RNG_SR_CEIS_Pos (5U) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk @@ -6104,14 +6113,134 @@ typedef struct #define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk -/******************** Bits definition for RNG_HTCR register *******************/ -#define RNG_HTCR_HTCFG_Pos (0U) -#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ -#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** Bits definition for RNG_HTCR0 register *******************/ +#define RNG_HTCR0_HTCFG_Pos (0U) +#define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR0_HTCFG RNG_HTCR0_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR1 register *******************/ +#define RNG_HTCR1_HTCFG_Pos (0U) +#define RNG_HTCR1_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR1_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR1_HTCFG RNG_HTCR1_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR2 register *******************/ +#define RNG_HTCR2_HTCFG_Pos (0U) +#define RNG_HTCR2_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR2_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR2_HTCFG RNG_HTCR2_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR3 register *******************/ +#define RNG_HTCR3_HTCFG_Pos (0U) +#define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk + +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ /******************** RNG Nist Compliance Values ******************************/ -#define RNG_CR_NIST_VALUE (0x00200F00U) -#define RNG_HTCR_NIST_VALUE (0xA2B0U) +#define RNG_HTCRx_VALUE 0x0003FFFF +#define RNG_CR_NIST_VALUE (0x08451F00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) + +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 /******************************************************************************/ /* */ @@ -18805,6 +18934,9 @@ typedef struct #define XSPI_CR_TCEN_Pos (3U) #define XSPI_CR_TCEN_Msk (0x1UL << XSPI_CR_TCEN_Pos) /*!< 0x00000008 */ #define XSPI_CR_TCEN XSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */ +#define XSPI_CR_ADOFFEN_Pos (4U) +#define XSPI_CR_ADOFFEN_Msk (0x1UL << XSPI_CR_ADOFFEN_Pos) /*!< 0x00000010 */ +#define XSPI_CR_ADOFFEN XSPI_CR_ADOFFEN_Msk /*!< Address offset enable */ #define XSPI_CR_DMM_Pos (6U) #define XSPI_CR_DMM_Msk (0x1UL << XSPI_CR_DMM_Pos) /*!< 0x00000040 */ #define XSPI_CR_DMM XSPI_CR_DMM_Msk /*!< Dual-memory configuration */ @@ -18826,6 +18958,9 @@ typedef struct #define XSPI_CR_TOIE_Pos (20U) #define XSPI_CR_TOIE_Msk (0x1UL << XSPI_CR_TOIE_Pos) /*!< 0x00100000 */ #define XSPI_CR_TOIE XSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */ +#define XSPI_CR_BERRIE_Pos (21U) +#define XSPI_CR_BERRIE_Msk (0x1UL << XSPI_CR_BERRIE_Pos) /*!< 0x00200000 */ +#define XSPI_CR_BERRIE XSPI_CR_BERRIE_Msk /*!< Bus error interrupt enable */ #define XSPI_CR_APMS_Pos (22U) #define XSPI_CR_APMS_Msk (0x1UL << XSPI_CR_APMS_Pos) /*!< 0x00400000 */ #define XSPI_CR_APMS XSPI_CR_APMS_Msk /*!< Automatic Poll Mode Stop */ @@ -18872,6 +19007,9 @@ typedef struct #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */ #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */ #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */ +#define XSPI_DCR1_ADOFF_Pos (27U) +#define XSPI_DCR1_ADOFF_Msk (0x1FUL << XSPI_DCR1_ADOFF_Pos) /*!< 0xF8000000 */ +#define XSPI_DCR1_ADOFF XSPI_DCR1_ADOFF_Msk /*!< Address offset */ /**************** Bit definition for XSPI_DCR2 register ******************/ #define XSPI_DCR2_PRESCALER_Pos (0U) @@ -18885,12 +19023,12 @@ typedef struct #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */ /**************** Bit definition for XSPI_DCR3 register ******************/ -#define XSPI_DCR3_MAXTRAN_Pos (0U) -#define XSPI_DCR3_MAXTRAN_Msk (0xFFUL << XSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */ -#define XSPI_DCR3_MAXTRAN XSPI_DCR3_MAXTRAN_Msk /*!< Maximum transfer */ +#define XSPI_DCR3_MAXTRAN_Pos (0U) +#define XSPI_DCR3_MAXTRAN_Msk (0xFFUL << XSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */ +#define XSPI_DCR3_MAXTRAN XSPI_DCR3_MAXTRAN_Msk /*!< Maximum transfer */ #define XSPI_DCR3_CSBOUND_Pos (16U) #define XSPI_DCR3_CSBOUND_Msk (0x1FUL << XSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */ -#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< Maximum transfer */ +#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< NCS boundary */ /**************** Bit definition for XSPI_DCR4 register ******************/ #define XSPI_DCR4_REFRESH_Pos (0U) @@ -18916,6 +19054,9 @@ typedef struct #define XSPI_SR_BUSY_Pos (5U) #define XSPI_SR_BUSY_Msk (0x1UL << XSPI_SR_BUSY_Pos) /*!< 0x00000020 */ #define XSPI_SR_BUSY XSPI_SR_BUSY_Msk /*!< Busy */ +#define XSPI_SR_BERRF_Pos (6U) +#define XSPI_SR_BERRF_Msk (0x1UL << XSPI_SR_BERRF_Pos) /*!< 0x00000040 */ +#define XSPI_SR_BERRF XSPI_SR_BERRF_Msk /*!< Bus error flag */ #define XSPI_SR_FLEVEL_Pos (8U) #define XSPI_SR_FLEVEL_Msk (0x3FUL << XSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */ #define XSPI_SR_FLEVEL XSPI_SR_FLEVEL_Msk /*!< FIFO Level */ @@ -18933,6 +19074,9 @@ typedef struct #define XSPI_FCR_CTOF_Pos (4U) #define XSPI_FCR_CTOF_Msk (0x1UL << XSPI_FCR_CTOF_Pos) /*!< 0x00000010 */ #define XSPI_FCR_CTOF XSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */ +#define XSPI_FCR_CBERRF_Pos (6U) +#define XSPI_FCR_CBERRF_Msk (0x1UL << XSPI_FCR_CBERRF_Pos) /*!< 0x00000040 */ +#define XSPI_FCR_CBERRF XSPI_FCR_CBERRF_Msk /*!< Clear bus error flag */ /**************** Bit definition for XSPI_DLR register *******************/ #define XSPI_DLR_DL_Pos (0U) @@ -19226,6 +19370,9 @@ typedef struct #define OCTOSPI_CR_TCEN_Pos XSPI_CR_TCEN_Pos #define OCTOSPI_CR_TCEN_Msk XSPI_CR_TCEN_Msk /*!< 0x00000008 */ #define OCTOSPI_CR_TCEN XSPI_CR_TCEN /*!< Timeout Counter Enable */ +#define OCTOSPI_CR_ADOFFEN_Pos XSPI_CR_ADOFFEN_Pos +#define OCTOSPI_CR_ADOFFEN_Msk XSPI_CR_ADOFFEN_Msk /*!< 0x00000010 */ +#define OCTOSPI_CR_ADOFFEN XSPI_CR_ADOFFEN /*!< Address offset enable */ #define OCTOSPI_CR_DMM_Pos XSPI_CR_DMM_Pos #define OCTOSPI_CR_DMM_Msk XSPI_CR_DMM_Msk /*!< 0x00000040 */ #define OCTOSPI_CR_DMM XSPI_CR_DMM /*!< Dual Memory Mode */ @@ -19247,6 +19394,9 @@ typedef struct #define OCTOSPI_CR_TOIE_Pos XSPI_CR_TOIE_Pos #define OCTOSPI_CR_TOIE_Msk XSPI_CR_TOIE_Msk /*!< 0x00100000 */ #define OCTOSPI_CR_TOIE XSPI_CR_TOIE /*!< TimeOut Interrupt Enable */ +#define OCTOSPI_CR_BERRIE_Pos XSPI_CR_BERRIE_Pos +#define OCTOSPI_CR_BERRIE_Msk XSPI_CR_BERRIE_Msk /*!< 0x00200000 */ +#define OCTOSPI_CR_BERRIE XSPI_CR_BERRIE /*!< Bus error interrupt enable */ #define OCTOSPI_CR_APMS_Pos XSPI_CR_APMS_Pos #define OCTOSPI_CR_APMS_Msk XSPI_CR_APMS_Msk /*!< 0x00400000 */ #define OCTOSPI_CR_APMS XSPI_CR_APMS /*!< Automatic Poll Mode Stop */ @@ -19293,6 +19443,9 @@ typedef struct #define OCTOSPI_DCR1_MTYP_0 XSPI_DCR1_MTYP_0 /*!< 0x01000000 */ #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02000000 */ #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04000000 */ +#define OCTOSPI_DCR1_ADOFF_Pos XSPI_DCR1_ADOFF_Pos +#define OCTOSPI_DCR1_ADOFF_Msk XSPI_DCR1_ADOFF_Msk /*!< 0xF8000000 */ +#define OCTOSPI_DCR1_ADOFF XSPI_DCR1_ADOFF /*!< Address offset */ /**************** Bit definition for OCTOSPI_DCR2 register ******************/ #define OCTOSPI_DCR2_PRESCALER_Pos XSPI_DCR2_PRESCALER_Pos @@ -19334,6 +19487,9 @@ typedef struct #define OCTOSPI_SR_BUSY_Pos XSPI_SR_BUSY_Pos #define OCTOSPI_SR_BUSY_Msk XSPI_SR_BUSY_Msk /*!< 0x00000020 */ #define OCTOSPI_SR_BUSY XSPI_SR_BUSY /*!< Busy */ +#define OCTOSPI_SR_BERRF_Pos XSPI_SR_BERRF_Pos +#define OCTOSPI_SR_BERRF_Msk XSPI_SR_BERRF_Msk /*!< 0x00000040 */ +#define OCTOSPI_SR_BERRF XSPI_SR_BERRF /*!< Bus error flag */ #define OCTOSPI_SR_FLEVEL_Pos XSPI_SR_FLEVEL_Pos #define OCTOSPI_SR_FLEVEL_Msk (0x3FUL << OCTOSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */ #define OCTOSPI_SR_FLEVEL XSPI_SR_FLEVEL /*!< FIFO Level */ @@ -19351,6 +19507,9 @@ typedef struct #define OCTOSPI_FCR_CTOF_Pos XSPI_FCR_CTOF_Pos #define OCTOSPI_FCR_CTOF_Msk XSPI_FCR_CTOF_Msk /*!< 0x00000010 */ #define OCTOSPI_FCR_CTOF XSPI_FCR_CTOF /*!< Clear Timeout Flag */ +#define OCTOSPI_FCR_CBERRF_Pos XSPI_FCR_CBERRF_Pos +#define OCTOSPI_FCR_CBERRF_Msk XSPI_FCR_CBERRF_Msk /*!< 0x00000040 */ +#define OCTOSPI_FCR_CBERRF XSPI_FCR_CBERRF /*!< Clear bus error flag */ /**************** Bit definition for OCTOSPI_DLR register *******************/ #define OCTOSPI_DLR_DL_Pos XSPI_DLR_DL_Pos @@ -27974,9 +28133,9 @@ typedef struct #define I3C_MISR_IBIMIS_Pos (15U) #define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ #define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Interrupt status */ -#define I3C_MISR_BIENDMIS_Pos (16U) -#define I3C_MISR_BIENDMIS_Msk (0x1UL << I3C_MISR_BIENDMIS_Pos) /*!< 0x00010000 */ -#define I3C_MISR_BIENDMIS I3C_MISR_BIENDMIS_Msk /*!< IBI End Interrupt status */ +#define I3C_MISR_IBIENDMIS_Pos (16U) +#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ +#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Interrupt status */ #define I3C_MISR_CRMIS_Pos (17U) #define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ #define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Interrupt status */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5f5xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5f5xx.h index f32d213773..393d7ec4ed 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5f5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5f5xx.h @@ -340,7 +340,7 @@ typedef struct __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ - uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t MISR; /*!< masked interrupt status register, Address offset: 0x5C */ __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ @@ -460,10 +460,14 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ } RNG_TypeDef; /** @@ -5592,10 +5596,6 @@ typedef struct #define COMP_CFGR1_WINMODE_Msk (0x1UL << COMP_CFGR1_WINMODE_Pos) /*!< 0x00000010 */ #define COMP_CFGR1_WINMODE COMP_CFGR1_WINMODE_Msk /*!< COMP1 window mode selection bit */ -#define COMP_CFGR1_WINOUT_Pos (5U) -#define COMP_CFGR1_WINOUT_Msk (0x1UL << COMP_CFGR1_WINOUT_Pos) /*!< 0x00000020 */ -#define COMP_CFGR1_WINOUT COMP_CFGR1_WINOUT_Msk /*!< COMP1 window output selection bit */ - #define COMP_CFGR1_ITEN_Pos (6U) #define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ #define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< COMP1 interrupt enable */ @@ -5612,6 +5612,10 @@ typedef struct #define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ #define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ +#define COMP_CFGR1_WINOUT_Pos (14U) +#define COMP_CFGR1_WINOUT_Msk (0x1UL << COMP_CFGR1_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CFGR1_WINOUT COMP_CFGR1_WINOUT_Msk /*!< COMP1 window output selection bit */ + #define COMP_CFGR1_INMSEL_Pos (16U) #define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ #define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< COMP1 input minus selection bit */ @@ -5684,6 +5688,7 @@ typedef struct #define COMP_CFGR2_PWRMODE_0 (0x1UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00001000 */ #define COMP_CFGR2_PWRMODE_1 (0x2UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00002000 */ + #define COMP_CFGR2_INMSEL_Pos (16U) #define COMP_CFGR2_INMSEL_Msk (0xFUL << COMP_CFGR2_INMSEL_Pos) /*!< 0x000F0000 */ #define COMP_CFGR2_INMSEL COMP_CFGR2_INMSEL_Msk /*!< COMP1 input minus selection bit */ @@ -5795,7 +5800,8 @@ typedef struct /* Coupling and chaining bridge (CCB) */ /* */ /******************************************************************************/ - +/* Specific device feature definitions */ +#define SW_SANITY_CHECK_SUPPORT /*!< CCB feature available only on specific devices: SW Sanity check is available on H5 4M devices */ /******************* Bit definition for CCB_CR register ******************/ #define CCB_CR_CCOP_Pos (0U) #define CCB_CR_CCOP_Msk (0xFFUL << CCB_CR_CCOP_Pos) /*!< 0x000000FF */ @@ -6050,42 +6056,42 @@ typedef struct /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2U) -#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3U) -#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5U) -#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7U) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8U) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12U) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13U) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16U) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30U) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31U) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0U) @@ -6097,6 +6103,9 @@ typedef struct #define RNG_SR_SECS_Pos (2U) #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ #define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_BUSY_Pos (4U) +#define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ #define RNG_SR_CEIS_Pos (5U) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk @@ -6115,14 +6124,134 @@ typedef struct #define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk -/******************** Bits definition for RNG_HTCR register *******************/ -#define RNG_HTCR_HTCFG_Pos (0U) -#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ -#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** Bits definition for RNG_HTCR0 register *******************/ +#define RNG_HTCR0_HTCFG_Pos (0U) +#define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR0_HTCFG RNG_HTCR0_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR1 register *******************/ +#define RNG_HTCR1_HTCFG_Pos (0U) +#define RNG_HTCR1_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR1_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR1_HTCFG RNG_HTCR1_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR2 register *******************/ +#define RNG_HTCR2_HTCFG_Pos (0U) +#define RNG_HTCR2_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR2_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR2_HTCFG RNG_HTCR2_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR3 register *******************/ +#define RNG_HTCR3_HTCFG_Pos (0U) +#define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk + +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ /******************** RNG Nist Compliance Values ******************************/ -#define RNG_CR_NIST_VALUE (0x00200F00U) -#define RNG_HTCR_NIST_VALUE (0xA2B0U) +#define RNG_HTCRx_VALUE 0x0003FFFF +#define RNG_CR_NIST_VALUE (0x08451F00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) + +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 /******************************************************************************/ /* */ @@ -18816,6 +18945,9 @@ typedef struct #define XSPI_CR_TCEN_Pos (3U) #define XSPI_CR_TCEN_Msk (0x1UL << XSPI_CR_TCEN_Pos) /*!< 0x00000008 */ #define XSPI_CR_TCEN XSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */ +#define XSPI_CR_ADOFFEN_Pos (4U) +#define XSPI_CR_ADOFFEN_Msk (0x1UL << XSPI_CR_ADOFFEN_Pos) /*!< 0x00000010 */ +#define XSPI_CR_ADOFFEN XSPI_CR_ADOFFEN_Msk /*!< Address offset enable */ #define XSPI_CR_DMM_Pos (6U) #define XSPI_CR_DMM_Msk (0x1UL << XSPI_CR_DMM_Pos) /*!< 0x00000040 */ #define XSPI_CR_DMM XSPI_CR_DMM_Msk /*!< Dual-memory configuration */ @@ -18837,6 +18969,9 @@ typedef struct #define XSPI_CR_TOIE_Pos (20U) #define XSPI_CR_TOIE_Msk (0x1UL << XSPI_CR_TOIE_Pos) /*!< 0x00100000 */ #define XSPI_CR_TOIE XSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */ +#define XSPI_CR_BERRIE_Pos (21U) +#define XSPI_CR_BERRIE_Msk (0x1UL << XSPI_CR_BERRIE_Pos) /*!< 0x00200000 */ +#define XSPI_CR_BERRIE XSPI_CR_BERRIE_Msk /*!< Bus error interrupt enable */ #define XSPI_CR_APMS_Pos (22U) #define XSPI_CR_APMS_Msk (0x1UL << XSPI_CR_APMS_Pos) /*!< 0x00400000 */ #define XSPI_CR_APMS XSPI_CR_APMS_Msk /*!< Automatic Poll Mode Stop */ @@ -18883,6 +19018,9 @@ typedef struct #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */ #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */ #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */ +#define XSPI_DCR1_ADOFF_Pos (27U) +#define XSPI_DCR1_ADOFF_Msk (0x1FUL << XSPI_DCR1_ADOFF_Pos) /*!< 0xF8000000 */ +#define XSPI_DCR1_ADOFF XSPI_DCR1_ADOFF_Msk /*!< Address offset */ /**************** Bit definition for XSPI_DCR2 register ******************/ #define XSPI_DCR2_PRESCALER_Pos (0U) @@ -18896,12 +19034,12 @@ typedef struct #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */ /**************** Bit definition for XSPI_DCR3 register ******************/ -#define XSPI_DCR3_MAXTRAN_Pos (0U) -#define XSPI_DCR3_MAXTRAN_Msk (0xFFUL << XSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */ -#define XSPI_DCR3_MAXTRAN XSPI_DCR3_MAXTRAN_Msk /*!< Maximum transfer */ +#define XSPI_DCR3_MAXTRAN_Pos (0U) +#define XSPI_DCR3_MAXTRAN_Msk (0xFFUL << XSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */ +#define XSPI_DCR3_MAXTRAN XSPI_DCR3_MAXTRAN_Msk /*!< Maximum transfer */ #define XSPI_DCR3_CSBOUND_Pos (16U) #define XSPI_DCR3_CSBOUND_Msk (0x1FUL << XSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */ -#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< Maximum transfer */ +#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< NCS boundary */ /**************** Bit definition for XSPI_DCR4 register ******************/ #define XSPI_DCR4_REFRESH_Pos (0U) @@ -18927,6 +19065,9 @@ typedef struct #define XSPI_SR_BUSY_Pos (5U) #define XSPI_SR_BUSY_Msk (0x1UL << XSPI_SR_BUSY_Pos) /*!< 0x00000020 */ #define XSPI_SR_BUSY XSPI_SR_BUSY_Msk /*!< Busy */ +#define XSPI_SR_BERRF_Pos (6U) +#define XSPI_SR_BERRF_Msk (0x1UL << XSPI_SR_BERRF_Pos) /*!< 0x00000040 */ +#define XSPI_SR_BERRF XSPI_SR_BERRF_Msk /*!< Bus error flag */ #define XSPI_SR_FLEVEL_Pos (8U) #define XSPI_SR_FLEVEL_Msk (0x3FUL << XSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */ #define XSPI_SR_FLEVEL XSPI_SR_FLEVEL_Msk /*!< FIFO Level */ @@ -18944,6 +19085,9 @@ typedef struct #define XSPI_FCR_CTOF_Pos (4U) #define XSPI_FCR_CTOF_Msk (0x1UL << XSPI_FCR_CTOF_Pos) /*!< 0x00000010 */ #define XSPI_FCR_CTOF XSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */ +#define XSPI_FCR_CBERRF_Pos (6U) +#define XSPI_FCR_CBERRF_Msk (0x1UL << XSPI_FCR_CBERRF_Pos) /*!< 0x00000040 */ +#define XSPI_FCR_CBERRF XSPI_FCR_CBERRF_Msk /*!< Clear bus error flag */ /**************** Bit definition for XSPI_DLR register *******************/ #define XSPI_DLR_DL_Pos (0U) @@ -19237,6 +19381,9 @@ typedef struct #define OCTOSPI_CR_TCEN_Pos XSPI_CR_TCEN_Pos #define OCTOSPI_CR_TCEN_Msk XSPI_CR_TCEN_Msk /*!< 0x00000008 */ #define OCTOSPI_CR_TCEN XSPI_CR_TCEN /*!< Timeout Counter Enable */ +#define OCTOSPI_CR_ADOFFEN_Pos XSPI_CR_ADOFFEN_Pos +#define OCTOSPI_CR_ADOFFEN_Msk XSPI_CR_ADOFFEN_Msk /*!< 0x00000010 */ +#define OCTOSPI_CR_ADOFFEN XSPI_CR_ADOFFEN /*!< Address offset enable */ #define OCTOSPI_CR_DMM_Pos XSPI_CR_DMM_Pos #define OCTOSPI_CR_DMM_Msk XSPI_CR_DMM_Msk /*!< 0x00000040 */ #define OCTOSPI_CR_DMM XSPI_CR_DMM /*!< Dual Memory Mode */ @@ -19258,6 +19405,9 @@ typedef struct #define OCTOSPI_CR_TOIE_Pos XSPI_CR_TOIE_Pos #define OCTOSPI_CR_TOIE_Msk XSPI_CR_TOIE_Msk /*!< 0x00100000 */ #define OCTOSPI_CR_TOIE XSPI_CR_TOIE /*!< TimeOut Interrupt Enable */ +#define OCTOSPI_CR_BERRIE_Pos XSPI_CR_BERRIE_Pos +#define OCTOSPI_CR_BERRIE_Msk XSPI_CR_BERRIE_Msk /*!< 0x00200000 */ +#define OCTOSPI_CR_BERRIE XSPI_CR_BERRIE /*!< Bus error interrupt enable */ #define OCTOSPI_CR_APMS_Pos XSPI_CR_APMS_Pos #define OCTOSPI_CR_APMS_Msk XSPI_CR_APMS_Msk /*!< 0x00400000 */ #define OCTOSPI_CR_APMS XSPI_CR_APMS /*!< Automatic Poll Mode Stop */ @@ -19304,6 +19454,9 @@ typedef struct #define OCTOSPI_DCR1_MTYP_0 XSPI_DCR1_MTYP_0 /*!< 0x01000000 */ #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02000000 */ #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04000000 */ +#define OCTOSPI_DCR1_ADOFF_Pos XSPI_DCR1_ADOFF_Pos +#define OCTOSPI_DCR1_ADOFF_Msk XSPI_DCR1_ADOFF_Msk /*!< 0xF8000000 */ +#define OCTOSPI_DCR1_ADOFF XSPI_DCR1_ADOFF /*!< Address offset */ /**************** Bit definition for OCTOSPI_DCR2 register ******************/ #define OCTOSPI_DCR2_PRESCALER_Pos XSPI_DCR2_PRESCALER_Pos @@ -19345,6 +19498,9 @@ typedef struct #define OCTOSPI_SR_BUSY_Pos XSPI_SR_BUSY_Pos #define OCTOSPI_SR_BUSY_Msk XSPI_SR_BUSY_Msk /*!< 0x00000020 */ #define OCTOSPI_SR_BUSY XSPI_SR_BUSY /*!< Busy */ +#define OCTOSPI_SR_BERRF_Pos XSPI_SR_BERRF_Pos +#define OCTOSPI_SR_BERRF_Msk XSPI_SR_BERRF_Msk /*!< 0x00000040 */ +#define OCTOSPI_SR_BERRF XSPI_SR_BERRF /*!< Bus error flag */ #define OCTOSPI_SR_FLEVEL_Pos XSPI_SR_FLEVEL_Pos #define OCTOSPI_SR_FLEVEL_Msk (0x3FUL << OCTOSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */ #define OCTOSPI_SR_FLEVEL XSPI_SR_FLEVEL /*!< FIFO Level */ @@ -19362,6 +19518,9 @@ typedef struct #define OCTOSPI_FCR_CTOF_Pos XSPI_FCR_CTOF_Pos #define OCTOSPI_FCR_CTOF_Msk XSPI_FCR_CTOF_Msk /*!< 0x00000010 */ #define OCTOSPI_FCR_CTOF XSPI_FCR_CTOF /*!< Clear Timeout Flag */ +#define OCTOSPI_FCR_CBERRF_Pos XSPI_FCR_CBERRF_Pos +#define OCTOSPI_FCR_CBERRF_Msk XSPI_FCR_CBERRF_Msk /*!< 0x00000040 */ +#define OCTOSPI_FCR_CBERRF XSPI_FCR_CBERRF /*!< Clear bus error flag */ /**************** Bit definition for OCTOSPI_DLR register *******************/ #define OCTOSPI_DLR_DL_Pos XSPI_DLR_DL_Pos @@ -28042,9 +28201,9 @@ typedef struct #define I3C_MISR_IBIMIS_Pos (15U) #define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ #define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Interrupt status */ -#define I3C_MISR_BIENDMIS_Pos (16U) -#define I3C_MISR_BIENDMIS_Msk (0x1UL << I3C_MISR_BIENDMIS_Pos) /*!< 0x00010000 */ -#define I3C_MISR_BIENDMIS I3C_MISR_BIENDMIS_Msk /*!< IBI End Interrupt status */ +#define I3C_MISR_IBIENDMIS_Pos (16U) +#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ +#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Interrupt status */ #define I3C_MISR_CRMIS_Pos (17U) #define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ #define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Interrupt status */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h index 22750f359e..49d7f1b7a2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h @@ -61,7 +61,8 @@ && !defined (STM32H5F4xx) && !defined (STM32H5E4xx) \ && !defined (STM32H573xx) && !defined (STM32H563xx) \ && !defined (STM32H562xx) && !defined (STM32H503xx) \ - && !defined (STM32H533xx) && !defined (STM32H523xx) + && !defined (STM32H533xx) && !defined (STM32H523xx) \ + && !defined (STM32H543xx) && !defined (STM32H553xx) /* #define STM32H543xx */ /*!< STM32H543xx Devices */ /* #define STM32H553xx */ /*!< STM32H553xx Devices */ /* #define STM32H5F5xx */ /*!< STM32H5F5xx Devices */ @@ -92,7 +93,7 @@ * @brief CMSIS Device version number 1.4.0 */ #define __STM32H5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32H5_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ +#define __STM32H5_CMSIS_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ #define __STM32H5_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32H5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32H5_CMSIS_VERSION ((__STM32H5_CMSIS_VERSION_MAIN << 24U)\ @@ -107,8 +108,11 @@ /** @addtogroup Device_Included * @{ */ - -#if defined(STM32H5F5xx) +#if defined(STM32H543xx) + #include "stm32h543xx.h" +#elif defined(STM32H553xx) + #include "stm32h553xx.h" +#elif defined(STM32H5F5xx) #include "stm32h5f5xx.h" #elif defined(STM32H5F4xx) #include "stm32h5f4xx.h" diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/README.md b/system/Drivers/CMSIS/Device/ST/STM32H5xx/README.md index e677e6abe5..964da4f10c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/README.md +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/README.md @@ -1,6 +1,6 @@ # STM32CubeH5 CMSIS Device MCU Component -![tag](https://img.shields.io/badge/tag-v1.6.0-brightgreen.svg) +![tag](https://img.shields.io/badge/tag-v1.7.0-brightgreen.svg) ## Overview @@ -33,4 +33,4 @@ The full **STM32CubeH5** MCU package is available [here](https://github.com/STMi ## Troubleshooting -Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.html index bb3abc32f0..0c370de893 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.html @@ -43,9 +43,9 @@

Purpose

This driver provides the CMSIS device for the STM32H5xx product. This covers

    -
  • STM32H573xx, STM32H533xx, STM32H523xx, STM32H562xx, STM32H563xx, -STM32H503xx, STM32H5E4xx, STM32H5E5xx, STM32H5F4xx and STM32H5F5xx -devices.
    • +
  • STM32H543xx and STM32H553xx, STM32H573xx, STM32H533xx, STM32H523xx, +STM32H562xx, STM32H563xx, STM32H503xx, STM32H5E4xx, STM32H5E5xx, +STM32H5F4xx and STM32H5F5xx devices.

This driver is composed of the description of the registers under “Include” directory.

@@ -63,11 +63,45 @@

Purpose

Update history

- + + +
+

Main Changes

+
    +
  • Official release of STM32H543xx and STM32H553xx +devices.
    • +
  • CMSIS Device Release version of bits and registers definition +aligned with RM0539 (STM32H543xx / STM32H553xx reference +manual) RM0481 (STM32H523xx, STM32H533xx, +STM32H562xx, STM32H563xx and STM32H573xx reference manual), +RM0492 (STM32H503xx reference manual) and +RM0517 (STM32H5E4xx, STM32H5E5xx, STM32H5F4xx and +STM32H5F5xx reference manual)
    • +
  • MISR field is added to I3C_TypeDef for H5 4M
    • +
  • The naming of the I3C_MISR_IBIENDMIS bit has been corrected
    • +
  • The COMP_CFGR1_WINOUT bit position has been fixed for H5 1M +devices
    • +
  • Registers and bit definitions have been updated following the latest +RNG 4.4 update
    • +
  • Linker and startup files have been added for STM32H553xx and +STM32H543xx devices for the GCC toolchain
    • +
  • The RNG HTCR NIST value has been corrected in the CMSIS headers for +H5 devices
    • +
  • The reset value of EXTI_IMR2_IM has been corrected
    • +
+

Known limitations

+
    +
  • None
    • +
+
+
+
+
-

Main Changes

+

Main Changes

  • CMSIS Device Release version of bits and registers definition aligned with RM0481 (STM32H523xx, STM32H533xx, @@ -88,7 +122,7 @@

    Main Changes

  • Remove non-present TIM register definition for STM32H5-128K and STM32H5-512K devices
-

Known limitations

+

Known limitations

  • None
@@ -99,7 +133,7 @@

Known limitations

-

Main Changes

+

Main Changes

  • CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0481 (STM32H523xx, @@ -108,7 +142,7 @@

    Main Changes

  • Rename ADC_AWD3CR_AWD2CH_19 to ADC_AWD3CR_AWD3CH_19 define
  • Remove HWCFGR, VERR, PIDR and SIDR registers from CRC_TypeDef
-

Known limitations

+

Known limitations

  • None
@@ -119,7 +153,7 @@

Known limitations

-

Main Changes

+

Main Changes

  • CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0481 (STM32H5 reference @@ -130,7 +164,7 @@

    Main Changes

    (Drivers\CMSIS\Core\Include)
  • Update IS_SPI_LIMITED macro to return an essential boolean
-

Known limitations

+

Known limitations

  • None
@@ -141,7 +175,7 @@

Known limitations

-

Main Changes

+

Main Changes

  • CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0481 (STM32H5 reference @@ -161,7 +195,7 @@

    Main Changes

    register
  • Correct TIM_CCRx_CCRx constants
-

Known limitations

+

Known limitations

  • None
@@ -172,7 +206,7 @@

Known limitations

-

Main Changes

+

Main Changes

  • First official release of STM32H5xx CMSIS drivers to support STM32H533xx and STM32H523xx devices
    • @@ -193,7 +227,7 @@

    Main Changes

  • Fix: Ticket 167776: [CMSIS] Missing TIM option register related definitions
-

Known limitations

+

Known limitations

  • None
@@ -204,7 +238,7 @@

Known limitations

-

Main Changes

+

Main Changes

  • Add DUA addresses constants definitions for STM32H573xx devices only
    • @@ -213,7 +247,7 @@

    Main Changes

  • Update possible values of the ATCKSEL field of TAMP active tamper control register and update the mask accordingly.
-

Known limitations

+

Known limitations

  • None
@@ -224,12 +258,12 @@

Known limitations

-

Main Changes

+

Main Changes

  • First official release version of bits and registers definition aligned with RM0481 and RM0492 (STM32H5 reference manuals)
-

Known limitations

+

Known limitations

  • None
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.md b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.md new file mode 100644 index 0000000000..6a278fcca4 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.md @@ -0,0 +1,175 @@ + + +# Release Notes for STM32H5xx CMSIS +Copyright © 2024 STMicroelectronics\ + +[![ST logo](_htmresc/st_logo_2020.png)](https://www.st.com) + +# Purpose + +This driver provides the CMSIS device for the STM32H5xx product. This covers + +- STM32H543xx and STM32H553xx, STM32H573xx, STM32H533xx, STM32H523xx, STM32H562xx, STM32H563xx, STM32H503xx, STM32H5E4xx, STM32H5E5xx, STM32H5F4xx and STM32H5F5xx devices. + +This driver is composed of the description of the registers under "Include" directory. + +Various template files are provided to easily build an application. They can be adapted to fit applications requirements. + +- Templates/system_stm32h5xx.c contains the initialization code referred as SystemInit. +- Startup files are provided as example for EWARM©, MDK-ARM©, STM32CubeIDE©. +- Linker files are provided as example for EWARM©, MDK-ARM©, STM32CubeIDE©. + + +# Update history + + +
+ +## Main Changes + +- Official release of **STM32H543xx and STM32H553xx** devices. +- CMSIS Device Release version of bits and registers definition aligned with **RM0539 (STM32H543xx / STM32H553xx reference manual)** + **RM0481** (STM32H523xx, STM32H533xx, STM32H562xx, STM32H563xx and STM32H573xx reference manual), **RM0492** (STM32H503xx reference manual) + and **RM0517** (STM32H5E4xx, STM32H5E5xx, STM32H5F4xx and STM32H5F5xx reference manual) +- MISR field is added to I3C_TypeDef for H5 4M +- The naming of the I3C_MISR_IBIENDMIS bit has been corrected +- The COMP_CFGR1_WINOUT bit position has been fixed for H5 1M devices +- Registers and bit definitions have been updated following the latest RNG 4.4 update +- Linker and startup files have been added for STM32H553xx and STM32H543xx devices for the GCC toolchain +- The RNG HTCR NIST value has been corrected in the CMSIS headers for H5 devices +- The reset value of EXTI_IMR2_IM has been corrected + +## Known limitations + +- None + +
+ + +
+ +## Main Changes + +- CMSIS Device Release version of bits and registers definition aligned with **RM0481** (STM32H523xx, STM32H533xx, STM32H562xx, STM32H563xx and STM32H573xx reference manual), **RM0492** (STM32H503xx reference manual) and **RM0517** (STM32H5E4xx, STM32H5E5xx, STM32H5F4xx and STM32H5F5xx reference manual) +- Official release of **STM32H5E4xx, STM32H5E5xx, STM32H5F4xx** and **STM32H5F5xx** +- Fix `SystemInit()` resetting HSIDIV, which caused wrong Flash latency configuration and potential hard faults +- Set stack limit (MSPLIM) in CMSIS Device templates for ARMv8-M–based products +- LTDC: interrupt name aligned with reference manual +- UCPD: removed bits defined in CMSIS file but unavailable in the reference manual +- USB: added missing bits definition in the CMSIS file +- Remove non-present TIM register definition for STM32H5-128K and STM32H5-512K devices + +## Known limitations + +- None + +
+ + +
+ +## Main Changes + +- CMSIS Device Maintenance Release version of bits and registers definition aligned with **RM0481** (STM32H523xx, STM32H533xx, STM32H562xx, STM32H563xx and STM32H573xx reference manual) and **RM0492** (STM32H503xx reference manual) +- Rename ADC_AWD3CR_AWD2CH_19 to ADC_AWD3CR_AWD3CH_19 define +- Remove HWCFGR, VERR, PIDR and SIDR registers from CRC_TypeDef + +## Known limitations + +- None + +
+ + +
+ +## Main Changes + +- CMSIS Device Maintenance Release version of bits and registers definition aligned with **RM0481** (STM32H5 reference manual) +- Update to use #include \"core_cm33.h\" instead of #include to force the first searches for the core_cm33.h file in the same directory as the file that contains the #include directive (Drivers\\CMSIS\\Core\\Include) +- Update IS_SPI_LIMITED macro to return an essential boolean + +## Known limitations + +- None + +
+ + + +
+ +## Main Changes + +- CMSIS Device Maintenance Release version of bits and registers definition aligned with **RM0481** (STM32H5 reference manual) +- Add RNG_CR_NIST_VALUE, RNG_NSCR_NIST_VALUE and RNG_HTCR_NIST_VALUE defines +- Add Bits definition for RNG_NSCR register : Add RNG_NSCR_EN_OSC1, RNG_NSCR_EN_OSC2, RNG_NSCR_EN_OSC3, RNG_NSCR_EN_OSC4, RNG_NSCR_EN_OSC5 and RNG_NSCR_EN_OSC6 defines +- Add USART_DMAREQUESTS_SW_WA define +- Rename EXTI_RTSR2_TR to EXTI_RTSR2_RT define +- Rename EXTI_FTSR2_TR to EXTI_FTSR2_FT define +- Remove unused ADC common status and ADC common group regular data registers for STM32H503xx devices +- Fix __SAUREGION_PRESENT value to 0 for STM32H503xx devices +- Fix incorrect character in the definition of OCTOSPI_CR register +- Correct TIM_CCRx_CCRx constants + +## Known limitations + +- None + +
+ + + +
+ +## Main Changes + +- First official release of STM32H5xx CMSIS drivers to support **STM32H533xx and STM32H523xx** devices +- Add bit definition for I3C_BCR register +- Add IS_DMA_PFREQ_INSTANCE macro +- Fix Ticket 163445: [FLASH][CMSIS] Wrong EDATA_STRT start sectors mask size +- Fix Ticket 163090: [FOSS-Audit] Licensing issues: Missing copyright from Arm Limited and original header not retained +- Update CubeIDE projects to be compliant with GCC12 diagnostics +- Fix Ticket 165407: [H5][GTZC][CMSIS]: wrong Flash illegal access bit definition +- Fix Ticket 147880: [STM32H5]|FLASH_HAL] Some option bytes are missing in stm32h5xx_hal_flash_ex.h +- Set FMC_SDCMR_MODE_2 bit field definition to 0x4 +- Fix Ticket 162902: [GitHub] Wrong declaration of g_pfnVectors size in gcc/startup files +- Fix: Ticket 167776: [CMSIS] Missing TIM option register related definitions + +## Known limitations + +- None + +
+ + +
+ +## Main Changes + +- Add DUA addresses constants definitions for STM32H573xx devices only +- Fix wrong definition of IS_TIM_CLOCKSOURCE_TIX_INSTANCE & IS_TIM_TISEL_INSTANCE macros +- Update possible values of the ATCKSEL field of TAMP active tamper control register and update the mask accordingly. + +## Known limitations + +- None + +
+ + +
+ +## Main Changes + +- First official release version of bits and registers definition aligned with RM0481 and RM0492 (STM32H5 reference manuals) + +## Known limitations + +- None + +
+ + +For complete documentation on STM32 Microcontrollers , +visit: http://www.st.com/stm32 diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H543xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H543xx_FLASH.ld new file mode 100644 index 0000000000..59a51239a8 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H543xx_FLASH.ld @@ -0,0 +1,188 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H543xx Device from STM32H5 series +** 1024Kbytes FLASH +** 304Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 304K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H543xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H543xx_FLASH_ns.ld new file mode 100644 index 0000000000..964869b8b6 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H543xx_FLASH_ns.ld @@ -0,0 +1,188 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H543xx Device from STM32H5 series +** 512KBytes FLASH +** 96KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20034000, LENGTH = 96K + FLASH (rx) : ORIGIN = 0x08080000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H543xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H543xx_FLASH_s.ld new file mode 100644 index 0000000000..d5b20e1f6a --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H543xx_FLASH_s.ld @@ -0,0 +1,197 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H543xx Device from STM32H5 series +** 504KBytes FLASH +** 8KBytes FLASH_NSC +** 208KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 208K + FLASH (rx) : ORIGIN = 0x0C000000, LENGTH = 504K + FLASH_NSC (rx) : ORIGIN = 0x0C07E000, LENGTH = 8K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H553xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H553xx_FLASH.ld new file mode 100644 index 0000000000..d280590161 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H553xx_FLASH.ld @@ -0,0 +1,188 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H553xx Device from STM32H5 series +** 1024Kbytes FLASH +** 304Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 304K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H553xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H553xx_FLASH_ns.ld new file mode 100644 index 0000000000..17eaac446d --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H553xx_FLASH_ns.ld @@ -0,0 +1,188 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H553xx Device from STM32H5 series +** 512KBytes FLASH +** 96KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20034000, LENGTH = 96K + FLASH (rx) : ORIGIN = 0x08080000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H553xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H553xx_FLASH_s.ld new file mode 100644 index 0000000000..743eff1658 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H553xx_FLASH_s.ld @@ -0,0 +1,197 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H553xx Device from STM32H5 series +** 504KBytes FLASH +** 8KBytes FLASH_NSC +** 208KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 208K + FLASH (rx) : ORIGIN = 0x0C000000, LENGTH = 504K + FLASH_NSC (rx) : ORIGIN = 0x0C07E000, LENGTH = 8K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h543xx.s b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h543xx.s new file mode 100644 index 0000000000..7315f3b709 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h543xx.s @@ -0,0 +1,679 @@ +/** + ****************************************************************************** + * @file startup_stm32h543xx.s + * @author MCD Application Team + * @brief STM32H553xx non-crypto devices vector table - GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M33 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m33 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. + defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None + */ + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + /* Set main stack pointer and limit */ + ldr sp, =_estack /* set stack pointer */ + ldr r0, =_sstack + msr MSPLIM, r0 /* set stack pointer limit */ + + /* Call the clock system initialization function. */ + bl SystemInit + + /* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + + /* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + /* Call static constructors */ + bl __libc_init_array + /* Call the application's entry point. */ + bl main + +LoopForever: + b LoopForever + + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32H543xx vector table (RM0539 Table 152). +* Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word SecureFault_Handler + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + .word WWDG_IRQHandler + .word PVD_AVD_IRQHandler + .word RTC_IRQHandler + .word RTC_S_IRQHandler + .word TAMP_IRQHandler + .word RAMCFG_IRQHandler + .word FLASH_IRQHandler + .word FLASH_S_IRQHandler + .word GTZC_IRQHandler + .word RCC_IRQHandler + .word RCC_S_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word EXTI5_IRQHandler + .word EXTI6_IRQHandler + .word EXTI7_IRQHandler + .word EXTI8_IRQHandler + .word EXTI9_IRQHandler + .word EXTI10_IRQHandler + .word EXTI11_IRQHandler + .word EXTI12_IRQHandler + .word EXTI13_IRQHandler + .word EXTI14_IRQHandler + .word EXTI15_IRQHandler + .word GPDMA1_Channel0_IRQHandler + .word GPDMA1_Channel1_IRQHandler + .word GPDMA1_Channel2_IRQHandler + .word GPDMA1_Channel3_IRQHandler + .word GPDMA1_Channel4_IRQHandler + .word GPDMA1_Channel5_IRQHandler + .word GPDMA1_Channel6_IRQHandler + .word GPDMA1_Channel7_IRQHandler + .word IWDG_IRQHandler + .word 0 + .word ADC1_IRQHandler + .word DAC1_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word TIM5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word SPI3_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word LPUART1_IRQHandler + .word LPTIM1_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC2_IRQHandler + .word LPTIM2_IRQHandler + .word TIM15_IRQHandler + .word 0 + .word 0 + .word USB_DRD_FS_IRQHandler + .word CRS_IRQHandler + .word UCPD1_IRQHandler + .word FMC_IRQHandler + .word OCTOSPI1_IRQHandler + .word SDMMC1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SPI4_IRQHandler + .word 0 + .word 0 + .word USART6_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word GPDMA2_Channel0_IRQHandler + .word GPDMA2_Channel1_IRQHandler + .word GPDMA2_Channel2_IRQHandler + .word GPDMA2_Channel3_IRQHandler + .word GPDMA2_Channel4_IRQHandler + .word GPDMA2_Channel5_IRQHandler + .word GPDMA2_Channel6_IRQHandler + .word GPDMA2_Channel7_IRQHandler + .word UART7_IRQHandler + .word UART8_IRQHandler + .word 0 + .word 0 + .word 0 + .word FPU_IRQHandler + .word ICACHE_IRQHandler + .word DCACHE1_IRQHandler + .word ETH_IRQHandler + .word ETH_WKUP_IRQHandler + .word 0 + .word FDCAN2_IT0_IRQHandler + .word FDCAN2_IT1_IRQHandler + .word CORDIC_IRQHandler + .word 0 + .word DTS_IRQHandler + .word RNG_IRQHandler + .word 0 + .word 0 + .word HASH_IRQHandler + .word 0 + .word CEC_IRQHandler + .word TIM12_IRQHandler + .word 0 + .word 0 + .word I3C1_EV_IRQHandler + .word I3C1_ER_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word I3C2_EV_IRQHandler + .word I3C2_ER_IRQHandler + .word COMP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word PLAY1_IRQHandler + .word PLAY1_S_IRQHandler + .word ADC3_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SecureFault_Handler + .thumb_set SecureFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_AVD_IRQHandler + .thumb_set PVD_AVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak RTC_S_IRQHandler + .thumb_set RTC_S_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak RAMCFG_IRQHandler + .thumb_set RAMCFG_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak FLASH_S_IRQHandler + .thumb_set FLASH_S_IRQHandler,Default_Handler + + .weak GTZC_IRQHandler + .thumb_set GTZC_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak RCC_S_IRQHandler + .thumb_set RCC_S_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak DAC1_IRQHandler + .thumb_set DAC1_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC2_IRQHandler + .thumb_set ADC2_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak USB_DRD_FS_IRQHandler + .thumb_set USB_DRD_FS_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak GPDMA2_Channel0_IRQHandler + .thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler + + .weak GPDMA2_Channel1_IRQHandler + .thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler + + .weak GPDMA2_Channel2_IRQHandler + .thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler + + .weak GPDMA2_Channel3_IRQHandler + .thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler + + .weak GPDMA2_Channel4_IRQHandler + .thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler + + .weak GPDMA2_Channel5_IRQHandler + .thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler + + .weak GPDMA2_Channel6_IRQHandler + .thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler + + .weak GPDMA2_Channel7_IRQHandler + .thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak DCACHE1_IRQHandler + .thumb_set DCACHE1_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak I3C1_EV_IRQHandler + .thumb_set I3C1_EV_IRQHandler,Default_Handler + + .weak I3C1_ER_IRQHandler + .thumb_set I3C1_ER_IRQHandler,Default_Handler + + .weak I3C2_EV_IRQHandler + .thumb_set I3C2_EV_IRQHandler,Default_Handler + + .weak I3C2_ER_IRQHandler + .thumb_set I3C2_ER_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak PLAY1_IRQHandler + .thumb_set PLAY1_IRQHandler,Default_Handler + + .weak PLAY1_S_IRQHandler + .thumb_set PLAY1_S_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h553xx.s b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h553xx.s new file mode 100644 index 0000000000..f5dfcf554c --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h553xx.s @@ -0,0 +1,691 @@ +/** + ****************************************************************************** + * @file startup_stm32h553xx.s + * @author MCD Application Team + * @brief STM32H553xx Crypto devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M33 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m33 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. + defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None + */ + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + /* Set main stack pointer and limit */ + ldr sp, =_estack /* set stack pointer */ + ldr r0, =_sstack + msr MSPLIM, r0 /* set stack pointer limit */ + + /* Call the clock system initialization function. */ + bl SystemInit + + /* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + + /* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + /* Call static constructors */ + bl __libc_init_array + /* Call the application's entry point. */ + bl main + +LoopForever: + b LoopForever + + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32H553xx vector table (RM0539 Table 152). +* Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word SecureFault_Handler + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + .word WWDG_IRQHandler + .word PVD_AVD_IRQHandler + .word RTC_IRQHandler + .word RTC_S_IRQHandler + .word TAMP_IRQHandler + .word RAMCFG_IRQHandler + .word FLASH_IRQHandler + .word FLASH_S_IRQHandler + .word GTZC_IRQHandler + .word RCC_IRQHandler + .word RCC_S_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word EXTI5_IRQHandler + .word EXTI6_IRQHandler + .word EXTI7_IRQHandler + .word EXTI8_IRQHandler + .word EXTI9_IRQHandler + .word EXTI10_IRQHandler + .word EXTI11_IRQHandler + .word EXTI12_IRQHandler + .word EXTI13_IRQHandler + .word EXTI14_IRQHandler + .word EXTI15_IRQHandler + .word GPDMA1_Channel0_IRQHandler + .word GPDMA1_Channel1_IRQHandler + .word GPDMA1_Channel2_IRQHandler + .word GPDMA1_Channel3_IRQHandler + .word GPDMA1_Channel4_IRQHandler + .word GPDMA1_Channel5_IRQHandler + .word GPDMA1_Channel6_IRQHandler + .word GPDMA1_Channel7_IRQHandler + .word IWDG_IRQHandler + .word SAES_IRQHandler + .word ADC1_IRQHandler + .word DAC1_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word TIM5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word SPI3_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word LPUART1_IRQHandler + .word LPTIM1_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC2_IRQHandler + .word LPTIM2_IRQHandler + .word TIM15_IRQHandler + .word 0 + .word 0 + .word USB_DRD_FS_IRQHandler + .word CRS_IRQHandler + .word UCPD1_IRQHandler + .word FMC_IRQHandler + .word OCTOSPI1_IRQHandler + .word SDMMC1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SPI4_IRQHandler + .word 0 + .word 0 + .word USART6_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word GPDMA2_Channel0_IRQHandler + .word GPDMA2_Channel1_IRQHandler + .word GPDMA2_Channel2_IRQHandler + .word GPDMA2_Channel3_IRQHandler + .word GPDMA2_Channel4_IRQHandler + .word GPDMA2_Channel5_IRQHandler + .word GPDMA2_Channel6_IRQHandler + .word GPDMA2_Channel7_IRQHandler + .word UART7_IRQHandler + .word UART8_IRQHandler + .word 0 + .word 0 + .word 0 + .word FPU_IRQHandler + .word ICACHE_IRQHandler + .word DCACHE1_IRQHandler + .word ETH_IRQHandler + .word ETH_WKUP_IRQHandler + .word 0 + .word FDCAN2_IT0_IRQHandler + .word FDCAN2_IT1_IRQHandler + .word CORDIC_IRQHandler + .word 0 + .word DTS_IRQHandler + .word RNG_IRQHandler + .word OTFDEC1_IRQHandler + .word AES_IRQHandler + .word HASH_IRQHandler + .word PKA_IRQHandler + .word CEC_IRQHandler + .word TIM12_IRQHandler + .word 0 + .word 0 + .word I3C1_EV_IRQHandler + .word I3C1_ER_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word I3C2_EV_IRQHandler + .word I3C2_ER_IRQHandler + .word COMP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word PLAY1_IRQHandler + .word PLAY1_S_IRQHandler + .word ADC3_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SecureFault_Handler + .thumb_set SecureFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_AVD_IRQHandler + .thumb_set PVD_AVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak RTC_S_IRQHandler + .thumb_set RTC_S_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak RAMCFG_IRQHandler + .thumb_set RAMCFG_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak FLASH_S_IRQHandler + .thumb_set FLASH_S_IRQHandler,Default_Handler + + .weak GTZC_IRQHandler + .thumb_set GTZC_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak RCC_S_IRQHandler + .thumb_set RCC_S_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak SAES_IRQHandler + .thumb_set SAES_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak DAC1_IRQHandler + .thumb_set DAC1_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC2_IRQHandler + .thumb_set ADC2_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak USB_DRD_FS_IRQHandler + .thumb_set USB_DRD_FS_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak GPDMA2_Channel0_IRQHandler + .thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler + + .weak GPDMA2_Channel1_IRQHandler + .thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler + + .weak GPDMA2_Channel2_IRQHandler + .thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler + + .weak GPDMA2_Channel3_IRQHandler + .thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler + + .weak GPDMA2_Channel4_IRQHandler + .thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler + + .weak GPDMA2_Channel5_IRQHandler + .thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler + + .weak GPDMA2_Channel6_IRQHandler + .thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler + + .weak GPDMA2_Channel7_IRQHandler + .thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak DCACHE1_IRQHandler + .thumb_set DCACHE1_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak OTFDEC1_IRQHandler + .thumb_set OTFDEC1_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak I3C1_EV_IRQHandler + .thumb_set I3C1_EV_IRQHandler,Default_Handler + + .weak I3C1_ER_IRQHandler + .thumb_set I3C1_ER_IRQHandler,Default_Handler + + .weak I3C2_EV_IRQHandler + .thumb_set I3C2_EV_IRQHandler,Default_Handler + + .weak I3C2_ER_IRQHandler + .thumb_set I3C2_ER_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak PLAY1_IRQHandler + .thumb_set PLAY1_IRQHandler,Default_Handler + + .weak PLAY1_S_IRQHandler + .thumb_set PLAY1_S_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h562xx.s b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h562xx.s index 81cbb85867..179b56a362 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h562xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h562xx.s @@ -1,8 +1,8 @@ /** ****************************************************************************** - * @file startup_stm32h573xx.s + * @file startup_stm32h562xx.s * @author MCD Application Team - * @brief STM32H563xx devices vector table GCC toolchain. + * @brief STM32H562xx devices vector table GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 0e7714891e..a131463323 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -9,7 +9,7 @@ * STM32F7: 1.2.10 * STM32G0: 1.4.5 * STM32G4: 1.2.6 - * STM32H5: 1.6.0 + * STM32H5: 1.7.0 * STM32H7: 1.10.7 * STM32L0: 1.9.4 * STM32L1: 2.3.4 From 33d6193c0e00f82bdf69213eefb362a0a37684a0 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Jul 2026 09:31:40 +0200 Subject: [PATCH 3/3] core(h5): update wrapped files Signed-off-by: Frederic Pillon --- cores/arduino/stm32/stm32_def_build.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index bb35e4c231..b63657aab4 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -240,6 +240,10 @@ #define CMSIS_STARTUP_FILE "startup_stm32h523xx.s" #elif defined(STM32H533xx) #define CMSIS_STARTUP_FILE "startup_stm32h533xx.s" + #elif defined(STM32H543xx) + #define CMSIS_STARTUP_FILE "startup_stm32h543xx.s" + #elif defined(STM32H553xx) + #define CMSIS_STARTUP_FILE "startup_stm32h553xx.s" #elif defined(STM32H562xx) #define CMSIS_STARTUP_FILE "startup_stm32h562xx.s" #elif defined(STM32H563xx)