diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index bb35e4c231..aec11279cb 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -454,6 +454,10 @@ #define CMSIS_STARTUP_FILE "startup_stm32u073xx.s" #elif defined(STM32U083xx) #define CMSIS_STARTUP_FILE "startup_stm32u083xx.s" + #elif defined(STM32U335xx) + #define CMSIS_STARTUP_FILE "startup_stm32u335xx.s" + #elif defined(STM32U345xx) + #define CMSIS_STARTUP_FILE "startup_stm32u345xx.s" #elif defined(STM32U356xx) #define CMSIS_STARTUP_FILE "startup_stm32u356xx.s" #elif defined(STM32U366xx) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/partition_stm32u3xx.h b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/partition_stm32u3xx.h index d8be2742e7..818bc96af6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/partition_stm32u3xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/partition_stm32u3xx.h @@ -41,7 +41,15 @@ /** @addtogroup Secure_configuration_section * @{ */ -#if defined(STM32U375xx) +#if defined(STM32U356xx) + #include "partition_stm32u356xx.h" +#elif defined(STM32U366xx) + #include "partition_stm32u366xx.h" +#elif defined(STM32U396xx) + #include "partition_stm32u396xx.h" +#elif defined(STM32U3A6xx) + #include "partition_stm32u3a6xx.h" +#elif defined(STM32U375xx) #include "partition_stm32u375xx.h" #elif defined(STM32U385xx) #include "partition_stm32u385xx.h" @@ -49,6 +57,10 @@ #include "partition_stm32u3b5xx.h" #elif defined(STM32U3C5xx) #include "partition_stm32u3c5xx.h" +#elif defined(STM32U335xx) + #include "partition_stm32u335xx.h" +#elif defined(STM32U345xx) + #include "partition_stm32u345xx.h" #else #error "Please select first the target STM32U3xx device used in your application (in stm32u3xx.h file)" #endif diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u335xx.h b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u335xx.h index 93cb2c72ca..becf68bee4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u335xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u335xx.h @@ -939,7 +939,10 @@ typedef struct __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ } RNG_TypeDef; /** @@ -1301,7 +1304,7 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define FLASH_BASE_NS 0x08000000UL /*!< FLASH non-secure base address */ #define SYSTEM_FLASH_BASE_NS 0x0BF80000UL /*!< System FLASH non-secure base address */ #define SRAM1_BASE_NS 0x20000000UL /*!< SRAM1 non-secure base address */ -#define SRAM2_BASE_NS 0x20040000UL /*!< SRAM2 non-secure base address */ +#define SRAM2_BASE_NS 0x20004000UL /*!< SRAM2 non-secure base address */ #define PERIPH_BASE_NS 0x40000000UL /*!< Peripheral non-secure base address */ #define EXTRAM_BASE_NS 0x90000000UL /*!< External RAM base address */ @@ -1413,6 +1416,7 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000C00UL) #define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001C00UL) #define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008000UL) +#define ADC1_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008300UL) #define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008400UL) #define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0400UL) #define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0710UL) @@ -1425,7 +1429,7 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define FLASH_BASE_S 0x0C000000UL /*!< FLASH secure base address */ #define SYSTEM_FLASH_BASE_S 0x0FF80000UL /*!< System FLASH secure base address */ #define SRAM1_BASE_S 0x30000000UL /*!< SRAM1 secure base address */ -#define SRAM2_BASE_S 0x30030000UL /*!< SRAM2 secure base address */ +#define SRAM2_BASE_S 0x30004000UL /*!< SRAM2 secure base address */ #define PERIPH_BASE_S 0x50000000UL /*!< Peripheral secure base address */ /*!< Peripheral memory map - secure */ @@ -1516,6 +1520,7 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00000C00UL) #define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x00001C00UL) #define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x00008000UL) +#define ADC1_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x00008300UL) #define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x00008400UL) #define HASH_BASE_S (AHB2PERIPH_BASE_S + 0x000A0400UL) #define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0x000A0710UL) @@ -1645,6 +1650,7 @@ typedef struct /** @addtogroup STM32U3xx_Peripheral_declaration * @{ */ +#define ADC1_COMMON_NS ((ADC_Common_TypeDef *) ADC1_COMMON_BASE_NS) #define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) #define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) #define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) @@ -1727,6 +1733,7 @@ typedef struct #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) #if defined (CPU_IN_SECURE_STATE) +#define ADC1_COMMON_S ((ADC_Common_TypeDef *) ADC1_COMMON_BASE_S) #define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) #define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) #define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) @@ -1813,6 +1820,8 @@ typedef struct #define SRAM2_BASE SRAM2_BASE_S /*!< Instance aliases and base addresses for Secure peripherals */ +#define ADC1_COMMON ADC1_COMMON_S +#define ADC1_COMMON_BASE ADC1_COMMON_BASE_S #define ADC1 ADC1_S #define ADC1_BASE ADC1_BASE_S #define ADF1 ADF1_S @@ -1978,6 +1987,8 @@ typedef struct #define SRAM2_BASE SRAM2_BASE_NS /*!< Instance aliases and base addresses for Secure peripherals */ +#define ADC1_COMMON ADC1_COMMON_NS +#define ADC1_COMMON_BASE ADC1_COMMON_BASE_NS #define ADC1 ADC1_NS #define ADC1_BASE ADC1_BASE_NS #define ADF1 ADF1_NS @@ -6492,10 +6503,10 @@ typedef struct /****************** Bits definition for FLASH_WRP1BR register ***************/ #define FLASH_WRP1BR_STRT_Pos (0UL) -#define FLASH_WRP1BR_STRT_Msk (0x7FUL << FLASH_WRP1BR_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP1BR_STRT_Msk (0x1FUL << FLASH_WRP1BR_STRT_Pos) /*!< 0x0000001F */ #define FLASH_WRP1BR_STRT FLASH_WRP1BR_STRT_Msk /*!< Bank 1 WRP second area B start page */ #define FLASH_WRP1BR_END_Pos (16UL) -#define FLASH_WRP1BR_END_Msk (0x7FUL << FLASH_WRP1BR_END_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP1BR_END_Msk (0x1FUL << FLASH_WRP1BR_END_Pos) /*!< 0x001F0000 */ #define FLASH_WRP1BR_END FLASH_WRP1BR_END_Msk /*!< Bank 1 WRP second area B end page */ #define FLASH_WRP1BR_UNLOCK_Pos (31UL) #define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ @@ -6503,15 +6514,15 @@ typedef struct /***************** Bits definition for FLASH_SECWM2R1 register **************/ #define FLASH_SECWM2R1_SECWM2_STRT_Pos (0UL) -#define FLASH_SECWM2R1_SECWM2_STRT_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_SECWM2R1_SECWM2_STRT_Msk (0x1FUL << FLASH_SECWM2R1_SECWM2_STRT_Pos) /*!< 0x0000001F */ #define FLASH_SECWM2R1_SECWM2_STRT FLASH_SECWM2R1_SECWM2_STRT_Msk /*!< Start page of second secure area */ #define FLASH_SECWM2R1_SECWM2_END_Pos (16UL) -#define FLASH_SECWM2R1_SECWM2_END_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_END_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWM2R1_SECWM2_END_Msk (0x1FUL << FLASH_SECWM2R1_SECWM2_END_Pos) /*!< 0x001F0000 */ #define FLASH_SECWM2R1_SECWM2_END FLASH_SECWM2R1_SECWM2_END_Msk /*!< End page of second secure area */ /***************** Bits definition for FLASH_SECWM2R2 register **************/ #define FLASH_SECWM2R2_HDP2_END_Pos (16UL) -#define FLASH_SECWM2R2_HDP2_END_Msk (0x7FUL << FLASH_SECWM2R2_HDP2_END_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWM2R2_HDP2_END_Msk (0x1FUL << FLASH_SECWM2R2_HDP2_END_Pos) /*!< 0x001F0000 */ #define FLASH_SECWM2R2_HDP2_END FLASH_SECWM2R2_HDP2_END_Msk /*!< End page of hide protection second area */ #define FLASH_SECWM2R2_HDP2EN_Pos (24UL) #define FLASH_SECWM2R2_HDP2EN_Msk (0xFFUL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0xFF000000 */ @@ -6519,10 +6530,10 @@ typedef struct /****************** Bits definition for FLASH_WRP2AR register ***************/ #define FLASH_WRP2AR_STRT_Pos (0UL) -#define FLASH_WRP2AR_STRT_Msk (0x7FUL << FLASH_WRP2AR_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP2AR_STRT_Msk (0x1FUL << FLASH_WRP2AR_STRT_Pos) /*!< 0x0000001F */ #define FLASH_WRP2AR_STRT FLASH_WRP2AR_STRT_Msk /*!< Bank 2 WPR first area A start page */ #define FLASH_WRP2AR_END_Pos (16UL) -#define FLASH_WRP2AR_END_Msk (0x7FUL << FLASH_WRP2AR_END_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP2AR_END_Msk (0x1FUL << FLASH_WRP2AR_END_Pos) /*!< 0x001F0000 */ #define FLASH_WRP2AR_END FLASH_WRP2AR_END_Msk /*!< Bank 2 WPR first area A end page */ #define FLASH_WRP2AR_UNLOCK_Pos (31UL) #define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ @@ -6530,10 +6541,10 @@ typedef struct /****************** Bits definition for FLASH_WRP2BR register ***************/ #define FLASH_WRP2BR_STRT_Pos (0UL) -#define FLASH_WRP2BR_STRT_Msk (0x7FUL << FLASH_WRP2BR_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP2BR_STRT_Msk (0x1FUL << FLASH_WRP2BR_STRT_Pos) /*!< 0x0000001F */ #define FLASH_WRP2BR_STRT FLASH_WRP2BR_STRT_Msk /*!< Bank 2 WPR second area B start page */ #define FLASH_WRP2BR_END_Pos (16UL) -#define FLASH_WRP2BR_END_Msk (0x7FUL << FLASH_WRP2BR_END_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP2BR_END_Msk (0x1FUL << FLASH_WRP2BR_END_Pos) /*!< 0x001F0000 */ #define FLASH_WRP2BR_END FLASH_WRP2BR_END_Msk /*!< Bank 2 WPR second area B end page */ #define FLASH_WRP2BR_UNLOCK_Pos (31UL) #define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ @@ -6637,299 +6648,6 @@ typedef struct #define FLASH_SECBB1R1_SEC31_Msk (0x1UL << FLASH_SECBB1R1_SEC31_Pos) /*!< 0x80000000 */ #define FLASH_SECBB1R1_SEC31 FLASH_SECBB1R1_SEC31_Msk /*!< Page 31 in bank 1 block-based secure */ -/******************* Bit definition for FLASH_SECBB1R2 register ******************/ -#define FLASH_SECBB1R2_SEC0_Pos (0UL) -#define FLASH_SECBB1R2_SEC0_Msk (0x1UL << FLASH_SECBB1R2_SEC0_Pos) /*!< 0x00000001 */ -#define FLASH_SECBB1R2_SEC0 FLASH_SECBB1R2_SEC0_Msk /*!< Page 32 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC1_Pos (1UL) -#define FLASH_SECBB1R2_SEC1_Msk (0x1UL << FLASH_SECBB1R2_SEC1_Pos) /*!< 0x00000002 */ -#define FLASH_SECBB1R2_SEC1 FLASH_SECBB1R2_SEC1_Msk /*!< Page 33 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC2_Pos (2UL) -#define FLASH_SECBB1R2_SEC2_Msk (0x1UL << FLASH_SECBB1R2_SEC2_Pos) /*!< 0x00000004 */ -#define FLASH_SECBB1R2_SEC2 FLASH_SECBB1R2_SEC2_Msk /*!< Page 34 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC3_Pos (3UL) -#define FLASH_SECBB1R2_SEC3_Msk (0x1UL << FLASH_SECBB1R2_SEC3_Pos) /*!< 0x00000008 */ -#define FLASH_SECBB1R2_SEC3 FLASH_SECBB1R2_SEC3_Msk /*!< Page 35 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC4_Pos (4UL) -#define FLASH_SECBB1R2_SEC4_Msk (0x1UL << FLASH_SECBB1R2_SEC4_Pos) /*!< 0x00000010 */ -#define FLASH_SECBB1R2_SEC4 FLASH_SECBB1R2_SEC4_Msk /*!< Page 36 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC5_Pos (5UL) -#define FLASH_SECBB1R2_SEC5_Msk (0x1UL << FLASH_SECBB1R2_SEC5_Pos) /*!< 0x00000020 */ -#define FLASH_SECBB1R2_SEC5 FLASH_SECBB1R2_SEC5_Msk /*!< Page 37 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC6_Pos (6UL) -#define FLASH_SECBB1R2_SEC6_Msk (0x1UL << FLASH_SECBB1R2_SEC6_Pos) /*!< 0x00000040 */ -#define FLASH_SECBB1R2_SEC6 FLASH_SECBB1R2_SEC6_Msk /*!< Page 38 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC7_Pos (7UL) -#define FLASH_SECBB1R2_SEC7_Msk (0x1UL << FLASH_SECBB1R2_SEC7_Pos) /*!< 0x00000080 */ -#define FLASH_SECBB1R2_SEC7 FLASH_SECBB1R2_SEC7_Msk /*!< Page 39 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC8_Pos (8UL) -#define FLASH_SECBB1R2_SEC8_Msk (0x1UL << FLASH_SECBB1R2_SEC8_Pos) /*!< 0x00000100 */ -#define FLASH_SECBB1R2_SEC8 FLASH_SECBB1R2_SEC8_Msk /*!< Page 40 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC9_Pos (9UL) -#define FLASH_SECBB1R2_SEC9_Msk (0x1UL << FLASH_SECBB1R2_SEC9_Pos) /*!< 0x00000200 */ -#define FLASH_SECBB1R2_SEC9 FLASH_SECBB1R2_SEC9_Msk /*!< Page 41 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC10_Pos (10UL) -#define FLASH_SECBB1R2_SEC10_Msk (0x1UL << FLASH_SECBB1R2_SEC10_Pos) /*!< 0x00000400 */ -#define FLASH_SECBB1R2_SEC10 FLASH_SECBB1R2_SEC10_Msk /*!< Page 42 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC11_Pos (11UL) -#define FLASH_SECBB1R2_SEC11_Msk (0x1UL << FLASH_SECBB1R2_SEC11_Pos) /*!< 0x00000800 */ -#define FLASH_SECBB1R2_SEC11 FLASH_SECBB1R2_SEC11_Msk /*!< Page 43 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC12_Pos (12UL) -#define FLASH_SECBB1R2_SEC12_Msk (0x1UL << FLASH_SECBB1R2_SEC12_Pos) /*!< 0x00001000 */ -#define FLASH_SECBB1R2_SEC12 FLASH_SECBB1R2_SEC12_Msk /*!< Page 44 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC13_Pos (13UL) -#define FLASH_SECBB1R2_SEC13_Msk (0x1UL << FLASH_SECBB1R2_SEC13_Pos) /*!< 0x00002000 */ -#define FLASH_SECBB1R2_SEC13 FLASH_SECBB1R2_SEC13_Msk /*!< Page 45 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC14_Pos (14UL) -#define FLASH_SECBB1R2_SEC14_Msk (0x1UL << FLASH_SECBB1R2_SEC14_Pos) /*!< 0x00004000 */ -#define FLASH_SECBB1R2_SEC14 FLASH_SECBB1R2_SEC14_Msk /*!< Page 46 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC15_Pos (15UL) -#define FLASH_SECBB1R2_SEC15_Msk (0x1UL << FLASH_SECBB1R2_SEC15_Pos) /*!< 0x00008000 */ -#define FLASH_SECBB1R2_SEC15 FLASH_SECBB1R2_SEC15_Msk /*!< Page 47 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC16_Pos (16UL) -#define FLASH_SECBB1R2_SEC16_Msk (0x1UL << FLASH_SECBB1R2_SEC16_Pos) /*!< 0x00010000 */ -#define FLASH_SECBB1R2_SEC16 FLASH_SECBB1R2_SEC16_Msk /*!< Page 48 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC17_Pos (17UL) -#define FLASH_SECBB1R2_SEC17_Msk (0x1UL << FLASH_SECBB1R2_SEC17_Pos) /*!< 0x00020000 */ -#define FLASH_SECBB1R2_SEC17 FLASH_SECBB1R2_SEC17_Msk /*!< Page 49 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC18_Pos (18UL) -#define FLASH_SECBB1R2_SEC18_Msk (0x1UL << FLASH_SECBB1R2_SEC18_Pos) /*!< 0x00040000 */ -#define FLASH_SECBB1R2_SEC18 FLASH_SECBB1R2_SEC18_Msk /*!< Page 50 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC19_Pos (19UL) -#define FLASH_SECBB1R2_SEC19_Msk (0x1UL << FLASH_SECBB1R2_SEC19_Pos) /*!< 0x00080000 */ -#define FLASH_SECBB1R2_SEC19 FLASH_SECBB1R2_SEC19_Msk /*!< Page 51 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC20_Pos (20UL) -#define FLASH_SECBB1R2_SEC20_Msk (0x1UL << FLASH_SECBB1R2_SEC20_Pos) /*!< 0x00100000 */ -#define FLASH_SECBB1R2_SEC20 FLASH_SECBB1R2_SEC20_Msk /*!< Page 52 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC21_Pos (21UL) -#define FLASH_SECBB1R2_SEC21_Msk (0x1UL << FLASH_SECBB1R2_SEC21_Pos) /*!< 0x00200000 */ -#define FLASH_SECBB1R2_SEC21 FLASH_SECBB1R2_SEC21_Msk /*!< Page 53 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC22_Pos (22UL) -#define FLASH_SECBB1R2_SEC22_Msk (0x1UL << FLASH_SECBB1R2_SEC22_Pos) /*!< 0x00400000 */ -#define FLASH_SECBB1R2_SEC22 FLASH_SECBB1R2_SEC22_Msk /*!< Page 54 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC23_Pos (23UL) -#define FLASH_SECBB1R2_SEC23_Msk (0x1UL << FLASH_SECBB1R2_SEC23_Pos) /*!< 0x00800000 */ -#define FLASH_SECBB1R2_SEC23 FLASH_SECBB1R2_SEC23_Msk /*!< Page 55 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC24_Pos (24UL) -#define FLASH_SECBB1R2_SEC24_Msk (0x1UL << FLASH_SECBB1R2_SEC24_Pos) /*!< 0x01000000 */ -#define FLASH_SECBB1R2_SEC24 FLASH_SECBB1R2_SEC24_Msk /*!< Page 56 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC25_Pos (25UL) -#define FLASH_SECBB1R2_SEC25_Msk (0x1UL << FLASH_SECBB1R2_SEC25_Pos) /*!< 0x02000000 */ -#define FLASH_SECBB1R2_SEC25 FLASH_SECBB1R2_SEC25_Msk /*!< Page 57 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC26_Pos (26UL) -#define FLASH_SECBB1R2_SEC26_Msk (0x1UL << FLASH_SECBB1R2_SEC26_Pos) /*!< 0x04000000 */ -#define FLASH_SECBB1R2_SEC26 FLASH_SECBB1R2_SEC26_Msk /*!< Page 58 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC27_Pos (27UL) -#define FLASH_SECBB1R2_SEC27_Msk (0x1UL << FLASH_SECBB1R2_SEC27_Pos) /*!< 0x08000000 */ -#define FLASH_SECBB1R2_SEC27 FLASH_SECBB1R2_SEC27_Msk /*!< Page 59 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC28_Pos (28UL) -#define FLASH_SECBB1R2_SEC28_Msk (0x1UL << FLASH_SECBB1R2_SEC28_Pos) /*!< 0x10000000 */ -#define FLASH_SECBB1R2_SEC28 FLASH_SECBB1R2_SEC28_Msk /*!< Page 60 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC29_Pos (29UL) -#define FLASH_SECBB1R2_SEC29_Msk (0x1UL << FLASH_SECBB1R2_SEC29_Pos) /*!< 0x20000000 */ -#define FLASH_SECBB1R2_SEC29 FLASH_SECBB1R2_SEC29_Msk /*!< Page 61 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC30_Pos (30UL) -#define FLASH_SECBB1R2_SEC30_Msk (0x1UL << FLASH_SECBB1R2_SEC30_Pos) /*!< 0x40000000 */ -#define FLASH_SECBB1R2_SEC30 FLASH_SECBB1R2_SEC30_Msk /*!< Page 62 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC31_Pos (31UL) -#define FLASH_SECBB1R2_SEC31_Msk (0x1UL << FLASH_SECBB1R2_SEC31_Pos) /*!< 0x80000000 */ -#define FLASH_SECBB1R2_SEC31 FLASH_SECBB1R2_SEC31_Msk /*!< Page 63 in bank 1 block-based secure */ - -/******************* Bit definition for FLASH_SECBB1R3 register ******************/ -#define FLASH_SECBB1R3_SEC0_Pos (0UL) -#define FLASH_SECBB1R3_SEC0_Msk (0x1UL << FLASH_SECBB1R3_SEC0_Pos) /*!< 0x00000001 */ -#define FLASH_SECBB1R3_SEC0 FLASH_SECBB1R3_SEC0_Msk /*!< Page 64 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC1_Pos (1UL) -#define FLASH_SECBB1R3_SEC1_Msk (0x1UL << FLASH_SECBB1R3_SEC1_Pos) /*!< 0x00000002 */ -#define FLASH_SECBB1R3_SEC1 FLASH_SECBB1R3_SEC1_Msk /*!< Page 65 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC2_Pos (2UL) -#define FLASH_SECBB1R3_SEC2_Msk (0x1UL << FLASH_SECBB1R3_SEC2_Pos) /*!< 0x00000004 */ -#define FLASH_SECBB1R3_SEC2 FLASH_SECBB1R3_SEC2_Msk /*!< Page 66 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC3_Pos (3UL) -#define FLASH_SECBB1R3_SEC3_Msk (0x1UL << FLASH_SECBB1R3_SEC3_Pos) /*!< 0x00000008 */ -#define FLASH_SECBB1R3_SEC3 FLASH_SECBB1R3_SEC3_Msk /*!< Page 67 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC4_Pos (4UL) -#define FLASH_SECBB1R3_SEC4_Msk (0x1UL << FLASH_SECBB1R3_SEC4_Pos) /*!< 0x00000010 */ -#define FLASH_SECBB1R3_SEC4 FLASH_SECBB1R3_SEC4_Msk /*!< Page 68 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC5_Pos (5UL) -#define FLASH_SECBB1R3_SEC5_Msk (0x1UL << FLASH_SECBB1R3_SEC5_Pos) /*!< 0x00000020 */ -#define FLASH_SECBB1R3_SEC5 FLASH_SECBB1R3_SEC5_Msk /*!< Page 69 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC6_Pos (6UL) -#define FLASH_SECBB1R3_SEC6_Msk (0x1UL << FLASH_SECBB1R3_SEC6_Pos) /*!< 0x00000040 */ -#define FLASH_SECBB1R3_SEC6 FLASH_SECBB1R3_SEC6_Msk /*!< Page 70 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC7_Pos (7UL) -#define FLASH_SECBB1R3_SEC7_Msk (0x1UL << FLASH_SECBB1R3_SEC7_Pos) /*!< 0x00000080 */ -#define FLASH_SECBB1R3_SEC7 FLASH_SECBB1R3_SEC7_Msk /*!< Page 71 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC8_Pos (8UL) -#define FLASH_SECBB1R3_SEC8_Msk (0x1UL << FLASH_SECBB1R3_SEC8_Pos) /*!< 0x00000100 */ -#define FLASH_SECBB1R3_SEC8 FLASH_SECBB1R3_SEC8_Msk /*!< Page 72 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC9_Pos (9UL) -#define FLASH_SECBB1R3_SEC9_Msk (0x1UL << FLASH_SECBB1R3_SEC9_Pos) /*!< 0x00000200 */ -#define FLASH_SECBB1R3_SEC9 FLASH_SECBB1R3_SEC9_Msk /*!< Page 73 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC10_Pos (10UL) -#define FLASH_SECBB1R3_SEC10_Msk (0x1UL << FLASH_SECBB1R3_SEC10_Pos) /*!< 0x00000400 */ -#define FLASH_SECBB1R3_SEC10 FLASH_SECBB1R3_SEC10_Msk /*!< Page 74 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC11_Pos (11UL) -#define FLASH_SECBB1R3_SEC11_Msk (0x1UL << FLASH_SECBB1R3_SEC11_Pos) /*!< 0x00000800 */ -#define FLASH_SECBB1R3_SEC11 FLASH_SECBB1R3_SEC11_Msk /*!< Page 75 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC12_Pos (12UL) -#define FLASH_SECBB1R3_SEC12_Msk (0x1UL << FLASH_SECBB1R3_SEC12_Pos) /*!< 0x00001000 */ -#define FLASH_SECBB1R3_SEC12 FLASH_SECBB1R3_SEC12_Msk /*!< Page 76 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC13_Pos (13UL) -#define FLASH_SECBB1R3_SEC13_Msk (0x1UL << FLASH_SECBB1R3_SEC13_Pos) /*!< 0x00002000 */ -#define FLASH_SECBB1R3_SEC13 FLASH_SECBB1R3_SEC13_Msk /*!< Page 77 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC14_Pos (14UL) -#define FLASH_SECBB1R3_SEC14_Msk (0x1UL << FLASH_SECBB1R3_SEC14_Pos) /*!< 0x00004000 */ -#define FLASH_SECBB1R3_SEC14 FLASH_SECBB1R3_SEC14_Msk /*!< Page 78 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC15_Pos (15UL) -#define FLASH_SECBB1R3_SEC15_Msk (0x1UL << FLASH_SECBB1R3_SEC15_Pos) /*!< 0x00008000 */ -#define FLASH_SECBB1R3_SEC15 FLASH_SECBB1R3_SEC15_Msk /*!< Page 79 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC16_Pos (16UL) -#define FLASH_SECBB1R3_SEC16_Msk (0x1UL << FLASH_SECBB1R3_SEC16_Pos) /*!< 0x00010000 */ -#define FLASH_SECBB1R3_SEC16 FLASH_SECBB1R3_SEC16_Msk /*!< Page 80 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC17_Pos (17UL) -#define FLASH_SECBB1R3_SEC17_Msk (0x1UL << FLASH_SECBB1R3_SEC17_Pos) /*!< 0x00020000 */ -#define FLASH_SECBB1R3_SEC17 FLASH_SECBB1R3_SEC17_Msk /*!< Page 81 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC18_Pos (18UL) -#define FLASH_SECBB1R3_SEC18_Msk (0x1UL << FLASH_SECBB1R3_SEC18_Pos) /*!< 0x00040000 */ -#define FLASH_SECBB1R3_SEC18 FLASH_SECBB1R3_SEC18_Msk /*!< Page 82 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC19_Pos (19UL) -#define FLASH_SECBB1R3_SEC19_Msk (0x1UL << FLASH_SECBB1R3_SEC19_Pos) /*!< 0x00080000 */ -#define FLASH_SECBB1R3_SEC19 FLASH_SECBB1R3_SEC19_Msk /*!< Page 83 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC20_Pos (20UL) -#define FLASH_SECBB1R3_SEC20_Msk (0x1UL << FLASH_SECBB1R3_SEC20_Pos) /*!< 0x00100000 */ -#define FLASH_SECBB1R3_SEC20 FLASH_SECBB1R3_SEC20_Msk /*!< Page 84 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC21_Pos (21UL) -#define FLASH_SECBB1R3_SEC21_Msk (0x1UL << FLASH_SECBB1R3_SEC21_Pos) /*!< 0x00200000 */ -#define FLASH_SECBB1R3_SEC21 FLASH_SECBB1R3_SEC21_Msk /*!< Page 85 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC22_Pos (22UL) -#define FLASH_SECBB1R3_SEC22_Msk (0x1UL << FLASH_SECBB1R3_SEC22_Pos) /*!< 0x00400000 */ -#define FLASH_SECBB1R3_SEC22 FLASH_SECBB1R3_SEC22_Msk /*!< Page 86 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC23_Pos (23UL) -#define FLASH_SECBB1R3_SEC23_Msk (0x1UL << FLASH_SECBB1R3_SEC23_Pos) /*!< 0x00800000 */ -#define FLASH_SECBB1R3_SEC23 FLASH_SECBB1R3_SEC23_Msk /*!< Page 87 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC24_Pos (24UL) -#define FLASH_SECBB1R3_SEC24_Msk (0x1UL << FLASH_SECBB1R3_SEC24_Pos) /*!< 0x01000000 */ -#define FLASH_SECBB1R3_SEC24 FLASH_SECBB1R3_SEC24_Msk /*!< Page 88 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC25_Pos (25UL) -#define FLASH_SECBB1R3_SEC25_Msk (0x1UL << FLASH_SECBB1R3_SEC25_Pos) /*!< 0x02000000 */ -#define FLASH_SECBB1R3_SEC25 FLASH_SECBB1R3_SEC25_Msk /*!< Page 89 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC26_Pos (26UL) -#define FLASH_SECBB1R3_SEC26_Msk (0x1UL << FLASH_SECBB1R3_SEC26_Pos) /*!< 0x04000000 */ -#define FLASH_SECBB1R3_SEC26 FLASH_SECBB1R3_SEC26_Msk /*!< Page 90 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC27_Pos (27UL) -#define FLASH_SECBB1R3_SEC27_Msk (0x1UL << FLASH_SECBB1R3_SEC27_Pos) /*!< 0x08000000 */ -#define FLASH_SECBB1R3_SEC27 FLASH_SECBB1R3_SEC27_Msk /*!< Page 91 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC28_Pos (28UL) -#define FLASH_SECBB1R3_SEC28_Msk (0x1UL << FLASH_SECBB1R3_SEC28_Pos) /*!< 0x10000000 */ -#define FLASH_SECBB1R3_SEC28 FLASH_SECBB1R3_SEC28_Msk /*!< Page 92 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC29_Pos (29UL) -#define FLASH_SECBB1R3_SEC29_Msk (0x1UL << FLASH_SECBB1R3_SEC29_Pos) /*!< 0x20000000 */ -#define FLASH_SECBB1R3_SEC29 FLASH_SECBB1R3_SEC29_Msk /*!< Page 93 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC30_Pos (30UL) -#define FLASH_SECBB1R3_SEC30_Msk (0x1UL << FLASH_SECBB1R3_SEC30_Pos) /*!< 0x40000000 */ -#define FLASH_SECBB1R3_SEC30 FLASH_SECBB1R3_SEC30_Msk /*!< Page 94 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC31_Pos (31UL) -#define FLASH_SECBB1R3_SEC31_Msk (0x1UL << FLASH_SECBB1R3_SEC31_Pos) /*!< 0x80000000 */ -#define FLASH_SECBB1R3_SEC31 FLASH_SECBB1R3_SEC31_Msk /*!< Page 95 in bank 1 block-based secure */ - -/******************* Bit definition for FLASH_SECBB1R4 register ******************/ -#define FLASH_SECBB1R4_SEC0_Pos (0UL) -#define FLASH_SECBB1R4_SEC0_Msk (0x1UL << FLASH_SECBB1R4_SEC0_Pos) /*!< 0x00000001 */ -#define FLASH_SECBB1R4_SEC0 FLASH_SECBB1R4_SEC0_Msk /*!< Page 96 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC1_Pos (1UL) -#define FLASH_SECBB1R4_SEC1_Msk (0x1UL << FLASH_SECBB1R4_SEC1_Pos) /*!< 0x00000002 */ -#define FLASH_SECBB1R4_SEC1 FLASH_SECBB1R4_SEC1_Msk /*!< Page 97 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC2_Pos (2UL) -#define FLASH_SECBB1R4_SEC2_Msk (0x1UL << FLASH_SECBB1R4_SEC2_Pos) /*!< 0x00000004 */ -#define FLASH_SECBB1R4_SEC2 FLASH_SECBB1R4_SEC2_Msk /*!< Page 98 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC3_Pos (3UL) -#define FLASH_SECBB1R4_SEC3_Msk (0x1UL << FLASH_SECBB1R4_SEC3_Pos) /*!< 0x00000008 */ -#define FLASH_SECBB1R4_SEC3 FLASH_SECBB1R4_SEC3_Msk /*!< Page 99 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC4_Pos (4UL) -#define FLASH_SECBB1R4_SEC4_Msk (0x1UL << FLASH_SECBB1R4_SEC4_Pos) /*!< 0x00000010 */ -#define FLASH_SECBB1R4_SEC4 FLASH_SECBB1R4_SEC4_Msk /*!< Page 100 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC5_Pos (5UL) -#define FLASH_SECBB1R4_SEC5_Msk (0x1UL << FLASH_SECBB1R4_SEC5_Pos) /*!< 0x00000020 */ -#define FLASH_SECBB1R4_SEC5 FLASH_SECBB1R4_SEC5_Msk /*!< Page 101 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC6_Pos (6UL) -#define FLASH_SECBB1R4_SEC6_Msk (0x1UL << FLASH_SECBB1R4_SEC6_Pos) /*!< 0x00000040 */ -#define FLASH_SECBB1R4_SEC6 FLASH_SECBB1R4_SEC6_Msk /*!< Page 102 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC7_Pos (7UL) -#define FLASH_SECBB1R4_SEC7_Msk (0x1UL << FLASH_SECBB1R4_SEC7_Pos) /*!< 0x00000080 */ -#define FLASH_SECBB1R4_SEC7 FLASH_SECBB1R4_SEC7_Msk /*!< Page 103 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC8_Pos (8UL) -#define FLASH_SECBB1R4_SEC8_Msk (0x1UL << FLASH_SECBB1R4_SEC8_Pos) /*!< 0x00000100 */ -#define FLASH_SECBB1R4_SEC8 FLASH_SECBB1R4_SEC8_Msk /*!< Page 104 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC9_Pos (9UL) -#define FLASH_SECBB1R4_SEC9_Msk (0x1UL << FLASH_SECBB1R4_SEC9_Pos) /*!< 0x00000200 */ -#define FLASH_SECBB1R4_SEC9 FLASH_SECBB1R4_SEC9_Msk /*!< Page 105 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC10_Pos (10UL) -#define FLASH_SECBB1R4_SEC10_Msk (0x1UL << FLASH_SECBB1R4_SEC10_Pos) /*!< 0x00000400 */ -#define FLASH_SECBB1R4_SEC10 FLASH_SECBB1R4_SEC10_Msk /*!< Page 106 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC11_Pos (11UL) -#define FLASH_SECBB1R4_SEC11_Msk (0x1UL << FLASH_SECBB1R4_SEC11_Pos) /*!< 0x00000800 */ -#define FLASH_SECBB1R4_SEC11 FLASH_SECBB1R4_SEC11_Msk /*!< Page 107 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC12_Pos (12UL) -#define FLASH_SECBB1R4_SEC12_Msk (0x1UL << FLASH_SECBB1R4_SEC12_Pos) /*!< 0x00001000 */ -#define FLASH_SECBB1R4_SEC12 FLASH_SECBB1R4_SEC12_Msk /*!< Page 108 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC13_Pos (13UL) -#define FLASH_SECBB1R4_SEC13_Msk (0x1UL << FLASH_SECBB1R4_SEC13_Pos) /*!< 0x00002000 */ -#define FLASH_SECBB1R4_SEC13 FLASH_SECBB1R4_SEC13_Msk /*!< Page 109 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC14_Pos (14UL) -#define FLASH_SECBB1R4_SEC14_Msk (0x1UL << FLASH_SECBB1R4_SEC14_Pos) /*!< 0x00004000 */ -#define FLASH_SECBB1R4_SEC14 FLASH_SECBB1R4_SEC14_Msk /*!< Page 110 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC15_Pos (15UL) -#define FLASH_SECBB1R4_SEC15_Msk (0x1UL << FLASH_SECBB1R4_SEC15_Pos) /*!< 0x00008000 */ -#define FLASH_SECBB1R4_SEC15 FLASH_SECBB1R4_SEC15_Msk /*!< Page 111 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC16_Pos (16UL) -#define FLASH_SECBB1R4_SEC16_Msk (0x1UL << FLASH_SECBB1R4_SEC16_Pos) /*!< 0x00010000 */ -#define FLASH_SECBB1R4_SEC16 FLASH_SECBB1R4_SEC16_Msk /*!< Page 112 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC17_Pos (17UL) -#define FLASH_SECBB1R4_SEC17_Msk (0x1UL << FLASH_SECBB1R4_SEC17_Pos) /*!< 0x00020000 */ -#define FLASH_SECBB1R4_SEC17 FLASH_SECBB1R4_SEC17_Msk /*!< Page 113 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC18_Pos (18UL) -#define FLASH_SECBB1R4_SEC18_Msk (0x1UL << FLASH_SECBB1R4_SEC18_Pos) /*!< 0x00040000 */ -#define FLASH_SECBB1R4_SEC18 FLASH_SECBB1R4_SEC18_Msk /*!< Page 114 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC19_Pos (19UL) -#define FLASH_SECBB1R4_SEC19_Msk (0x1UL << FLASH_SECBB1R4_SEC19_Pos) /*!< 0x00080000 */ -#define FLASH_SECBB1R4_SEC19 FLASH_SECBB1R4_SEC19_Msk /*!< Page 115 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC20_Pos (20UL) -#define FLASH_SECBB1R4_SEC20_Msk (0x1UL << FLASH_SECBB1R4_SEC20_Pos) /*!< 0x00100000 */ -#define FLASH_SECBB1R4_SEC20 FLASH_SECBB1R4_SEC20_Msk /*!< Page 116 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC21_Pos (21UL) -#define FLASH_SECBB1R4_SEC21_Msk (0x1UL << FLASH_SECBB1R4_SEC21_Pos) /*!< 0x00200000 */ -#define FLASH_SECBB1R4_SEC21 FLASH_SECBB1R4_SEC21_Msk /*!< Page 117 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC22_Pos (22UL) -#define FLASH_SECBB1R4_SEC22_Msk (0x1UL << FLASH_SECBB1R4_SEC22_Pos) /*!< 0x00400000 */ -#define FLASH_SECBB1R4_SEC22 FLASH_SECBB1R4_SEC22_Msk /*!< Page 118 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC23_Pos (23UL) -#define FLASH_SECBB1R4_SEC23_Msk (0x1UL << FLASH_SECBB1R4_SEC23_Pos) /*!< 0x00800000 */ -#define FLASH_SECBB1R4_SEC23 FLASH_SECBB1R4_SEC23_Msk /*!< Page 119 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC24_Pos (24UL) -#define FLASH_SECBB1R4_SEC24_Msk (0x1UL << FLASH_SECBB1R4_SEC24_Pos) /*!< 0x01000000 */ -#define FLASH_SECBB1R4_SEC24 FLASH_SECBB1R4_SEC24_Msk /*!< Page 120 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC25_Pos (25UL) -#define FLASH_SECBB1R4_SEC25_Msk (0x1UL << FLASH_SECBB1R4_SEC25_Pos) /*!< 0x02000000 */ -#define FLASH_SECBB1R4_SEC25 FLASH_SECBB1R4_SEC25_Msk /*!< Page 121 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC26_Pos (26UL) -#define FLASH_SECBB1R4_SEC26_Msk (0x1UL << FLASH_SECBB1R4_SEC26_Pos) /*!< 0x04000000 */ -#define FLASH_SECBB1R4_SEC26 FLASH_SECBB1R4_SEC26_Msk /*!< Page 122 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC27_Pos (27UL) -#define FLASH_SECBB1R4_SEC27_Msk (0x1UL << FLASH_SECBB1R4_SEC27_Pos) /*!< 0x08000000 */ -#define FLASH_SECBB1R4_SEC27 FLASH_SECBB1R4_SEC27_Msk /*!< Page 123 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC28_Pos (28UL) -#define FLASH_SECBB1R4_SEC28_Msk (0x1UL << FLASH_SECBB1R4_SEC28_Pos) /*!< 0x10000000 */ -#define FLASH_SECBB1R4_SEC28 FLASH_SECBB1R4_SEC28_Msk /*!< Page 124 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC29_Pos (29UL) -#define FLASH_SECBB1R4_SEC29_Msk (0x1UL << FLASH_SECBB1R4_SEC29_Pos) /*!< 0x20000000 */ -#define FLASH_SECBB1R4_SEC29 FLASH_SECBB1R4_SEC29_Msk /*!< Page 125 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC30_Pos (30UL) -#define FLASH_SECBB1R4_SEC30_Msk (0x1UL << FLASH_SECBB1R4_SEC30_Pos) /*!< 0x40000000 */ -#define FLASH_SECBB1R4_SEC30 FLASH_SECBB1R4_SEC30_Msk /*!< Page 126 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC31_Pos (31UL) -#define FLASH_SECBB1R4_SEC31_Msk (0x1UL << FLASH_SECBB1R4_SEC31_Pos) /*!< 0x80000000 */ -#define FLASH_SECBB1R4_SEC31 FLASH_SECBB1R4_SEC31_Msk /*!< Page 127 in bank 1 block-based secure */ /******************* Bit definition for FLASH_SECBB2R1 register ******************/ #define FLASH_SECBB2R1_SEC0_Pos (0UL) @@ -7029,299 +6747,6 @@ typedef struct #define FLASH_SECBB2R1_SEC31_Msk (0x1UL << FLASH_SECBB2R1_SEC31_Pos) /*!< 0x80000000 */ #define FLASH_SECBB2R1_SEC31 FLASH_SECBB2R1_SEC31_Msk /*!< Page 31 in bank 2 block-based secure */ -/******************* Bit definition for FLASH_SECBB2R2 register ******************/ -#define FLASH_SECBB2R2_SEC0_Pos (0UL) -#define FLASH_SECBB2R2_SEC0_Msk (0x1UL << FLASH_SECBB2R2_SEC0_Pos) /*!< 0x00000001 */ -#define FLASH_SECBB2R2_SEC0 FLASH_SECBB2R2_SEC0_Msk /*!< Page 32 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC1_Pos (1UL) -#define FLASH_SECBB2R2_SEC1_Msk (0x1UL << FLASH_SECBB2R2_SEC1_Pos) /*!< 0x00000002 */ -#define FLASH_SECBB2R2_SEC1 FLASH_SECBB2R2_SEC1_Msk /*!< Page 33 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC2_Pos (2UL) -#define FLASH_SECBB2R2_SEC2_Msk (0x1UL << FLASH_SECBB2R2_SEC2_Pos) /*!< 0x00000004 */ -#define FLASH_SECBB2R2_SEC2 FLASH_SECBB2R2_SEC2_Msk /*!< Page 34 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC3_Pos (3UL) -#define FLASH_SECBB2R2_SEC3_Msk (0x1UL << FLASH_SECBB2R2_SEC3_Pos) /*!< 0x00000008 */ -#define FLASH_SECBB2R2_SEC3 FLASH_SECBB2R2_SEC3_Msk /*!< Page 35 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC4_Pos (4UL) -#define FLASH_SECBB2R2_SEC4_Msk (0x1UL << FLASH_SECBB2R2_SEC4_Pos) /*!< 0x00000010 */ -#define FLASH_SECBB2R2_SEC4 FLASH_SECBB2R2_SEC4_Msk /*!< Page 36 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC5_Pos (5UL) -#define FLASH_SECBB2R2_SEC5_Msk (0x1UL << FLASH_SECBB2R2_SEC5_Pos) /*!< 0x00000020 */ -#define FLASH_SECBB2R2_SEC5 FLASH_SECBB2R2_SEC5_Msk /*!< Page 37 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC6_Pos (6UL) -#define FLASH_SECBB2R2_SEC6_Msk (0x1UL << FLASH_SECBB2R2_SEC6_Pos) /*!< 0x00000040 */ -#define FLASH_SECBB2R2_SEC6 FLASH_SECBB2R2_SEC6_Msk /*!< Page 38 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC7_Pos (7UL) -#define FLASH_SECBB2R2_SEC7_Msk (0x1UL << FLASH_SECBB2R2_SEC7_Pos) /*!< 0x00000080 */ -#define FLASH_SECBB2R2_SEC7 FLASH_SECBB2R2_SEC7_Msk /*!< Page 39 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC8_Pos (8UL) -#define FLASH_SECBB2R2_SEC8_Msk (0x1UL << FLASH_SECBB2R2_SEC8_Pos) /*!< 0x00000100 */ -#define FLASH_SECBB2R2_SEC8 FLASH_SECBB2R2_SEC8_Msk /*!< Page 40 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC9_Pos (9UL) -#define FLASH_SECBB2R2_SEC9_Msk (0x1UL << FLASH_SECBB2R2_SEC9_Pos) /*!< 0x00000200 */ -#define FLASH_SECBB2R2_SEC9 FLASH_SECBB2R2_SEC9_Msk /*!< Page 41 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC10_Pos (10UL) -#define FLASH_SECBB2R2_SEC10_Msk (0x1UL << FLASH_SECBB2R2_SEC10_Pos) /*!< 0x00000400 */ -#define FLASH_SECBB2R2_SEC10 FLASH_SECBB2R2_SEC10_Msk /*!< Page 42 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC11_Pos (11UL) -#define FLASH_SECBB2R2_SEC11_Msk (0x1UL << FLASH_SECBB2R2_SEC11_Pos) /*!< 0x00000800 */ -#define FLASH_SECBB2R2_SEC11 FLASH_SECBB2R2_SEC11_Msk /*!< Page 43 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC12_Pos (12UL) -#define FLASH_SECBB2R2_SEC12_Msk (0x1UL << FLASH_SECBB2R2_SEC12_Pos) /*!< 0x00001000 */ -#define FLASH_SECBB2R2_SEC12 FLASH_SECBB2R2_SEC12_Msk /*!< Page 44 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC13_Pos (13UL) -#define FLASH_SECBB2R2_SEC13_Msk (0x1UL << FLASH_SECBB2R2_SEC13_Pos) /*!< 0x00002000 */ -#define FLASH_SECBB2R2_SEC13 FLASH_SECBB2R2_SEC13_Msk /*!< Page 45 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC14_Pos (14UL) -#define FLASH_SECBB2R2_SEC14_Msk (0x1UL << FLASH_SECBB2R2_SEC14_Pos) /*!< 0x00004000 */ -#define FLASH_SECBB2R2_SEC14 FLASH_SECBB2R2_SEC14_Msk /*!< Page 46 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC15_Pos (15UL) -#define FLASH_SECBB2R2_SEC15_Msk (0x1UL << FLASH_SECBB2R2_SEC15_Pos) /*!< 0x00008000 */ -#define FLASH_SECBB2R2_SEC15 FLASH_SECBB2R2_SEC15_Msk /*!< Page 47 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC16_Pos (16UL) -#define FLASH_SECBB2R2_SEC16_Msk (0x1UL << FLASH_SECBB2R2_SEC16_Pos) /*!< 0x00010000 */ -#define FLASH_SECBB2R2_SEC16 FLASH_SECBB2R2_SEC16_Msk /*!< Page 48 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC17_Pos (17UL) -#define FLASH_SECBB2R2_SEC17_Msk (0x1UL << FLASH_SECBB2R2_SEC17_Pos) /*!< 0x00020000 */ -#define FLASH_SECBB2R2_SEC17 FLASH_SECBB2R2_SEC17_Msk /*!< Page 49 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC18_Pos (18UL) -#define FLASH_SECBB2R2_SEC18_Msk (0x1UL << FLASH_SECBB2R2_SEC18_Pos) /*!< 0x00040000 */ -#define FLASH_SECBB2R2_SEC18 FLASH_SECBB2R2_SEC18_Msk /*!< Page 50 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC19_Pos (19UL) -#define FLASH_SECBB2R2_SEC19_Msk (0x1UL << FLASH_SECBB2R2_SEC19_Pos) /*!< 0x00080000 */ -#define FLASH_SECBB2R2_SEC19 FLASH_SECBB2R2_SEC19_Msk /*!< Page 51 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC20_Pos (20UL) -#define FLASH_SECBB2R2_SEC20_Msk (0x1UL << FLASH_SECBB2R2_SEC20_Pos) /*!< 0x00100000 */ -#define FLASH_SECBB2R2_SEC20 FLASH_SECBB2R2_SEC20_Msk /*!< Page 52 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC21_Pos (21UL) -#define FLASH_SECBB2R2_SEC21_Msk (0x1UL << FLASH_SECBB2R2_SEC21_Pos) /*!< 0x00200000 */ -#define FLASH_SECBB2R2_SEC21 FLASH_SECBB2R2_SEC21_Msk /*!< Page 53 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC22_Pos (22UL) -#define FLASH_SECBB2R2_SEC22_Msk (0x1UL << FLASH_SECBB2R2_SEC22_Pos) /*!< 0x00400000 */ -#define FLASH_SECBB2R2_SEC22 FLASH_SECBB2R2_SEC22_Msk /*!< Page 54 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC23_Pos (23UL) -#define FLASH_SECBB2R2_SEC23_Msk (0x1UL << FLASH_SECBB2R2_SEC23_Pos) /*!< 0x00800000 */ -#define FLASH_SECBB2R2_SEC23 FLASH_SECBB2R2_SEC23_Msk /*!< Page 55 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC24_Pos (24UL) -#define FLASH_SECBB2R2_SEC24_Msk (0x1UL << FLASH_SECBB2R2_SEC24_Pos) /*!< 0x01000000 */ -#define FLASH_SECBB2R2_SEC24 FLASH_SECBB2R2_SEC24_Msk /*!< Page 56 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC25_Pos (25UL) -#define FLASH_SECBB2R2_SEC25_Msk (0x1UL << FLASH_SECBB2R2_SEC25_Pos) /*!< 0x02000000 */ -#define FLASH_SECBB2R2_SEC25 FLASH_SECBB2R2_SEC25_Msk /*!< Page 57 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC26_Pos (26UL) -#define FLASH_SECBB2R2_SEC26_Msk (0x1UL << FLASH_SECBB2R2_SEC26_Pos) /*!< 0x04000000 */ -#define FLASH_SECBB2R2_SEC26 FLASH_SECBB2R2_SEC26_Msk /*!< Page 58 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC27_Pos (27UL) -#define FLASH_SECBB2R2_SEC27_Msk (0x1UL << FLASH_SECBB2R2_SEC27_Pos) /*!< 0x08000000 */ -#define FLASH_SECBB2R2_SEC27 FLASH_SECBB2R2_SEC27_Msk /*!< Page 59 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC28_Pos (28UL) -#define FLASH_SECBB2R2_SEC28_Msk (0x1UL << FLASH_SECBB2R2_SEC28_Pos) /*!< 0x10000000 */ -#define FLASH_SECBB2R2_SEC28 FLASH_SECBB2R2_SEC28_Msk /*!< Page 60 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC29_Pos (29UL) -#define FLASH_SECBB2R2_SEC29_Msk (0x1UL << FLASH_SECBB2R2_SEC29_Pos) /*!< 0x20000000 */ -#define FLASH_SECBB2R2_SEC29 FLASH_SECBB2R2_SEC29_Msk /*!< Page 61 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC30_Pos (30UL) -#define FLASH_SECBB2R2_SEC30_Msk (0x1UL << FLASH_SECBB2R2_SEC30_Pos) /*!< 0x40000000 */ -#define FLASH_SECBB2R2_SEC30 FLASH_SECBB2R2_SEC30_Msk /*!< Page 62 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC31_Pos (31UL) -#define FLASH_SECBB2R2_SEC31_Msk (0x1UL << FLASH_SECBB2R2_SEC31_Pos) /*!< 0x80000000 */ -#define FLASH_SECBB2R2_SEC31 FLASH_SECBB2R2_SEC31_Msk /*!< Page 63 in bank 2 block-based secure */ - -/******************* Bit definition for FLASH_SECBB2R3 register ******************/ -#define FLASH_SECBB2R3_SEC0_Pos (0UL) -#define FLASH_SECBB2R3_SEC0_Msk (0x1UL << FLASH_SECBB2R3_SEC0_Pos) /*!< 0x00000001 */ -#define FLASH_SECBB2R3_SEC0 FLASH_SECBB2R3_SEC0_Msk /*!< Page 64 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC1_Pos (1UL) -#define FLASH_SECBB2R3_SEC1_Msk (0x1UL << FLASH_SECBB2R3_SEC1_Pos) /*!< 0x00000002 */ -#define FLASH_SECBB2R3_SEC1 FLASH_SECBB2R3_SEC1_Msk /*!< Page 65 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC2_Pos (2UL) -#define FLASH_SECBB2R3_SEC2_Msk (0x1UL << FLASH_SECBB2R3_SEC2_Pos) /*!< 0x00000004 */ -#define FLASH_SECBB2R3_SEC2 FLASH_SECBB2R3_SEC2_Msk /*!< Page 66 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC3_Pos (3UL) -#define FLASH_SECBB2R3_SEC3_Msk (0x1UL << FLASH_SECBB2R3_SEC3_Pos) /*!< 0x00000008 */ -#define FLASH_SECBB2R3_SEC3 FLASH_SECBB2R3_SEC3_Msk /*!< Page 67 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC4_Pos (4UL) -#define FLASH_SECBB2R3_SEC4_Msk (0x1UL << FLASH_SECBB2R3_SEC4_Pos) /*!< 0x00000010 */ -#define FLASH_SECBB2R3_SEC4 FLASH_SECBB2R3_SEC4_Msk /*!< Page 68 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC5_Pos (5UL) -#define FLASH_SECBB2R3_SEC5_Msk (0x1UL << FLASH_SECBB2R3_SEC5_Pos) /*!< 0x00000020 */ -#define FLASH_SECBB2R3_SEC5 FLASH_SECBB2R3_SEC5_Msk /*!< Page 69 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC6_Pos (6UL) -#define FLASH_SECBB2R3_SEC6_Msk (0x1UL << FLASH_SECBB2R3_SEC6_Pos) /*!< 0x00000040 */ -#define FLASH_SECBB2R3_SEC6 FLASH_SECBB2R3_SEC6_Msk /*!< Page 70 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC7_Pos (7UL) -#define FLASH_SECBB2R3_SEC7_Msk (0x1UL << FLASH_SECBB2R3_SEC7_Pos) /*!< 0x00000080 */ -#define FLASH_SECBB2R3_SEC7 FLASH_SECBB2R3_SEC7_Msk /*!< Page 71 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC8_Pos (8UL) -#define FLASH_SECBB2R3_SEC8_Msk (0x1UL << FLASH_SECBB2R3_SEC8_Pos) /*!< 0x00000100 */ -#define FLASH_SECBB2R3_SEC8 FLASH_SECBB2R3_SEC8_Msk /*!< Page 72 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC9_Pos (9UL) -#define FLASH_SECBB2R3_SEC9_Msk (0x1UL << FLASH_SECBB2R3_SEC9_Pos) /*!< 0x00000200 */ -#define FLASH_SECBB2R3_SEC9 FLASH_SECBB2R3_SEC9_Msk /*!< Page 73 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC10_Pos (10UL) -#define FLASH_SECBB2R3_SEC10_Msk (0x1UL << FLASH_SECBB2R3_SEC10_Pos) /*!< 0x00000400 */ -#define FLASH_SECBB2R3_SEC10 FLASH_SECBB2R3_SEC10_Msk /*!< Page 74 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC11_Pos (11UL) -#define FLASH_SECBB2R3_SEC11_Msk (0x1UL << FLASH_SECBB2R3_SEC11_Pos) /*!< 0x00000800 */ -#define FLASH_SECBB2R3_SEC11 FLASH_SECBB2R3_SEC11_Msk /*!< Page 75 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC12_Pos (12UL) -#define FLASH_SECBB2R3_SEC12_Msk (0x1UL << FLASH_SECBB2R3_SEC12_Pos) /*!< 0x00001000 */ -#define FLASH_SECBB2R3_SEC12 FLASH_SECBB2R3_SEC12_Msk /*!< Page 76 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC13_Pos (13UL) -#define FLASH_SECBB2R3_SEC13_Msk (0x1UL << FLASH_SECBB2R3_SEC13_Pos) /*!< 0x00002000 */ -#define FLASH_SECBB2R3_SEC13 FLASH_SECBB2R3_SEC13_Msk /*!< Page 77 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC14_Pos (14UL) -#define FLASH_SECBB2R3_SEC14_Msk (0x1UL << FLASH_SECBB2R3_SEC14_Pos) /*!< 0x00004000 */ -#define FLASH_SECBB2R3_SEC14 FLASH_SECBB2R3_SEC14_Msk /*!< Page 78 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC15_Pos (15UL) -#define FLASH_SECBB2R3_SEC15_Msk (0x1UL << FLASH_SECBB2R3_SEC15_Pos) /*!< 0x00008000 */ -#define FLASH_SECBB2R3_SEC15 FLASH_SECBB2R3_SEC15_Msk /*!< Page 79 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC16_Pos (16UL) -#define FLASH_SECBB2R3_SEC16_Msk (0x1UL << FLASH_SECBB2R3_SEC16_Pos) /*!< 0x00010000 */ -#define FLASH_SECBB2R3_SEC16 FLASH_SECBB2R3_SEC16_Msk /*!< Page 80 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC17_Pos (17UL) -#define FLASH_SECBB2R3_SEC17_Msk (0x1UL << FLASH_SECBB2R3_SEC17_Pos) /*!< 0x00020000 */ -#define FLASH_SECBB2R3_SEC17 FLASH_SECBB2R3_SEC17_Msk /*!< Page 81 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC18_Pos (18UL) -#define FLASH_SECBB2R3_SEC18_Msk (0x1UL << FLASH_SECBB2R3_SEC18_Pos) /*!< 0x00040000 */ -#define FLASH_SECBB2R3_SEC18 FLASH_SECBB2R3_SEC18_Msk /*!< Page 82 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC19_Pos (19UL) -#define FLASH_SECBB2R3_SEC19_Msk (0x1UL << FLASH_SECBB2R3_SEC19_Pos) /*!< 0x00080000 */ -#define FLASH_SECBB2R3_SEC19 FLASH_SECBB2R3_SEC19_Msk /*!< Page 83 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC20_Pos (20UL) -#define FLASH_SECBB2R3_SEC20_Msk (0x1UL << FLASH_SECBB2R3_SEC20_Pos) /*!< 0x00100000 */ -#define FLASH_SECBB2R3_SEC20 FLASH_SECBB2R3_SEC20_Msk /*!< Page 84 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC21_Pos (21UL) -#define FLASH_SECBB2R3_SEC21_Msk (0x1UL << FLASH_SECBB2R3_SEC21_Pos) /*!< 0x00200000 */ -#define FLASH_SECBB2R3_SEC21 FLASH_SECBB2R3_SEC21_Msk /*!< Page 85 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC22_Pos (22UL) -#define FLASH_SECBB2R3_SEC22_Msk (0x1UL << FLASH_SECBB2R3_SEC22_Pos) /*!< 0x00400000 */ -#define FLASH_SECBB2R3_SEC22 FLASH_SECBB2R3_SEC22_Msk /*!< Page 86 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC23_Pos (23UL) -#define FLASH_SECBB2R3_SEC23_Msk (0x1UL << FLASH_SECBB2R3_SEC23_Pos) /*!< 0x00800000 */ -#define FLASH_SECBB2R3_SEC23 FLASH_SECBB2R3_SEC23_Msk /*!< Page 87 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC24_Pos (24UL) -#define FLASH_SECBB2R3_SEC24_Msk (0x1UL << FLASH_SECBB2R3_SEC24_Pos) /*!< 0x01000000 */ -#define FLASH_SECBB2R3_SEC24 FLASH_SECBB2R3_SEC24_Msk /*!< Page 88 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC25_Pos (25UL) -#define FLASH_SECBB2R3_SEC25_Msk (0x1UL << FLASH_SECBB2R3_SEC25_Pos) /*!< 0x02000000 */ -#define FLASH_SECBB2R3_SEC25 FLASH_SECBB2R3_SEC25_Msk /*!< Page 89 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC26_Pos (26UL) -#define FLASH_SECBB2R3_SEC26_Msk (0x1UL << FLASH_SECBB2R3_SEC26_Pos) /*!< 0x04000000 */ -#define FLASH_SECBB2R3_SEC26 FLASH_SECBB2R3_SEC26_Msk /*!< Page 90 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC27_Pos (27UL) -#define FLASH_SECBB2R3_SEC27_Msk (0x1UL << FLASH_SECBB2R3_SEC27_Pos) /*!< 0x08000000 */ -#define FLASH_SECBB2R3_SEC27 FLASH_SECBB2R3_SEC27_Msk /*!< Page 91 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC28_Pos (28UL) -#define FLASH_SECBB2R3_SEC28_Msk (0x1UL << FLASH_SECBB2R3_SEC28_Pos) /*!< 0x10000000 */ -#define FLASH_SECBB2R3_SEC28 FLASH_SECBB2R3_SEC28_Msk /*!< Page 92 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC29_Pos (29UL) -#define FLASH_SECBB2R3_SEC29_Msk (0x1UL << FLASH_SECBB2R3_SEC29_Pos) /*!< 0x20000000 */ -#define FLASH_SECBB2R3_SEC29 FLASH_SECBB2R3_SEC29_Msk /*!< Page 93 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC30_Pos (30UL) -#define FLASH_SECBB2R3_SEC30_Msk (0x1UL << FLASH_SECBB2R3_SEC30_Pos) /*!< 0x40000000 */ -#define FLASH_SECBB2R3_SEC30 FLASH_SECBB2R3_SEC30_Msk /*!< Page 94 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC31_Pos (31UL) -#define FLASH_SECBB2R3_SEC31_Msk (0x1UL << FLASH_SECBB2R3_SEC31_Pos) /*!< 0x80000000 */ -#define FLASH_SECBB2R3_SEC31 FLASH_SECBB2R3_SEC31_Msk /*!< Page 95 in bank 2 block-based secure */ - -/******************* Bit definition for FLASH_SECBB2R4 register ******************/ -#define FLASH_SECBB2R4_SEC0_Pos (0UL) -#define FLASH_SECBB2R4_SEC0_Msk (0x1UL << FLASH_SECBB2R4_SEC0_Pos) /*!< 0x00000001 */ -#define FLASH_SECBB2R4_SEC0 FLASH_SECBB2R4_SEC0_Msk /*!< Page 96 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC1_Pos (1UL) -#define FLASH_SECBB2R4_SEC1_Msk (0x1UL << FLASH_SECBB2R4_SEC1_Pos) /*!< 0x00000002 */ -#define FLASH_SECBB2R4_SEC1 FLASH_SECBB2R4_SEC1_Msk /*!< Page 97 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC2_Pos (2UL) -#define FLASH_SECBB2R4_SEC2_Msk (0x1UL << FLASH_SECBB2R4_SEC2_Pos) /*!< 0x00000004 */ -#define FLASH_SECBB2R4_SEC2 FLASH_SECBB2R4_SEC2_Msk /*!< Page 98 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC3_Pos (3UL) -#define FLASH_SECBB2R4_SEC3_Msk (0x1UL << FLASH_SECBB2R4_SEC3_Pos) /*!< 0x00000008 */ -#define FLASH_SECBB2R4_SEC3 FLASH_SECBB2R4_SEC3_Msk /*!< Page 99 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC4_Pos (4UL) -#define FLASH_SECBB2R4_SEC4_Msk (0x1UL << FLASH_SECBB2R4_SEC4_Pos) /*!< 0x00000010 */ -#define FLASH_SECBB2R4_SEC4 FLASH_SECBB2R4_SEC4_Msk /*!< Page 100 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC5_Pos (5UL) -#define FLASH_SECBB2R4_SEC5_Msk (0x1UL << FLASH_SECBB2R4_SEC5_Pos) /*!< 0x00000020 */ -#define FLASH_SECBB2R4_SEC5 FLASH_SECBB2R4_SEC5_Msk /*!< Page 101 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC6_Pos (6UL) -#define FLASH_SECBB2R4_SEC6_Msk (0x1UL << FLASH_SECBB2R4_SEC6_Pos) /*!< 0x00000040 */ -#define FLASH_SECBB2R4_SEC6 FLASH_SECBB2R4_SEC6_Msk /*!< Page 102 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC7_Pos (7UL) -#define FLASH_SECBB2R4_SEC7_Msk (0x1UL << FLASH_SECBB2R4_SEC7_Pos) /*!< 0x00000080 */ -#define FLASH_SECBB2R4_SEC7 FLASH_SECBB2R4_SEC7_Msk /*!< Page 103 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC8_Pos (8UL) -#define FLASH_SECBB2R4_SEC8_Msk (0x1UL << FLASH_SECBB2R4_SEC8_Pos) /*!< 0x00000100 */ -#define FLASH_SECBB2R4_SEC8 FLASH_SECBB2R4_SEC8_Msk /*!< Page 104 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC9_Pos (9UL) -#define FLASH_SECBB2R4_SEC9_Msk (0x1UL << FLASH_SECBB2R4_SEC9_Pos) /*!< 0x00000200 */ -#define FLASH_SECBB2R4_SEC9 FLASH_SECBB2R4_SEC9_Msk /*!< Page 105 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC10_Pos (10UL) -#define FLASH_SECBB2R4_SEC10_Msk (0x1UL << FLASH_SECBB2R4_SEC10_Pos) /*!< 0x00000400 */ -#define FLASH_SECBB2R4_SEC10 FLASH_SECBB2R4_SEC10_Msk /*!< Page 106 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC11_Pos (11UL) -#define FLASH_SECBB2R4_SEC11_Msk (0x1UL << FLASH_SECBB2R4_SEC11_Pos) /*!< 0x00000800 */ -#define FLASH_SECBB2R4_SEC11 FLASH_SECBB2R4_SEC11_Msk /*!< Page 107 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC12_Pos (12UL) -#define FLASH_SECBB2R4_SEC12_Msk (0x1UL << FLASH_SECBB2R4_SEC12_Pos) /*!< 0x00001000 */ -#define FLASH_SECBB2R4_SEC12 FLASH_SECBB2R4_SEC12_Msk /*!< Page 108 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC13_Pos (13UL) -#define FLASH_SECBB2R4_SEC13_Msk (0x1UL << FLASH_SECBB2R4_SEC13_Pos) /*!< 0x00002000 */ -#define FLASH_SECBB2R4_SEC13 FLASH_SECBB2R4_SEC13_Msk /*!< Page 109 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC14_Pos (14UL) -#define FLASH_SECBB2R4_SEC14_Msk (0x1UL << FLASH_SECBB2R4_SEC14_Pos) /*!< 0x00004000 */ -#define FLASH_SECBB2R4_SEC14 FLASH_SECBB2R4_SEC14_Msk /*!< Page 110 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC15_Pos (15UL) -#define FLASH_SECBB2R4_SEC15_Msk (0x1UL << FLASH_SECBB2R4_SEC15_Pos) /*!< 0x00008000 */ -#define FLASH_SECBB2R4_SEC15 FLASH_SECBB2R4_SEC15_Msk /*!< Page 111 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC16_Pos (16UL) -#define FLASH_SECBB2R4_SEC16_Msk (0x1UL << FLASH_SECBB2R4_SEC16_Pos) /*!< 0x00010000 */ -#define FLASH_SECBB2R4_SEC16 FLASH_SECBB2R4_SEC16_Msk /*!< Page 112 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC17_Pos (17UL) -#define FLASH_SECBB2R4_SEC17_Msk (0x1UL << FLASH_SECBB2R4_SEC17_Pos) /*!< 0x00020000 */ -#define FLASH_SECBB2R4_SEC17 FLASH_SECBB2R4_SEC17_Msk /*!< Page 113 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC18_Pos (18UL) -#define FLASH_SECBB2R4_SEC18_Msk (0x1UL << FLASH_SECBB2R4_SEC18_Pos) /*!< 0x00040000 */ -#define FLASH_SECBB2R4_SEC18 FLASH_SECBB2R4_SEC18_Msk /*!< Page 114 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC19_Pos (19UL) -#define FLASH_SECBB2R4_SEC19_Msk (0x1UL << FLASH_SECBB2R4_SEC19_Pos) /*!< 0x00080000 */ -#define FLASH_SECBB2R4_SEC19 FLASH_SECBB2R4_SEC19_Msk /*!< Page 115 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC20_Pos (20UL) -#define FLASH_SECBB2R4_SEC20_Msk (0x1UL << FLASH_SECBB2R4_SEC20_Pos) /*!< 0x00100000 */ -#define FLASH_SECBB2R4_SEC20 FLASH_SECBB2R4_SEC20_Msk /*!< Page 116 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC21_Pos (21UL) -#define FLASH_SECBB2R4_SEC21_Msk (0x1UL << FLASH_SECBB2R4_SEC21_Pos) /*!< 0x00200000 */ -#define FLASH_SECBB2R4_SEC21 FLASH_SECBB2R4_SEC21_Msk /*!< Page 117 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC22_Pos (22UL) -#define FLASH_SECBB2R4_SEC22_Msk (0x1UL << FLASH_SECBB2R4_SEC22_Pos) /*!< 0x00400000 */ -#define FLASH_SECBB2R4_SEC22 FLASH_SECBB2R4_SEC22_Msk /*!< Page 118 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC23_Pos (23UL) -#define FLASH_SECBB2R4_SEC23_Msk (0x1UL << FLASH_SECBB2R4_SEC23_Pos) /*!< 0x00800000 */ -#define FLASH_SECBB2R4_SEC23 FLASH_SECBB2R4_SEC23_Msk /*!< Page 119 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC24_Pos (24UL) -#define FLASH_SECBB2R4_SEC24_Msk (0x1UL << FLASH_SECBB2R4_SEC24_Pos) /*!< 0x01000000 */ -#define FLASH_SECBB2R4_SEC24 FLASH_SECBB2R4_SEC24_Msk /*!< Page 120 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC25_Pos (25UL) -#define FLASH_SECBB2R4_SEC25_Msk (0x1UL << FLASH_SECBB2R4_SEC25_Pos) /*!< 0x02000000 */ -#define FLASH_SECBB2R4_SEC25 FLASH_SECBB2R4_SEC25_Msk /*!< Page 121 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC26_Pos (26UL) -#define FLASH_SECBB2R4_SEC26_Msk (0x1UL << FLASH_SECBB2R4_SEC26_Pos) /*!< 0x04000000 */ -#define FLASH_SECBB2R4_SEC26 FLASH_SECBB2R4_SEC26_Msk /*!< Page 122 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC27_Pos (27UL) -#define FLASH_SECBB2R4_SEC27_Msk (0x1UL << FLASH_SECBB2R4_SEC27_Pos) /*!< 0x08000000 */ -#define FLASH_SECBB2R4_SEC27 FLASH_SECBB2R4_SEC27_Msk /*!< Page 123 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC28_Pos (28UL) -#define FLASH_SECBB2R4_SEC28_Msk (0x1UL << FLASH_SECBB2R4_SEC28_Pos) /*!< 0x10000000 */ -#define FLASH_SECBB2R4_SEC28 FLASH_SECBB2R4_SEC28_Msk /*!< Page 124 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC29_Pos (29UL) -#define FLASH_SECBB2R4_SEC29_Msk (0x1UL << FLASH_SECBB2R4_SEC29_Pos) /*!< 0x20000000 */ -#define FLASH_SECBB2R4_SEC29 FLASH_SECBB2R4_SEC29_Msk /*!< Page 125 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC30_Pos (30UL) -#define FLASH_SECBB2R4_SEC30_Msk (0x1UL << FLASH_SECBB2R4_SEC30_Pos) /*!< 0x40000000 */ -#define FLASH_SECBB2R4_SEC30 FLASH_SECBB2R4_SEC30_Msk /*!< Page 126 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC31_Pos (31UL) -#define FLASH_SECBB2R4_SEC31_Msk (0x1UL << FLASH_SECBB2R4_SEC31_Pos) /*!< 0x80000000 */ -#define FLASH_SECBB2R4_SEC31 FLASH_SECBB2R4_SEC31_Msk /*!< Page 127 in bank 2 block-based secure */ /********************** Bits definition for FLASH_SECHDPCR register ***************/ #define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) @@ -9084,6 +8509,8 @@ typedef struct #define GTZC_CFGR3_TSC_Msk (0x01UL << GTZC_CFGR3_TSC_Pos) /*!< 0x00000008 */ #define GTZC_CFGR3_ICACHE_REG_Pos (6UL) #define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) /*!< 0x00000020 */ +#define GTZC_CFGR3_ADC1_Pos (8UL) +#define GTZC_CFGR3_ADC1_Msk (0x01UL << GTZC_CFGR3_ADC1_Pos) /*!< 0x00000100 */ #define GTZC_CFGR3_HASH_Pos (12UL) #define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) /*!< 0x00001000 */ #define GTZC_CFGR3_RNG_Pos (13UL) @@ -9200,6 +8627,8 @@ typedef struct #define GTZC_TZSC1_SECCFGR3_TSC_Msk GTZC_CFGR3_TSC_Msk #define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos #define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_SECCFGR3_ADC1_Pos GTZC_CFGR3_ADC1_Pos +#define GTZC_TZSC1_SECCFGR3_ADC1_Msk GTZC_CFGR3_ADC1_Msk #define GTZC_TZSC1_SECCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos #define GTZC_TZSC1_SECCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk #define GTZC_TZSC1_SECCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos @@ -9284,6 +8713,8 @@ typedef struct #define GTZC_TZSC1_PRIVCFGR3_TSC_Msk GTZC_CFGR3_TSC_Msk #define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos #define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_ADC1_Pos GTZC_CFGR3_ADC1_Pos +#define GTZC_TZSC1_PRIVCFGR3_ADC1_Msk GTZC_CFGR3_ADC1_Msk #define GTZC_TZSC1_PRIVCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos #define GTZC_TZSC1_PRIVCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk #define GTZC_TZSC1_PRIVCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos @@ -9368,6 +8799,8 @@ typedef struct #define GTZC_TZIC1_IER3_TSC_Msk GTZC_CFGR3_TSC_Msk #define GTZC_TZIC1_IER3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos #define GTZC_TZIC1_IER3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_IER3_ADC1_Pos GTZC_CFGR3_ADC1_Pos +#define GTZC_TZIC1_IER3_ADC1_Msk GTZC_CFGR3_ADC1_Msk #define GTZC_TZIC1_IER3_HASH_Pos GTZC_CFGR3_HASH_Pos #define GTZC_TZIC1_IER3_HASH_Msk GTZC_CFGR3_HASH_Msk #define GTZC_TZIC1_IER3_RNG_Pos GTZC_CFGR3_RNG_Pos @@ -9484,6 +8917,8 @@ typedef struct #define GTZC_TZIC1_SR3_TSC_Msk GTZC_CFGR3_TSC_Msk #define GTZC_TZIC1_SR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos #define GTZC_TZIC1_SR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_SR3_ADC1_Pos GTZC_CFGR3_ADC1_Pos +#define GTZC_TZIC1_SR3_ADC1_Msk GTZC_CFGR3_ADC1_Msk #define GTZC_TZIC1_SR3_HASH_Pos GTZC_CFGR3_HASH_Pos #define GTZC_TZIC1_SR3_HASH_Msk GTZC_CFGR3_HASH_Msk #define GTZC_TZIC1_SR3_RNG_Pos GTZC_CFGR3_RNG_Pos @@ -9600,6 +9035,8 @@ typedef struct #define GTZC_TZIC1_FCR3_TSC_Msk GTZC_CFGR3_TSC_Msk #define GTZC_TZIC1_FCR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos #define GTZC_TZIC1_FCR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_FCR3_ADC1_Pos GTZC_CFGR3_ADC1_Pos +#define GTZC_TZIC1_FCR3_ADC1_Msk GTZC_CFGR3_ADC1_Msk #define GTZC_TZIC1_FCR3_HASH_Pos GTZC_CFGR3_HASH_Pos #define GTZC_TZIC1_FCR3_HASH_Msk GTZC_CFGR3_HASH_Msk #define GTZC_TZIC1_FCR3_RNG_Pos GTZC_CFGR3_RNG_Pos @@ -11816,24 +11253,6 @@ typedef struct #define PWR_CR2_SRAM1PDS1_Pos (0UL) #define PWR_CR2_SRAM1PDS1_Msk (0x1UL << PWR_CR2_SRAM1PDS1_Pos) /*!< 0x00000001 */ #define PWR_CR2_SRAM1PDS1 PWR_CR2_SRAM1PDS1_Msk /*!< SRAM1 page 1 (16 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_CR2_SRAM1PDS2_Pos (1UL) -#define PWR_CR2_SRAM1PDS2_Msk (0x1UL << PWR_CR2_SRAM1PDS2_Pos) /*!< 0x00000002 */ -#define PWR_CR2_SRAM1PDS2 PWR_CR2_SRAM1PDS2_Msk /*!< SRAM1 page 2 (16 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_CR2_SRAM1PDS3_Pos (2UL) -#define PWR_CR2_SRAM1PDS3_Msk (0x1UL << PWR_CR2_SRAM1PDS3_Pos) /*!< 0x00000004 */ -#define PWR_CR2_SRAM1PDS3 PWR_CR2_SRAM1PDS3_Msk /*!< SRAM1 page 3 (32 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_CR2_SRAM1PDS4_Pos (3UL) -#define PWR_CR2_SRAM1PDS4_Msk (0x1UL << PWR_CR2_SRAM1PDS4_Pos) /*!< 0x00000008 */ -#define PWR_CR2_SRAM1PDS4 PWR_CR2_SRAM1PDS4_Msk /*!< SRAM1 page 4 (32 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_CR2_SRAM1PDS5_Pos (4UL) -#define PWR_CR2_SRAM1PDS5_Msk (0x1UL << PWR_CR2_SRAM1PDS5_Pos) /*!< 0x00000010 */ -#define PWR_CR2_SRAM1PDS5 PWR_CR2_SRAM1PDS5_Msk /*!< SRAM1 page 5 (32 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_CR2_SRAM1PDS6_Pos (5UL) -#define PWR_CR2_SRAM1PDS6_Msk (0x1UL << PWR_CR2_SRAM1PDS6_Pos) /*!< 0x00000020 */ -#define PWR_CR2_SRAM1PDS6 PWR_CR2_SRAM1PDS6_Msk /*!< SRAM1 page 6 (32 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_CR2_SRAM1PDS7_Pos (6UL) -#define PWR_CR2_SRAM1PDS7_Msk (0x1UL << PWR_CR2_SRAM1PDS7_Pos) /*!< 0x00000040 */ -#define PWR_CR2_SRAM1PDS7 PWR_CR2_SRAM1PDS7_Msk /*!< SRAM1 page 7 (32 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */ #define PWR_CR2_SRAM2PDS1_Pos (16UL) #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00010000 */ #define PWR_CR2_SRAM2PDS1 PWR_CR2_SRAM2PDS1_Msk /*!< SRAM2 page 1 (8 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */ @@ -12569,193 +11988,7 @@ typedef struct #define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */ #define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Apply pull-down for PD15 */ -/******************** Bit definition for PWR_PUCRE register *****************/ -#define PWR_PUCRE_PU0_Pos (0UL) -#define PWR_PUCRE_PU0_Msk (0x1UL << PWR_PUCRE_PU0_Pos) /*!< 0x00000001 */ -#define PWR_PUCRE_PU0 PWR_PUCRE_PU0_Msk /*!< Apply pull-up for PE0 */ -#define PWR_PUCRE_PU1_Pos (1UL) -#define PWR_PUCRE_PU1_Msk (0x1UL << PWR_PUCRE_PU1_Pos) /*!< 0x00000002 */ -#define PWR_PUCRE_PU1 PWR_PUCRE_PU1_Msk /*!< Apply pull-up for PE1 */ -#define PWR_PUCRE_PU2_Pos (2UL) -#define PWR_PUCRE_PU2_Msk (0x1UL << PWR_PUCRE_PU2_Pos) /*!< 0x00000004 */ -#define PWR_PUCRE_PU2 PWR_PUCRE_PU2_Msk /*!< Apply pull-up for PE2 */ -#define PWR_PUCRE_PU3_Pos (3UL) -#define PWR_PUCRE_PU3_Msk (0x1UL << PWR_PUCRE_PU3_Pos) /*!< 0x00000008 */ -#define PWR_PUCRE_PU3 PWR_PUCRE_PU3_Msk /*!< Apply pull-up for PE3 */ -#define PWR_PUCRE_PU4_Pos (4UL) -#define PWR_PUCRE_PU4_Msk (0x1UL << PWR_PUCRE_PU4_Pos) /*!< 0x00000010 */ -#define PWR_PUCRE_PU4 PWR_PUCRE_PU4_Msk /*!< Apply pull-up for PE4 */ -#define PWR_PUCRE_PU5_Pos (5UL) -#define PWR_PUCRE_PU5_Msk (0x1UL << PWR_PUCRE_PU5_Pos) /*!< 0x00000020 */ -#define PWR_PUCRE_PU5 PWR_PUCRE_PU5_Msk /*!< Apply pull-up for PE5 */ -#define PWR_PUCRE_PU6_Pos (6UL) -#define PWR_PUCRE_PU6_Msk (0x1UL << PWR_PUCRE_PU6_Pos) /*!< 0x00000040 */ -#define PWR_PUCRE_PU6 PWR_PUCRE_PU6_Msk /*!< Apply pull-up for PE6 */ -#define PWR_PUCRE_PU7_Pos (7UL) -#define PWR_PUCRE_PU7_Msk (0x1UL << PWR_PUCRE_PU7_Pos) /*!< 0x00000080 */ -#define PWR_PUCRE_PU7 PWR_PUCRE_PU7_Msk /*!< Apply pull-up for PE7 */ -#define PWR_PUCRE_PU8_Pos (8UL) -#define PWR_PUCRE_PU8_Msk (0x1UL << PWR_PUCRE_PU8_Pos) /*!< 0x00000100 */ -#define PWR_PUCRE_PU8 PWR_PUCRE_PU8_Msk /*!< Apply pull-up for PE8 */ -#define PWR_PUCRE_PU9_Pos (9UL) -#define PWR_PUCRE_PU9_Msk (0x1UL << PWR_PUCRE_PU9_Pos) /*!< 0x00000200 */ -#define PWR_PUCRE_PU9 PWR_PUCRE_PU9_Msk /*!< Apply pull-up for PE9 */ -#define PWR_PUCRE_PU10_Pos (10UL) -#define PWR_PUCRE_PU10_Msk (0x1UL << PWR_PUCRE_PU10_Pos) /*!< 0x00000400 */ -#define PWR_PUCRE_PU10 PWR_PUCRE_PU10_Msk /*!< Apply pull-up for PE10 */ -#define PWR_PUCRE_PU11_Pos (11UL) -#define PWR_PUCRE_PU11_Msk (0x1UL << PWR_PUCRE_PU11_Pos) /*!< 0x00000800 */ -#define PWR_PUCRE_PU11 PWR_PUCRE_PU11_Msk /*!< Apply pull-up for PE11 */ -#define PWR_PUCRE_PU12_Pos (12UL) -#define PWR_PUCRE_PU12_Msk (0x1UL << PWR_PUCRE_PU12_Pos) /*!< 0x00001000 */ -#define PWR_PUCRE_PU12 PWR_PUCRE_PU12_Msk /*!< Apply pull-up for PE12 */ -#define PWR_PUCRE_PU13_Pos (13UL) -#define PWR_PUCRE_PU13_Msk (0x1UL << PWR_PUCRE_PU13_Pos) /*!< 0x00002000 */ -#define PWR_PUCRE_PU13 PWR_PUCRE_PU13_Msk /*!< Apply pull-up for PE13 */ -#define PWR_PUCRE_PU14_Pos (14UL) -#define PWR_PUCRE_PU14_Msk (0x1UL << PWR_PUCRE_PU14_Pos) /*!< 0x00004000 */ -#define PWR_PUCRE_PU14 PWR_PUCRE_PU14_Msk /*!< Apply pull-up for PE14 */ -#define PWR_PUCRE_PU15_Pos (15UL) -#define PWR_PUCRE_PU15_Msk (0x1UL << PWR_PUCRE_PU15_Pos) /*!< 0x00008000 */ -#define PWR_PUCRE_PU15 PWR_PUCRE_PU15_Msk /*!< Apply pull-up for PE15 */ - -/******************** Bit definition for PWR_PDCRE register *****************/ -#define PWR_PDCRE_PD0_Pos (0UL) -#define PWR_PDCRE_PD0_Msk (0x1UL << PWR_PDCRE_PD0_Pos) /*!< 0x00000001 */ -#define PWR_PDCRE_PD0 PWR_PDCRE_PD0_Msk /*!< Apply pull-down for PE0 */ -#define PWR_PDCRE_PD1_Pos (1UL) -#define PWR_PDCRE_PD1_Msk (0x1UL << PWR_PDCRE_PD1_Pos) /*!< 0x00000002 */ -#define PWR_PDCRE_PD1 PWR_PDCRE_PD1_Msk /*!< Apply pull-down for PE1 */ -#define PWR_PDCRE_PD2_Pos (2UL) -#define PWR_PDCRE_PD2_Msk (0x1UL << PWR_PDCRE_PD2_Pos) /*!< 0x00000004 */ -#define PWR_PDCRE_PD2 PWR_PDCRE_PD2_Msk /*!< Apply pull-down for PE2 */ -#define PWR_PDCRE_PD3_Pos (3UL) -#define PWR_PDCRE_PD3_Msk (0x1UL << PWR_PDCRE_PD3_Pos) /*!< 0x00000008 */ -#define PWR_PDCRE_PD3 PWR_PDCRE_PD3_Msk /*!< Apply pull-down for PE3 */ -#define PWR_PDCRE_PD4_Pos (4UL) -#define PWR_PDCRE_PD4_Msk (0x1UL << PWR_PDCRE_PD4_Pos) /*!< 0x00000010 */ -#define PWR_PDCRE_PD4 PWR_PDCRE_PD4_Msk /*!< Apply pull-down for PE4 */ -#define PWR_PDCRE_PD5_Pos (5UL) -#define PWR_PDCRE_PD5_Msk (0x1UL << PWR_PDCRE_PD5_Pos) /*!< 0x00000020 */ -#define PWR_PDCRE_PD5 PWR_PDCRE_PD5_Msk /*!< Apply pull-down for PE5 */ -#define PWR_PDCRE_PD6_Pos (6UL) -#define PWR_PDCRE_PD6_Msk (0x1UL << PWR_PDCRE_PD6_Pos) /*!< 0x00000040 */ -#define PWR_PDCRE_PD6 PWR_PDCRE_PD6_Msk /*!< Apply pull-down for PE6 */ -#define PWR_PDCRE_PD7_Pos (7UL) -#define PWR_PDCRE_PD7_Msk (0x1UL << PWR_PDCRE_PD7_Pos) /*!< 0x00000080 */ -#define PWR_PDCRE_PD7 PWR_PDCRE_PD7_Msk /*!< Apply pull-down for PE7 */ -#define PWR_PDCRE_PD8_Pos (8UL) -#define PWR_PDCRE_PD8_Msk (0x1UL << PWR_PDCRE_PD8_Pos) /*!< 0x00000100 */ -#define PWR_PDCRE_PD8 PWR_PDCRE_PD8_Msk /*!< Apply pull-down for PE8 */ -#define PWR_PDCRE_PD9_Pos (9UL) -#define PWR_PDCRE_PD9_Msk (0x1UL << PWR_PDCRE_PD9_Pos) /*!< 0x00000200 */ -#define PWR_PDCRE_PD9 PWR_PDCRE_PD9_Msk /*!< Apply pull-down for PE9 */ -#define PWR_PDCRE_PD10_Pos (10UL) -#define PWR_PDCRE_PD10_Msk (0x1UL << PWR_PDCRE_PD10_Pos) /*!< 0x00000400 */ -#define PWR_PDCRE_PD10 PWR_PDCRE_PD10_Msk /*!< Apply pull-down for PE10 */ -#define PWR_PDCRE_PD11_Pos (11UL) -#define PWR_PDCRE_PD11_Msk (0x1UL << PWR_PDCRE_PD11_Pos) /*!< 0x00000800 */ -#define PWR_PDCRE_PD11 PWR_PDCRE_PD11_Msk /*!< Apply pull-down for PE11 */ -#define PWR_PDCRE_PD12_Pos (12UL) -#define PWR_PDCRE_PD12_Msk (0x1UL << PWR_PDCRE_PD12_Pos) /*!< 0x00001000 */ -#define PWR_PDCRE_PD12 PWR_PDCRE_PD12_Msk /*!< Apply pull-down for PE12 */ -#define PWR_PDCRE_PD13_Pos (13UL) -#define PWR_PDCRE_PD13_Msk (0x1UL << PWR_PDCRE_PD13_Pos) /*!< 0x00002000 */ -#define PWR_PDCRE_PD13 PWR_PDCRE_PD13_Msk /*!< Apply pull-down for PE13 */ -#define PWR_PDCRE_PD14_Pos (14UL) -#define PWR_PDCRE_PD14_Msk (0x1UL << PWR_PDCRE_PD14_Pos) /*!< 0x00004000 */ -#define PWR_PDCRE_PD14 PWR_PDCRE_PD14_Msk /*!< Apply pull-down for PE14 */ -#define PWR_PDCRE_PD15_Pos (15UL) -#define PWR_PDCRE_PD15_Msk (0x1UL << PWR_PDCRE_PD15_Pos) /*!< 0x00008000 */ -#define PWR_PDCRE_PD15 PWR_PDCRE_PD15_Msk /*!< Apply pull-down for PE15 */ - -/******************** Bit definition for PWR_PUCRG register *****************/ -#define PWR_PUCRG_PU2_Pos (2UL) -#define PWR_PUCRG_PU2_Msk (0x1UL << PWR_PUCRG_PU2_Pos) /*!< 0x00000004 */ -#define PWR_PUCRG_PU2 PWR_PUCRG_PU2_Msk /*!< Apply pull-up for PG2 */ -#define PWR_PUCRG_PU3_Pos (3UL) -#define PWR_PUCRG_PU3_Msk (0x1UL << PWR_PUCRG_PU3_Pos) /*!< 0x00000008 */ -#define PWR_PUCRG_PU3 PWR_PUCRG_PU3_Msk /*!< Apply pull-up for PG3 */ -#define PWR_PUCRG_PU4_Pos (4UL) -#define PWR_PUCRG_PU4_Msk (0x1UL << PWR_PUCRG_PU4_Pos) /*!< 0x00000010 */ -#define PWR_PUCRG_PU4 PWR_PUCRG_PU4_Msk /*!< Apply pull-up for PG4 */ -#define PWR_PUCRG_PU5_Pos (5UL) -#define PWR_PUCRG_PU5_Msk (0x1UL << PWR_PUCRG_PU5_Pos) /*!< 0x00000020 */ -#define PWR_PUCRG_PU5 PWR_PUCRG_PU5_Msk /*!< Apply pull-up for PG5 */ -#define PWR_PUCRG_PU6_Pos (6UL) -#define PWR_PUCRG_PU6_Msk (0x1UL << PWR_PUCRG_PU6_Pos) /*!< 0x00000040 */ -#define PWR_PUCRG_PU6 PWR_PUCRG_PU6_Msk /*!< Apply pull-up for PG6 */ -#define PWR_PUCRG_PU7_Pos (7UL) -#define PWR_PUCRG_PU7_Msk (0x1UL << PWR_PUCRG_PU7_Pos) /*!< 0x00000080 */ -#define PWR_PUCRG_PU7 PWR_PUCRG_PU7_Msk /*!< Apply pull-up for PG7 */ -#define PWR_PUCRG_PU8_Pos (8UL) -#define PWR_PUCRG_PU8_Msk (0x1UL << PWR_PUCRG_PU8_Pos) /*!< 0x00000100 */ -#define PWR_PUCRG_PU8 PWR_PUCRG_PU8_Msk /*!< Apply pull-up for PG8 */ -#define PWR_PUCRG_PU9_Pos (9UL) -#define PWR_PUCRG_PU9_Msk (0x1UL << PWR_PUCRG_PU9_Pos) /*!< 0x00000200 */ -#define PWR_PUCRG_PU9 PWR_PUCRG_PU9_Msk /*!< Apply pull-up for PG9 */ -#define PWR_PUCRG_PU10_Pos (10UL) -#define PWR_PUCRG_PU10_Msk (0x1UL << PWR_PUCRG_PU10_Pos) /*!< 0x00000400 */ -#define PWR_PUCRG_PU10 PWR_PUCRG_PU10_Msk /*!< Apply pull-up for PG10 */ -#define PWR_PUCRG_PU11_Pos (11UL) -#define PWR_PUCRG_PU11_Msk (0x1UL << PWR_PUCRG_PU11_Pos) /*!< 0x00000800 */ -#define PWR_PUCRG_PU11 PWR_PUCRG_PU11_Msk /*!< Apply pull-up for PG11 */ -#define PWR_PUCRG_PU12_Pos (12UL) -#define PWR_PUCRG_PU12_Msk (0x1UL << PWR_PUCRG_PU12_Pos) /*!< 0x00001000 */ -#define PWR_PUCRG_PU12 PWR_PUCRG_PU12_Msk /*!< Apply pull-up for PG12 */ -#define PWR_PUCRG_PU13_Pos (13UL) -#define PWR_PUCRG_PU13_Msk (0x1UL << PWR_PUCRG_PU13_Pos) /*!< 0x00002000 */ -#define PWR_PUCRG_PU13 PWR_PUCRG_PU13_Msk /*!< Apply pull-up for PG13 */ -#define PWR_PUCRG_PU14_Pos (14UL) -#define PWR_PUCRG_PU14_Msk (0x1UL << PWR_PUCRG_PU14_Pos) /*!< 0x00004000 */ -#define PWR_PUCRG_PU14 PWR_PUCRG_PU14_Msk /*!< Apply pull-up for PG14 */ -#define PWR_PUCRG_PU15_Pos (15UL) -#define PWR_PUCRG_PU15_Msk (0x1UL << PWR_PUCRG_PU15_Pos) /*!< 0x00008000 */ -#define PWR_PUCRG_PU15 PWR_PUCRG_PU15_Msk /*!< Apply pull-up for PG15 */ - -/******************** Bit definition for PWR_PDCRG register *****************/ -#define PWR_PDCRG_PD2_Pos (2UL) -#define PWR_PDCRG_PD2_Msk (0x1UL << PWR_PDCRG_PD2_Pos) /*!< 0x00000004 */ -#define PWR_PDCRG_PD2 PWR_PDCRG_PD2_Msk /*!< Apply pull-down for PG2 */ -#define PWR_PDCRG_PD3_Pos (3UL) -#define PWR_PDCRG_PD3_Msk (0x1UL << PWR_PDCRG_PD3_Pos) /*!< 0x00000008 */ -#define PWR_PDCRG_PD3 PWR_PDCRG_PD3_Msk /*!< Apply pull-down for PG3 */ -#define PWR_PDCRG_PD4_Pos (4UL) -#define PWR_PDCRG_PD4_Msk (0x1UL << PWR_PDCRG_PD4_Pos) /*!< 0x00000010 */ -#define PWR_PDCRG_PD4 PWR_PDCRG_PD4_Msk /*!< Apply pull-down for PG4 */ -#define PWR_PDCRG_PD5_Pos (5UL) -#define PWR_PDCRG_PD5_Msk (0x1UL << PWR_PDCRG_PD5_Pos) /*!< 0x00000020 */ -#define PWR_PDCRG_PD5 PWR_PDCRG_PD5_Msk /*!< Apply pull-down for PG5 */ -#define PWR_PDCRG_PD6_Pos (6UL) -#define PWR_PDCRG_PD6_Msk (0x1UL << PWR_PDCRG_PD6_Pos) /*!< 0x00000040 */ -#define PWR_PDCRG_PD6 PWR_PDCRG_PD6_Msk /*!< Apply pull-down for PG6 */ -#define PWR_PDCRG_PD7_Pos (7UL) -#define PWR_PDCRG_PD7_Msk (0x1UL << PWR_PDCRG_PD7_Pos) /*!< 0x00000080 */ -#define PWR_PDCRG_PD7 PWR_PDCRG_PD7_Msk /*!< Apply pull-down for PG7 */ -#define PWR_PDCRG_PD8_Pos (8UL) -#define PWR_PDCRG_PD8_Msk (0x1UL << PWR_PDCRG_PD8_Pos) /*!< 0x00000100 */ -#define PWR_PDCRG_PD8 PWR_PDCRG_PD8_Msk /*!< Apply pull-down for PG8 */ -#define PWR_PDCRG_PD9_Pos (9UL) -#define PWR_PDCRG_PD9_Msk (0x1UL << PWR_PDCRG_PD9_Pos) /*!< 0x00000200 */ -#define PWR_PDCRG_PD9 PWR_PDCRG_PD9_Msk /*!< Apply pull-down for PG9 */ -#define PWR_PDCRG_PD10_Pos (10UL) -#define PWR_PDCRG_PD10_Msk (0x1UL << PWR_PDCRG_PD10_Pos) /*!< 0x00000400 */ -#define PWR_PDCRG_PD10 PWR_PDCRG_PD10_Msk /*!< Apply pull-down for PG10 */ -#define PWR_PDCRG_PD11_Pos (11UL) -#define PWR_PDCRG_PD11_Msk (0x1UL << PWR_PDCRG_PD11_Pos) /*!< 0x00000800 */ -#define PWR_PDCRG_PD11 PWR_PDCRG_PD11_Msk /*!< Apply pull-down for PG11 */ -#define PWR_PDCRG_PD12_Pos (12UL) -#define PWR_PDCRG_PD12_Msk (0x1UL << PWR_PDCRG_PD12_Pos) /*!< 0x00001000 */ -#define PWR_PDCRG_PD12 PWR_PDCRG_PD12_Msk /*!< Apply pull-down for PG12 */ -#define PWR_PDCRG_PD13_Pos (13UL) -#define PWR_PDCRG_PD13_Msk (0x1UL << PWR_PDCRG_PD13_Pos) /*!< 0x00002000 */ -#define PWR_PDCRG_PD13 PWR_PDCRG_PD13_Msk /*!< Apply pull-down for PG13 */ -#define PWR_PDCRG_PD14_Pos (14UL) -#define PWR_PDCRG_PD14_Msk (0x1UL << PWR_PDCRG_PD14_Pos) /*!< 0x00004000 */ -#define PWR_PDCRG_PD14 PWR_PDCRG_PD14_Msk /*!< Apply pull-down for PG14 */ -#define PWR_PDCRG_PD15_Pos (15UL) -#define PWR_PDCRG_PD15_Msk (0x1UL << PWR_PDCRG_PD15_Pos) /*!< 0x00008000 */ -#define PWR_PDCRG_PD15 PWR_PDCRG_PD15_Msk /*!< Apply pull-down for PG15 */ + /******************** Bit definition for PWR_PUCRH register *****************/ #define PWR_PUCRH_PU0_Pos (0UL) @@ -12810,35 +12043,11 @@ typedef struct #define PWR_I3CPUCR1_PB13_I3CPU_Pos (10UL) #define PWR_I3CPUCR1_PB13_I3CPU_Msk (0x1UL << PWR_I3CPUCR1_PB13_I3CPU_Pos) /*!< 0x00000400 */ #define PWR_I3CPUCR1_PB13_I3CPU PWR_I3CPUCR1_PB13_I3CPU_Msk /*!< Port B pin 13 I3C pull-up */ -#define PWR_I3CPUCR1_PB14_I3CPU_Pos (11UL) -#define PWR_I3CPUCR1_PB14_I3CPU_Msk (0x1UL << PWR_I3CPUCR1_PB14_I3CPU_Pos) /*!< 0x00000800 */ -#define PWR_I3CPUCR1_PB14_I3CPU PWR_I3CPUCR1_PB14_I3CPU_Msk /*!< Port B pin 14 I3C pull-up */ +#define PWR_I3CPUCR1_PB7_I3CPU_Pos (12UL) +#define PWR_I3CPUCR1_PB7_I3CPU_Msk (0x1UL << PWR_I3CPUCR1_PB7_I3CPU_Pos) /*!< 0x00001000 */ +#define PWR_I3CPUCR1_PB7_I3CPU PWR_I3CPUCR1_PB7_I3CPU_Msk /*!< Port B pin 7 I3C pull-up */ /******************** Bit definition for PWR_I3CPUCR2 register *****************/ -#define PWR_I3CPUCR2_PC0_I3CPU_Pos (0UL) -#define PWR_I3CPUCR2_PC0_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PC0_I3CPU_Pos) /*!< 0x00000001 */ -#define PWR_I3CPUCR2_PC0_I3CPU PWR_I3CPUCR2_PC0_I3CPU_Msk /*!< Port C pin 0 I3C pull-up */ -#define PWR_I3CPUCR2_PC1_I3CPU_Pos (1UL) -#define PWR_I3CPUCR2_PC1_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PC1_I3CPU_Pos) /*!< 0x00000002 */ -#define PWR_I3CPUCR2_PC1_I3CPU PWR_I3CPUCR2_PC1_I3CPU_Msk /*!< Port C pin 1 I3C pull-up */ -#define PWR_I3CPUCR2_PD12_I3CPU_Pos (3UL) -#define PWR_I3CPUCR2_PD12_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PD12_I3CPU_Pos) /*!< 0x00000008 */ -#define PWR_I3CPUCR2_PD12_I3CPU PWR_I3CPUCR2_PD12_I3CPU_Msk /*!< Port D pin 12 I3C pull-up */ -#define PWR_I3CPUCR2_PD13_I3CPU_Pos (4UL) -#define PWR_I3CPUCR2_PD13_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PD13_I3CPU_Pos) /*!< 0x00000010 */ -#define PWR_I3CPUCR2_PD13_I3CPU PWR_I3CPUCR2_PD13_I3CPU_Msk /*!< Port D pin 13 I3C pull-up */ -#define PWR_I3CPUCR2_PG7_I3CPU_Pos (6UL) -#define PWR_I3CPUCR2_PG7_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PG7_I3CPU_Pos) /*!< 0x00000040 */ -#define PWR_I3CPUCR2_PG7_I3CPU PWR_I3CPUCR2_PG7_I3CPU_Msk /*!< Port G pin 7 I3C pull-up */ -#define PWR_I3CPUCR2_PG8_I3CPU_Pos (7UL) -#define PWR_I3CPUCR2_PG8_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PG8_I3CPU_Pos) /*!< 0x00000080 */ -#define PWR_I3CPUCR2_PG8_I3CPU PWR_I3CPUCR2_PG8_I3CPU_Msk /*!< Port G pin 8 I3C pull-up */ -#define PWR_I3CPUCR2_PG13_I3CPU_Pos (8UL) -#define PWR_I3CPUCR2_PG13_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PG13_I3CPU_Pos) /*!< 0x00000100 */ -#define PWR_I3CPUCR2_PG13_I3CPU PWR_I3CPUCR2_PG13_I3CPU_Msk /*!< Port G pin 13 I3C pull-up */ -#define PWR_I3CPUCR2_PG14_I3CPU_Pos (9UL) -#define PWR_I3CPUCR2_PG14_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PG14_I3CPU_Pos) /*!< 0x00000200 */ -#define PWR_I3CPUCR2_PG14_I3CPU PWR_I3CPUCR2_PG14_I3CPU_Msk /*!< Port G pin 14 I3C pull-up */ #define PWR_I3CPUCR2_PH3_I3CPU_Pos (11UL) #define PWR_I3CPUCR2_PH3_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PH3_I3CPU_Pos) /*!< 0x00000800 */ #define PWR_I3CPUCR2_PH3_I3CPU PWR_I3CPUCR2_PH3_I3CPU_Msk /*!< Port H pin 3 I3C pull-up */ @@ -13668,6 +12877,9 @@ typedef struct #define RCC_AHB2ENR1_GPIOHEN_Pos (7UL) #define RCC_AHB2ENR1_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOHEN_Pos) /*!< 0x00000080 */ #define RCC_AHB2ENR1_GPIOHEN RCC_AHB2ENR1_GPIOHEN_Msk /*!< IO port H Enable */ +#define RCC_AHB2ENR1_ADC12EN_Pos (10UL) +#define RCC_AHB2ENR1_ADC12EN_Msk (0x1UL << RCC_AHB2ENR1_ADC12EN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2ENR1_ADC12EN RCC_AHB2ENR1_ADC12EN_Msk /*!< ADC12 Enable */ #define RCC_AHB2ENR1_DAC1EN_Pos (11UL) #define RCC_AHB2ENR1_DAC1EN_Msk (0x1UL << RCC_AHB2ENR1_DAC1EN_Pos) /*!< 0x00000800 */ #define RCC_AHB2ENR1_DAC1EN RCC_AHB2ENR1_DAC1EN_Msk /*!< DAC1 Enable */ @@ -14308,41 +13520,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -14356,7 +13568,7 @@ typedef struct #define RNG_SR_SECS RNG_SR_SECS_Msk #define RNG_SR_BUSY_Pos (4UL) #define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ -#define RNG_SR_BUSY RNG_SR_BUSY_Msk +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ #define RNG_SR_CEIS_Pos (5UL) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk @@ -14366,15 +13578,138 @@ typedef struct /******************** Bits definition for RNG_NSCR register *******************/ #define RNG_NSCR_EN_OSC1_Pos (0UL) -#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ #define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk #define RNG_NSCR_EN_OSC2_Pos (3UL) -#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ #define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk -#define RNG_NSCR_EN_OSC3_Pos (06UL) -#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +/******************** Bits definition for RNG_HTCR0 register *******************/ +#define RNG_HTCR0_HTCFG_Pos (0UL) +#define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR0_HTCFG RNG_HTCR0_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR1 register *******************/ +#define RNG_HTCR1_HTCFG_Pos (0UL) +#define RNG_HTCR1_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR1_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR1_HTCFG RNG_HTCR1_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR2 register *******************/ +#define RNG_HTCR2_HTCFG_Pos (0UL) +#define RNG_HTCR2_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR2_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR2_HTCFG RNG_HTCR2_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR3 register *******************/ +#define RNG_HTCR3_HTCFG_Pos (0UL) +#define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk + +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0UL) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1UL) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2UL) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3UL) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4UL) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5UL) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6UL) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7UL) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8UL) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9UL) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0UL) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1UL) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2UL) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3UL) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4UL) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5UL) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6UL) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7UL) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8UL) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9UL) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0UL) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1UL) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2UL) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3UL) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4UL) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5UL) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6UL) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7UL) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8UL) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ @@ -18724,6 +18059,7 @@ typedef struct #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || ((INSTANCE) == ADC1_S)) +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_COMMON_NS)) @@ -18862,6 +18198,8 @@ typedef struct #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (0) + #define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) @@ -18869,6 +18207,7 @@ typedef struct #define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (0) /****************** LPTIM Instances : All supported instances *****************/ #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ @@ -19292,10 +18631,11 @@ typedef struct #else /* CPU_IN_SECURE_STATE */ /******************************* ADC Instances ********************************/ -#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_NS) +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS)) #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_NS) +#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON_NS) /******************************* HASH Instances ********************************/ #define IS_HASH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HASH_NS) @@ -19426,6 +18766,8 @@ typedef struct #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \ ((INSTANCE) == SPI2_NS)) +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (0) + #define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \ ((INSTANCE) == SPI2_NS)) @@ -19433,6 +18775,7 @@ typedef struct #define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \ ((INSTANCE) == SPI2_NS)) +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (0) /****************** LPTIM Instances : All supported instances *****************/ #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) ||\ @@ -19857,7 +19200,7 @@ typedef struct #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_DRD_FS_NS) #endif /* CPU_IN_SECURE_STATE */ -/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */ +/** @} */ /* End of group STM32U3xx_Peripheral_Exported_macros */ /** @} */ /* End of group STM32U335xx */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u345xx.h b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u345xx.h index 26953ee9a6..1a47247d21 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u345xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u345xx.h @@ -975,7 +975,10 @@ typedef struct __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ } RNG_TypeDef; /** @@ -1337,7 +1340,7 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define FLASH_BASE_NS 0x08000000UL /*!< FLASH non-secure base address */ #define SYSTEM_FLASH_BASE_NS 0x0BF80000UL /*!< System FLASH non-secure base address */ #define SRAM1_BASE_NS 0x20000000UL /*!< SRAM1 non-secure base address */ -#define SRAM2_BASE_NS 0x20040000UL /*!< SRAM2 non-secure base address */ +#define SRAM2_BASE_NS 0x20004000UL /*!< SRAM2 non-secure base address */ #define PERIPH_BASE_NS 0x40000000UL /*!< Peripheral non-secure base address */ #define EXTRAM_BASE_NS 0x90000000UL /*!< External RAM base address */ @@ -1449,6 +1452,7 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000C00UL) #define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001C00UL) #define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008000UL) +#define ADC1_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008300UL) #define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008400UL) #define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0000UL) #define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0400UL) @@ -1462,7 +1466,7 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define FLASH_BASE_S 0x0C000000UL /*!< FLASH secure base address */ #define SYSTEM_FLASH_BASE_S 0x0FF80000UL /*!< System FLASH secure base address */ #define SRAM1_BASE_S 0x30000000UL /*!< SRAM1 secure base address */ -#define SRAM2_BASE_S 0x30030000UL /*!< SRAM2 secure base address */ +#define SRAM2_BASE_S 0x30004000UL /*!< SRAM2 secure base address */ #define PERIPH_BASE_S 0x50000000UL /*!< Peripheral secure base address */ /*!< Peripheral memory map - secure */ @@ -1553,6 +1557,7 @@ typedef XSPIM_TypeDef OCTOSPIM_TypeDef; #define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00000C00UL) #define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x00001C00UL) #define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x00008000UL) +#define ADC1_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x00008300UL) #define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x00008400UL) #define AES_BASE_S (AHB2PERIPH_BASE_S + 0x000A0000UL) #define HASH_BASE_S (AHB2PERIPH_BASE_S + 0x000A0400UL) @@ -1683,6 +1688,7 @@ typedef struct /** @addtogroup STM32U3xx_Peripheral_declaration * @{ */ +#define ADC1_COMMON_NS ((ADC_Common_TypeDef *) ADC1_COMMON_BASE_NS) #define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) #define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) #define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) @@ -1766,6 +1772,7 @@ typedef struct #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) #if defined (CPU_IN_SECURE_STATE) +#define ADC1_COMMON_S ((ADC_Common_TypeDef *) ADC1_COMMON_BASE_S) #define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) #define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) #define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) @@ -1853,6 +1860,8 @@ typedef struct #define SRAM2_BASE SRAM2_BASE_S /*!< Instance aliases and base addresses for Secure peripherals */ +#define ADC1_COMMON ADC1_COMMON_S +#define ADC1_COMMON_BASE ADC1_COMMON_BASE_S #define ADC1 ADC1_S #define ADC1_BASE ADC1_BASE_S #define ADF1 ADF1_S @@ -2020,6 +2029,8 @@ typedef struct #define SRAM2_BASE SRAM2_BASE_NS /*!< Instance aliases and base addresses for Secure peripherals */ +#define ADC1_COMMON ADC1_COMMON_NS +#define ADC1_COMMON_BASE ADC1_COMMON_BASE_NS #define ADC1 ADC1_NS #define ADC1_BASE ADC1_BASE_NS #define ADF1 ADF1_NS @@ -6773,10 +6784,10 @@ typedef struct /****************** Bits definition for FLASH_WRP1BR register ***************/ #define FLASH_WRP1BR_STRT_Pos (0UL) -#define FLASH_WRP1BR_STRT_Msk (0x7FUL << FLASH_WRP1BR_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP1BR_STRT_Msk (0x1FUL << FLASH_WRP1BR_STRT_Pos) /*!< 0x0000001F */ #define FLASH_WRP1BR_STRT FLASH_WRP1BR_STRT_Msk /*!< Bank 1 WRP second area B start page */ #define FLASH_WRP1BR_END_Pos (16UL) -#define FLASH_WRP1BR_END_Msk (0x7FUL << FLASH_WRP1BR_END_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP1BR_END_Msk (0x1FUL << FLASH_WRP1BR_END_Pos) /*!< 0x001F0000 */ #define FLASH_WRP1BR_END FLASH_WRP1BR_END_Msk /*!< Bank 1 WRP second area B end page */ #define FLASH_WRP1BR_UNLOCK_Pos (31UL) #define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ @@ -6784,15 +6795,15 @@ typedef struct /***************** Bits definition for FLASH_SECWM2R1 register **************/ #define FLASH_SECWM2R1_SECWM2_STRT_Pos (0UL) -#define FLASH_SECWM2R1_SECWM2_STRT_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_SECWM2R1_SECWM2_STRT_Msk (0x1FUL << FLASH_SECWM2R1_SECWM2_STRT_Pos) /*!< 0x0000001F */ #define FLASH_SECWM2R1_SECWM2_STRT FLASH_SECWM2R1_SECWM2_STRT_Msk /*!< Start page of second secure area */ #define FLASH_SECWM2R1_SECWM2_END_Pos (16UL) -#define FLASH_SECWM2R1_SECWM2_END_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_END_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWM2R1_SECWM2_END_Msk (0x1FUL << FLASH_SECWM2R1_SECWM2_END_Pos) /*!< 0x001F0000 */ #define FLASH_SECWM2R1_SECWM2_END FLASH_SECWM2R1_SECWM2_END_Msk /*!< End page of second secure area */ /***************** Bits definition for FLASH_SECWM2R2 register **************/ #define FLASH_SECWM2R2_HDP2_END_Pos (16UL) -#define FLASH_SECWM2R2_HDP2_END_Msk (0x7FUL << FLASH_SECWM2R2_HDP2_END_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWM2R2_HDP2_END_Msk (0x1FUL << FLASH_SECWM2R2_HDP2_END_Pos) /*!< 0x001F0000 */ #define FLASH_SECWM2R2_HDP2_END FLASH_SECWM2R2_HDP2_END_Msk /*!< End page of hide protection second area */ #define FLASH_SECWM2R2_HDP2EN_Pos (24UL) #define FLASH_SECWM2R2_HDP2EN_Msk (0xFFUL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0xFF000000 */ @@ -6800,10 +6811,10 @@ typedef struct /****************** Bits definition for FLASH_WRP2AR register ***************/ #define FLASH_WRP2AR_STRT_Pos (0UL) -#define FLASH_WRP2AR_STRT_Msk (0x7FUL << FLASH_WRP2AR_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP2AR_STRT_Msk (0x1FUL << FLASH_WRP2AR_STRT_Pos) /*!< 0x0000001F */ #define FLASH_WRP2AR_STRT FLASH_WRP2AR_STRT_Msk /*!< Bank 2 WPR first area A start page */ #define FLASH_WRP2AR_END_Pos (16UL) -#define FLASH_WRP2AR_END_Msk (0x7FUL << FLASH_WRP2AR_END_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP2AR_END_Msk (0x1FUL << FLASH_WRP2AR_END_Pos) /*!< 0x001F0000 */ #define FLASH_WRP2AR_END FLASH_WRP2AR_END_Msk /*!< Bank 2 WPR first area A end page */ #define FLASH_WRP2AR_UNLOCK_Pos (31UL) #define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ @@ -6811,10 +6822,10 @@ typedef struct /****************** Bits definition for FLASH_WRP2BR register ***************/ #define FLASH_WRP2BR_STRT_Pos (0UL) -#define FLASH_WRP2BR_STRT_Msk (0x7FUL << FLASH_WRP2BR_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP2BR_STRT_Msk (0x1FUL << FLASH_WRP2BR_STRT_Pos) /*!< 0x0000001F */ #define FLASH_WRP2BR_STRT FLASH_WRP2BR_STRT_Msk /*!< Bank 2 WPR second area B start page */ #define FLASH_WRP2BR_END_Pos (16UL) -#define FLASH_WRP2BR_END_Msk (0x7FUL << FLASH_WRP2BR_END_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP2BR_END_Msk (0x1FUL << FLASH_WRP2BR_END_Pos) /*!< 0x001F0000 */ #define FLASH_WRP2BR_END FLASH_WRP2BR_END_Msk /*!< Bank 2 WPR second area B end page */ #define FLASH_WRP2BR_UNLOCK_Pos (31UL) #define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ @@ -6918,299 +6929,6 @@ typedef struct #define FLASH_SECBB1R1_SEC31_Msk (0x1UL << FLASH_SECBB1R1_SEC31_Pos) /*!< 0x80000000 */ #define FLASH_SECBB1R1_SEC31 FLASH_SECBB1R1_SEC31_Msk /*!< Page 31 in bank 1 block-based secure */ -/******************* Bit definition for FLASH_SECBB1R2 register ******************/ -#define FLASH_SECBB1R2_SEC0_Pos (0UL) -#define FLASH_SECBB1R2_SEC0_Msk (0x1UL << FLASH_SECBB1R2_SEC0_Pos) /*!< 0x00000001 */ -#define FLASH_SECBB1R2_SEC0 FLASH_SECBB1R2_SEC0_Msk /*!< Page 32 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC1_Pos (1UL) -#define FLASH_SECBB1R2_SEC1_Msk (0x1UL << FLASH_SECBB1R2_SEC1_Pos) /*!< 0x00000002 */ -#define FLASH_SECBB1R2_SEC1 FLASH_SECBB1R2_SEC1_Msk /*!< Page 33 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC2_Pos (2UL) -#define FLASH_SECBB1R2_SEC2_Msk (0x1UL << FLASH_SECBB1R2_SEC2_Pos) /*!< 0x00000004 */ -#define FLASH_SECBB1R2_SEC2 FLASH_SECBB1R2_SEC2_Msk /*!< Page 34 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC3_Pos (3UL) -#define FLASH_SECBB1R2_SEC3_Msk (0x1UL << FLASH_SECBB1R2_SEC3_Pos) /*!< 0x00000008 */ -#define FLASH_SECBB1R2_SEC3 FLASH_SECBB1R2_SEC3_Msk /*!< Page 35 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC4_Pos (4UL) -#define FLASH_SECBB1R2_SEC4_Msk (0x1UL << FLASH_SECBB1R2_SEC4_Pos) /*!< 0x00000010 */ -#define FLASH_SECBB1R2_SEC4 FLASH_SECBB1R2_SEC4_Msk /*!< Page 36 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC5_Pos (5UL) -#define FLASH_SECBB1R2_SEC5_Msk (0x1UL << FLASH_SECBB1R2_SEC5_Pos) /*!< 0x00000020 */ -#define FLASH_SECBB1R2_SEC5 FLASH_SECBB1R2_SEC5_Msk /*!< Page 37 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC6_Pos (6UL) -#define FLASH_SECBB1R2_SEC6_Msk (0x1UL << FLASH_SECBB1R2_SEC6_Pos) /*!< 0x00000040 */ -#define FLASH_SECBB1R2_SEC6 FLASH_SECBB1R2_SEC6_Msk /*!< Page 38 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC7_Pos (7UL) -#define FLASH_SECBB1R2_SEC7_Msk (0x1UL << FLASH_SECBB1R2_SEC7_Pos) /*!< 0x00000080 */ -#define FLASH_SECBB1R2_SEC7 FLASH_SECBB1R2_SEC7_Msk /*!< Page 39 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC8_Pos (8UL) -#define FLASH_SECBB1R2_SEC8_Msk (0x1UL << FLASH_SECBB1R2_SEC8_Pos) /*!< 0x00000100 */ -#define FLASH_SECBB1R2_SEC8 FLASH_SECBB1R2_SEC8_Msk /*!< Page 40 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC9_Pos (9UL) -#define FLASH_SECBB1R2_SEC9_Msk (0x1UL << FLASH_SECBB1R2_SEC9_Pos) /*!< 0x00000200 */ -#define FLASH_SECBB1R2_SEC9 FLASH_SECBB1R2_SEC9_Msk /*!< Page 41 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC10_Pos (10UL) -#define FLASH_SECBB1R2_SEC10_Msk (0x1UL << FLASH_SECBB1R2_SEC10_Pos) /*!< 0x00000400 */ -#define FLASH_SECBB1R2_SEC10 FLASH_SECBB1R2_SEC10_Msk /*!< Page 42 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC11_Pos (11UL) -#define FLASH_SECBB1R2_SEC11_Msk (0x1UL << FLASH_SECBB1R2_SEC11_Pos) /*!< 0x00000800 */ -#define FLASH_SECBB1R2_SEC11 FLASH_SECBB1R2_SEC11_Msk /*!< Page 43 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC12_Pos (12UL) -#define FLASH_SECBB1R2_SEC12_Msk (0x1UL << FLASH_SECBB1R2_SEC12_Pos) /*!< 0x00001000 */ -#define FLASH_SECBB1R2_SEC12 FLASH_SECBB1R2_SEC12_Msk /*!< Page 44 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC13_Pos (13UL) -#define FLASH_SECBB1R2_SEC13_Msk (0x1UL << FLASH_SECBB1R2_SEC13_Pos) /*!< 0x00002000 */ -#define FLASH_SECBB1R2_SEC13 FLASH_SECBB1R2_SEC13_Msk /*!< Page 45 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC14_Pos (14UL) -#define FLASH_SECBB1R2_SEC14_Msk (0x1UL << FLASH_SECBB1R2_SEC14_Pos) /*!< 0x00004000 */ -#define FLASH_SECBB1R2_SEC14 FLASH_SECBB1R2_SEC14_Msk /*!< Page 46 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC15_Pos (15UL) -#define FLASH_SECBB1R2_SEC15_Msk (0x1UL << FLASH_SECBB1R2_SEC15_Pos) /*!< 0x00008000 */ -#define FLASH_SECBB1R2_SEC15 FLASH_SECBB1R2_SEC15_Msk /*!< Page 47 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC16_Pos (16UL) -#define FLASH_SECBB1R2_SEC16_Msk (0x1UL << FLASH_SECBB1R2_SEC16_Pos) /*!< 0x00010000 */ -#define FLASH_SECBB1R2_SEC16 FLASH_SECBB1R2_SEC16_Msk /*!< Page 48 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC17_Pos (17UL) -#define FLASH_SECBB1R2_SEC17_Msk (0x1UL << FLASH_SECBB1R2_SEC17_Pos) /*!< 0x00020000 */ -#define FLASH_SECBB1R2_SEC17 FLASH_SECBB1R2_SEC17_Msk /*!< Page 49 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC18_Pos (18UL) -#define FLASH_SECBB1R2_SEC18_Msk (0x1UL << FLASH_SECBB1R2_SEC18_Pos) /*!< 0x00040000 */ -#define FLASH_SECBB1R2_SEC18 FLASH_SECBB1R2_SEC18_Msk /*!< Page 50 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC19_Pos (19UL) -#define FLASH_SECBB1R2_SEC19_Msk (0x1UL << FLASH_SECBB1R2_SEC19_Pos) /*!< 0x00080000 */ -#define FLASH_SECBB1R2_SEC19 FLASH_SECBB1R2_SEC19_Msk /*!< Page 51 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC20_Pos (20UL) -#define FLASH_SECBB1R2_SEC20_Msk (0x1UL << FLASH_SECBB1R2_SEC20_Pos) /*!< 0x00100000 */ -#define FLASH_SECBB1R2_SEC20 FLASH_SECBB1R2_SEC20_Msk /*!< Page 52 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC21_Pos (21UL) -#define FLASH_SECBB1R2_SEC21_Msk (0x1UL << FLASH_SECBB1R2_SEC21_Pos) /*!< 0x00200000 */ -#define FLASH_SECBB1R2_SEC21 FLASH_SECBB1R2_SEC21_Msk /*!< Page 53 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC22_Pos (22UL) -#define FLASH_SECBB1R2_SEC22_Msk (0x1UL << FLASH_SECBB1R2_SEC22_Pos) /*!< 0x00400000 */ -#define FLASH_SECBB1R2_SEC22 FLASH_SECBB1R2_SEC22_Msk /*!< Page 54 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC23_Pos (23UL) -#define FLASH_SECBB1R2_SEC23_Msk (0x1UL << FLASH_SECBB1R2_SEC23_Pos) /*!< 0x00800000 */ -#define FLASH_SECBB1R2_SEC23 FLASH_SECBB1R2_SEC23_Msk /*!< Page 55 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC24_Pos (24UL) -#define FLASH_SECBB1R2_SEC24_Msk (0x1UL << FLASH_SECBB1R2_SEC24_Pos) /*!< 0x01000000 */ -#define FLASH_SECBB1R2_SEC24 FLASH_SECBB1R2_SEC24_Msk /*!< Page 56 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC25_Pos (25UL) -#define FLASH_SECBB1R2_SEC25_Msk (0x1UL << FLASH_SECBB1R2_SEC25_Pos) /*!< 0x02000000 */ -#define FLASH_SECBB1R2_SEC25 FLASH_SECBB1R2_SEC25_Msk /*!< Page 57 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC26_Pos (26UL) -#define FLASH_SECBB1R2_SEC26_Msk (0x1UL << FLASH_SECBB1R2_SEC26_Pos) /*!< 0x04000000 */ -#define FLASH_SECBB1R2_SEC26 FLASH_SECBB1R2_SEC26_Msk /*!< Page 58 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC27_Pos (27UL) -#define FLASH_SECBB1R2_SEC27_Msk (0x1UL << FLASH_SECBB1R2_SEC27_Pos) /*!< 0x08000000 */ -#define FLASH_SECBB1R2_SEC27 FLASH_SECBB1R2_SEC27_Msk /*!< Page 59 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC28_Pos (28UL) -#define FLASH_SECBB1R2_SEC28_Msk (0x1UL << FLASH_SECBB1R2_SEC28_Pos) /*!< 0x10000000 */ -#define FLASH_SECBB1R2_SEC28 FLASH_SECBB1R2_SEC28_Msk /*!< Page 60 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC29_Pos (29UL) -#define FLASH_SECBB1R2_SEC29_Msk (0x1UL << FLASH_SECBB1R2_SEC29_Pos) /*!< 0x20000000 */ -#define FLASH_SECBB1R2_SEC29 FLASH_SECBB1R2_SEC29_Msk /*!< Page 61 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC30_Pos (30UL) -#define FLASH_SECBB1R2_SEC30_Msk (0x1UL << FLASH_SECBB1R2_SEC30_Pos) /*!< 0x40000000 */ -#define FLASH_SECBB1R2_SEC30 FLASH_SECBB1R2_SEC30_Msk /*!< Page 62 in bank 1 block-based secure */ -#define FLASH_SECBB1R2_SEC31_Pos (31UL) -#define FLASH_SECBB1R2_SEC31_Msk (0x1UL << FLASH_SECBB1R2_SEC31_Pos) /*!< 0x80000000 */ -#define FLASH_SECBB1R2_SEC31 FLASH_SECBB1R2_SEC31_Msk /*!< Page 63 in bank 1 block-based secure */ - -/******************* Bit definition for FLASH_SECBB1R3 register ******************/ -#define FLASH_SECBB1R3_SEC0_Pos (0UL) -#define FLASH_SECBB1R3_SEC0_Msk (0x1UL << FLASH_SECBB1R3_SEC0_Pos) /*!< 0x00000001 */ -#define FLASH_SECBB1R3_SEC0 FLASH_SECBB1R3_SEC0_Msk /*!< Page 64 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC1_Pos (1UL) -#define FLASH_SECBB1R3_SEC1_Msk (0x1UL << FLASH_SECBB1R3_SEC1_Pos) /*!< 0x00000002 */ -#define FLASH_SECBB1R3_SEC1 FLASH_SECBB1R3_SEC1_Msk /*!< Page 65 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC2_Pos (2UL) -#define FLASH_SECBB1R3_SEC2_Msk (0x1UL << FLASH_SECBB1R3_SEC2_Pos) /*!< 0x00000004 */ -#define FLASH_SECBB1R3_SEC2 FLASH_SECBB1R3_SEC2_Msk /*!< Page 66 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC3_Pos (3UL) -#define FLASH_SECBB1R3_SEC3_Msk (0x1UL << FLASH_SECBB1R3_SEC3_Pos) /*!< 0x00000008 */ -#define FLASH_SECBB1R3_SEC3 FLASH_SECBB1R3_SEC3_Msk /*!< Page 67 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC4_Pos (4UL) -#define FLASH_SECBB1R3_SEC4_Msk (0x1UL << FLASH_SECBB1R3_SEC4_Pos) /*!< 0x00000010 */ -#define FLASH_SECBB1R3_SEC4 FLASH_SECBB1R3_SEC4_Msk /*!< Page 68 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC5_Pos (5UL) -#define FLASH_SECBB1R3_SEC5_Msk (0x1UL << FLASH_SECBB1R3_SEC5_Pos) /*!< 0x00000020 */ -#define FLASH_SECBB1R3_SEC5 FLASH_SECBB1R3_SEC5_Msk /*!< Page 69 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC6_Pos (6UL) -#define FLASH_SECBB1R3_SEC6_Msk (0x1UL << FLASH_SECBB1R3_SEC6_Pos) /*!< 0x00000040 */ -#define FLASH_SECBB1R3_SEC6 FLASH_SECBB1R3_SEC6_Msk /*!< Page 70 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC7_Pos (7UL) -#define FLASH_SECBB1R3_SEC7_Msk (0x1UL << FLASH_SECBB1R3_SEC7_Pos) /*!< 0x00000080 */ -#define FLASH_SECBB1R3_SEC7 FLASH_SECBB1R3_SEC7_Msk /*!< Page 71 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC8_Pos (8UL) -#define FLASH_SECBB1R3_SEC8_Msk (0x1UL << FLASH_SECBB1R3_SEC8_Pos) /*!< 0x00000100 */ -#define FLASH_SECBB1R3_SEC8 FLASH_SECBB1R3_SEC8_Msk /*!< Page 72 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC9_Pos (9UL) -#define FLASH_SECBB1R3_SEC9_Msk (0x1UL << FLASH_SECBB1R3_SEC9_Pos) /*!< 0x00000200 */ -#define FLASH_SECBB1R3_SEC9 FLASH_SECBB1R3_SEC9_Msk /*!< Page 73 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC10_Pos (10UL) -#define FLASH_SECBB1R3_SEC10_Msk (0x1UL << FLASH_SECBB1R3_SEC10_Pos) /*!< 0x00000400 */ -#define FLASH_SECBB1R3_SEC10 FLASH_SECBB1R3_SEC10_Msk /*!< Page 74 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC11_Pos (11UL) -#define FLASH_SECBB1R3_SEC11_Msk (0x1UL << FLASH_SECBB1R3_SEC11_Pos) /*!< 0x00000800 */ -#define FLASH_SECBB1R3_SEC11 FLASH_SECBB1R3_SEC11_Msk /*!< Page 75 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC12_Pos (12UL) -#define FLASH_SECBB1R3_SEC12_Msk (0x1UL << FLASH_SECBB1R3_SEC12_Pos) /*!< 0x00001000 */ -#define FLASH_SECBB1R3_SEC12 FLASH_SECBB1R3_SEC12_Msk /*!< Page 76 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC13_Pos (13UL) -#define FLASH_SECBB1R3_SEC13_Msk (0x1UL << FLASH_SECBB1R3_SEC13_Pos) /*!< 0x00002000 */ -#define FLASH_SECBB1R3_SEC13 FLASH_SECBB1R3_SEC13_Msk /*!< Page 77 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC14_Pos (14UL) -#define FLASH_SECBB1R3_SEC14_Msk (0x1UL << FLASH_SECBB1R3_SEC14_Pos) /*!< 0x00004000 */ -#define FLASH_SECBB1R3_SEC14 FLASH_SECBB1R3_SEC14_Msk /*!< Page 78 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC15_Pos (15UL) -#define FLASH_SECBB1R3_SEC15_Msk (0x1UL << FLASH_SECBB1R3_SEC15_Pos) /*!< 0x00008000 */ -#define FLASH_SECBB1R3_SEC15 FLASH_SECBB1R3_SEC15_Msk /*!< Page 79 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC16_Pos (16UL) -#define FLASH_SECBB1R3_SEC16_Msk (0x1UL << FLASH_SECBB1R3_SEC16_Pos) /*!< 0x00010000 */ -#define FLASH_SECBB1R3_SEC16 FLASH_SECBB1R3_SEC16_Msk /*!< Page 80 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC17_Pos (17UL) -#define FLASH_SECBB1R3_SEC17_Msk (0x1UL << FLASH_SECBB1R3_SEC17_Pos) /*!< 0x00020000 */ -#define FLASH_SECBB1R3_SEC17 FLASH_SECBB1R3_SEC17_Msk /*!< Page 81 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC18_Pos (18UL) -#define FLASH_SECBB1R3_SEC18_Msk (0x1UL << FLASH_SECBB1R3_SEC18_Pos) /*!< 0x00040000 */ -#define FLASH_SECBB1R3_SEC18 FLASH_SECBB1R3_SEC18_Msk /*!< Page 82 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC19_Pos (19UL) -#define FLASH_SECBB1R3_SEC19_Msk (0x1UL << FLASH_SECBB1R3_SEC19_Pos) /*!< 0x00080000 */ -#define FLASH_SECBB1R3_SEC19 FLASH_SECBB1R3_SEC19_Msk /*!< Page 83 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC20_Pos (20UL) -#define FLASH_SECBB1R3_SEC20_Msk (0x1UL << FLASH_SECBB1R3_SEC20_Pos) /*!< 0x00100000 */ -#define FLASH_SECBB1R3_SEC20 FLASH_SECBB1R3_SEC20_Msk /*!< Page 84 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC21_Pos (21UL) -#define FLASH_SECBB1R3_SEC21_Msk (0x1UL << FLASH_SECBB1R3_SEC21_Pos) /*!< 0x00200000 */ -#define FLASH_SECBB1R3_SEC21 FLASH_SECBB1R3_SEC21_Msk /*!< Page 85 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC22_Pos (22UL) -#define FLASH_SECBB1R3_SEC22_Msk (0x1UL << FLASH_SECBB1R3_SEC22_Pos) /*!< 0x00400000 */ -#define FLASH_SECBB1R3_SEC22 FLASH_SECBB1R3_SEC22_Msk /*!< Page 86 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC23_Pos (23UL) -#define FLASH_SECBB1R3_SEC23_Msk (0x1UL << FLASH_SECBB1R3_SEC23_Pos) /*!< 0x00800000 */ -#define FLASH_SECBB1R3_SEC23 FLASH_SECBB1R3_SEC23_Msk /*!< Page 87 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC24_Pos (24UL) -#define FLASH_SECBB1R3_SEC24_Msk (0x1UL << FLASH_SECBB1R3_SEC24_Pos) /*!< 0x01000000 */ -#define FLASH_SECBB1R3_SEC24 FLASH_SECBB1R3_SEC24_Msk /*!< Page 88 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC25_Pos (25UL) -#define FLASH_SECBB1R3_SEC25_Msk (0x1UL << FLASH_SECBB1R3_SEC25_Pos) /*!< 0x02000000 */ -#define FLASH_SECBB1R3_SEC25 FLASH_SECBB1R3_SEC25_Msk /*!< Page 89 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC26_Pos (26UL) -#define FLASH_SECBB1R3_SEC26_Msk (0x1UL << FLASH_SECBB1R3_SEC26_Pos) /*!< 0x04000000 */ -#define FLASH_SECBB1R3_SEC26 FLASH_SECBB1R3_SEC26_Msk /*!< Page 90 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC27_Pos (27UL) -#define FLASH_SECBB1R3_SEC27_Msk (0x1UL << FLASH_SECBB1R3_SEC27_Pos) /*!< 0x08000000 */ -#define FLASH_SECBB1R3_SEC27 FLASH_SECBB1R3_SEC27_Msk /*!< Page 91 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC28_Pos (28UL) -#define FLASH_SECBB1R3_SEC28_Msk (0x1UL << FLASH_SECBB1R3_SEC28_Pos) /*!< 0x10000000 */ -#define FLASH_SECBB1R3_SEC28 FLASH_SECBB1R3_SEC28_Msk /*!< Page 92 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC29_Pos (29UL) -#define FLASH_SECBB1R3_SEC29_Msk (0x1UL << FLASH_SECBB1R3_SEC29_Pos) /*!< 0x20000000 */ -#define FLASH_SECBB1R3_SEC29 FLASH_SECBB1R3_SEC29_Msk /*!< Page 93 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC30_Pos (30UL) -#define FLASH_SECBB1R3_SEC30_Msk (0x1UL << FLASH_SECBB1R3_SEC30_Pos) /*!< 0x40000000 */ -#define FLASH_SECBB1R3_SEC30 FLASH_SECBB1R3_SEC30_Msk /*!< Page 94 in bank 1 block-based secure */ -#define FLASH_SECBB1R3_SEC31_Pos (31UL) -#define FLASH_SECBB1R3_SEC31_Msk (0x1UL << FLASH_SECBB1R3_SEC31_Pos) /*!< 0x80000000 */ -#define FLASH_SECBB1R3_SEC31 FLASH_SECBB1R3_SEC31_Msk /*!< Page 95 in bank 1 block-based secure */ - -/******************* Bit definition for FLASH_SECBB1R4 register ******************/ -#define FLASH_SECBB1R4_SEC0_Pos (0UL) -#define FLASH_SECBB1R4_SEC0_Msk (0x1UL << FLASH_SECBB1R4_SEC0_Pos) /*!< 0x00000001 */ -#define FLASH_SECBB1R4_SEC0 FLASH_SECBB1R4_SEC0_Msk /*!< Page 96 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC1_Pos (1UL) -#define FLASH_SECBB1R4_SEC1_Msk (0x1UL << FLASH_SECBB1R4_SEC1_Pos) /*!< 0x00000002 */ -#define FLASH_SECBB1R4_SEC1 FLASH_SECBB1R4_SEC1_Msk /*!< Page 97 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC2_Pos (2UL) -#define FLASH_SECBB1R4_SEC2_Msk (0x1UL << FLASH_SECBB1R4_SEC2_Pos) /*!< 0x00000004 */ -#define FLASH_SECBB1R4_SEC2 FLASH_SECBB1R4_SEC2_Msk /*!< Page 98 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC3_Pos (3UL) -#define FLASH_SECBB1R4_SEC3_Msk (0x1UL << FLASH_SECBB1R4_SEC3_Pos) /*!< 0x00000008 */ -#define FLASH_SECBB1R4_SEC3 FLASH_SECBB1R4_SEC3_Msk /*!< Page 99 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC4_Pos (4UL) -#define FLASH_SECBB1R4_SEC4_Msk (0x1UL << FLASH_SECBB1R4_SEC4_Pos) /*!< 0x00000010 */ -#define FLASH_SECBB1R4_SEC4 FLASH_SECBB1R4_SEC4_Msk /*!< Page 100 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC5_Pos (5UL) -#define FLASH_SECBB1R4_SEC5_Msk (0x1UL << FLASH_SECBB1R4_SEC5_Pos) /*!< 0x00000020 */ -#define FLASH_SECBB1R4_SEC5 FLASH_SECBB1R4_SEC5_Msk /*!< Page 101 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC6_Pos (6UL) -#define FLASH_SECBB1R4_SEC6_Msk (0x1UL << FLASH_SECBB1R4_SEC6_Pos) /*!< 0x00000040 */ -#define FLASH_SECBB1R4_SEC6 FLASH_SECBB1R4_SEC6_Msk /*!< Page 102 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC7_Pos (7UL) -#define FLASH_SECBB1R4_SEC7_Msk (0x1UL << FLASH_SECBB1R4_SEC7_Pos) /*!< 0x00000080 */ -#define FLASH_SECBB1R4_SEC7 FLASH_SECBB1R4_SEC7_Msk /*!< Page 103 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC8_Pos (8UL) -#define FLASH_SECBB1R4_SEC8_Msk (0x1UL << FLASH_SECBB1R4_SEC8_Pos) /*!< 0x00000100 */ -#define FLASH_SECBB1R4_SEC8 FLASH_SECBB1R4_SEC8_Msk /*!< Page 104 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC9_Pos (9UL) -#define FLASH_SECBB1R4_SEC9_Msk (0x1UL << FLASH_SECBB1R4_SEC9_Pos) /*!< 0x00000200 */ -#define FLASH_SECBB1R4_SEC9 FLASH_SECBB1R4_SEC9_Msk /*!< Page 105 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC10_Pos (10UL) -#define FLASH_SECBB1R4_SEC10_Msk (0x1UL << FLASH_SECBB1R4_SEC10_Pos) /*!< 0x00000400 */ -#define FLASH_SECBB1R4_SEC10 FLASH_SECBB1R4_SEC10_Msk /*!< Page 106 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC11_Pos (11UL) -#define FLASH_SECBB1R4_SEC11_Msk (0x1UL << FLASH_SECBB1R4_SEC11_Pos) /*!< 0x00000800 */ -#define FLASH_SECBB1R4_SEC11 FLASH_SECBB1R4_SEC11_Msk /*!< Page 107 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC12_Pos (12UL) -#define FLASH_SECBB1R4_SEC12_Msk (0x1UL << FLASH_SECBB1R4_SEC12_Pos) /*!< 0x00001000 */ -#define FLASH_SECBB1R4_SEC12 FLASH_SECBB1R4_SEC12_Msk /*!< Page 108 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC13_Pos (13UL) -#define FLASH_SECBB1R4_SEC13_Msk (0x1UL << FLASH_SECBB1R4_SEC13_Pos) /*!< 0x00002000 */ -#define FLASH_SECBB1R4_SEC13 FLASH_SECBB1R4_SEC13_Msk /*!< Page 109 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC14_Pos (14UL) -#define FLASH_SECBB1R4_SEC14_Msk (0x1UL << FLASH_SECBB1R4_SEC14_Pos) /*!< 0x00004000 */ -#define FLASH_SECBB1R4_SEC14 FLASH_SECBB1R4_SEC14_Msk /*!< Page 110 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC15_Pos (15UL) -#define FLASH_SECBB1R4_SEC15_Msk (0x1UL << FLASH_SECBB1R4_SEC15_Pos) /*!< 0x00008000 */ -#define FLASH_SECBB1R4_SEC15 FLASH_SECBB1R4_SEC15_Msk /*!< Page 111 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC16_Pos (16UL) -#define FLASH_SECBB1R4_SEC16_Msk (0x1UL << FLASH_SECBB1R4_SEC16_Pos) /*!< 0x00010000 */ -#define FLASH_SECBB1R4_SEC16 FLASH_SECBB1R4_SEC16_Msk /*!< Page 112 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC17_Pos (17UL) -#define FLASH_SECBB1R4_SEC17_Msk (0x1UL << FLASH_SECBB1R4_SEC17_Pos) /*!< 0x00020000 */ -#define FLASH_SECBB1R4_SEC17 FLASH_SECBB1R4_SEC17_Msk /*!< Page 113 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC18_Pos (18UL) -#define FLASH_SECBB1R4_SEC18_Msk (0x1UL << FLASH_SECBB1R4_SEC18_Pos) /*!< 0x00040000 */ -#define FLASH_SECBB1R4_SEC18 FLASH_SECBB1R4_SEC18_Msk /*!< Page 114 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC19_Pos (19UL) -#define FLASH_SECBB1R4_SEC19_Msk (0x1UL << FLASH_SECBB1R4_SEC19_Pos) /*!< 0x00080000 */ -#define FLASH_SECBB1R4_SEC19 FLASH_SECBB1R4_SEC19_Msk /*!< Page 115 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC20_Pos (20UL) -#define FLASH_SECBB1R4_SEC20_Msk (0x1UL << FLASH_SECBB1R4_SEC20_Pos) /*!< 0x00100000 */ -#define FLASH_SECBB1R4_SEC20 FLASH_SECBB1R4_SEC20_Msk /*!< Page 116 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC21_Pos (21UL) -#define FLASH_SECBB1R4_SEC21_Msk (0x1UL << FLASH_SECBB1R4_SEC21_Pos) /*!< 0x00200000 */ -#define FLASH_SECBB1R4_SEC21 FLASH_SECBB1R4_SEC21_Msk /*!< Page 117 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC22_Pos (22UL) -#define FLASH_SECBB1R4_SEC22_Msk (0x1UL << FLASH_SECBB1R4_SEC22_Pos) /*!< 0x00400000 */ -#define FLASH_SECBB1R4_SEC22 FLASH_SECBB1R4_SEC22_Msk /*!< Page 118 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC23_Pos (23UL) -#define FLASH_SECBB1R4_SEC23_Msk (0x1UL << FLASH_SECBB1R4_SEC23_Pos) /*!< 0x00800000 */ -#define FLASH_SECBB1R4_SEC23 FLASH_SECBB1R4_SEC23_Msk /*!< Page 119 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC24_Pos (24UL) -#define FLASH_SECBB1R4_SEC24_Msk (0x1UL << FLASH_SECBB1R4_SEC24_Pos) /*!< 0x01000000 */ -#define FLASH_SECBB1R4_SEC24 FLASH_SECBB1R4_SEC24_Msk /*!< Page 120 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC25_Pos (25UL) -#define FLASH_SECBB1R4_SEC25_Msk (0x1UL << FLASH_SECBB1R4_SEC25_Pos) /*!< 0x02000000 */ -#define FLASH_SECBB1R4_SEC25 FLASH_SECBB1R4_SEC25_Msk /*!< Page 121 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC26_Pos (26UL) -#define FLASH_SECBB1R4_SEC26_Msk (0x1UL << FLASH_SECBB1R4_SEC26_Pos) /*!< 0x04000000 */ -#define FLASH_SECBB1R4_SEC26 FLASH_SECBB1R4_SEC26_Msk /*!< Page 122 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC27_Pos (27UL) -#define FLASH_SECBB1R4_SEC27_Msk (0x1UL << FLASH_SECBB1R4_SEC27_Pos) /*!< 0x08000000 */ -#define FLASH_SECBB1R4_SEC27 FLASH_SECBB1R4_SEC27_Msk /*!< Page 123 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC28_Pos (28UL) -#define FLASH_SECBB1R4_SEC28_Msk (0x1UL << FLASH_SECBB1R4_SEC28_Pos) /*!< 0x10000000 */ -#define FLASH_SECBB1R4_SEC28 FLASH_SECBB1R4_SEC28_Msk /*!< Page 124 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC29_Pos (29UL) -#define FLASH_SECBB1R4_SEC29_Msk (0x1UL << FLASH_SECBB1R4_SEC29_Pos) /*!< 0x20000000 */ -#define FLASH_SECBB1R4_SEC29 FLASH_SECBB1R4_SEC29_Msk /*!< Page 125 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC30_Pos (30UL) -#define FLASH_SECBB1R4_SEC30_Msk (0x1UL << FLASH_SECBB1R4_SEC30_Pos) /*!< 0x40000000 */ -#define FLASH_SECBB1R4_SEC30 FLASH_SECBB1R4_SEC30_Msk /*!< Page 126 in bank 1 block-based secure */ -#define FLASH_SECBB1R4_SEC31_Pos (31UL) -#define FLASH_SECBB1R4_SEC31_Msk (0x1UL << FLASH_SECBB1R4_SEC31_Pos) /*!< 0x80000000 */ -#define FLASH_SECBB1R4_SEC31 FLASH_SECBB1R4_SEC31_Msk /*!< Page 127 in bank 1 block-based secure */ /******************* Bit definition for FLASH_SECBB2R1 register ******************/ #define FLASH_SECBB2R1_SEC0_Pos (0UL) @@ -7310,299 +7028,6 @@ typedef struct #define FLASH_SECBB2R1_SEC31_Msk (0x1UL << FLASH_SECBB2R1_SEC31_Pos) /*!< 0x80000000 */ #define FLASH_SECBB2R1_SEC31 FLASH_SECBB2R1_SEC31_Msk /*!< Page 31 in bank 2 block-based secure */ -/******************* Bit definition for FLASH_SECBB2R2 register ******************/ -#define FLASH_SECBB2R2_SEC0_Pos (0UL) -#define FLASH_SECBB2R2_SEC0_Msk (0x1UL << FLASH_SECBB2R2_SEC0_Pos) /*!< 0x00000001 */ -#define FLASH_SECBB2R2_SEC0 FLASH_SECBB2R2_SEC0_Msk /*!< Page 32 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC1_Pos (1UL) -#define FLASH_SECBB2R2_SEC1_Msk (0x1UL << FLASH_SECBB2R2_SEC1_Pos) /*!< 0x00000002 */ -#define FLASH_SECBB2R2_SEC1 FLASH_SECBB2R2_SEC1_Msk /*!< Page 33 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC2_Pos (2UL) -#define FLASH_SECBB2R2_SEC2_Msk (0x1UL << FLASH_SECBB2R2_SEC2_Pos) /*!< 0x00000004 */ -#define FLASH_SECBB2R2_SEC2 FLASH_SECBB2R2_SEC2_Msk /*!< Page 34 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC3_Pos (3UL) -#define FLASH_SECBB2R2_SEC3_Msk (0x1UL << FLASH_SECBB2R2_SEC3_Pos) /*!< 0x00000008 */ -#define FLASH_SECBB2R2_SEC3 FLASH_SECBB2R2_SEC3_Msk /*!< Page 35 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC4_Pos (4UL) -#define FLASH_SECBB2R2_SEC4_Msk (0x1UL << FLASH_SECBB2R2_SEC4_Pos) /*!< 0x00000010 */ -#define FLASH_SECBB2R2_SEC4 FLASH_SECBB2R2_SEC4_Msk /*!< Page 36 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC5_Pos (5UL) -#define FLASH_SECBB2R2_SEC5_Msk (0x1UL << FLASH_SECBB2R2_SEC5_Pos) /*!< 0x00000020 */ -#define FLASH_SECBB2R2_SEC5 FLASH_SECBB2R2_SEC5_Msk /*!< Page 37 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC6_Pos (6UL) -#define FLASH_SECBB2R2_SEC6_Msk (0x1UL << FLASH_SECBB2R2_SEC6_Pos) /*!< 0x00000040 */ -#define FLASH_SECBB2R2_SEC6 FLASH_SECBB2R2_SEC6_Msk /*!< Page 38 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC7_Pos (7UL) -#define FLASH_SECBB2R2_SEC7_Msk (0x1UL << FLASH_SECBB2R2_SEC7_Pos) /*!< 0x00000080 */ -#define FLASH_SECBB2R2_SEC7 FLASH_SECBB2R2_SEC7_Msk /*!< Page 39 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC8_Pos (8UL) -#define FLASH_SECBB2R2_SEC8_Msk (0x1UL << FLASH_SECBB2R2_SEC8_Pos) /*!< 0x00000100 */ -#define FLASH_SECBB2R2_SEC8 FLASH_SECBB2R2_SEC8_Msk /*!< Page 40 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC9_Pos (9UL) -#define FLASH_SECBB2R2_SEC9_Msk (0x1UL << FLASH_SECBB2R2_SEC9_Pos) /*!< 0x00000200 */ -#define FLASH_SECBB2R2_SEC9 FLASH_SECBB2R2_SEC9_Msk /*!< Page 41 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC10_Pos (10UL) -#define FLASH_SECBB2R2_SEC10_Msk (0x1UL << FLASH_SECBB2R2_SEC10_Pos) /*!< 0x00000400 */ -#define FLASH_SECBB2R2_SEC10 FLASH_SECBB2R2_SEC10_Msk /*!< Page 42 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC11_Pos (11UL) -#define FLASH_SECBB2R2_SEC11_Msk (0x1UL << FLASH_SECBB2R2_SEC11_Pos) /*!< 0x00000800 */ -#define FLASH_SECBB2R2_SEC11 FLASH_SECBB2R2_SEC11_Msk /*!< Page 43 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC12_Pos (12UL) -#define FLASH_SECBB2R2_SEC12_Msk (0x1UL << FLASH_SECBB2R2_SEC12_Pos) /*!< 0x00001000 */ -#define FLASH_SECBB2R2_SEC12 FLASH_SECBB2R2_SEC12_Msk /*!< Page 44 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC13_Pos (13UL) -#define FLASH_SECBB2R2_SEC13_Msk (0x1UL << FLASH_SECBB2R2_SEC13_Pos) /*!< 0x00002000 */ -#define FLASH_SECBB2R2_SEC13 FLASH_SECBB2R2_SEC13_Msk /*!< Page 45 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC14_Pos (14UL) -#define FLASH_SECBB2R2_SEC14_Msk (0x1UL << FLASH_SECBB2R2_SEC14_Pos) /*!< 0x00004000 */ -#define FLASH_SECBB2R2_SEC14 FLASH_SECBB2R2_SEC14_Msk /*!< Page 46 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC15_Pos (15UL) -#define FLASH_SECBB2R2_SEC15_Msk (0x1UL << FLASH_SECBB2R2_SEC15_Pos) /*!< 0x00008000 */ -#define FLASH_SECBB2R2_SEC15 FLASH_SECBB2R2_SEC15_Msk /*!< Page 47 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC16_Pos (16UL) -#define FLASH_SECBB2R2_SEC16_Msk (0x1UL << FLASH_SECBB2R2_SEC16_Pos) /*!< 0x00010000 */ -#define FLASH_SECBB2R2_SEC16 FLASH_SECBB2R2_SEC16_Msk /*!< Page 48 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC17_Pos (17UL) -#define FLASH_SECBB2R2_SEC17_Msk (0x1UL << FLASH_SECBB2R2_SEC17_Pos) /*!< 0x00020000 */ -#define FLASH_SECBB2R2_SEC17 FLASH_SECBB2R2_SEC17_Msk /*!< Page 49 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC18_Pos (18UL) -#define FLASH_SECBB2R2_SEC18_Msk (0x1UL << FLASH_SECBB2R2_SEC18_Pos) /*!< 0x00040000 */ -#define FLASH_SECBB2R2_SEC18 FLASH_SECBB2R2_SEC18_Msk /*!< Page 50 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC19_Pos (19UL) -#define FLASH_SECBB2R2_SEC19_Msk (0x1UL << FLASH_SECBB2R2_SEC19_Pos) /*!< 0x00080000 */ -#define FLASH_SECBB2R2_SEC19 FLASH_SECBB2R2_SEC19_Msk /*!< Page 51 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC20_Pos (20UL) -#define FLASH_SECBB2R2_SEC20_Msk (0x1UL << FLASH_SECBB2R2_SEC20_Pos) /*!< 0x00100000 */ -#define FLASH_SECBB2R2_SEC20 FLASH_SECBB2R2_SEC20_Msk /*!< Page 52 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC21_Pos (21UL) -#define FLASH_SECBB2R2_SEC21_Msk (0x1UL << FLASH_SECBB2R2_SEC21_Pos) /*!< 0x00200000 */ -#define FLASH_SECBB2R2_SEC21 FLASH_SECBB2R2_SEC21_Msk /*!< Page 53 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC22_Pos (22UL) -#define FLASH_SECBB2R2_SEC22_Msk (0x1UL << FLASH_SECBB2R2_SEC22_Pos) /*!< 0x00400000 */ -#define FLASH_SECBB2R2_SEC22 FLASH_SECBB2R2_SEC22_Msk /*!< Page 54 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC23_Pos (23UL) -#define FLASH_SECBB2R2_SEC23_Msk (0x1UL << FLASH_SECBB2R2_SEC23_Pos) /*!< 0x00800000 */ -#define FLASH_SECBB2R2_SEC23 FLASH_SECBB2R2_SEC23_Msk /*!< Page 55 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC24_Pos (24UL) -#define FLASH_SECBB2R2_SEC24_Msk (0x1UL << FLASH_SECBB2R2_SEC24_Pos) /*!< 0x01000000 */ -#define FLASH_SECBB2R2_SEC24 FLASH_SECBB2R2_SEC24_Msk /*!< Page 56 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC25_Pos (25UL) -#define FLASH_SECBB2R2_SEC25_Msk (0x1UL << FLASH_SECBB2R2_SEC25_Pos) /*!< 0x02000000 */ -#define FLASH_SECBB2R2_SEC25 FLASH_SECBB2R2_SEC25_Msk /*!< Page 57 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC26_Pos (26UL) -#define FLASH_SECBB2R2_SEC26_Msk (0x1UL << FLASH_SECBB2R2_SEC26_Pos) /*!< 0x04000000 */ -#define FLASH_SECBB2R2_SEC26 FLASH_SECBB2R2_SEC26_Msk /*!< Page 58 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC27_Pos (27UL) -#define FLASH_SECBB2R2_SEC27_Msk (0x1UL << FLASH_SECBB2R2_SEC27_Pos) /*!< 0x08000000 */ -#define FLASH_SECBB2R2_SEC27 FLASH_SECBB2R2_SEC27_Msk /*!< Page 59 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC28_Pos (28UL) -#define FLASH_SECBB2R2_SEC28_Msk (0x1UL << FLASH_SECBB2R2_SEC28_Pos) /*!< 0x10000000 */ -#define FLASH_SECBB2R2_SEC28 FLASH_SECBB2R2_SEC28_Msk /*!< Page 60 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC29_Pos (29UL) -#define FLASH_SECBB2R2_SEC29_Msk (0x1UL << FLASH_SECBB2R2_SEC29_Pos) /*!< 0x20000000 */ -#define FLASH_SECBB2R2_SEC29 FLASH_SECBB2R2_SEC29_Msk /*!< Page 61 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC30_Pos (30UL) -#define FLASH_SECBB2R2_SEC30_Msk (0x1UL << FLASH_SECBB2R2_SEC30_Pos) /*!< 0x40000000 */ -#define FLASH_SECBB2R2_SEC30 FLASH_SECBB2R2_SEC30_Msk /*!< Page 62 in bank 2 block-based secure */ -#define FLASH_SECBB2R2_SEC31_Pos (31UL) -#define FLASH_SECBB2R2_SEC31_Msk (0x1UL << FLASH_SECBB2R2_SEC31_Pos) /*!< 0x80000000 */ -#define FLASH_SECBB2R2_SEC31 FLASH_SECBB2R2_SEC31_Msk /*!< Page 63 in bank 2 block-based secure */ - -/******************* Bit definition for FLASH_SECBB2R3 register ******************/ -#define FLASH_SECBB2R3_SEC0_Pos (0UL) -#define FLASH_SECBB2R3_SEC0_Msk (0x1UL << FLASH_SECBB2R3_SEC0_Pos) /*!< 0x00000001 */ -#define FLASH_SECBB2R3_SEC0 FLASH_SECBB2R3_SEC0_Msk /*!< Page 64 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC1_Pos (1UL) -#define FLASH_SECBB2R3_SEC1_Msk (0x1UL << FLASH_SECBB2R3_SEC1_Pos) /*!< 0x00000002 */ -#define FLASH_SECBB2R3_SEC1 FLASH_SECBB2R3_SEC1_Msk /*!< Page 65 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC2_Pos (2UL) -#define FLASH_SECBB2R3_SEC2_Msk (0x1UL << FLASH_SECBB2R3_SEC2_Pos) /*!< 0x00000004 */ -#define FLASH_SECBB2R3_SEC2 FLASH_SECBB2R3_SEC2_Msk /*!< Page 66 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC3_Pos (3UL) -#define FLASH_SECBB2R3_SEC3_Msk (0x1UL << FLASH_SECBB2R3_SEC3_Pos) /*!< 0x00000008 */ -#define FLASH_SECBB2R3_SEC3 FLASH_SECBB2R3_SEC3_Msk /*!< Page 67 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC4_Pos (4UL) -#define FLASH_SECBB2R3_SEC4_Msk (0x1UL << FLASH_SECBB2R3_SEC4_Pos) /*!< 0x00000010 */ -#define FLASH_SECBB2R3_SEC4 FLASH_SECBB2R3_SEC4_Msk /*!< Page 68 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC5_Pos (5UL) -#define FLASH_SECBB2R3_SEC5_Msk (0x1UL << FLASH_SECBB2R3_SEC5_Pos) /*!< 0x00000020 */ -#define FLASH_SECBB2R3_SEC5 FLASH_SECBB2R3_SEC5_Msk /*!< Page 69 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC6_Pos (6UL) -#define FLASH_SECBB2R3_SEC6_Msk (0x1UL << FLASH_SECBB2R3_SEC6_Pos) /*!< 0x00000040 */ -#define FLASH_SECBB2R3_SEC6 FLASH_SECBB2R3_SEC6_Msk /*!< Page 70 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC7_Pos (7UL) -#define FLASH_SECBB2R3_SEC7_Msk (0x1UL << FLASH_SECBB2R3_SEC7_Pos) /*!< 0x00000080 */ -#define FLASH_SECBB2R3_SEC7 FLASH_SECBB2R3_SEC7_Msk /*!< Page 71 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC8_Pos (8UL) -#define FLASH_SECBB2R3_SEC8_Msk (0x1UL << FLASH_SECBB2R3_SEC8_Pos) /*!< 0x00000100 */ -#define FLASH_SECBB2R3_SEC8 FLASH_SECBB2R3_SEC8_Msk /*!< Page 72 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC9_Pos (9UL) -#define FLASH_SECBB2R3_SEC9_Msk (0x1UL << FLASH_SECBB2R3_SEC9_Pos) /*!< 0x00000200 */ -#define FLASH_SECBB2R3_SEC9 FLASH_SECBB2R3_SEC9_Msk /*!< Page 73 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC10_Pos (10UL) -#define FLASH_SECBB2R3_SEC10_Msk (0x1UL << FLASH_SECBB2R3_SEC10_Pos) /*!< 0x00000400 */ -#define FLASH_SECBB2R3_SEC10 FLASH_SECBB2R3_SEC10_Msk /*!< Page 74 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC11_Pos (11UL) -#define FLASH_SECBB2R3_SEC11_Msk (0x1UL << FLASH_SECBB2R3_SEC11_Pos) /*!< 0x00000800 */ -#define FLASH_SECBB2R3_SEC11 FLASH_SECBB2R3_SEC11_Msk /*!< Page 75 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC12_Pos (12UL) -#define FLASH_SECBB2R3_SEC12_Msk (0x1UL << FLASH_SECBB2R3_SEC12_Pos) /*!< 0x00001000 */ -#define FLASH_SECBB2R3_SEC12 FLASH_SECBB2R3_SEC12_Msk /*!< Page 76 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC13_Pos (13UL) -#define FLASH_SECBB2R3_SEC13_Msk (0x1UL << FLASH_SECBB2R3_SEC13_Pos) /*!< 0x00002000 */ -#define FLASH_SECBB2R3_SEC13 FLASH_SECBB2R3_SEC13_Msk /*!< Page 77 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC14_Pos (14UL) -#define FLASH_SECBB2R3_SEC14_Msk (0x1UL << FLASH_SECBB2R3_SEC14_Pos) /*!< 0x00004000 */ -#define FLASH_SECBB2R3_SEC14 FLASH_SECBB2R3_SEC14_Msk /*!< Page 78 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC15_Pos (15UL) -#define FLASH_SECBB2R3_SEC15_Msk (0x1UL << FLASH_SECBB2R3_SEC15_Pos) /*!< 0x00008000 */ -#define FLASH_SECBB2R3_SEC15 FLASH_SECBB2R3_SEC15_Msk /*!< Page 79 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC16_Pos (16UL) -#define FLASH_SECBB2R3_SEC16_Msk (0x1UL << FLASH_SECBB2R3_SEC16_Pos) /*!< 0x00010000 */ -#define FLASH_SECBB2R3_SEC16 FLASH_SECBB2R3_SEC16_Msk /*!< Page 80 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC17_Pos (17UL) -#define FLASH_SECBB2R3_SEC17_Msk (0x1UL << FLASH_SECBB2R3_SEC17_Pos) /*!< 0x00020000 */ -#define FLASH_SECBB2R3_SEC17 FLASH_SECBB2R3_SEC17_Msk /*!< Page 81 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC18_Pos (18UL) -#define FLASH_SECBB2R3_SEC18_Msk (0x1UL << FLASH_SECBB2R3_SEC18_Pos) /*!< 0x00040000 */ -#define FLASH_SECBB2R3_SEC18 FLASH_SECBB2R3_SEC18_Msk /*!< Page 82 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC19_Pos (19UL) -#define FLASH_SECBB2R3_SEC19_Msk (0x1UL << FLASH_SECBB2R3_SEC19_Pos) /*!< 0x00080000 */ -#define FLASH_SECBB2R3_SEC19 FLASH_SECBB2R3_SEC19_Msk /*!< Page 83 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC20_Pos (20UL) -#define FLASH_SECBB2R3_SEC20_Msk (0x1UL << FLASH_SECBB2R3_SEC20_Pos) /*!< 0x00100000 */ -#define FLASH_SECBB2R3_SEC20 FLASH_SECBB2R3_SEC20_Msk /*!< Page 84 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC21_Pos (21UL) -#define FLASH_SECBB2R3_SEC21_Msk (0x1UL << FLASH_SECBB2R3_SEC21_Pos) /*!< 0x00200000 */ -#define FLASH_SECBB2R3_SEC21 FLASH_SECBB2R3_SEC21_Msk /*!< Page 85 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC22_Pos (22UL) -#define FLASH_SECBB2R3_SEC22_Msk (0x1UL << FLASH_SECBB2R3_SEC22_Pos) /*!< 0x00400000 */ -#define FLASH_SECBB2R3_SEC22 FLASH_SECBB2R3_SEC22_Msk /*!< Page 86 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC23_Pos (23UL) -#define FLASH_SECBB2R3_SEC23_Msk (0x1UL << FLASH_SECBB2R3_SEC23_Pos) /*!< 0x00800000 */ -#define FLASH_SECBB2R3_SEC23 FLASH_SECBB2R3_SEC23_Msk /*!< Page 87 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC24_Pos (24UL) -#define FLASH_SECBB2R3_SEC24_Msk (0x1UL << FLASH_SECBB2R3_SEC24_Pos) /*!< 0x01000000 */ -#define FLASH_SECBB2R3_SEC24 FLASH_SECBB2R3_SEC24_Msk /*!< Page 88 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC25_Pos (25UL) -#define FLASH_SECBB2R3_SEC25_Msk (0x1UL << FLASH_SECBB2R3_SEC25_Pos) /*!< 0x02000000 */ -#define FLASH_SECBB2R3_SEC25 FLASH_SECBB2R3_SEC25_Msk /*!< Page 89 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC26_Pos (26UL) -#define FLASH_SECBB2R3_SEC26_Msk (0x1UL << FLASH_SECBB2R3_SEC26_Pos) /*!< 0x04000000 */ -#define FLASH_SECBB2R3_SEC26 FLASH_SECBB2R3_SEC26_Msk /*!< Page 90 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC27_Pos (27UL) -#define FLASH_SECBB2R3_SEC27_Msk (0x1UL << FLASH_SECBB2R3_SEC27_Pos) /*!< 0x08000000 */ -#define FLASH_SECBB2R3_SEC27 FLASH_SECBB2R3_SEC27_Msk /*!< Page 91 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC28_Pos (28UL) -#define FLASH_SECBB2R3_SEC28_Msk (0x1UL << FLASH_SECBB2R3_SEC28_Pos) /*!< 0x10000000 */ -#define FLASH_SECBB2R3_SEC28 FLASH_SECBB2R3_SEC28_Msk /*!< Page 92 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC29_Pos (29UL) -#define FLASH_SECBB2R3_SEC29_Msk (0x1UL << FLASH_SECBB2R3_SEC29_Pos) /*!< 0x20000000 */ -#define FLASH_SECBB2R3_SEC29 FLASH_SECBB2R3_SEC29_Msk /*!< Page 93 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC30_Pos (30UL) -#define FLASH_SECBB2R3_SEC30_Msk (0x1UL << FLASH_SECBB2R3_SEC30_Pos) /*!< 0x40000000 */ -#define FLASH_SECBB2R3_SEC30 FLASH_SECBB2R3_SEC30_Msk /*!< Page 94 in bank 2 block-based secure */ -#define FLASH_SECBB2R3_SEC31_Pos (31UL) -#define FLASH_SECBB2R3_SEC31_Msk (0x1UL << FLASH_SECBB2R3_SEC31_Pos) /*!< 0x80000000 */ -#define FLASH_SECBB2R3_SEC31 FLASH_SECBB2R3_SEC31_Msk /*!< Page 95 in bank 2 block-based secure */ - -/******************* Bit definition for FLASH_SECBB2R4 register ******************/ -#define FLASH_SECBB2R4_SEC0_Pos (0UL) -#define FLASH_SECBB2R4_SEC0_Msk (0x1UL << FLASH_SECBB2R4_SEC0_Pos) /*!< 0x00000001 */ -#define FLASH_SECBB2R4_SEC0 FLASH_SECBB2R4_SEC0_Msk /*!< Page 96 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC1_Pos (1UL) -#define FLASH_SECBB2R4_SEC1_Msk (0x1UL << FLASH_SECBB2R4_SEC1_Pos) /*!< 0x00000002 */ -#define FLASH_SECBB2R4_SEC1 FLASH_SECBB2R4_SEC1_Msk /*!< Page 97 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC2_Pos (2UL) -#define FLASH_SECBB2R4_SEC2_Msk (0x1UL << FLASH_SECBB2R4_SEC2_Pos) /*!< 0x00000004 */ -#define FLASH_SECBB2R4_SEC2 FLASH_SECBB2R4_SEC2_Msk /*!< Page 98 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC3_Pos (3UL) -#define FLASH_SECBB2R4_SEC3_Msk (0x1UL << FLASH_SECBB2R4_SEC3_Pos) /*!< 0x00000008 */ -#define FLASH_SECBB2R4_SEC3 FLASH_SECBB2R4_SEC3_Msk /*!< Page 99 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC4_Pos (4UL) -#define FLASH_SECBB2R4_SEC4_Msk (0x1UL << FLASH_SECBB2R4_SEC4_Pos) /*!< 0x00000010 */ -#define FLASH_SECBB2R4_SEC4 FLASH_SECBB2R4_SEC4_Msk /*!< Page 100 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC5_Pos (5UL) -#define FLASH_SECBB2R4_SEC5_Msk (0x1UL << FLASH_SECBB2R4_SEC5_Pos) /*!< 0x00000020 */ -#define FLASH_SECBB2R4_SEC5 FLASH_SECBB2R4_SEC5_Msk /*!< Page 101 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC6_Pos (6UL) -#define FLASH_SECBB2R4_SEC6_Msk (0x1UL << FLASH_SECBB2R4_SEC6_Pos) /*!< 0x00000040 */ -#define FLASH_SECBB2R4_SEC6 FLASH_SECBB2R4_SEC6_Msk /*!< Page 102 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC7_Pos (7UL) -#define FLASH_SECBB2R4_SEC7_Msk (0x1UL << FLASH_SECBB2R4_SEC7_Pos) /*!< 0x00000080 */ -#define FLASH_SECBB2R4_SEC7 FLASH_SECBB2R4_SEC7_Msk /*!< Page 103 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC8_Pos (8UL) -#define FLASH_SECBB2R4_SEC8_Msk (0x1UL << FLASH_SECBB2R4_SEC8_Pos) /*!< 0x00000100 */ -#define FLASH_SECBB2R4_SEC8 FLASH_SECBB2R4_SEC8_Msk /*!< Page 104 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC9_Pos (9UL) -#define FLASH_SECBB2R4_SEC9_Msk (0x1UL << FLASH_SECBB2R4_SEC9_Pos) /*!< 0x00000200 */ -#define FLASH_SECBB2R4_SEC9 FLASH_SECBB2R4_SEC9_Msk /*!< Page 105 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC10_Pos (10UL) -#define FLASH_SECBB2R4_SEC10_Msk (0x1UL << FLASH_SECBB2R4_SEC10_Pos) /*!< 0x00000400 */ -#define FLASH_SECBB2R4_SEC10 FLASH_SECBB2R4_SEC10_Msk /*!< Page 106 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC11_Pos (11UL) -#define FLASH_SECBB2R4_SEC11_Msk (0x1UL << FLASH_SECBB2R4_SEC11_Pos) /*!< 0x00000800 */ -#define FLASH_SECBB2R4_SEC11 FLASH_SECBB2R4_SEC11_Msk /*!< Page 107 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC12_Pos (12UL) -#define FLASH_SECBB2R4_SEC12_Msk (0x1UL << FLASH_SECBB2R4_SEC12_Pos) /*!< 0x00001000 */ -#define FLASH_SECBB2R4_SEC12 FLASH_SECBB2R4_SEC12_Msk /*!< Page 108 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC13_Pos (13UL) -#define FLASH_SECBB2R4_SEC13_Msk (0x1UL << FLASH_SECBB2R4_SEC13_Pos) /*!< 0x00002000 */ -#define FLASH_SECBB2R4_SEC13 FLASH_SECBB2R4_SEC13_Msk /*!< Page 109 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC14_Pos (14UL) -#define FLASH_SECBB2R4_SEC14_Msk (0x1UL << FLASH_SECBB2R4_SEC14_Pos) /*!< 0x00004000 */ -#define FLASH_SECBB2R4_SEC14 FLASH_SECBB2R4_SEC14_Msk /*!< Page 110 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC15_Pos (15UL) -#define FLASH_SECBB2R4_SEC15_Msk (0x1UL << FLASH_SECBB2R4_SEC15_Pos) /*!< 0x00008000 */ -#define FLASH_SECBB2R4_SEC15 FLASH_SECBB2R4_SEC15_Msk /*!< Page 111 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC16_Pos (16UL) -#define FLASH_SECBB2R4_SEC16_Msk (0x1UL << FLASH_SECBB2R4_SEC16_Pos) /*!< 0x00010000 */ -#define FLASH_SECBB2R4_SEC16 FLASH_SECBB2R4_SEC16_Msk /*!< Page 112 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC17_Pos (17UL) -#define FLASH_SECBB2R4_SEC17_Msk (0x1UL << FLASH_SECBB2R4_SEC17_Pos) /*!< 0x00020000 */ -#define FLASH_SECBB2R4_SEC17 FLASH_SECBB2R4_SEC17_Msk /*!< Page 113 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC18_Pos (18UL) -#define FLASH_SECBB2R4_SEC18_Msk (0x1UL << FLASH_SECBB2R4_SEC18_Pos) /*!< 0x00040000 */ -#define FLASH_SECBB2R4_SEC18 FLASH_SECBB2R4_SEC18_Msk /*!< Page 114 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC19_Pos (19UL) -#define FLASH_SECBB2R4_SEC19_Msk (0x1UL << FLASH_SECBB2R4_SEC19_Pos) /*!< 0x00080000 */ -#define FLASH_SECBB2R4_SEC19 FLASH_SECBB2R4_SEC19_Msk /*!< Page 115 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC20_Pos (20UL) -#define FLASH_SECBB2R4_SEC20_Msk (0x1UL << FLASH_SECBB2R4_SEC20_Pos) /*!< 0x00100000 */ -#define FLASH_SECBB2R4_SEC20 FLASH_SECBB2R4_SEC20_Msk /*!< Page 116 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC21_Pos (21UL) -#define FLASH_SECBB2R4_SEC21_Msk (0x1UL << FLASH_SECBB2R4_SEC21_Pos) /*!< 0x00200000 */ -#define FLASH_SECBB2R4_SEC21 FLASH_SECBB2R4_SEC21_Msk /*!< Page 117 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC22_Pos (22UL) -#define FLASH_SECBB2R4_SEC22_Msk (0x1UL << FLASH_SECBB2R4_SEC22_Pos) /*!< 0x00400000 */ -#define FLASH_SECBB2R4_SEC22 FLASH_SECBB2R4_SEC22_Msk /*!< Page 118 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC23_Pos (23UL) -#define FLASH_SECBB2R4_SEC23_Msk (0x1UL << FLASH_SECBB2R4_SEC23_Pos) /*!< 0x00800000 */ -#define FLASH_SECBB2R4_SEC23 FLASH_SECBB2R4_SEC23_Msk /*!< Page 119 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC24_Pos (24UL) -#define FLASH_SECBB2R4_SEC24_Msk (0x1UL << FLASH_SECBB2R4_SEC24_Pos) /*!< 0x01000000 */ -#define FLASH_SECBB2R4_SEC24 FLASH_SECBB2R4_SEC24_Msk /*!< Page 120 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC25_Pos (25UL) -#define FLASH_SECBB2R4_SEC25_Msk (0x1UL << FLASH_SECBB2R4_SEC25_Pos) /*!< 0x02000000 */ -#define FLASH_SECBB2R4_SEC25 FLASH_SECBB2R4_SEC25_Msk /*!< Page 121 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC26_Pos (26UL) -#define FLASH_SECBB2R4_SEC26_Msk (0x1UL << FLASH_SECBB2R4_SEC26_Pos) /*!< 0x04000000 */ -#define FLASH_SECBB2R4_SEC26 FLASH_SECBB2R4_SEC26_Msk /*!< Page 122 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC27_Pos (27UL) -#define FLASH_SECBB2R4_SEC27_Msk (0x1UL << FLASH_SECBB2R4_SEC27_Pos) /*!< 0x08000000 */ -#define FLASH_SECBB2R4_SEC27 FLASH_SECBB2R4_SEC27_Msk /*!< Page 123 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC28_Pos (28UL) -#define FLASH_SECBB2R4_SEC28_Msk (0x1UL << FLASH_SECBB2R4_SEC28_Pos) /*!< 0x10000000 */ -#define FLASH_SECBB2R4_SEC28 FLASH_SECBB2R4_SEC28_Msk /*!< Page 124 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC29_Pos (29UL) -#define FLASH_SECBB2R4_SEC29_Msk (0x1UL << FLASH_SECBB2R4_SEC29_Pos) /*!< 0x20000000 */ -#define FLASH_SECBB2R4_SEC29 FLASH_SECBB2R4_SEC29_Msk /*!< Page 125 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC30_Pos (30UL) -#define FLASH_SECBB2R4_SEC30_Msk (0x1UL << FLASH_SECBB2R4_SEC30_Pos) /*!< 0x40000000 */ -#define FLASH_SECBB2R4_SEC30 FLASH_SECBB2R4_SEC30_Msk /*!< Page 126 in bank 2 block-based secure */ -#define FLASH_SECBB2R4_SEC31_Pos (31UL) -#define FLASH_SECBB2R4_SEC31_Msk (0x1UL << FLASH_SECBB2R4_SEC31_Pos) /*!< 0x80000000 */ -#define FLASH_SECBB2R4_SEC31 FLASH_SECBB2R4_SEC31_Msk /*!< Page 127 in bank 2 block-based secure */ /********************** Bits definition for FLASH_SECHDPCR register ***************/ #define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) @@ -9365,6 +8790,8 @@ typedef struct #define GTZC_CFGR3_TSC_Msk (0x01UL << GTZC_CFGR3_TSC_Pos) /*!< 0x00000008 */ #define GTZC_CFGR3_ICACHE_REG_Pos (6UL) #define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) /*!< 0x00000020 */ +#define GTZC_CFGR3_ADC1_Pos (8UL) +#define GTZC_CFGR3_ADC1_Msk (0x01UL << GTZC_CFGR3_ADC1_Pos) /*!< 0x00000100 */ #define GTZC_CFGR3_AES_Pos (11UL) #define GTZC_CFGR3_AES_Msk (0x01UL << GTZC_CFGR3_AES_Pos) /*!< 0x00000800 */ #define GTZC_CFGR3_HASH_Pos (12UL) @@ -9483,6 +8910,8 @@ typedef struct #define GTZC_TZSC1_SECCFGR3_TSC_Msk GTZC_CFGR3_TSC_Msk #define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos #define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_SECCFGR3_ADC1_Pos GTZC_CFGR3_ADC1_Pos +#define GTZC_TZSC1_SECCFGR3_ADC1_Msk GTZC_CFGR3_ADC1_Msk #define GTZC_TZSC1_SECCFGR3_AES_Pos GTZC_CFGR3_AES_Pos #define GTZC_TZSC1_SECCFGR3_AES_Msk GTZC_CFGR3_AES_Msk #define GTZC_TZSC1_SECCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos @@ -9569,6 +8998,8 @@ typedef struct #define GTZC_TZSC1_PRIVCFGR3_TSC_Msk GTZC_CFGR3_TSC_Msk #define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos #define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_ADC1_Pos GTZC_CFGR3_ADC1_Pos +#define GTZC_TZSC1_PRIVCFGR3_ADC1_Msk GTZC_CFGR3_ADC1_Msk #define GTZC_TZSC1_PRIVCFGR3_AES_Pos GTZC_CFGR3_AES_Pos #define GTZC_TZSC1_PRIVCFGR3_AES_Msk GTZC_CFGR3_AES_Msk #define GTZC_TZSC1_PRIVCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos @@ -9655,6 +9086,8 @@ typedef struct #define GTZC_TZIC1_IER3_TSC_Msk GTZC_CFGR3_TSC_Msk #define GTZC_TZIC1_IER3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos #define GTZC_TZIC1_IER3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_IER3_ADC1_Pos GTZC_CFGR3_ADC1_Pos +#define GTZC_TZIC1_IER3_ADC1_Msk GTZC_CFGR3_ADC1_Msk #define GTZC_TZIC1_IER3_AES_Pos GTZC_CFGR3_AES_Pos #define GTZC_TZIC1_IER3_AES_Msk GTZC_CFGR3_AES_Msk #define GTZC_TZIC1_IER3_HASH_Pos GTZC_CFGR3_HASH_Pos @@ -9773,6 +9206,8 @@ typedef struct #define GTZC_TZIC1_SR3_TSC_Msk GTZC_CFGR3_TSC_Msk #define GTZC_TZIC1_SR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos #define GTZC_TZIC1_SR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_SR3_ADC1_Pos GTZC_CFGR3_ADC1_Pos +#define GTZC_TZIC1_SR3_ADC1_Msk GTZC_CFGR3_ADC1_Msk #define GTZC_TZIC1_SR3_AES_Pos GTZC_CFGR3_AES_Pos #define GTZC_TZIC1_SR3_AES_Msk GTZC_CFGR3_AES_Msk #define GTZC_TZIC1_SR3_HASH_Pos GTZC_CFGR3_HASH_Pos @@ -9891,6 +9326,8 @@ typedef struct #define GTZC_TZIC1_FCR3_TSC_Msk GTZC_CFGR3_TSC_Msk #define GTZC_TZIC1_FCR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos #define GTZC_TZIC1_FCR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_FCR3_ADC1_Pos GTZC_CFGR3_ADC1_Pos +#define GTZC_TZIC1_FCR3_ADC1_Msk GTZC_CFGR3_ADC1_Msk #define GTZC_TZIC1_FCR3_AES_Pos GTZC_CFGR3_AES_Pos #define GTZC_TZIC1_FCR3_AES_Msk GTZC_CFGR3_AES_Msk #define GTZC_TZIC1_FCR3_HASH_Pos GTZC_CFGR3_HASH_Pos @@ -12109,24 +11546,6 @@ typedef struct #define PWR_CR2_SRAM1PDS1_Pos (0UL) #define PWR_CR2_SRAM1PDS1_Msk (0x1UL << PWR_CR2_SRAM1PDS1_Pos) /*!< 0x00000001 */ #define PWR_CR2_SRAM1PDS1 PWR_CR2_SRAM1PDS1_Msk /*!< SRAM1 page 1 (16 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_CR2_SRAM1PDS2_Pos (1UL) -#define PWR_CR2_SRAM1PDS2_Msk (0x1UL << PWR_CR2_SRAM1PDS2_Pos) /*!< 0x00000002 */ -#define PWR_CR2_SRAM1PDS2 PWR_CR2_SRAM1PDS2_Msk /*!< SRAM1 page 2 (16 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_CR2_SRAM1PDS3_Pos (2UL) -#define PWR_CR2_SRAM1PDS3_Msk (0x1UL << PWR_CR2_SRAM1PDS3_Pos) /*!< 0x00000004 */ -#define PWR_CR2_SRAM1PDS3 PWR_CR2_SRAM1PDS3_Msk /*!< SRAM1 page 3 (32 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_CR2_SRAM1PDS4_Pos (3UL) -#define PWR_CR2_SRAM1PDS4_Msk (0x1UL << PWR_CR2_SRAM1PDS4_Pos) /*!< 0x00000008 */ -#define PWR_CR2_SRAM1PDS4 PWR_CR2_SRAM1PDS4_Msk /*!< SRAM1 page 4 (32 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_CR2_SRAM1PDS5_Pos (4UL) -#define PWR_CR2_SRAM1PDS5_Msk (0x1UL << PWR_CR2_SRAM1PDS5_Pos) /*!< 0x00000010 */ -#define PWR_CR2_SRAM1PDS5 PWR_CR2_SRAM1PDS5_Msk /*!< SRAM1 page 5 (32 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_CR2_SRAM1PDS6_Pos (5UL) -#define PWR_CR2_SRAM1PDS6_Msk (0x1UL << PWR_CR2_SRAM1PDS6_Pos) /*!< 0x00000020 */ -#define PWR_CR2_SRAM1PDS6 PWR_CR2_SRAM1PDS6_Msk /*!< SRAM1 page 6 (32 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_CR2_SRAM1PDS7_Pos (6UL) -#define PWR_CR2_SRAM1PDS7_Msk (0x1UL << PWR_CR2_SRAM1PDS7_Pos) /*!< 0x00000040 */ -#define PWR_CR2_SRAM1PDS7 PWR_CR2_SRAM1PDS7_Msk /*!< SRAM1 page 7 (32 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */ #define PWR_CR2_SRAM2PDS1_Pos (16UL) #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00010000 */ #define PWR_CR2_SRAM2PDS1 PWR_CR2_SRAM2PDS1_Msk /*!< SRAM2 page 1 (8 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */ @@ -12862,193 +12281,7 @@ typedef struct #define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */ #define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Apply pull-down for PD15 */ -/******************** Bit definition for PWR_PUCRE register *****************/ -#define PWR_PUCRE_PU0_Pos (0UL) -#define PWR_PUCRE_PU0_Msk (0x1UL << PWR_PUCRE_PU0_Pos) /*!< 0x00000001 */ -#define PWR_PUCRE_PU0 PWR_PUCRE_PU0_Msk /*!< Apply pull-up for PE0 */ -#define PWR_PUCRE_PU1_Pos (1UL) -#define PWR_PUCRE_PU1_Msk (0x1UL << PWR_PUCRE_PU1_Pos) /*!< 0x00000002 */ -#define PWR_PUCRE_PU1 PWR_PUCRE_PU1_Msk /*!< Apply pull-up for PE1 */ -#define PWR_PUCRE_PU2_Pos (2UL) -#define PWR_PUCRE_PU2_Msk (0x1UL << PWR_PUCRE_PU2_Pos) /*!< 0x00000004 */ -#define PWR_PUCRE_PU2 PWR_PUCRE_PU2_Msk /*!< Apply pull-up for PE2 */ -#define PWR_PUCRE_PU3_Pos (3UL) -#define PWR_PUCRE_PU3_Msk (0x1UL << PWR_PUCRE_PU3_Pos) /*!< 0x00000008 */ -#define PWR_PUCRE_PU3 PWR_PUCRE_PU3_Msk /*!< Apply pull-up for PE3 */ -#define PWR_PUCRE_PU4_Pos (4UL) -#define PWR_PUCRE_PU4_Msk (0x1UL << PWR_PUCRE_PU4_Pos) /*!< 0x00000010 */ -#define PWR_PUCRE_PU4 PWR_PUCRE_PU4_Msk /*!< Apply pull-up for PE4 */ -#define PWR_PUCRE_PU5_Pos (5UL) -#define PWR_PUCRE_PU5_Msk (0x1UL << PWR_PUCRE_PU5_Pos) /*!< 0x00000020 */ -#define PWR_PUCRE_PU5 PWR_PUCRE_PU5_Msk /*!< Apply pull-up for PE5 */ -#define PWR_PUCRE_PU6_Pos (6UL) -#define PWR_PUCRE_PU6_Msk (0x1UL << PWR_PUCRE_PU6_Pos) /*!< 0x00000040 */ -#define PWR_PUCRE_PU6 PWR_PUCRE_PU6_Msk /*!< Apply pull-up for PE6 */ -#define PWR_PUCRE_PU7_Pos (7UL) -#define PWR_PUCRE_PU7_Msk (0x1UL << PWR_PUCRE_PU7_Pos) /*!< 0x00000080 */ -#define PWR_PUCRE_PU7 PWR_PUCRE_PU7_Msk /*!< Apply pull-up for PE7 */ -#define PWR_PUCRE_PU8_Pos (8UL) -#define PWR_PUCRE_PU8_Msk (0x1UL << PWR_PUCRE_PU8_Pos) /*!< 0x00000100 */ -#define PWR_PUCRE_PU8 PWR_PUCRE_PU8_Msk /*!< Apply pull-up for PE8 */ -#define PWR_PUCRE_PU9_Pos (9UL) -#define PWR_PUCRE_PU9_Msk (0x1UL << PWR_PUCRE_PU9_Pos) /*!< 0x00000200 */ -#define PWR_PUCRE_PU9 PWR_PUCRE_PU9_Msk /*!< Apply pull-up for PE9 */ -#define PWR_PUCRE_PU10_Pos (10UL) -#define PWR_PUCRE_PU10_Msk (0x1UL << PWR_PUCRE_PU10_Pos) /*!< 0x00000400 */ -#define PWR_PUCRE_PU10 PWR_PUCRE_PU10_Msk /*!< Apply pull-up for PE10 */ -#define PWR_PUCRE_PU11_Pos (11UL) -#define PWR_PUCRE_PU11_Msk (0x1UL << PWR_PUCRE_PU11_Pos) /*!< 0x00000800 */ -#define PWR_PUCRE_PU11 PWR_PUCRE_PU11_Msk /*!< Apply pull-up for PE11 */ -#define PWR_PUCRE_PU12_Pos (12UL) -#define PWR_PUCRE_PU12_Msk (0x1UL << PWR_PUCRE_PU12_Pos) /*!< 0x00001000 */ -#define PWR_PUCRE_PU12 PWR_PUCRE_PU12_Msk /*!< Apply pull-up for PE12 */ -#define PWR_PUCRE_PU13_Pos (13UL) -#define PWR_PUCRE_PU13_Msk (0x1UL << PWR_PUCRE_PU13_Pos) /*!< 0x00002000 */ -#define PWR_PUCRE_PU13 PWR_PUCRE_PU13_Msk /*!< Apply pull-up for PE13 */ -#define PWR_PUCRE_PU14_Pos (14UL) -#define PWR_PUCRE_PU14_Msk (0x1UL << PWR_PUCRE_PU14_Pos) /*!< 0x00004000 */ -#define PWR_PUCRE_PU14 PWR_PUCRE_PU14_Msk /*!< Apply pull-up for PE14 */ -#define PWR_PUCRE_PU15_Pos (15UL) -#define PWR_PUCRE_PU15_Msk (0x1UL << PWR_PUCRE_PU15_Pos) /*!< 0x00008000 */ -#define PWR_PUCRE_PU15 PWR_PUCRE_PU15_Msk /*!< Apply pull-up for PE15 */ - -/******************** Bit definition for PWR_PDCRE register *****************/ -#define PWR_PDCRE_PD0_Pos (0UL) -#define PWR_PDCRE_PD0_Msk (0x1UL << PWR_PDCRE_PD0_Pos) /*!< 0x00000001 */ -#define PWR_PDCRE_PD0 PWR_PDCRE_PD0_Msk /*!< Apply pull-down for PE0 */ -#define PWR_PDCRE_PD1_Pos (1UL) -#define PWR_PDCRE_PD1_Msk (0x1UL << PWR_PDCRE_PD1_Pos) /*!< 0x00000002 */ -#define PWR_PDCRE_PD1 PWR_PDCRE_PD1_Msk /*!< Apply pull-down for PE1 */ -#define PWR_PDCRE_PD2_Pos (2UL) -#define PWR_PDCRE_PD2_Msk (0x1UL << PWR_PDCRE_PD2_Pos) /*!< 0x00000004 */ -#define PWR_PDCRE_PD2 PWR_PDCRE_PD2_Msk /*!< Apply pull-down for PE2 */ -#define PWR_PDCRE_PD3_Pos (3UL) -#define PWR_PDCRE_PD3_Msk (0x1UL << PWR_PDCRE_PD3_Pos) /*!< 0x00000008 */ -#define PWR_PDCRE_PD3 PWR_PDCRE_PD3_Msk /*!< Apply pull-down for PE3 */ -#define PWR_PDCRE_PD4_Pos (4UL) -#define PWR_PDCRE_PD4_Msk (0x1UL << PWR_PDCRE_PD4_Pos) /*!< 0x00000010 */ -#define PWR_PDCRE_PD4 PWR_PDCRE_PD4_Msk /*!< Apply pull-down for PE4 */ -#define PWR_PDCRE_PD5_Pos (5UL) -#define PWR_PDCRE_PD5_Msk (0x1UL << PWR_PDCRE_PD5_Pos) /*!< 0x00000020 */ -#define PWR_PDCRE_PD5 PWR_PDCRE_PD5_Msk /*!< Apply pull-down for PE5 */ -#define PWR_PDCRE_PD6_Pos (6UL) -#define PWR_PDCRE_PD6_Msk (0x1UL << PWR_PDCRE_PD6_Pos) /*!< 0x00000040 */ -#define PWR_PDCRE_PD6 PWR_PDCRE_PD6_Msk /*!< Apply pull-down for PE6 */ -#define PWR_PDCRE_PD7_Pos (7UL) -#define PWR_PDCRE_PD7_Msk (0x1UL << PWR_PDCRE_PD7_Pos) /*!< 0x00000080 */ -#define PWR_PDCRE_PD7 PWR_PDCRE_PD7_Msk /*!< Apply pull-down for PE7 */ -#define PWR_PDCRE_PD8_Pos (8UL) -#define PWR_PDCRE_PD8_Msk (0x1UL << PWR_PDCRE_PD8_Pos) /*!< 0x00000100 */ -#define PWR_PDCRE_PD8 PWR_PDCRE_PD8_Msk /*!< Apply pull-down for PE8 */ -#define PWR_PDCRE_PD9_Pos (9UL) -#define PWR_PDCRE_PD9_Msk (0x1UL << PWR_PDCRE_PD9_Pos) /*!< 0x00000200 */ -#define PWR_PDCRE_PD9 PWR_PDCRE_PD9_Msk /*!< Apply pull-down for PE9 */ -#define PWR_PDCRE_PD10_Pos (10UL) -#define PWR_PDCRE_PD10_Msk (0x1UL << PWR_PDCRE_PD10_Pos) /*!< 0x00000400 */ -#define PWR_PDCRE_PD10 PWR_PDCRE_PD10_Msk /*!< Apply pull-down for PE10 */ -#define PWR_PDCRE_PD11_Pos (11UL) -#define PWR_PDCRE_PD11_Msk (0x1UL << PWR_PDCRE_PD11_Pos) /*!< 0x00000800 */ -#define PWR_PDCRE_PD11 PWR_PDCRE_PD11_Msk /*!< Apply pull-down for PE11 */ -#define PWR_PDCRE_PD12_Pos (12UL) -#define PWR_PDCRE_PD12_Msk (0x1UL << PWR_PDCRE_PD12_Pos) /*!< 0x00001000 */ -#define PWR_PDCRE_PD12 PWR_PDCRE_PD12_Msk /*!< Apply pull-down for PE12 */ -#define PWR_PDCRE_PD13_Pos (13UL) -#define PWR_PDCRE_PD13_Msk (0x1UL << PWR_PDCRE_PD13_Pos) /*!< 0x00002000 */ -#define PWR_PDCRE_PD13 PWR_PDCRE_PD13_Msk /*!< Apply pull-down for PE13 */ -#define PWR_PDCRE_PD14_Pos (14UL) -#define PWR_PDCRE_PD14_Msk (0x1UL << PWR_PDCRE_PD14_Pos) /*!< 0x00004000 */ -#define PWR_PDCRE_PD14 PWR_PDCRE_PD14_Msk /*!< Apply pull-down for PE14 */ -#define PWR_PDCRE_PD15_Pos (15UL) -#define PWR_PDCRE_PD15_Msk (0x1UL << PWR_PDCRE_PD15_Pos) /*!< 0x00008000 */ -#define PWR_PDCRE_PD15 PWR_PDCRE_PD15_Msk /*!< Apply pull-down for PE15 */ - -/******************** Bit definition for PWR_PUCRG register *****************/ -#define PWR_PUCRG_PU2_Pos (2UL) -#define PWR_PUCRG_PU2_Msk (0x1UL << PWR_PUCRG_PU2_Pos) /*!< 0x00000004 */ -#define PWR_PUCRG_PU2 PWR_PUCRG_PU2_Msk /*!< Apply pull-up for PG2 */ -#define PWR_PUCRG_PU3_Pos (3UL) -#define PWR_PUCRG_PU3_Msk (0x1UL << PWR_PUCRG_PU3_Pos) /*!< 0x00000008 */ -#define PWR_PUCRG_PU3 PWR_PUCRG_PU3_Msk /*!< Apply pull-up for PG3 */ -#define PWR_PUCRG_PU4_Pos (4UL) -#define PWR_PUCRG_PU4_Msk (0x1UL << PWR_PUCRG_PU4_Pos) /*!< 0x00000010 */ -#define PWR_PUCRG_PU4 PWR_PUCRG_PU4_Msk /*!< Apply pull-up for PG4 */ -#define PWR_PUCRG_PU5_Pos (5UL) -#define PWR_PUCRG_PU5_Msk (0x1UL << PWR_PUCRG_PU5_Pos) /*!< 0x00000020 */ -#define PWR_PUCRG_PU5 PWR_PUCRG_PU5_Msk /*!< Apply pull-up for PG5 */ -#define PWR_PUCRG_PU6_Pos (6UL) -#define PWR_PUCRG_PU6_Msk (0x1UL << PWR_PUCRG_PU6_Pos) /*!< 0x00000040 */ -#define PWR_PUCRG_PU6 PWR_PUCRG_PU6_Msk /*!< Apply pull-up for PG6 */ -#define PWR_PUCRG_PU7_Pos (7UL) -#define PWR_PUCRG_PU7_Msk (0x1UL << PWR_PUCRG_PU7_Pos) /*!< 0x00000080 */ -#define PWR_PUCRG_PU7 PWR_PUCRG_PU7_Msk /*!< Apply pull-up for PG7 */ -#define PWR_PUCRG_PU8_Pos (8UL) -#define PWR_PUCRG_PU8_Msk (0x1UL << PWR_PUCRG_PU8_Pos) /*!< 0x00000100 */ -#define PWR_PUCRG_PU8 PWR_PUCRG_PU8_Msk /*!< Apply pull-up for PG8 */ -#define PWR_PUCRG_PU9_Pos (9UL) -#define PWR_PUCRG_PU9_Msk (0x1UL << PWR_PUCRG_PU9_Pos) /*!< 0x00000200 */ -#define PWR_PUCRG_PU9 PWR_PUCRG_PU9_Msk /*!< Apply pull-up for PG9 */ -#define PWR_PUCRG_PU10_Pos (10UL) -#define PWR_PUCRG_PU10_Msk (0x1UL << PWR_PUCRG_PU10_Pos) /*!< 0x00000400 */ -#define PWR_PUCRG_PU10 PWR_PUCRG_PU10_Msk /*!< Apply pull-up for PG10 */ -#define PWR_PUCRG_PU11_Pos (11UL) -#define PWR_PUCRG_PU11_Msk (0x1UL << PWR_PUCRG_PU11_Pos) /*!< 0x00000800 */ -#define PWR_PUCRG_PU11 PWR_PUCRG_PU11_Msk /*!< Apply pull-up for PG11 */ -#define PWR_PUCRG_PU12_Pos (12UL) -#define PWR_PUCRG_PU12_Msk (0x1UL << PWR_PUCRG_PU12_Pos) /*!< 0x00001000 */ -#define PWR_PUCRG_PU12 PWR_PUCRG_PU12_Msk /*!< Apply pull-up for PG12 */ -#define PWR_PUCRG_PU13_Pos (13UL) -#define PWR_PUCRG_PU13_Msk (0x1UL << PWR_PUCRG_PU13_Pos) /*!< 0x00002000 */ -#define PWR_PUCRG_PU13 PWR_PUCRG_PU13_Msk /*!< Apply pull-up for PG13 */ -#define PWR_PUCRG_PU14_Pos (14UL) -#define PWR_PUCRG_PU14_Msk (0x1UL << PWR_PUCRG_PU14_Pos) /*!< 0x00004000 */ -#define PWR_PUCRG_PU14 PWR_PUCRG_PU14_Msk /*!< Apply pull-up for PG14 */ -#define PWR_PUCRG_PU15_Pos (15UL) -#define PWR_PUCRG_PU15_Msk (0x1UL << PWR_PUCRG_PU15_Pos) /*!< 0x00008000 */ -#define PWR_PUCRG_PU15 PWR_PUCRG_PU15_Msk /*!< Apply pull-up for PG15 */ - -/******************** Bit definition for PWR_PDCRG register *****************/ -#define PWR_PDCRG_PD2_Pos (2UL) -#define PWR_PDCRG_PD2_Msk (0x1UL << PWR_PDCRG_PD2_Pos) /*!< 0x00000004 */ -#define PWR_PDCRG_PD2 PWR_PDCRG_PD2_Msk /*!< Apply pull-down for PG2 */ -#define PWR_PDCRG_PD3_Pos (3UL) -#define PWR_PDCRG_PD3_Msk (0x1UL << PWR_PDCRG_PD3_Pos) /*!< 0x00000008 */ -#define PWR_PDCRG_PD3 PWR_PDCRG_PD3_Msk /*!< Apply pull-down for PG3 */ -#define PWR_PDCRG_PD4_Pos (4UL) -#define PWR_PDCRG_PD4_Msk (0x1UL << PWR_PDCRG_PD4_Pos) /*!< 0x00000010 */ -#define PWR_PDCRG_PD4 PWR_PDCRG_PD4_Msk /*!< Apply pull-down for PG4 */ -#define PWR_PDCRG_PD5_Pos (5UL) -#define PWR_PDCRG_PD5_Msk (0x1UL << PWR_PDCRG_PD5_Pos) /*!< 0x00000020 */ -#define PWR_PDCRG_PD5 PWR_PDCRG_PD5_Msk /*!< Apply pull-down for PG5 */ -#define PWR_PDCRG_PD6_Pos (6UL) -#define PWR_PDCRG_PD6_Msk (0x1UL << PWR_PDCRG_PD6_Pos) /*!< 0x00000040 */ -#define PWR_PDCRG_PD6 PWR_PDCRG_PD6_Msk /*!< Apply pull-down for PG6 */ -#define PWR_PDCRG_PD7_Pos (7UL) -#define PWR_PDCRG_PD7_Msk (0x1UL << PWR_PDCRG_PD7_Pos) /*!< 0x00000080 */ -#define PWR_PDCRG_PD7 PWR_PDCRG_PD7_Msk /*!< Apply pull-down for PG7 */ -#define PWR_PDCRG_PD8_Pos (8UL) -#define PWR_PDCRG_PD8_Msk (0x1UL << PWR_PDCRG_PD8_Pos) /*!< 0x00000100 */ -#define PWR_PDCRG_PD8 PWR_PDCRG_PD8_Msk /*!< Apply pull-down for PG8 */ -#define PWR_PDCRG_PD9_Pos (9UL) -#define PWR_PDCRG_PD9_Msk (0x1UL << PWR_PDCRG_PD9_Pos) /*!< 0x00000200 */ -#define PWR_PDCRG_PD9 PWR_PDCRG_PD9_Msk /*!< Apply pull-down for PG9 */ -#define PWR_PDCRG_PD10_Pos (10UL) -#define PWR_PDCRG_PD10_Msk (0x1UL << PWR_PDCRG_PD10_Pos) /*!< 0x00000400 */ -#define PWR_PDCRG_PD10 PWR_PDCRG_PD10_Msk /*!< Apply pull-down for PG10 */ -#define PWR_PDCRG_PD11_Pos (11UL) -#define PWR_PDCRG_PD11_Msk (0x1UL << PWR_PDCRG_PD11_Pos) /*!< 0x00000800 */ -#define PWR_PDCRG_PD11 PWR_PDCRG_PD11_Msk /*!< Apply pull-down for PG11 */ -#define PWR_PDCRG_PD12_Pos (12UL) -#define PWR_PDCRG_PD12_Msk (0x1UL << PWR_PDCRG_PD12_Pos) /*!< 0x00001000 */ -#define PWR_PDCRG_PD12 PWR_PDCRG_PD12_Msk /*!< Apply pull-down for PG12 */ -#define PWR_PDCRG_PD13_Pos (13UL) -#define PWR_PDCRG_PD13_Msk (0x1UL << PWR_PDCRG_PD13_Pos) /*!< 0x00002000 */ -#define PWR_PDCRG_PD13 PWR_PDCRG_PD13_Msk /*!< Apply pull-down for PG13 */ -#define PWR_PDCRG_PD14_Pos (14UL) -#define PWR_PDCRG_PD14_Msk (0x1UL << PWR_PDCRG_PD14_Pos) /*!< 0x00004000 */ -#define PWR_PDCRG_PD14 PWR_PDCRG_PD14_Msk /*!< Apply pull-down for PG14 */ -#define PWR_PDCRG_PD15_Pos (15UL) -#define PWR_PDCRG_PD15_Msk (0x1UL << PWR_PDCRG_PD15_Pos) /*!< 0x00008000 */ -#define PWR_PDCRG_PD15 PWR_PDCRG_PD15_Msk /*!< Apply pull-down for PG15 */ + /******************** Bit definition for PWR_PUCRH register *****************/ #define PWR_PUCRH_PU0_Pos (0UL) @@ -13103,35 +12336,11 @@ typedef struct #define PWR_I3CPUCR1_PB13_I3CPU_Pos (10UL) #define PWR_I3CPUCR1_PB13_I3CPU_Msk (0x1UL << PWR_I3CPUCR1_PB13_I3CPU_Pos) /*!< 0x00000400 */ #define PWR_I3CPUCR1_PB13_I3CPU PWR_I3CPUCR1_PB13_I3CPU_Msk /*!< Port B pin 13 I3C pull-up */ -#define PWR_I3CPUCR1_PB14_I3CPU_Pos (11UL) -#define PWR_I3CPUCR1_PB14_I3CPU_Msk (0x1UL << PWR_I3CPUCR1_PB14_I3CPU_Pos) /*!< 0x00000800 */ -#define PWR_I3CPUCR1_PB14_I3CPU PWR_I3CPUCR1_PB14_I3CPU_Msk /*!< Port B pin 14 I3C pull-up */ +#define PWR_I3CPUCR1_PB7_I3CPU_Pos (12UL) +#define PWR_I3CPUCR1_PB7_I3CPU_Msk (0x1UL << PWR_I3CPUCR1_PB7_I3CPU_Pos) /*!< 0x00001000 */ +#define PWR_I3CPUCR1_PB7_I3CPU PWR_I3CPUCR1_PB7_I3CPU_Msk /*!< Port B pin 7 I3C pull-up */ /******************** Bit definition for PWR_I3CPUCR2 register *****************/ -#define PWR_I3CPUCR2_PC0_I3CPU_Pos (0UL) -#define PWR_I3CPUCR2_PC0_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PC0_I3CPU_Pos) /*!< 0x00000001 */ -#define PWR_I3CPUCR2_PC0_I3CPU PWR_I3CPUCR2_PC0_I3CPU_Msk /*!< Port C pin 0 I3C pull-up */ -#define PWR_I3CPUCR2_PC1_I3CPU_Pos (1UL) -#define PWR_I3CPUCR2_PC1_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PC1_I3CPU_Pos) /*!< 0x00000002 */ -#define PWR_I3CPUCR2_PC1_I3CPU PWR_I3CPUCR2_PC1_I3CPU_Msk /*!< Port C pin 1 I3C pull-up */ -#define PWR_I3CPUCR2_PD12_I3CPU_Pos (3UL) -#define PWR_I3CPUCR2_PD12_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PD12_I3CPU_Pos) /*!< 0x00000008 */ -#define PWR_I3CPUCR2_PD12_I3CPU PWR_I3CPUCR2_PD12_I3CPU_Msk /*!< Port D pin 12 I3C pull-up */ -#define PWR_I3CPUCR2_PD13_I3CPU_Pos (4UL) -#define PWR_I3CPUCR2_PD13_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PD13_I3CPU_Pos) /*!< 0x00000010 */ -#define PWR_I3CPUCR2_PD13_I3CPU PWR_I3CPUCR2_PD13_I3CPU_Msk /*!< Port D pin 13 I3C pull-up */ -#define PWR_I3CPUCR2_PG7_I3CPU_Pos (6UL) -#define PWR_I3CPUCR2_PG7_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PG7_I3CPU_Pos) /*!< 0x00000040 */ -#define PWR_I3CPUCR2_PG7_I3CPU PWR_I3CPUCR2_PG7_I3CPU_Msk /*!< Port G pin 7 I3C pull-up */ -#define PWR_I3CPUCR2_PG8_I3CPU_Pos (7UL) -#define PWR_I3CPUCR2_PG8_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PG8_I3CPU_Pos) /*!< 0x00000080 */ -#define PWR_I3CPUCR2_PG8_I3CPU PWR_I3CPUCR2_PG8_I3CPU_Msk /*!< Port G pin 8 I3C pull-up */ -#define PWR_I3CPUCR2_PG13_I3CPU_Pos (8UL) -#define PWR_I3CPUCR2_PG13_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PG13_I3CPU_Pos) /*!< 0x00000100 */ -#define PWR_I3CPUCR2_PG13_I3CPU PWR_I3CPUCR2_PG13_I3CPU_Msk /*!< Port G pin 13 I3C pull-up */ -#define PWR_I3CPUCR2_PG14_I3CPU_Pos (9UL) -#define PWR_I3CPUCR2_PG14_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PG14_I3CPU_Pos) /*!< 0x00000200 */ -#define PWR_I3CPUCR2_PG14_I3CPU PWR_I3CPUCR2_PG14_I3CPU_Msk /*!< Port G pin 14 I3C pull-up */ #define PWR_I3CPUCR2_PH3_I3CPU_Pos (11UL) #define PWR_I3CPUCR2_PH3_I3CPU_Msk (0x1UL << PWR_I3CPUCR2_PH3_I3CPU_Pos) /*!< 0x00000800 */ #define PWR_I3CPUCR2_PH3_I3CPU PWR_I3CPUCR2_PH3_I3CPU_Msk /*!< Port H pin 3 I3C pull-up */ @@ -13964,6 +13173,9 @@ typedef struct #define RCC_AHB2ENR1_GPIOHEN_Pos (7UL) #define RCC_AHB2ENR1_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOHEN_Pos) /*!< 0x00000080 */ #define RCC_AHB2ENR1_GPIOHEN RCC_AHB2ENR1_GPIOHEN_Msk /*!< IO port H Enable */ +#define RCC_AHB2ENR1_ADC12EN_Pos (10UL) +#define RCC_AHB2ENR1_ADC12EN_Msk (0x1UL << RCC_AHB2ENR1_ADC12EN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2ENR1_ADC12EN RCC_AHB2ENR1_ADC12EN_Msk /*!< ADC12 Enable */ #define RCC_AHB2ENR1_DAC1EN_Pos (11UL) #define RCC_AHB2ENR1_DAC1EN_Msk (0x1UL << RCC_AHB2ENR1_DAC1EN_Pos) /*!< 0x00000800 */ #define RCC_AHB2ENR1_DAC1EN RCC_AHB2ENR1_DAC1EN_Msk /*!< DAC1 Enable */ @@ -14610,41 +13822,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -14658,7 +13870,7 @@ typedef struct #define RNG_SR_SECS RNG_SR_SECS_Msk #define RNG_SR_BUSY_Pos (4UL) #define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ -#define RNG_SR_BUSY RNG_SR_BUSY_Msk +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ #define RNG_SR_CEIS_Pos (5UL) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk @@ -14668,15 +13880,138 @@ typedef struct /******************** Bits definition for RNG_NSCR register *******************/ #define RNG_NSCR_EN_OSC1_Pos (0UL) -#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ #define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk #define RNG_NSCR_EN_OSC2_Pos (3UL) -#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ #define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk -#define RNG_NSCR_EN_OSC3_Pos (06UL) -#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +/******************** Bits definition for RNG_HTCR0 register *******************/ +#define RNG_HTCR0_HTCFG_Pos (0UL) +#define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR0_HTCFG RNG_HTCR0_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR1 register *******************/ +#define RNG_HTCR1_HTCFG_Pos (0UL) +#define RNG_HTCR1_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR1_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR1_HTCFG RNG_HTCR1_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR2 register *******************/ +#define RNG_HTCR2_HTCFG_Pos (0UL) +#define RNG_HTCR2_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR2_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR2_HTCFG RNG_HTCR2_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR3 register *******************/ +#define RNG_HTCR3_HTCFG_Pos (0UL) +#define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk + +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0UL) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1UL) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2UL) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3UL) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4UL) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5UL) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6UL) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7UL) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8UL) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9UL) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0UL) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1UL) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2UL) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3UL) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4UL) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5UL) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6UL) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7UL) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8UL) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9UL) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0UL) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1UL) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2UL) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3UL) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4UL) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5UL) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6UL) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7UL) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8UL) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ @@ -19026,6 +18361,7 @@ typedef struct #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || ((INSTANCE) == ADC1_S)) +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_COMMON_NS)) /******************************* AES Instances ********************************/ #define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) @@ -19168,6 +18504,8 @@ typedef struct #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (0) + #define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) @@ -19175,6 +18513,7 @@ typedef struct #define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (0) /****************** LPTIM Instances : All supported instances *****************/ #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ @@ -19598,10 +18937,11 @@ typedef struct #else /* CPU_IN_SECURE_STATE */ /******************************* ADC Instances ********************************/ -#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_NS) +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS)) #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_NS) +#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON_NS) /******************************* AES Instances ********************************/ #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES_NS) @@ -19737,6 +19077,8 @@ typedef struct #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \ ((INSTANCE) == SPI2_NS)) +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (0) + #define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \ ((INSTANCE) == SPI2_NS)) @@ -19744,6 +19086,7 @@ typedef struct #define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \ ((INSTANCE) == SPI2_NS)) +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (0) /****************** LPTIM Instances : All supported instances *****************/ #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) ||\ @@ -20168,7 +19511,7 @@ typedef struct #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_DRD_FS_NS) #endif /* CPU_IN_SECURE_STATE */ -/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */ +/** @} */ /* End of group STM32U3xx_Peripheral_Exported_macros */ /** @} */ /* End of group STM32U345xx */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u356xx.h b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u356xx.h index f037172ab3..3efb597a35 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u356xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u356xx.h @@ -893,7 +893,10 @@ typedef struct __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ } RNG_TypeDef; /** @@ -10811,6 +10814,9 @@ typedef struct #define PWR_WUCR2_WUPP8_Pos (7UL) #define PWR_WUCR2_WUPP8_Msk (0x1UL << PWR_WUCR2_WUPP8_Pos) /*!< 0x00000080 */ #define PWR_WUCR2_WUPP8 PWR_WUCR2_WUPP8_Msk /*!< Wakeup line WKUP8 polarity */ +#define PWR_WUCR2_WUPP10_Pos (9UL) +#define PWR_WUCR2_WUPP10_Msk (0x1UL << PWR_WUCR2_WUPP10_Pos) /*!< 0x00000100 */ +#define PWR_WUCR2_WUPP10 PWR_WUCR2_WUPP10_Msk /*!< Wakeup line WKUP10 polarity */ /******************* Bit definition for PWR_WUCR3 register ******************/ #define PWR_WUCR3_WUSEL1_Pos (0UL) @@ -11552,6 +11558,9 @@ typedef struct #define PWR_I3CPUCR1_PB13_I3CPU_Pos (10UL) #define PWR_I3CPUCR1_PB13_I3CPU_Msk (0x1UL << PWR_I3CPUCR1_PB13_I3CPU_Pos) /*!< 0x00000400 */ #define PWR_I3CPUCR1_PB13_I3CPU PWR_I3CPUCR1_PB13_I3CPU_Msk /*!< Port B pin 13 I3C pull-up */ +#define PWR_I3CPUCR1_PB7_I3CPU_Pos (12UL) +#define PWR_I3CPUCR1_PB7_I3CPU_Msk (0x1UL << PWR_I3CPUCR1_PB7_I3CPU_Pos) /*!< 0x00001000 */ +#define PWR_I3CPUCR1_PB7_I3CPU PWR_I3CPUCR1_PB7_I3CPU_Msk /*!< Port B pin 7 I3C pull-up */ /******************** Bit definition for PWR_I3CPUCR2 register *****************/ #define PWR_I3CPUCR2_PC1_I3CPU_Pos (1UL) @@ -13081,41 +13090,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -13129,7 +13138,7 @@ typedef struct #define RNG_SR_SECS RNG_SR_SECS_Msk #define RNG_SR_BUSY_Pos (4UL) #define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ -#define RNG_SR_BUSY RNG_SR_BUSY_Msk +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ #define RNG_SR_CEIS_Pos (5UL) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk @@ -13139,15 +13148,138 @@ typedef struct /******************** Bits definition for RNG_NSCR register *******************/ #define RNG_NSCR_EN_OSC1_Pos (0UL) -#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ #define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk #define RNG_NSCR_EN_OSC2_Pos (3UL) -#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ #define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk -#define RNG_NSCR_EN_OSC3_Pos (06UL) -#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +/******************** Bits definition for RNG_HTCR0 register *******************/ +#define RNG_HTCR0_HTCFG_Pos (0UL) +#define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR0_HTCFG RNG_HTCR0_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR1 register *******************/ +#define RNG_HTCR1_HTCFG_Pos (0UL) +#define RNG_HTCR1_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR1_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR1_HTCFG RNG_HTCR1_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR2 register *******************/ +#define RNG_HTCR2_HTCFG_Pos (0UL) +#define RNG_HTCR2_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR2_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR2_HTCFG RNG_HTCR2_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR3 register *******************/ +#define RNG_HTCR3_HTCFG_Pos (0UL) +#define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk + +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0UL) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1UL) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2UL) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3UL) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4UL) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5UL) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6UL) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7UL) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8UL) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9UL) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0UL) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1UL) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2UL) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3UL) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4UL) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5UL) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6UL) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7UL) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8UL) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9UL) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0UL) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1UL) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2UL) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3UL) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4UL) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5UL) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6UL) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7UL) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8UL) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ @@ -19785,7 +19917,7 @@ typedef struct #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_DRD_FS_NS) #endif /* CPU_IN_SECURE_STATE */ -/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */ +/** @} */ /* End of group STM32U3xx_Peripheral_Exported_macros */ /** @} */ /* End of group STM32U356xx */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u366xx.h b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u366xx.h index e2d424022d..db6dc39bfd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u366xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u366xx.h @@ -940,7 +940,10 @@ typedef struct __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ } RNG_TypeDef; /** @@ -3936,7 +3939,7 @@ typedef struct /******************************************************************************/ /* Specific device feature definitions */ -#define HW_SANITY_CHECK_SUPPORT /*!< CCB feature available only on specific devices: HW Sanity check is available on U3 2M devices */ +#define HW_SANITY_CHECK_SUPPORT /*!< CCB feature available only on specific devices: HW Sanity check is available on U3 512K, 1.5M and 2M devices */ /******************* Bit definition for CCB_CR register ******************/ #define CCB_CR_CCOP_Pos (0UL) @@ -11197,6 +11200,9 @@ typedef struct #define PWR_WUCR2_WUPP8_Pos (7UL) #define PWR_WUCR2_WUPP8_Msk (0x1UL << PWR_WUCR2_WUPP8_Pos) /*!< 0x00000080 */ #define PWR_WUCR2_WUPP8 PWR_WUCR2_WUPP8_Msk /*!< Wakeup line WKUP8 polarity */ +#define PWR_WUCR2_WUPP10_Pos (9UL) +#define PWR_WUCR2_WUPP10_Msk (0x1UL << PWR_WUCR2_WUPP10_Pos) /*!< 0x00000100 */ +#define PWR_WUCR2_WUPP10 PWR_WUCR2_WUPP10_Msk /*!< Wakeup line WKUP10 polarity */ /******************* Bit definition for PWR_WUCR3 register ******************/ #define PWR_WUCR3_WUSEL1_Pos (0UL) @@ -11938,6 +11944,9 @@ typedef struct #define PWR_I3CPUCR1_PB13_I3CPU_Pos (10UL) #define PWR_I3CPUCR1_PB13_I3CPU_Msk (0x1UL << PWR_I3CPUCR1_PB13_I3CPU_Pos) /*!< 0x00000400 */ #define PWR_I3CPUCR1_PB13_I3CPU PWR_I3CPUCR1_PB13_I3CPU_Msk /*!< Port B pin 13 I3C pull-up */ +#define PWR_I3CPUCR1_PB7_I3CPU_Pos (12UL) +#define PWR_I3CPUCR1_PB7_I3CPU_Msk (0x1UL << PWR_I3CPUCR1_PB7_I3CPU_Pos) /*!< 0x00001000 */ +#define PWR_I3CPUCR1_PB7_I3CPU PWR_I3CPUCR1_PB7_I3CPU_Msk /*!< Port B pin 7 I3C pull-up */ /******************** Bit definition for PWR_I3CPUCR2 register *****************/ #define PWR_I3CPUCR2_PC1_I3CPU_Pos (1UL) @@ -13494,41 +13503,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -13542,7 +13551,7 @@ typedef struct #define RNG_SR_SECS RNG_SR_SECS_Msk #define RNG_SR_BUSY_Pos (4UL) #define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ -#define RNG_SR_BUSY RNG_SR_BUSY_Msk +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ #define RNG_SR_CEIS_Pos (5UL) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk @@ -13552,15 +13561,138 @@ typedef struct /******************** Bits definition for RNG_NSCR register *******************/ #define RNG_NSCR_EN_OSC1_Pos (0UL) -#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ #define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk #define RNG_NSCR_EN_OSC2_Pos (3UL) -#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ #define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk -#define RNG_NSCR_EN_OSC3_Pos (06UL) -#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +/******************** Bits definition for RNG_HTCR0 register *******************/ +#define RNG_HTCR0_HTCFG_Pos (0UL) +#define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR0_HTCFG RNG_HTCR0_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR1 register *******************/ +#define RNG_HTCR1_HTCFG_Pos (0UL) +#define RNG_HTCR1_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR1_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR1_HTCFG RNG_HTCR1_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR2 register *******************/ +#define RNG_HTCR2_HTCFG_Pos (0UL) +#define RNG_HTCR2_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR2_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR2_HTCFG RNG_HTCR2_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR3 register *******************/ +#define RNG_HTCR3_HTCFG_Pos (0UL) +#define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk + +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0UL) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1UL) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2UL) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3UL) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4UL) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5UL) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6UL) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7UL) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8UL) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9UL) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0UL) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1UL) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2UL) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3UL) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4UL) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5UL) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6UL) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7UL) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8UL) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9UL) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0UL) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1UL) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2UL) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3UL) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4UL) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5UL) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6UL) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7UL) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8UL) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ @@ -20211,7 +20343,7 @@ typedef struct #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_DRD_FS_NS) #endif /* CPU_IN_SECURE_STATE */ -/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */ +/** @} */ /* End of group STM32U3xx_Peripheral_Exported_macros */ /** @} */ /* End of group STM32U366xx */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u375xx.h b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u375xx.h index 6be009e191..e28e7e31c8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u375xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u375xx.h @@ -961,7 +961,10 @@ typedef struct __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ } RNG_TypeDef; /** @@ -14774,41 +14777,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -14822,7 +14825,7 @@ typedef struct #define RNG_SR_SECS RNG_SR_SECS_Msk #define RNG_SR_BUSY_Pos (4UL) #define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ -#define RNG_SR_BUSY RNG_SR_BUSY_Msk +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ #define RNG_SR_CEIS_Pos (5UL) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk @@ -14832,15 +14835,143 @@ typedef struct /******************** Bits definition for RNG_NSCR register *******************/ #define RNG_NSCR_EN_OSC1_Pos (0UL) -#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ #define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk #define RNG_NSCR_EN_OSC2_Pos (3UL) -#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ #define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk -#define RNG_NSCR_EN_OSC3_Pos (06UL) -#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +/******************** Bits definition for RNG_HTCR0 register *******************/ +#define RNG_HTCR0_HTCFG_Pos (0UL) +#define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR0_HTCFG RNG_HTCR0_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR1 register *******************/ +#define RNG_HTCR1_HTCFG_Pos (0UL) +#define RNG_HTCR1_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR1_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR1_HTCFG RNG_HTCR1_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR2 register *******************/ +#define RNG_HTCR2_HTCFG_Pos (0UL) +#define RNG_HTCR2_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR2_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR2_HTCFG RNG_HTCR2_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR3 register *******************/ +#define RNG_HTCR3_HTCFG_Pos (0UL) +#define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk + +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0UL) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1UL) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2UL) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3UL) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4UL) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5UL) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6UL) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7UL) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8UL) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9UL) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0UL) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1UL) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2UL) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3UL) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4UL) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5UL) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6UL) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7UL) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8UL) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9UL) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0UL) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1UL) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2UL) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3UL) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4UL) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5UL) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6UL) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7UL) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8UL) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************** RNG Nist Compliance Values ******************************/ +#define RNG_HTCRx_VALUE (0x0003FFFF) +#define RNG_CR_NIST_VALUE (0x08351F00U) +#define RNG_HTCR_NIST_VALUE (0x6A8BU) +#define RNG_NSCR_NIST_VALUE (0x01FFU) +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u385xx.h b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u385xx.h index 7802ff0c00..1c34fa900a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u385xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u385xx.h @@ -1008,7 +1008,10 @@ typedef struct __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ } RNG_TypeDef; /** @@ -15187,41 +15190,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -15235,7 +15238,7 @@ typedef struct #define RNG_SR_SECS RNG_SR_SECS_Msk #define RNG_SR_BUSY_Pos (4UL) #define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ -#define RNG_SR_BUSY RNG_SR_BUSY_Msk +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ #define RNG_SR_CEIS_Pos (5UL) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk @@ -15245,15 +15248,143 @@ typedef struct /******************** Bits definition for RNG_NSCR register *******************/ #define RNG_NSCR_EN_OSC1_Pos (0UL) -#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ #define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk #define RNG_NSCR_EN_OSC2_Pos (3UL) -#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ #define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk -#define RNG_NSCR_EN_OSC3_Pos (06UL) -#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +/******************** Bits definition for RNG_HTCR0 register *******************/ +#define RNG_HTCR0_HTCFG_Pos (0UL) +#define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR0_HTCFG RNG_HTCR0_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR1 register *******************/ +#define RNG_HTCR1_HTCFG_Pos (0UL) +#define RNG_HTCR1_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR1_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR1_HTCFG RNG_HTCR1_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR2 register *******************/ +#define RNG_HTCR2_HTCFG_Pos (0UL) +#define RNG_HTCR2_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR2_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR2_HTCFG RNG_HTCR2_HTCFG_Msk + +/******************** Bits definition for RNG_HTCR3 register *******************/ +#define RNG_HTCR3_HTCFG_Pos (0UL) +#define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk + +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0UL) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1UL) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2UL) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3UL) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4UL) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5UL) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6UL) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7UL) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8UL) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9UL) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0UL) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1UL) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2UL) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3UL) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4UL) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5UL) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6UL) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7UL) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8UL) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9UL) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0UL) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1UL) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2UL) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3UL) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4UL) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5UL) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6UL) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7UL) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8UL) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************** RNG Nist Compliance Values ******************************/ +#define RNG_HTCRx_VALUE (0x0003FFFF) +#define RNG_CR_NIST_VALUE (0x08351F00U) +#define RNG_HTCR_NIST_VALUE (0x6A8BU) +#define RNG_NSCR_NIST_VALUE (0x01FFU) +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u396xx.h b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u396xx.h deleted file mode 100644 index d1b5b1d033..0000000000 --- a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/stm32u396xx.h +++ /dev/null @@ -1,24147 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u396xx.h - * @author MCD Application Team - * @brief CMSIS STM32U396xx Device Peripheral Access Layer Header File. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral's registers hardware - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -#ifndef STM32U396xx_H -#define STM32U396xx_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup ST - * @{ - */ - -/** @addtogroup STM32U396xx - * @{ - */ - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define CPU_IN_SECURE_STATE -#endif - -/* ================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* ================================================================================================================== */ -typedef enum -{ - /* ================================== ARM Cortex-M33 Specific Interrupt Numbers =================================== */ - NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No - No Match */ - BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch, Memory Access Fault, other address/memory - related Fault */ - UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SecureFault_IRQn = -9, /*!< -9 Secure Fault */ - SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ - PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ - SysTick_IRQn = -1, /*!< -1 System Tick Timer */ - - /* ================================== STM32U396xx Specific Interrupt Numbers ================================= */ - WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ - PVD_PVM_IRQn = 1, /*!< PVD and PVM through EXTI Line detection Interrupt */ - RTC_IRQn = 2, /*!< RTC non-secure interrupt */ - RTC_S_IRQn = 3, /*!< RTC secure interrupt */ - TAMP_IRQn = 4, /*!< Tamper global interrupt */ - RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ - FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ - FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ - GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ - RCC_IRQn = 9, /*!< RCC non secure global interrupt */ - RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ - EXTI0_IRQn = 11, /*!< EXTI Line 0 interrupt */ - EXTI1_IRQn = 12, /*!< EXTI Line 1 interrupt */ - EXTI2_IRQn = 13, /*!< EXTI Line 2 interrupt */ - EXTI3_IRQn = 14, /*!< EXTI Line 3 interrupt */ - EXTI4_IRQn = 15, /*!< EXTI Line 4 interrupt */ - EXTI5_IRQn = 16, /*!< EXTI Line 5 interrupt */ - EXTI6_IRQn = 17, /*!< EXTI Line 6 interrupt */ - EXTI7_IRQn = 18, /*!< EXTI Line 7 interrupt */ - EXTI8_IRQn = 19, /*!< EXTI Line 8 interrupt */ - EXTI9_IRQn = 20, /*!< EXTI Line 9 interrupt */ - EXTI10_IRQn = 21, /*!< EXTI Line 10 interrupt */ - EXTI11_IRQn = 22, /*!< EXTI Line 11 interrupt */ - EXTI12_IRQn = 23, /*!< EXTI Line 12 interrupt */ - EXTI13_IRQn = 24, /*!< EXTI Line 13 interrupt */ - EXTI14_IRQn = 25, /*!< EXTI Line 14 interrupt */ - EXTI15_IRQn = 26, /*!< EXTI Line 15 interrupt */ - IWDG_IRQn = 27, /*!< IWDG global interrupt */ - GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ - GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ - GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ - GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ - GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ - GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ - GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ - GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ - ADC1_IRQn = 37, /*!< ADC1 global interrupt */ - DAC1_IRQn = 38, /*!< DAC1 global interrupt */ - FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ - FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ - TIM1_BRK_TERR_IERR_IRQn = 41, /*!< TIM1 Break, Transition error and Index error interrupt */ - TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ - TIM1_TRG_COM_DIR_IDX_IRQn = 43, /*!< TIM1 Trigger, Commutation, Direction change and Index interrupt */ - TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ - TIM2_IRQn = 45, /*!< TIM2 global interrupt */ - TIM3_IRQn = 46, /*!< TIM3 global interrupt */ - TIM4_IRQn = 47, /*!< TIM4 global interrupt */ - TIM6_IRQn = 49, /*!< TIM6 global interrupt */ - TIM7_IRQn = 50, /*!< TIM7 global interrupt */ - TIM12_IRQn = 51, /*!< TIM12 global interrupt */ - I3C1_EV_IRQn = 53, /*!< I3C1 event interrupt */ - I3C1_ER_IRQn = 54, /*!< I3C1 error interrupt */ - I2C1_EV_IRQn = 55, /*!< I2C1 Event interrupt */ - I2C1_ER_IRQn = 56, /*!< I2C1 Error interrupt */ - I2C2_EV_IRQn = 57, /*!< I2C2 Event interrupt */ - I2C2_ER_IRQn = 58, /*!< I2C2 Error interrupt */ - SPI1_IRQn = 59, /*!< SPI1 global interrupt */ - SPI2_IRQn = 60, /*!< SPI2 global interrupt */ - USART1_IRQn = 61, /*!< USART1 global interrupt */ - USART2_IRQn = 62, /*!< USART2 global interrupt */ - USART3_IRQn = 63, /*!< USART3 global interrupt */ - UART4_IRQn = 64, /*!< UART4 global interrupt */ - UART5_IRQn = 65, /*!< UART5 global interrupt */ - LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */ - LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */ - LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */ - TIM15_IRQn = 69, /*!< TIM15 global interrupt */ - TIM16_IRQn = 70, /*!< TIM16 global interrupt */ - TIM17_IRQn = 71, /*!< TIM17 global interrupt */ - COMP_IRQn = 72, /*!< COMP1 and COMP2 through EXTI Lines interrupts */ - USB_FS_IRQn = 73, /*!< USB FS global interrupt */ - CRS_IRQn = 74, /*!< CRS global interrupt */ - FMC_IRQn = 75, /*!< FMC global interrupt */ - OCTOSPI1_IRQn = 76, /*!< OctoSPI1 global interrupt */ - HSP1_IRQn = 77, /*!< HSP1 global interrupt */ - SDMMC1_IRQn = 78, /*!< SDMMC1 global interrupt */ - GPDMA1_Channel8_IRQn = 80, /*!< GPDMA1 Channel 8 global interrupt */ - GPDMA1_Channel9_IRQn = 81, /*!< GPDMA1 Channel 9 global interrupt */ - GPDMA1_Channel10_IRQn = 82, /*!< GPDMA1 Channel 10 global interrupt */ - GPDMA1_Channel11_IRQn = 83, /*!< GPDMA1 Channel 11 global interrupt */ - I2C3_EV_IRQn = 88, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 89, /*!< I2C3 error interrupt */ - SAI1_IRQn = 90, /*!< Serial Audio Interface 1 global interrupt */ - TSC_IRQn = 92, /*!< Touch Sense Controller global interrupt */ - RNG_IRQn = 94, /*!< RNG global interrupt */ - FPU_IRQn = 95, /*!< FPU global interrupt */ - HASH_IRQn = 96, /*!< HASH global interrupt */ - PKA_IRQn = 97, /*!< PKA global interrupt */ - LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */ - SPI3_IRQn = 99, /*!< SPI3 global interrupt */ - I3C2_EV_IRQn = 100, /*!< I3C2 Event interrupt */ - I3C2_ER_IRQn = 101, /*!< I3C2 Error interrupt */ - TIM8_BRK_TERR_IERR_IRQn = 102, /*!< TIM8 Break, Transition error and Index error interrupt */ - TIM8_UP_IRQn = 103, /*!< TIM8 Update interrupt */ - TIM8_TRG_COM_DIR_IDX_IRQn = 104, /*!< TIM8 Trigger, Commutation, Direction change and Index interrupt */ - TIM8_CC_IRQn = 105, /*!< TIM8 Capture Compare interrupt */ - ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */ - GFXPAND1_IRQn = 108, /*!< GFXPAND1 global interrupt */ - LCD_IRQn = 109, /*!< LCD global interrupt */ - LPTIM4_IRQn = 110, /*!< LPTIM4 global interrupt */ - ADF1_IRQn = 112, /*!< ADF1 interrupt */ - ADC2_IRQn = 113, /*!< ADC2 (12bits) global interrupt */ - DMA2D_IRQn = 118, /*!< DMA2D global interrupt */ - OCTOSPI2_IRQn = 120, /* OCTOSPI global interrupt */ - PWR_IRQn = 123, /*!< PWR non-secure interrupt */ - PWR_S_IRQn = 124 /*!< PWR secure interrupt */ -} IRQn_Type; - -/* ================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================================================== */ -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - -/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ -#define __CM33_REV 0x0000U /* Core revision r0p4 */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __DSP_PRESENT 1U /* DSP extension present */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ -#include "system_stm32u3xx.h" /*!< STM32U3xx System */ - - -/* ================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================================================== */ -/** @addtogroup STM32U3xx_peripherals - * @{ - */ - -/** - * @brief ADC Analog to Digital Converter - */ -typedef struct -{ - __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ - __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ - __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ - __IO uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x1C */ - uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x20 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ - uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x44 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ - __IO uint32_t OFCFGR1; /*!< ADC offset configuration register 1, Address offset: 0x50 */ - __IO uint32_t OFCFGR2; /*!< ADC offset configuration register 2, Address offset: 0x54 */ - __IO uint32_t OFCFGR3; /*!< ADC offset configuration register 3, Address offset: 0x58 */ - __IO uint32_t OFCFGR4; /*!< ADC offset configuration register 4, Address offset: 0x5C */ - __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ - __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ - __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ - __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ - __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ - uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x74 */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ - uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x90 */ - __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ - __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ - __IO uint32_t AWD1LTR; /*!< ADC analog watchdog 1 low threshold register, Address offset: 0xA8 */ - __IO uint32_t AWD1HTR; /*!< ADC analog watchdog 1 high threshold register, Address offset: 0xAC */ - __IO uint32_t AWD2LTR; /*!< ADC analog watchdog 2 low threshold register, Address offset: 0xB0 */ - __IO uint32_t AWD2HTR; /*!< ADC analog watchdog 2 high threshold register, Address offset: 0xB4 */ - __IO uint32_t AWD3LTR; /*!< ADC analog watchdog 3 low threshold register, Address offset: 0xB8 */ - __IO uint32_t AWD3HTR; /*!< ADC analog watchdog 3 high threshold register, Address offset: 0xBC */ - uint32_t RESERVED5; /*!< Reserved, Address offset: 0xC0 */ - __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xC4 */ - uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0xC8 */ - __IO uint32_t OR; /*!< ADC option register, Address offset: 0xD0 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for dual mode 32-bit, Address offset: 0x310 */ -} ADC_Common_TypeDef; - - -/** - * @brief Comparator - */ -typedef struct -{ - __IO uint32_t CSR; /*!< Comparator control/status register , Address offset: 0x00 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ - __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ -} COMP_Common_TypeDef; - -/** - * @brief CRC calculation unit - */ -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief DAC - */ -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ - __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ - __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ - __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ - __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ - __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ - __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ - __IO uint32_t RESERVED[1]; - __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1LFZR; /*!< Debug MCU APB1L freeze register, Address offset: 0x08 */ - __IO uint32_t APB1HFZR; /*!< Debug MCU APB1H freeze register, Address offset: 0x0C */ - __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ - __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x20 */ - __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ - uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xFC */ - __IO uint32_t SR; /*!< Debug MCU status register, Address offset: 0xFC */ - __IO uint32_t DGB_AUTH_HOST; /*!< Debug MCU debug host authentication register, Address offset: 0x100 */ - __IO uint32_t DGB_AUTH_DEVICE; /*!< Debug MCU debug device authentication register, Address offset: 0x104 */ - uint32_t RESERVED3[946]; /*!< Reserved, 0x108 - 0xFD0 */ - __IO uint32_t PIDR4; /*!< Debug MCU CoreSight peripheral identity register 4, Address offset: 0xFD0 */ - __IO uint32_t PIDR0; /*!< Debug MCU CoreSight peripheral identity register 0, Address offset: 0xFE0 */ - __IO uint32_t PIDR1; /*!< Debug MCU CoreSight peripheral identity register 1, Address offset: 0xFE4 */ - __IO uint32_t PIDR2; /*!< Debug MCU CoreSight peripheral identity register 2, Address offset: 0xFE8 */ - __IO uint32_t PIDR3; /*!< Debug MCU CoreSight peripheral identity register 3, Address offset: 0xFEC */ - __IO uint32_t CIDR0; /*!< Debug MCU CoreSight component identity register 0, Address offset: 0xFF0 */ - __IO uint32_t CIDR1; /*!< Debug MCU CoreSight component identity register 1, Address offset: 0xFF4 */ - __IO uint32_t CIDR2; /*!< Debug MCU CoreSight component identity register 2, Address offset: 0xFF8 */ - __IO uint32_t CIDR3; /*!< Debug MCU CoreSight component identity register 3, Address offset: 0xFFC */ -} DBGMCU_TypeDef; - -/** - * @ brief Delay Block - */ -typedef struct -{ - __IO uint32_t CR; /*!< Delay Block Control Register, Address offset: 0x00 */ - __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */ -} DLYB_TypeDef; - -/** - * @brief DMA Controller - */ -typedef struct -{ - __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ - __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ - __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ - __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ - __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ - uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ - __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ - __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ - __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ - uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ - __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ - __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ - __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ - __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ - __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ - __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ - __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ - uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ - __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ -} DMA_Channel_TypeDef; - -/** - * @brief Asynch Interrupt/Event Controller (EXTI) - */ -typedef struct -{ - __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ - __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ - __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ - __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ - __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ - __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ - __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ - uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ - __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ - __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ - uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ - __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ - __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ -} EXTI_TypeDef; - -/** - * @brief FD Controller Area Network - */ -typedef struct -{ - __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ - __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ - uint32_t RESERVED1; /*!< Reserved, 0x008 */ - __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ - __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ - __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ - __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ - __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ - __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ - __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ - __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ - __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ - uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ - __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ - __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ - __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ - uint32_t RESERVED3; /*!< Reserved, 0x04C */ - __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ - __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ - __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ - __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ - uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ - __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ - __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ - __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ - uint32_t RESERVED5; /*!< Reserved, 0x08C */ - __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ - __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ - __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ - __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ - uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ - __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ - __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ - __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ - __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ - __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ - __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ - __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ - __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ - __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ - __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ - __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ -} FDCAN_GlobalTypeDef; - -/** - * @brief FD Controller Area Network Configuration - */ -typedef struct -{ - __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ - uint32_t RESERVED1[128]; /*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ - __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ - uint32_t RESERVED2[58]; /*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ - __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ - __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ - __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ - __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ -} FDCAN_Config_TypeDef; - -/** - * @brief FLASH Registers - */ -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x04 */ - __IO uint32_t KEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ - __IO uint32_t SKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x14 */ - __IO uint32_t PDKEY1R; /*!< FLASH bank 1 power-down key register, Address offset: 0x18 */ - __IO uint32_t PDKEY2R; /*!< FLASH bank 2 power-down key register, Address offset: 0x1C */ - __IO uint32_t SR; /*!< FLASH non-secure status register, Address offset: 0x20 */ - __IO uint32_t SSR; /*!< FLASH secure status register, Address offset: 0x24 */ - __IO uint32_t CR; /*!< FLASH non-secure control register, Address offset: 0x28 */ - __IO uint32_t SCR; /*!< FLASH secure control register, Address offset: 0x2C */ - __IO uint32_t ECCCR; /*!< FLASH ECC correction register, Address offset: 0x30 */ - __IO uint32_t ECCDR; /*!< FLASH ECC detection register, Address offset: 0x34 */ - __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x38 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x3C */ - __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ - __IO uint32_t BOOT0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ - __IO uint32_t BOOT1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ - __IO uint32_t SBOOT0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ - __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ - __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ - __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ - __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ - __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ - __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ - __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ - __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ - uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x70-0x7C */ - __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ - __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ - __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ - __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ - uint32_t RESERVED5[4]; /*!< Reserved, Address offset: 0x90-0x9C */ - __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ - __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ - __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ - __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ - uint32_t RESERVED6[4]; /*!< Reserved, Address offset: 0xB0-0xBC */ - __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ - __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ - __IO uint32_t SECHDPEXTR; /*!< FLASH HDP extension register, Address offset: 0xC8 */ - uint32_t RESERVED7; /*!< Reserved, Address offset: 0xCC */ - __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ - __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ - __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ - __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ - uint32_t RESERVED8[4]; /*!< Reserved, Address offset: 0xE0-0xEC */ - __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ - __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ - __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ - __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ - uint32_t RESERVED9[4]; /*!< Reserved, Address offset: 0x100-0x10C */ - __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x110 */ - __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x114 */ - __IO uint32_t OEM1KEYR3; /*!< FLASH OEM1 key register 3, Address offset: 0x118 */ - __IO uint32_t OEM1KEYR4; /*!< FLASH OEM1 key register 4, Address offset: 0x11C */ - __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x120 */ - __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x124 */ - __IO uint32_t OEM2KEYR3; /*!< FLASH OEM2 key register 3, Address offset: 0x128 */ - __IO uint32_t OEM2KEYR4; /*!< FLASH OEM2 key register 4, Address offset: 0x12C */ - __IO uint32_t OEMKEYSR; /*!< FLASH OEM key status register, Address offset: 0x130 */ -} FLASH_TypeDef; - -/** - * @brief General Purpose I/O - */ -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ - __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ -} GPIO_TypeDef; - -typedef struct -{ - __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ - __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ - __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ - __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ - __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ - __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ - __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ - __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ - __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ - __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ - __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ - __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ -} GTZC_TZIC_TypeDef; - -typedef struct -{ - __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ - uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ - __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register, Address offset: 0x10 */ - uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ - __IO uint32_t SECCFGR[12]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x12C */ - uint32_t RESERVED3[52]; /*!< Reserved3, Address offset: 0x130-0x200 */ - __IO uint32_t PRIVCFGR[12]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x22C */ -} GTZC_MPCBB_TypeDef; - -/** - * @brief Global TrustZone Controller - */ -typedef struct -{ - __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ - uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ - __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ - __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ - __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ - uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ - __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ - __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ - __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ -} GTZC_TZSC_TypeDef; - -/** - * @brief HASH - */ -typedef struct -{ - __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ - __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ - __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ - __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ - __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ - __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ - __IO uint32_t SHA3CFGR; /*!< HASH SHA-3 configuration register, Address offset: 0x28 */ - uint32_t RESERVED[51]; /*!< Reserved, 0x2C-0xF4 */ - __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ -} HASH_TypeDef; - -/** - * @brief HASH_DIGEST - */ -typedef struct -{ - __IO uint32_t HR[50]; /*!< HASH digest registers, Address offset: 0x310-0x3D4 */ -} HASH_DIGEST_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ - __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ - __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ - __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ - __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ - __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ - __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ - __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ - __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ - __IO uint32_t AUTOCR; /*!< I2C Autonomous mode control register, Address offset: 0x2C */ -} I2C_TypeDef; - -/** - * @brief Improved Inter-integrated Circuit Interface - */ -typedef struct -{ - __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ - __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ - uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ - __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ - __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ - __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ - __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ - __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ - __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ - uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ - __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ - uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ - __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ - uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ - __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ - __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ - __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ - __IO uint32_t MISR; /*!< I3C Masked Interrupt Status register, Address offset: 0x5C */ - __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ - __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ - uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ - __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ - __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ - uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ - __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ - __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ - __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ - uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ - __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ - __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ - __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ - __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ - __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ - __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ -} I3C_TypeDef; - -/** - * @brief Instruction Cache - */ -typedef struct -{ - __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ - __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ - __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ - __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ - __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x018-0x01C */ - __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ - __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ - __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ - __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ -} ICACHE_TypeDef; - -/** - * @brief IWDG - */ -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ - __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ - __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ -} IWDG_TypeDef; - -/** - * @brief LCD - */ -typedef struct -{ - __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ - __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ - __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ - __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ -} LCD_TypeDef; - -/** - * @brief LPTIMER - */ -typedef struct -{ - __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ - __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ - __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ - __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ - __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ - __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ - __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ - __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ - __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ - __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ - __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ -} LPTIM_TypeDef; - -/** - * @brief MDF/ADF - */ -typedef struct -{ - __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ - __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ - uint32_t RESERVED0[6]; /*!< Reserved, 0x08-0x1C */ - __IO uint32_t TRGISELR; /*!< MDF Trigger Input Selection Register, Address offset: 0x20 */ -} MDF_TypeDef; - -/** - * @brief MDF/ADF filter - */ -typedef struct -{ - __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ - __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ - __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ - __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ - __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ - uint32_t RESERVED0[4]; /*!< Reserved, 0x94-0xA0 */ - __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ - uint32_t RESERVED1[1]; /*!< Reserved, 0xA8 */ - __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ - __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ - uint32_t RESERVED2[1]; /*!< Reserved, 0xB4 */ - __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ - __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ - __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ - __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ - uint32_t RESERVED3[10]; /*!< Reserved, 0xC8-0xEC */ - __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ -} MDF_Filter_TypeDef; - -/** - * @brief Operational Amplifier (OPAMP) - */ -typedef struct -{ - __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ - __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ - __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ -} OPAMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to - several OPAMP instances, Address offset: 0x00 */ -} OPAMP_Common_TypeDef; - -/** - * @brief PKA - */ -typedef struct -{ - __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ - __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ - uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ - __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ -} PKA_TypeDef; - -/** - * @brief Power Control - */ -typedef struct -{ - __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ - __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ - __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ - __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ - __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ - __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ - __IO uint32_t BDCR; /*!< Power backup domain control register, Address offset: 0x24 */ - __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x2C */ - __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ - __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ - __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ - __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */ - __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ - __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ - __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ - __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ - __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ - __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ - __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ - __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ - __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ - __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ - __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ - __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ - __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ - __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ - __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ - __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ - __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ - __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ - __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ - uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x90 -> 0xAC */ - __IO uint32_t I3CPUCR1; /*!< Power I3C pull-up control register 1, Address offset: 0xB0 */ - __IO uint32_t I3CPUCR2; /*!< Power I3C pull-up control register 2, Address offset: 0xB4 */ -} PWR_TypeDef; - -/** - * @brief SRAMs configuration controller - */ -typedef struct -{ - __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< Interrupt enable register, Address offset: 0x04 */ - __IO uint32_t ISR; /*!< Interrupt status register, Address offset: 0x08 */ - uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ - __IO uint32_t PEAR; /*!< Parity error address register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< Interrupt clear register, Address offset: 0x14 */ - __IO uint32_t WPR1; /*!< Write protection register 1, Address offset: 0x18 */ - __IO uint32_t WPR2; /*!< Write protection register 2, Address offset: 0x1C */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ - __IO uint32_t PARKEYR; /*!< Parity key register, Address offset: 0x24 */ - __IO uint32_t ERKEYR; /*!< Erase key register, Address offset: 0x28 */ -}RAMCFG_TypeDef; - -/** - * @brief Reset and Clock Control - */ -typedef struct -{ - __IO uint32_t CR; /*!< RCC Clock Control Register Address offset: 0x000 */ - uint32_t RESERVED0; /*!< Reserved Address offset: 0x004 */ - __IO uint32_t ICSCR1; /*!< RCC Internal Clock Sources Calibration Register 1 Address offset: 0x008 */ - __IO uint32_t ICSCR2; /*!< RCC Internal Clock Sources Calibration Register 2 Address offset: 0x00C */ - __IO uint32_t ICSCR3; /*!< RCC Internal Clock Sources Calibration Register 3 Address offset: 0x010 */ - __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x014 */ - uint32_t RESERVED1; /*!< Reserved Address offset: 0x018 */ - __IO uint32_t CFGR1; /*!< RCC Clock Configuration Register 1 Address offset: 0x01C */ - __IO uint32_t CFGR2; /*!< RCC Clock Configuration Register 2 Address offset: 0x020 */ - __IO uint32_t CFGR3; /*!< RCC Clock Configuration Register 3 Address offset: 0x024 */ - __IO uint32_t CFGR4; /*!< RCC Clock Configuration Register 4 Address offset: 0x028 */ - uint32_t RESERVED2[9]; /*!< Reserved Address offset: 0x02C */ - __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x050 */ - __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x054 */ - __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x058 */ - uint32_t RESERVED3; /*!< Reserved Address offset: 0x05C */ - __IO uint32_t AHB1RSTR1; /*!< AHB1 Peripherals Reset Register 1 Address offset: 0x060 */ - __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x064 */ - __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x068 */ - uint32_t RESERVED4[2]; /*!< Reserved Address offset: 0x06C */ - __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x074 */ - __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x078 */ - __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x07C */ - __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x080 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x084 */ - __IO uint32_t AHB1ENR1; /*!< AHB1 Peripherals Clock Enable Register 1 Address offset: 0x088 */ - __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x08C */ - __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x090 */ - __IO uint32_t AHB1ENR2; /*!< AHB1 Peripherals Clock Enable Register 2 Address offset: 0x094 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x098 */ - __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x09C */ - __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0x0A0 */ - __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0x0A4 */ - __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0x0A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x0AC */ - __IO uint32_t AHB1SLPENR1; /*!< AHB1 Peripherals Clock Enable in Sleep Mode Register 1 Address offset: 0x0B0 */ - __IO uint32_t AHB2SLPENR1; /*!< AHB2 Peripherals Clock Enable in Sleep Mode Register 1 Address offset: 0x0B4 */ - __IO uint32_t AHB2SLPENR2; /*!< AHB2 Peripherals Clock Enable in Sleep Mode Register 2 Address offset: 0x0B8 */ - __IO uint32_t AHB1SLPENR2; /*!< AHB1 Peripherals Clock Enable in Sleep Mode Register 2 Address offset: 0x0BC */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x0C0 */ - __IO uint32_t APB1SLPENR1; /*!< APB1 Peripherals Clock Enable in Sleep Mode Register 1 Address offset: 0x0C4 */ - __IO uint32_t APB1SLPENR2; /*!< APB1 Peripherals Clock Enable in Sleep Mode Register 2 Address offset: 0x0C8 */ - __IO uint32_t APB2SLPENR; /*!< APB2 Peripherals Clock Enable in Sleep Mode Register Address offset: 0x0CC */ - __IO uint32_t APB3SLPENR; /*!< APB3 Peripherals Clock Enable in Sleep Mode Register Address offset: 0x0D0 */ - uint32_t RESERVED9; /*!< Reserved Address offset: 0x0D4 */ - __IO uint32_t AHB1STPENR1; /*!< AHB1 Peripherals Clock Enable in Stop Mode Register 1 Address offset: 0x0D8 */ - __IO uint32_t AHB2STPENR1; /*!< AHB2 Peripherals Clock Enable in Stop Mode Register 1 Address offset: 0x0DC */ - uint32_t RESERVED10[3]; /*!< Reserved Address offset: 0x0E0 */ - __IO uint32_t APB1STPENR1; /*!< APB1 Peripherals Clock Enable in Stop Mode Register 1 Address offset: 0x0EC */ - __IO uint32_t APB1STPENR2; /*!< APB1 Peripherals Clock Enable in Stop Mode Register 2 Address offset: 0x0F0 */ - __IO uint32_t APB2STPENR; /*!< APB2 Peripherals Clock Enable in Stop Mode Register Address offset: 0x0F4 */ - __IO uint32_t APB3STPENR; /*!< APB3 Peripherals Clock Enable in Stop Mode Register Address offset: 0x0F8 */ - uint32_t RESERVED11; /*!< Reserved Address offset: 0x0FC */ - __IO uint32_t CCIPR1; /*!< Peripherals Independent Clocks Configuration Register 1 Address offset: 0x100 */ - __IO uint32_t CCIPR2; /*!< Peripherals Independent Clocks Configuration Register 2 Address offset: 0x104 */ - __IO uint32_t CCIPR3; /*!< Peripherals Independent Clocks Configuration Register 3 Address offset: 0x108 */ - uint32_t RESERVED12; /*!< Reserved Address offset: 0x10C */ - __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0x110 */ - __IO uint32_t CSR; /*!< Control & Status Register Address offset: 0x114 */ - uint32_t RESERVED13[6]; /*!< Reserved Address offset: 0x118 */ - __IO uint32_t SECCFGR; /*!< RCC Secure Configuration Register Address offset: 0x130 */ - __IO uint32_t PRIVCFGR; /*!< RCC Privilege Configuration Register Address offset: 0x134 */ -} RCC_TypeDef; - -/** - * @brief RNG - */ -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ -} RNG_TypeDef; - -/** - * @brief Real-Time Clock - */ -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ - __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x60 */ - __IO uint32_t TAMPTSCR; /*!< RTC timestamp on tamper control register, Address offset: 0x64 */ - __IO uint32_t TSIDR; /*!< RTC timestamp status register, Address offset: 0x68 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x6C */ - __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ - __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ -} RTC_TypeDef; - -/** - * @brief Serial Audio Interface - */ -typedef struct -{ - uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ - __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ - __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ -} SAI_TypeDef; - -typedef struct -{ - __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ - __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ - __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ - __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ - __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ - __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ -} SAI_Block_TypeDef; - -/** - * @brief Secure digital input/output Interface - */ -typedef struct -{ - __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ - __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ - uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ - __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ - __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ - __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ - __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ - __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ - uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ -} SDMMC_TypeDef; - -/** - * @brief SPI - */ -typedef struct -{ - __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ - __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ - __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ - __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ - __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ - __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ - __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ - __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ - uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ - __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ - uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ - __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ - __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ - __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ - __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ -} SPI_TypeDef; - -/** - * @brief System configuration controller - */ -typedef struct -{ - __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ - __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ - __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ - __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ - __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ - __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ - __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ - uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x28 */ - __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ -} SYSCFG_TypeDef; - -/** - * @brief Tamper and backup registers - */ -typedef struct -{ - __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ - __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - uint32_t RESERVED1[4]; /*!< Reserved, 0x10 -- 0x1C */ - __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ - __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ - uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ - __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ - __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ - __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ - __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ - __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ - __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ - uint32_t RESERVED2[4]; /*!< Reserved, 0x44 -- 0x50 */ - __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ - uint32_t RESERVED3[42]; /*!< Reserved, 0x58 -- 0xFC */ - __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ - __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ - __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ - __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ - __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ - __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ - __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ - __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ - __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ - __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ - __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ - __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ - __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ - __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ - __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ - __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ - __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ - __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ - __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ - __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ - __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ - __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ - __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ - __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ - __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ - __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ - __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ - __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ - __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ - __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ - __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ - __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ -} TAMP_TypeDef; - -/** - * @brief Touch Sensing Controller (TSC) - */ -typedef struct -{ - __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ - __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ - __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ - __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ - __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ - __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ - __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ - __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, 0x34-0x4C */ -} TSC_TypeDef; - -/** - * @brief TIM - */ -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ - __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ - __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ - __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ - __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ - __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ - __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ - __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ - __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ - uint32_t RESERVED0[220]; /*!< Reserved, Address offset: 0x6C */ - __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ - __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ -typedef struct -{ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ - __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ - __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ - __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ -} USART_TypeDef; - -/** - * @brief Universal Serial Bus Full Speed Dual Role Device - */ -typedef struct -{ - __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ - __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ - __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ - __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ - __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ - __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ - __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ - __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ - __IO uint32_t RESERVED0[8]; /*!< Reserved, */ - __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ - __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ - __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ - __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ - __IO uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ - __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ -} USB_DRD_TypeDef; - -/** - * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table - */ -typedef struct -{ - __IO uint32_t TXBD; /*!= 6010050) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* ================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* ================================================================================================================== */ -/** @addtogroup STM32U3xx_Peripheral_peripheralAddr - * @{ - */ - -/*!< Flash, Peripheral and internal SRAMs base addresses - Non secure */ -#define FLASH_BASE_NS 0x08000000UL /*!< FLASH non-secure base address */ -#define SYSTEM_FLASH_BASE_NS 0x0BF80000UL /*!< System FLASH non-secure base address */ -#define SRAM1_BASE_NS 0x20000000UL /*!< SRAM1 non-secure base address */ -#define SRAM2_BASE_NS 0x20018000UL /*!< SRAM2 non-secure base address */ -#define SRAM3_BASE_NS 0x20028000UL /*!< SRAM3 non-secure base address */ -#define SRAM4_BASE_NS 0x20068000UL /*!< SRAM4 non-secure base address */ - -#define PERIPH_BASE_NS 0x40000000UL /*!< Peripheral non-secure base address */ -#define EXTRAM_BASE_NS 0x90000000UL /*!< External RAM base address */ -#define EPPB_BASE 0xE0040000UL /*!< External Private Peripheral Bus */ - -/*!< OTP, Engineering bytes, Option bytes defines */ -#define FLASH_OTP_BASE (SYSTEM_FLASH_BASE_NS + 0x00020000UL) /*!< FLASH OTP (one-time programmable) base address */ -#define FLASH_OTP_SIZE 0x00000200U /*!< 512 bytes OTP (one-time programmable) */ -#define FLASH_ENGY_BASE (SYSTEM_FLASH_BASE_NS + 0x00020500UL) -#define PACKAGE_BASE (FLASH_ENGY_BASE) /*!< Package data register base address */ -#define UID_BASE (FLASH_ENGY_BASE + 0x00000200UL) /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE (FLASH_ENGY_BASE + 0x000002A0UL) /*!< Flash size data register base address */ -#define UID64_BASE (FLASH_ENGY_BASE + 0x00000500UL) /*!< 64-bit Unique device Identification */ - -/*!< Memory sizes */ -/* Internal Flash size */ -#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x180000U : \ - ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x180000U : \ - (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) - -/*!< Internal SRAMs size */ -#define SRAM1_SIZE 0x00018000UL /*!< SRAM1=96k */ -#define SRAM2_SIZE 0x00010000UL /*!< SRAM2=64k */ -#define SRAM3_SIZE 0x00040000UL /*!< SRAM3=256k */ -#define SRAM4_SIZE 0x00010000UL /*!< SRAM4=64k */ - -/*!< Peripheral memory map - Non secure */ -#define APB1PERIPH_BASE_NS PERIPH_BASE_NS -#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) -#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) -#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00040000UL) -#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) - -/*!< APB1 Non secure peripherals */ -#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x00000000UL) -#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x00000400UL) -#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x00000800UL) -#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x00001000UL) -#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x00001400UL) -#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x00002000UL) -#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x00002C00UL) -#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x00003000UL) -#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x00003800UL) -#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x00004400UL) -#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x00004800UL) -#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x00004C00UL) -#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x00005000UL) -#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x00005400UL) -#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x00005800UL) -#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x00005C00UL) -#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x00006000UL) -#define OPAMP1_BASE_NS (APB1PERIPH_BASE_NS + 0x00007000UL) -#define OPAMP2_BASE_NS (OPAMP1_BASE_NS + 0x0000010UL) -#define VREFBUF_BASE_NS (APB1PERIPH_BASE_NS + 0x00007400UL) -#define RTC_BASE_NS (APB1PERIPH_BASE_NS + 0x00007800UL) -#define TAMP_BASE_NS (APB1PERIPH_BASE_NS + 0x00007C00UL) -#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x00009400UL) -#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0x0000A400UL) -#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0x0000A500UL) -#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0x0000AC00UL) - -/*!< APB2 Non secure peripherals */ -#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x00002C00UL) -#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x00003000UL) -#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x00003400UL) -#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x00003800UL) -#define TIM12_BASE_NS (APB2PERIPH_BASE_NS + 0x00003C00UL) -#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x00004000UL) -#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x00004400UL) -#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x00004800UL) -#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x00005400UL) -#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x0000004UL) -#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x0000024UL) -#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x00006000UL) -#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x00006400UL) -#define I3C2_BASE_NS (APB2PERIPH_BASE_NS + 0x00006C00UL) - -/*!< AHB1 Non secure peripherals */ -#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) -#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x00000050UL) -#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x000000D0UL) -#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x00000150UL) -#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x000001D0UL) -#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x00000250UL) -#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x000002D0UL) -#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x00000350UL) -#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x000003D0UL) -#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x00000450UL) -#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x000004D0UL) -#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x00000550UL) -#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x000005D0UL) -#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x00002000UL) -#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x00003000UL) -#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x00004000UL) -#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x00006000UL) -#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) -#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x00000040UL) -#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x00000080UL) -#define HSP1_BASE_NS (AHB1PERIPH_BASE_NS + 0x0000C000UL) -#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x00010400UL) -#define PWR_BASE_NS (AHB1PERIPH_BASE_NS + 0x00010800UL) -#define RCC_BASE_NS (AHB1PERIPH_BASE_NS + 0x00010C00UL) -#define EXTI_BASE_NS (AHB1PERIPH_BASE_NS + 0x00012000UL) -#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x00012400UL) -#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x00012C00UL) -#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x00013000UL) -#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x00013400UL) -#define GTZC_MPCBB4_BASE_NS (AHB1PERIPH_BASE_NS + 0x00013800UL) -#define ADF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x00014000UL) -#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x00000080UL) - -/*!< APB3 Non secure peripherals */ -#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x00000400UL) -#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x00002400UL) -#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x00002800UL) -#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x00004400UL) -#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x00004800UL) -#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x00004C00UL) -#define COMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x00005400UL) -#define COMP2_BASE_NS (COMP1_BASE_NS + 0x00000004UL) -#define LCD_BASE_NS (APB3PERIPH_BASE_NS + 0x00008000UL) - -/*!< AHB2 Non secure peripherals */ -#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000000UL) -#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000400UL) -#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000800UL) -#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000C00UL) -#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001000UL) -#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001400UL) -#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001800UL) -#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001C00UL) -#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008000UL) -#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008100UL) -#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008300UL) -#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008400UL) -#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0400UL) -#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0710UL) -#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0800UL) -#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A2000UL) -#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A2400UL) -#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A8000UL) -#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A8400UL) -#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000AF000UL) -#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0x000B1400UL) - -#if defined(CPU_IN_SECURE_STATE) -/*!< Flash, Peripheral and internal SRAMs base addresses - secure */ -#define FLASH_BASE_S 0x0C000000UL /*!< FLASH secure base address */ -#define SYSTEM_FLASH_BASE_S 0x0FF80000UL /*!< System FLASH secure base address */ -#define SRAM1_BASE_S 0x30000000UL /*!< SRAM1 secure base address */ -#define SRAM2_BASE_S 0x30018000UL /*!< SRAM2 secure base address */ -#define SRAM3_BASE_S 0x30028000UL /*!< SRAM3 secure base address */ -#define SRAM4_BASE_S 0x30068000UL /*!< SRAM4 secure base address */ -#define PERIPH_BASE_S 0x50000000UL /*!< Peripheral secure base address */ - -/*!< Peripheral memory map - secure */ -#define APB1PERIPH_BASE_S PERIPH_BASE_S -#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) -#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) -#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x00040000UL) -#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) - -/*!< APB1 secure peripherals */ -#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x00000000UL) -#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x00000400UL) -#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x00000800UL) -#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x00001000UL) -#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x00001400UL) -#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x00002000UL) -#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x00002C00UL) -#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x00003000UL) -#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x00003800UL) -#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x00004400UL) -#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x00004800UL) -#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x00004C00UL) -#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x00005000UL) -#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x00005400UL) -#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x00005800UL) -#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x00005C00UL) -#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x00006000UL) -#define OPAMP1_BASE_S (APB1PERIPH_BASE_S + 0x00007000UL) -#define OPAMP2_BASE_S (OPAMP1_BASE_S + 0x0000010UL) -#define VREFBUF_BASE_S (APB1PERIPH_BASE_S + 0x00007400UL) -#define RTC_BASE_S (APB1PERIPH_BASE_S + 0x00007800UL) -#define TAMP_BASE_S (APB1PERIPH_BASE_S + 0x00007C00UL) -#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x00009400UL) -#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0x0000A400UL) -#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0x0000A500UL) -#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0x0000AC00UL) - -/*!< APB2 secure peripherals */ -#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x00002C00UL) -#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x00003000UL) -#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x00003400UL) -#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x00003800UL) -#define TIM12_BASE_S (APB2PERIPH_BASE_S + 0x00003C00UL) -#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x00004000UL) -#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x00004400UL) -#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x00004800UL) -#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x00005400UL) -#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x0000004UL) -#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x0000024UL) -#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x00006000UL) -#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x00006400UL) -#define I3C2_BASE_S (APB2PERIPH_BASE_S + 0x00006C00UL) - -/*!< AHB1 secure peripherals */ -#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) -#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x00000050UL) -#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x000000D0UL) -#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x00000150UL) -#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x000001D0UL) -#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x00000250UL) -#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x000002D0UL) -#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x00000350UL) -#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x000003D0UL) -#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x00000450UL) -#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x000004D0UL) -#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x00000550UL) -#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x000005D0UL) -#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x00002000UL) -#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x00003000UL) -#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x00004000UL) -#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x00006000UL) -#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) -#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x00000040UL) -#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x00000080UL) -#define HSP1_BASE_S (AHB1PERIPH_BASE_S + 0x0000C000UL) -#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x00010400UL) -#define PWR_BASE_S (AHB1PERIPH_BASE_S + 0x00010800UL) -#define RCC_BASE_S (AHB1PERIPH_BASE_S + 0x00010C00UL) -#define EXTI_BASE_S (AHB1PERIPH_BASE_S + 0x00012000UL) -#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x00012400UL) -#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x00012800UL) -#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x00012C00UL) -#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x00013000UL) -#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x00013400UL) -#define GTZC_MPCBB4_BASE_S (AHB1PERIPH_BASE_S + 0x00013800UL) -#define ADF1_BASE_S (AHB1PERIPH_BASE_S + 0x00014000UL) -#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x00000080UL) - -/*!< APB3 secure peripherals */ -#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x00000400UL) -#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x00002400UL) -#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x00002800UL) -#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x00004400UL) -#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x00004800UL) -#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x00004C00UL) -#define COMP1_BASE_S (APB3PERIPH_BASE_S + 0x00005400UL) -#define COMP2_BASE_S (COMP1_BASE_S + 0x00000004UL) -#define LCD_BASE_S (APB3PERIPH_BASE_S + 0x00008000UL) - -/*!< AHB2 secure peripherals */ -#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000000UL) -#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00000400UL) -#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00000800UL) -#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00000C00UL) -#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x00001000UL) -#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x00001400UL) -#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x00001800UL) -#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x00001C00UL) -#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x00008000UL) -#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x00008100UL) -#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x00008300UL) -#define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x00008400UL) -#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0x000A0400UL) -#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0x000A0710UL) -#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0x000A0800UL) -#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0x000A2000UL) -#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0x000A2400UL) -#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0x000A8000UL) -#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0x000A8400UL) -#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0x000AF000UL) -#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0x000B1400UL) -#endif /* CPU_IN_SECURE_STATE */ - -/*!< External memories base addresses - Not aliased */ -#define OCTOSPI1_BASE EXTRAM_BASE_NS - -/*!< DBGMCU base addresses - Not aliased */ -#define DBGMCU_BASE (EPPB_BASE + 0x00004000UL) - -/*!< USB PMA SIZE */ -#define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */ - -/*!< Root Secure Service Library */ -/************ RSSLIB SAU system Flash region definition constants *************/ -#define RSSLIB_SYS_FLASH_NS_PFUNC_START 0x0BF99040UL -#define RSSLIB_SYS_FLASH_NS_PFUNC_END 0x0BF990FFUL - -/************ RSSLIB function return constants ********************************/ -#define RSSLIB_ERROR 0xF5F5F5F5UL -#define RSSLIB_SUCCESS 0xEAEAEAEAUL - -/*!< RSSLIB pointer function structure address definition */ -#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START -#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) - -/*!< HDP Area constant definition */ -#define RSSLIB_HDP_AREA_Pos 0UL -#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) -#define RSSLIB_HDP_AREA1_Pos 0UL -#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) -#define RSSLIB_HDP_AREA2_Pos 1UL -#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) -#define RSSLIB_HDPEXT_CLOSE_BOUNDARY_OPEN 0xC9C9C9C9UL /* Access to HDPx extension area and HDPx area denied but HDPx_EXT (in FLASH_HDPEXTR) increment allowed at any time */ -#define RSSLIB_HDPEXT_CLOSE_BOUNDARY_LOCK 0xD6D6D6D6UL /* Access to HDPx extension area and HDPx area denied. Update of HDPx_EXT size is not possible anymore */ - -/** - * @brief Prototype of RSSLIB Close and exit HDP Function - * @detail This function close the requested hdp area passed in input - * parameter and jump to the reset handler present within the - * Vector table. The function does not return on successful execution. - * @param HdpArea notifies which hdp area to close, can be a combination of - * hdpa area 1 and hdp area 2 - * @param VectorTableAddr pointer on the vector table containing the reset handler the function - * jumps to. - * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. - */ -typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); - -/** - * @brief Prototype of RSSLIB Close and exit HDP extension Function - * @detail This function close the requested hdp extension area passed in input - * parameter and jump to the reset handler present within the - * Vector table. The function does not return on successful execution. - * @param HdpExtArea notifies which hdp extension area to close, can be a combination of - * hdp extension area 1 and hdp extension area 2 - * @param VectorTableAddr pointer on the vector table containing the reset handler the function - * jumps to. - * @param CloseBound notifies if the HDP extension area should be closed with - * HDPx_EXT increment allowed or not - * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. - */ -typedef uint32_t ( *RSSLIB_S_CloseExitHDPExt_TypeDef)( uint32_t HdpExtArea, uint32_t VectorTableAddr, uint32_t CloseBound ); - - -/** - * @brief RSSLib non-secure callable function pointer structure - */ -typedef struct -{ - __IM uint32_t Reserved[8]; -}NSC_pFuncTypeDef; - -/** - * @brief RSSLib secure callable function pointer structure - */ -typedef struct -{ - __IM uint32_t Reserved2[2]; - __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ - __IM RSSLIB_S_CloseExitHDPExt_TypeDef CloseExitHDPExt; /*!< RSSLIB Bootloader Close and exit HDP extension Address offset: 0x2C */ -}S_pFuncTypeDef; - -/** - * @brief RSSLib function pointer structure - */ -typedef struct -{ - NSC_pFuncTypeDef NSC; - S_pFuncTypeDef S; -}RSSLIB_pFunc_TypeDef; - -/* - * Certificate address description - */ -#define CERT_CHIP_PACK1_ADDR (0x0BF9FE00U) -#define CERT_CHIP_PACK1_SIZE (0x200U) -#define CERT_CHIP_PACK2_ADDR (0x0BF9FC00U) -#define CERT_CHIP_PACK2_SIZE (0x200U) - -#define CERT_CHIP_PACK_ADDR (CERT_CHIP_PACK2_ADDR) -#define CERT_CHIP_PACK_SIZE (CERT_CHIP_PACK1_SIZE + CERT_CHIP_PACK2_SIZE) - -#define CERT_ST_DUA_USER_FU_PUB_KEY_OFFSET (12U) -#define CERT_ST_DUA_USER_FU_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_PUB_KEY_OFFSET) -#define CERT_ST_DUA_USER_FU_SIGN_OFFSET (76U) -#define CERT_ST_DUA_USER_FU_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_SIGN_OFFSET) -#define CERT_ST_DUA_USER_FU_SERIAL_OFFSET (140U) -#define CERT_ST_DUA_USER_FU_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_SERIAL_OFFSET) - -#define CERT_ST_DUA_USER_LU_PUB_KEY_OFFSET (162U) -#define CERT_ST_DUA_USER_LU_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_PUB_KEY_OFFSET) -#define CERT_ST_DUA_USER_LU_SIGN_OFFSET (226U) -#define CERT_ST_DUA_USER_LU_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_SIGN_OFFSET) -#define CERT_ST_DUA_USER_LU_SERIAL_OFFSET (290U) -#define CERT_ST_DUA_USER_LU_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_SERIAL_OFFSET) -/** @} */ /* End of group STM32U3xx_Peripheral_peripheralAddr */ - - -/* ================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* ================================================================================================================== */ -/** @addtogroup STM32U3xx_Peripheral_declaration - * @{ - */ -#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) -#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) -#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) -#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) -#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) -#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) -#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) -#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) -#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) -#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) -#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) -#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) -#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) -#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) -#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) -#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) -#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) -#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) -#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) -#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) -#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) -#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) -#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) -#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) -#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) -#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) -#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) -#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) -#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) -#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) -#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) -#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) -#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) -#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) -#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) -#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) -#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) -#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) -#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) -#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) -#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) -#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) -#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) -#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) -#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) -#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) -#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) -#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) -#define I3C1_NS ((I3C_TypeDef *) I3C1_BASE_NS) -#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) -#define HSP1_NS ((HSP_TypeDef *) HSP1_BASE_NS) -#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) -#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) -#define LCD_NS ((LCD_TypeDef *) LCD_BASE_NS) -#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) -#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) -#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) -#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) -#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) -#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) -#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) -#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) -#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) -#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) -#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) -#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) -#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) -#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) -#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) -#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) -#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) -#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) -#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) -#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) -#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) -#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) -#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) -#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) -#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) -#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) -#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) -#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) -#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) -#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) -#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) -#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) -#define TIM12_NS ((TIM_TypeDef *) TIM12_BASE_NS) -#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) -#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) -#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) -#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) -#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) -#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) -#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) -#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) -#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) -#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) -#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) -#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) -#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) -#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) - -/*!< DBGMCU peripheral */ -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -#if defined (CPU_IN_SECURE_STATE) -#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) -#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) -#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) -#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) -#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) -#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) -#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) -#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) -#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) -#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) -#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) -#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) -#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) -#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) -#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) -#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) -#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) -#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) -#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) -#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) -#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) -#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) -#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) -#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) -#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) -#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) -#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) -#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) -#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) -#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) -#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) -#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) -#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) -#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) -#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) -#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) -#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) -#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) -#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) -#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) -#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) -#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) -#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) -#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) -#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) -#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) -#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) -#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) -#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) -#define I3C1_S ((I3C_TypeDef *) I3C1_BASE_S) -#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) -#define HSP1_S ((HSP_TypeDef *) HSP1_BASE_S) -#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) -#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) -#define LCD_S ((LCD_TypeDef *) LCD_BASE_S) -#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) -#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) -#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) -#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) -#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) -#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) -#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) -#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) -#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) -#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) -#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) -#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) -#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) -#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) -#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) -#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) -#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) -#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) -#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) -#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) -#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) -#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) -#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) -#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) -#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) -#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) -#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) -#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) -#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) -#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) -#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) -#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) -#define TIM12_S ((TIM_TypeDef *) TIM12_BASE_S) -#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) -#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) -#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) -#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) -#define UART4_S ((USART_TypeDef *) UART4_BASE_S) -#define UART5_S ((USART_TypeDef *) UART5_BASE_S) -#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) -#define USART1_S ((USART_TypeDef *) USART1_BASE_S) -#define USART2_S ((USART_TypeDef *) USART2_BASE_S) -#define USART3_S ((USART_TypeDef *) USART3_BASE_S) -#define USB_DRD_FS_S ((USB_DRD_TypeDef *) USB_DRD_BASE_S) -#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) -#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) -#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) - -/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ -/*!< Memory base addresses for Secure peripherals */ -#define FLASH_BASE FLASH_BASE_S -#define SRAM1_BASE SRAM1_BASE_S -#define SRAM2_BASE SRAM2_BASE_S -#define SRAM3_BASE SRAM3_BASE_S -#define SRAM4_BASE SRAM4_BASE_S - -/*!< Instance aliases and base addresses for Secure peripherals */ -#define ADC12_COMMON ADC12_COMMON_S -#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S -#define ADC1 ADC1_S -#define ADC1_BASE ADC1_BASE_S -#define ADC2 ADC2_S -#define ADC2_BASE ADC2_BASE_S -#define ADF1 ADF1_S -#define ADF1_BASE ADF1_BASE_S -#define ADF1_Filter0 ADF1_Filter0_S -#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S -#define COMP1 COMP1_S -#define COMP1_BASE COMP1_BASE_S -#define COMP2 COMP2_S -#define COMP2_BASE COMP2_BASE_S -#define COMP12_COMMON COMP12_COMMON_S -#define COMP12_COMMON_BASE COMP12_BASE_S -#define CRC CRC_S -#define CRC_BASE CRC_BASE_S -#define CRS CRS_S -#define CRS_BASE CRS_BASE_S -#define DAC1 DAC1_S -#define DAC1_BASE DAC1_BASE_S -#define DLYB_SDMMC1 DLYB_SDMMC1_S -#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S -#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S -#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S -#define EXTI EXTI_S -#define EXTI_BASE EXTI_BASE_S -#define FDCAN1 FDCAN1_S -#define FDCAN1_BASE FDCAN1_BASE_S -#define FDCAN_CONFIG FDCAN_CONFIG_S -#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S -#define FLASH FLASH_S -#define FLASH_R_BASE FLASH_R_BASE_S -#define GPDMA1 GPDMA1_S -#define GPDMA1_BASE GPDMA1_BASE_S -#define GPDMA1_Channel0 GPDMA1_Channel0_S -#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S -#define GPDMA1_Channel1 GPDMA1_Channel1_S -#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S -#define GPDMA1_Channel2 GPDMA1_Channel2_S -#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S -#define GPDMA1_Channel3 GPDMA1_Channel3_S -#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S -#define GPDMA1_Channel4 GPDMA1_Channel4_S -#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S -#define GPDMA1_Channel5 GPDMA1_Channel5_S -#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S -#define GPDMA1_Channel6 GPDMA1_Channel6_S -#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S -#define GPDMA1_Channel7 GPDMA1_Channel7_S -#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S -#define GPDMA1_Channel8 GPDMA1_Channel8_S -#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S -#define GPDMA1_Channel9 GPDMA1_Channel9_S -#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S -#define GPDMA1_Channel10 GPDMA1_Channel10_S -#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S -#define GPDMA1_Channel11 GPDMA1_Channel11_S -#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S -#define GPIOA GPIOA_S -#define GPIOA_BASE GPIOA_BASE_S -#define GPIOB GPIOB_S -#define GPIOB_BASE GPIOB_BASE_S -#define GPIOC GPIOC_S -#define GPIOC_BASE GPIOC_BASE_S -#define GPIOD GPIOD_S -#define GPIOD_BASE GPIOD_BASE_S -#define GPIOE GPIOE_S -#define GPIOE_BASE GPIOE_BASE_S -#define GPIOF GPIOF_S -#define GPIOF_BASE GPIOF_BASE_S -#define GPIOG GPIOG_S -#define GPIOG_BASE GPIOG_BASE_S -#define GPIOH GPIOH_S -#define GPIOH_BASE GPIOH_BASE_S -#define GTZC_MPCBB1 GTZC_MPCBB1_S -#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S -#define GTZC_MPCBB2 GTZC_MPCBB2_S -#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S -#define GTZC_MPCBB3 GTZC_MPCBB3_S -#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S -#define GTZC_MPCBB4 GTZC_MPCBB4_S -#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S -#define GTZC_TZSC1 GTZC_TZSC1_S -#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S -#define GTZC_TZIC1 GTZC_TZIC1_S -#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S -#define HASH HASH_S -#define HASH_BASE HASH_BASE_S -#define HASH_DIGEST HASH_DIGEST_S -#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S -#define I2C1 I2C1_S -#define I2C1_BASE I2C1_BASE_S -#define I2C2 I2C2_S -#define I2C2_BASE I2C2_BASE_S -#define I2C3 I2C3_S -#define I2C3_BASE I2C3_BASE_S -#define I3C1 I3C1_S -#define I3C1_BASE I3C1_BASE_S -#define I3C2 I3C2_S -#define I3C2_BASE I3C2_BASE_S -#define HSP1 HSP1_S -#define HSP1_BASE HSP1_BASE_S -#define ICACHE ICACHE_S -#define ICACHE_BASE ICACHE_BASE_S -#define IWDG IWDG_S -#define IWDG_BASE IWDG_BASE_S -#define LCD LCD_S -#define LCD_BASE LCD_BASE_S -#define LPTIM1 LPTIM1_S -#define LPTIM1_BASE LPTIM1_BASE_S -#define LPTIM2 LPTIM2_S -#define LPTIM2_BASE LPTIM2_BASE_S -#define LPTIM3 LPTIM3_S -#define LPTIM3_BASE LPTIM3_BASE_S -#define LPTIM4 LPTIM4_S -#define LPTIM4_BASE LPTIM4_BASE_S -#define LPUART1 LPUART1_S -#define LPUART1_BASE LPUART1_BASE_S -#define OCTOSPI1 OCTOSPI1_S -#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S -#define OPAMP1 OPAMP1_S -#define OPAMP1_BASE OPAMP1_BASE_S -#define OPAMP2 OPAMP2_S -#define OPAMP2_BASE OPAMP2_BASE_S -#define OPAMP12_COMMON OPAMP12_COMMON_S -#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S -#define PKA PKA_S -#define PKA_BASE PKA_BASE_S -#define PKA_RAM_BASE PKA_RAM_BASE_S -#define PWR PWR_S -#define PWR_BASE PWR_BASE_S -#define RAMCFG_SRAM1 RAMCFG_SRAM1_S -#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S -#define RAMCFG_SRAM2 RAMCFG_SRAM2_S -#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S -#define RAMCFG_SRAM3 RAMCFG_SRAM3_S -#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S -#define RCC RCC_S -#define RCC_BASE RCC_BASE_S -#define RNG RNG_S -#define RNG_BASE RNG_BASE_S -#define RTC RTC_S -#define RTC_BASE RTC_BASE_S -#define SAI1 SAI1_S -#define SAI1_BASE SAI1_BASE_S -#define SAI1_Block_A SAI1_Block_A_S -#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S -#define SAI1_Block_B SAI1_Block_B_S -#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S -#define SDMMC1 SDMMC1_S -#define SDMMC1_BASE SDMMC1_BASE_S -#define SPI1 SPI1_S -#define SPI1_BASE SPI1_BASE_S -#define SPI2 SPI2_S -#define SPI2_BASE SPI2_BASE_S -#define SPI3 SPI3_S -#define SPI3_BASE SPI3_BASE_S -#define SRAMCAN_BASE SRAMCAN_BASE_S -#define SYSCFG SYSCFG_S -#define SYSCFG_BASE SYSCFG_BASE_S -#define TAMP TAMP_S -#define TAMP_BASE TAMP_BASE_S -#define TIM1 TIM1_S -#define TIM1_BASE TIM1_BASE_S -#define TIM2 TIM2_S -#define TIM2_BASE TIM2_BASE_S -#define TIM3 TIM3_S -#define TIM3_BASE TIM3_BASE_S -#define TIM4 TIM4_S -#define TIM4_BASE TIM4_BASE_S -#define TIM6 TIM6_S -#define TIM6_BASE TIM6_BASE_S -#define TIM7 TIM7_S -#define TIM7_BASE TIM7_BASE_S -#define TIM12 TIM12_S -#define TIM12_BASE TIM12_BASE_S -#define TIM15 TIM15_S -#define TIM15_BASE TIM15_BASE_S -#define TIM16 TIM16_S -#define TIM16_BASE TIM16_BASE_S -#define TIM17 TIM17_S -#define TIM17_BASE TIM17_BASE_S -#define TSC TSC_S -#define TSC_BASE TSC_BASE_S -#define UART4 UART4_S -#define UART4_BASE UART4_BASE_S -#define UART5 UART5_S -#define UART5_BASE UART5_BASE_S -#define TIM8 TIM8_S -#define TIM8_BASE TIM8_BASE_S -#define USART1 USART1_S -#define USART1_BASE USART1_BASE_S -#define USART2 USART2_S -#define USART2_BASE USART2_BASE_S -#define USART3 USART3_S -#define USART3_BASE USART3_BASE_S -#define USB_DRD_FS USB_DRD_FS_S -#define USB_DRD_BASE USB_DRD_BASE_S -#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S -#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S -#define VREFBUF VREFBUF_S -#define VREFBUF_BASE VREFBUF_BASE_S -#define WWDG WWDG_S -#define WWDG_BASE WWDG_BASE_S - -#else /* CPU_IN_SECURE_STATE */ -/*!< Memory base addresses for Secure peripherals */ -#define FLASH_BASE FLASH_BASE_NS -#define SRAM1_BASE SRAM1_BASE_NS -#define SRAM2_BASE SRAM2_BASE_NS -#define SRAM3_BASE SRAM3_BASE_NS -#define SRAM4_BASE SRAM4_BASE_NS - -/*!< Instance aliases and base addresses for Secure peripherals */ -#define ADC12_COMMON ADC12_COMMON_NS -#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS -#define ADC1 ADC1_NS -#define ADC1_BASE ADC1_BASE_NS -#define ADC2 ADC2_NS -#define ADC2_BASE ADC2_BASE_NS -#define ADF1 ADF1_NS -#define ADF1_BASE ADF1_BASE_NS -#define ADF1_Filter0 ADF1_Filter0_NS -#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS -#define COMP1 COMP1_NS -#define COMP1_BASE COMP1_BASE_NS -#define COMP2 COMP2_NS -#define COMP2_BASE COMP2_BASE_NS -#define COMP12_COMMON COMP12_COMMON_NS -#define COMP12_COMMON_BASE COMP12_BASE_NS -#define CRC CRC_NS -#define CRC_BASE CRC_BASE_NS -#define CRS CRS_NS -#define CRS_BASE CRS_BASE_NS -#define DAC1 DAC1_NS -#define DAC1_BASE DAC1_BASE_NS -#define DLYB_SDMMC1 DLYB_SDMMC1_NS -#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS -#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS -#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS -#define EXTI EXTI_NS -#define EXTI_BASE EXTI_BASE_NS -#define FDCAN1 FDCAN1_NS -#define FDCAN1_BASE FDCAN1_BASE_NS -#define FDCAN_CONFIG FDCAN_CONFIG_NS -#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS -#define FLASH FLASH_NS -#define FLASH_R_BASE FLASH_R_BASE_NS -#define GPDMA1 GPDMA1_NS -#define GPDMA1_BASE GPDMA1_BASE_NS -#define GPDMA1_Channel0 GPDMA1_Channel0_NS -#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS -#define GPDMA1_Channel1 GPDMA1_Channel1_NS -#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS -#define GPDMA1_Channel2 GPDMA1_Channel2_NS -#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS -#define GPDMA1_Channel3 GPDMA1_Channel3_NS -#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS -#define GPDMA1_Channel4 GPDMA1_Channel4_NS -#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS -#define GPDMA1_Channel5 GPDMA1_Channel5_NS -#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS -#define GPDMA1_Channel6 GPDMA1_Channel6_NS -#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS -#define GPDMA1_Channel7 GPDMA1_Channel7_NS -#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS -#define GPDMA1_Channel8 GPDMA1_Channel8_NS -#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS -#define GPDMA1_Channel9 GPDMA1_Channel9_NS -#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS -#define GPDMA1_Channel10 GPDMA1_Channel10_NS -#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS -#define GPDMA1_Channel11 GPDMA1_Channel11_NS -#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS -#define GPIOA GPIOA_NS -#define GPIOA_BASE GPIOA_BASE_NS -#define GPIOB GPIOB_NS -#define GPIOB_BASE GPIOB_BASE_NS -#define GPIOC GPIOC_NS -#define GPIOC_BASE GPIOC_BASE_NS -#define GPIOD GPIOD_NS -#define GPIOD_BASE GPIOD_BASE_NS -#define GPIOE GPIOE_NS -#define GPIOE_BASE GPIOE_BASE_NS -#define GPIOF GPIOF_NS -#define GPIOF_BASE GPIOF_BASE_NS -#define GPIOG GPIOG_NS -#define GPIOG_BASE GPIOG_BASE_NS -#define GPIOH GPIOH_NS -#define GPIOH_BASE GPIOH_BASE_NS -#define GTZC_MPCBB1 GTZC_MPCBB1_NS -#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS -#define GTZC_MPCBB2 GTZC_MPCBB2_NS -#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS -#define GTZC_MPCBB3 GTZC_MPCBB3_NS -#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS -#define GTZC_MPCBB4 GTZC_MPCBB4_NS -#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS -#define GTZC_TZSC1 GTZC_TZSC1_NS -#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS -#define HASH HASH_NS -#define HASH_BASE HASH_BASE_NS -#define HASH_DIGEST HASH_DIGEST_NS -#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS -#define I2C1 I2C1_NS -#define I2C1_BASE I2C1_BASE_NS -#define I2C2 I2C2_NS -#define I2C2_BASE I2C2_BASE_NS -#define I2C3 I2C3_NS -#define I2C3_BASE I2C3_BASE_NS -#define I3C1 I3C1_NS -#define I3C1_BASE I3C1_BASE_NS -#define I3C2 I3C2_NS -#define I3C2_BASE I3C2_BASE_NS -#define HSP1 HSP1_NS -#define HSP1_BASE HSP1_BASE_NS -#define ICACHE ICACHE_NS -#define ICACHE_BASE ICACHE_BASE_NS -#define IWDG IWDG_NS -#define IWDG_BASE IWDG_BASE_NS -#define LCD LCD_NS -#define LCD_BASE LCD_BASE_NS -#define LPTIM1 LPTIM1_NS -#define LPTIM1_BASE LPTIM1_BASE_NS -#define LPTIM2 LPTIM2_NS -#define LPTIM2_BASE LPTIM2_BASE_NS -#define LPTIM3 LPTIM3_NS -#define LPTIM3_BASE LPTIM3_BASE_NS -#define LPTIM4 LPTIM4_NS -#define LPTIM4_BASE LPTIM4_BASE_NS -#define LPUART1 LPUART1_NS -#define LPUART1_BASE LPUART1_BASE_NS -#define OCTOSPI1 OCTOSPI1_NS -#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS -#define OPAMP1 OPAMP1_NS -#define OPAMP1_BASE OPAMP1_BASE_NS -#define OPAMP2 OPAMP2_NS -#define OPAMP2_BASE OPAMP2_BASE_NS -#define OPAMP12_COMMON OPAMP12_COMMON_NS -#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS -#define PKA PKA_NS -#define PKA_BASE PKA_BASE_NS -#define PKA_RAM_BASE PKA_RAM_BASE_NS -#define PWR PWR_NS -#define PWR_BASE PWR_BASE_NS -#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS -#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS -#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS -#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS -#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS -#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS -#define RCC RCC_NS -#define RCC_BASE RCC_BASE_NS -#define RNG RNG_NS -#define RNG_BASE RNG_BASE_NS -#define RTC RTC_NS -#define RTC_BASE RTC_BASE_NS -#define SAI1 SAI1_NS -#define SAI1_BASE SAI1_BASE_NS -#define SAI1_Block_A SAI1_Block_A_NS -#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS -#define SAI1_Block_B SAI1_Block_B_NS -#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS -#define SDMMC1 SDMMC1_NS -#define SDMMC1_BASE SDMMC1_BASE_NS -#define SPI1 SPI1_NS -#define SPI1_BASE SPI1_BASE_NS -#define SPI2 SPI2_NS -#define SPI2_BASE SPI2_BASE_NS -#define SPI3 SPI3_NS -#define SPI3_BASE SPI3_BASE_NS -#define SRAMCAN_BASE SRAMCAN_BASE_NS -#define SYSCFG SYSCFG_NS -#define SYSCFG_BASE SYSCFG_BASE_NS -#define TAMP TAMP_NS -#define TAMP_BASE TAMP_BASE_NS -#define TIM1 TIM1_NS -#define TIM1_BASE TIM1_BASE_NS -#define TIM2 TIM2_NS -#define TIM2_BASE TIM2_BASE_NS -#define TIM3 TIM3_NS -#define TIM3_BASE TIM3_BASE_NS -#define TIM4 TIM4_NS -#define TIM4_BASE TIM4_BASE_NS -#define TIM6 TIM6_NS -#define TIM6_BASE TIM6_BASE_NS -#define TIM7 TIM7_NS -#define TIM7_BASE TIM7_BASE_NS -#define TIM12 TIM12_NS -#define TIM12_BASE TIM12_BASE_NS -#define TIM15 TIM15_NS -#define TIM15_BASE TIM15_BASE_NS -#define TIM16 TIM16_NS -#define TIM16_BASE TIM16_BASE_NS -#define TIM17 TIM17_NS -#define TIM17_BASE TIM17_BASE_NS -#define TSC TSC_NS -#define TSC_BASE TSC_BASE_NS -#define UART4 UART4_NS -#define UART4_BASE UART4_BASE_NS -#define UART5 UART5_NS -#define UART5_BASE UART5_BASE_NS -#define TIM8 TIM8_NS -#define TIM8_BASE TIM8_BASE_NS -#define USART1 USART1_NS -#define USART1_BASE USART1_BASE_NS -#define USART2 USART2_NS -#define USART2_BASE USART2_BASE_NS -#define USART3 USART3_NS -#define USART3_BASE USART3_BASE_NS -#define USB_DRD_FS USB_DRD_FS_NS -#define USB_DRD_BASE USB_DRD_BASE_NS -#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS -#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS -#define VREFBUF VREFBUF_NS -#define VREFBUF_BASE VREFBUF_BASE_NS -#define WWDG WWDG_NS -#define WWDG_BASE WWDG_BASE_NS -#endif /* CPU_IN_SECURE_STATE */ - -/** @addtogroup Exported_constants - * @{ - */ - -/** @addtogroup Hardware_Constant_Definition - * @{ - */ -#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ -/** - * @} - */ - -/** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter (ADC) */ -/* */ -/******************************************************************************/ - -/* Specific device feature definitions */ -#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ - -/******************** Bit definition for ADC_ISR register *******************/ -#define ADC_ISR_ADRDY_Pos (0UL) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ -#define ADC_ISR_EOSMP_Pos (1UL) -#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ -#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ -#define ADC_ISR_EOC_Pos (2UL) -#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ -#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ -#define ADC_ISR_EOS_Pos (3UL) -#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ -#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_ISR_OVR_Pos (4UL) -#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ -#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ -#define ADC_ISR_JEOC_Pos (5UL) -#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ -#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ -#define ADC_ISR_JEOS_Pos (6UL) -#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ -#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_ISR_AWD1_Pos (7UL) -#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ -#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8UL) -#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ -#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9UL) -#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ -#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ -#define ADC_ISR_JQOVF_Pos (10UL) -#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ -#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ -#define ADC_ISR_LDORDY_Pos (12UL) -#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ -#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready flag */ - -/******************** Bit definition for ADC_IER register *******************/ -#define ADC_IER_ADRDYIE_Pos (0UL) -#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ -#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ -#define ADC_IER_EOSMPIE_Pos (1UL) -#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ -#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ -#define ADC_IER_EOCIE_Pos (2UL) -#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ -#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ -#define ADC_IER_EOSIE_Pos (3UL) -#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ -#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_IER_OVRIE_Pos (4UL) -#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ -#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ -#define ADC_IER_JEOCIE_Pos (5UL) -#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ -#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ -#define ADC_IER_JEOSIE_Pos (6UL) -#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ -#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_IER_AWD1IE_Pos (7UL) -#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ -#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_IER_AWD2IE_Pos (8UL) -#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ -#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ -#define ADC_IER_AWD3IE_Pos (9UL) -#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ -#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ -#define ADC_IER_JQOVFIE_Pos (10UL) -#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ -#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ -#define ADC_IER_LDORDYIE_Pos (12UL) -#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ -#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt*/ - -/******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0UL) -#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ -#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ -#define ADC_CR_ADDIS_Pos (1UL) -#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ -#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ -#define ADC_CR_ADSTART_Pos (2UL) -#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ -#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR_JADSTART_Pos (3UL) -#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ -#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR_ADSTP_Pos (4UL) -#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ -#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ -#define ADC_CR_JADSTP_Pos (5UL) -#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ -#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ -#define ADC_CR_ADVREGEN_Pos (28UL) -#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ -#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator */ -#define ADC_CR_DEEPPWD_Pos (29UL) -#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ -#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ -#define ADC_CR_ADCAL_Pos (31UL) -#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ -#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ - -/******************** Bit definition for ADC_CFGR1 register ******************/ -#define ADC_CFGR1_DMNGT_Pos (0UL) -#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ -#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC data management configuration */ -#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ -#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ - -#define ADC_CFGR1_RES_Pos (2UL) -#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ -#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ -#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ -#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ - -#define ADC_CFGR1_EXTSEL_Pos (5UL) -#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ -#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ - -#define ADC_CFGR1_EXTEN_Pos (10UL) -#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ -#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ -#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ - -#define ADC_CFGR1_OVRMOD_Pos (12UL) -#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ -#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ -#define ADC_CFGR1_CONT_Pos (13UL) -#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ -#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CFGR1_AUTDLY_Pos (14UL) -#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ -#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC low power auto wait */ - -#define ADC_CFGR1_DISCEN_Pos (16UL) -#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ -#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ - -#define ADC_CFGR1_DISCNUM_Pos (17UL) -#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ -#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ -#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ -#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ - -#define ADC_CFGR1_JDISCEN_Pos (20UL) -#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ -#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ - -#define ADC_CFGR1_JQM_Pos (21UL) -#define ADC_CFGR1_JQM_Msk (0x1UL << ADC_CFGR1_JQM_Pos) /*!< 0x00200000 */ -#define ADC_CFGR1_JQM ADC_CFGR1_JQM_Msk /*!< ADC group injected contexts queue mode */ - -#define ADC_CFGR1_AWD1SGL_Pos (22UL) -#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ -#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CFGR1_AWD1EN_Pos (23UL) -#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ -#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ -#define ADC_CFGR1_JAWD1EN_Pos (24UL) -#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ -#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CFGR1_JAUTO_Pos (25UL) -#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ -#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ - -#define ADC_CFGR1_AWD1CH_Pos (26UL) -#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ -#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ -#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ -#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ -#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ -#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ - -#define ADC_CFGR1_JQDIS_Pos (31UL) -#define ADC_CFGR1_JQDIS_Msk (0x1UL << ADC_CFGR1_JQDIS_Pos) /*!< 0x80000000 */ -#define ADC_CFGR1_JQDIS ADC_CFGR1_JQDIS_Msk /*!< ADC group injected contexts queue disable */ - -/******************** Bit definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_ROVSE_Pos (0UL) -#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ -#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ -#define ADC_CFGR2_JOVSE_Pos (1UL) -#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ -#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ - -#define ADC_CFGR2_OVSS_Pos (5UL) -#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ -#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ -#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ -#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ -#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ -#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ - -#define ADC_CFGR2_TROVS_Pos (9UL) -#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ -#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ -#define ADC_CFGR2_ROVSM_Pos (10UL) -#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ -#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ - -#define ADC_CFGR2_BULB_Pos (13UL) -#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ -#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC bulb sampling mode */ - -#define ADC_CFGR2_SWTRIG_Pos (14UL) -#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ -#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC software trigger bit for sampling time control trigger mode */ - -#define ADC_CFGR2_SMPTRIG_Pos (15UL) -#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ -#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC sampling time control trigger mode */ - -#define ADC_CFGR2_OVSR_Pos (16UL) -#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ -#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ - -#define ADC_CFGR2_LFTRIG_Pos (27UL) -#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ -#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low-frequency trigge */ - -#define ADC_CFGR2_LSHIFT_Pos (28UL) -#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ -#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC left shift factor */ -#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ -#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ -#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ -#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_SMPR1 register *****************/ -#define ADC_SMPR1_SMP0_Pos (0UL) -#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ -#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR1_SMP1_Pos (3UL) -#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ -#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR1_SMP2_Pos (6UL) -#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR1_SMP3_Pos (9UL) -#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR1_SMP4_Pos (12UL) -#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ -#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR1_SMP5_Pos (15UL) -#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ -#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR1_SMP6_Pos (18UL) -#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR1_SMP7_Pos (21UL) -#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ - -#define ADC_SMPR1_SMP8_Pos (24UL) -#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ -#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ - -#define ADC_SMPR1_SMP9_Pos (27UL) -#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ -#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ - -/******************** Bit definition for ADC_SMPR2 register *****************/ -#define ADC_SMPR2_SMP10_Pos (0UL) -#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ -#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR2_SMP11_Pos (3UL) -#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ -#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR2_SMP12_Pos (6UL) -#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR2_SMP13_Pos (9UL) -#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR2_SMP14_Pos (12UL) -#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ -#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR2_SMP15_Pos (15UL) -#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ -#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR2_SMP16_Pos (18UL) -#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR2_SMP17_Pos (21UL) -#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ - -#define ADC_SMPR2_SMP18_Pos (24UL) -#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ -#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ - -#define ADC_SMPR2_SMP19_Pos (27UL) -#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ -#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ -#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ -#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ -#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ - -/******************** Bit definition for ADC_PCSEL register *****************/ -#define ADC_PCSEL_PCSEL_Pos (0UL) -#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ -#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC channel preselection */ -#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ -#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ -#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ -#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ -#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ -#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ -#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ -#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ -#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ -#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ -#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ -#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ -#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ -#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ -#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ -#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ -#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ -#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ -#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for ADC_SQR1 register ******************/ -#define ADC_SQR1_L_Pos (0UL) -#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ -#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ - -#define ADC_SQR1_SQ1_Pos (6UL) -#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ -#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ - -#define ADC_SQR1_SQ2_Pos (12UL) -#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ -#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ - -#define ADC_SQR1_SQ3_Pos (18UL) -#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ -#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ - -#define ADC_SQR1_SQ4_Pos (24UL) -#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ -#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ -#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ -#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ -#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ -#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR2 register ******************/ -#define ADC_SQR2_SQ5_Pos (0UL) -#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ -#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ - -#define ADC_SQR2_SQ6_Pos (6UL) -#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ -#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ - -#define ADC_SQR2_SQ7_Pos (12UL) -#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ -#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ - -#define ADC_SQR2_SQ8_Pos (18UL) -#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ -#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ - -#define ADC_SQR2_SQ9_Pos (24UL) -#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ -#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR3 register ******************/ -#define ADC_SQR3_SQ10_Pos (0UL) -#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ -#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ - -#define ADC_SQR3_SQ11_Pos (6UL) -#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ -#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ -#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ - -#define ADC_SQR3_SQ12_Pos (12UL) -#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ -#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ - -#define ADC_SQR3_SQ13_Pos (18UL) -#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ -#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ - -#define ADC_SQR3_SQ14_Pos (24UL) -#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ -#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR4 register ******************/ -#define ADC_SQR4_SQ15_Pos (0UL) -#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ -#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ -#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ -#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ -#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ -#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ - -#define ADC_SQR4_SQ16_Pos (6UL) -#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ -#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ -#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ -#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ -#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ -#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_RDATA_Pos (0UL) -#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_RDATA_0 (0x00000001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ -#define ADC_DR_RDATA_1 (0x00000002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ -#define ADC_DR_RDATA_2 (0x00000004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ -#define ADC_DR_RDATA_3 (0x00000008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ -#define ADC_DR_RDATA_4 (0x00000010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ -#define ADC_DR_RDATA_5 (0x00000020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ -#define ADC_DR_RDATA_6 (0x00000040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ -#define ADC_DR_RDATA_7 (0x00000080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ -#define ADC_DR_RDATA_8 (0x00000100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ -#define ADC_DR_RDATA_9 (0x00000200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ -#define ADC_DR_RDATA_10 (0x00000400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ -#define ADC_DR_RDATA_11 (0x00000800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ -#define ADC_DR_RDATA_12 (0x00001000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ -#define ADC_DR_RDATA_13 (0x00002000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ -#define ADC_DR_RDATA_14 (0x00004000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ -#define ADC_DR_RDATA_15 (0x00008000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ -#define ADC_DR_RDATA_16 (0x00010000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ -#define ADC_DR_RDATA_17 (0x00020000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ -#define ADC_DR_RDATA_18 (0x00040000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ -#define ADC_DR_RDATA_19 (0x00080000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ -#define ADC_DR_RDATA_20 (0x00100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ -#define ADC_DR_RDATA_21 (0x00200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ -#define ADC_DR_RDATA_22 (0x00400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ -#define ADC_DR_RDATA_23 (0x00800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ -#define ADC_DR_RDATA_24 (0x01000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ -#define ADC_DR_RDATA_25 (0x02000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ -#define ADC_DR_RDATA_26 (0x04000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ -#define ADC_DR_RDATA_27 (0x08000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ -#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ -#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ -#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ -#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_JSQR register ******************/ -#define ADC_JSQR_JL_Pos (0UL) -#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ -#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ - -#define ADC_JSQR_JEXTSEL_Pos (2UL) -#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ -#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ -#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ - -#define ADC_JSQR_JEXTEN_Pos (7UL) -#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ -#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ -#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ -#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ - -#define ADC_JSQR_JSQ1_Pos (9UL) -#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ -#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ -#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ - -#define ADC_JSQR_JSQ2_Pos (15UL) -#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ -#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ -#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ - -#define ADC_JSQR_JSQ3_Pos (21UL) -#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ -#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ -#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ - -#define ADC_JSQR_JSQ4_Pos (27UL) -#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ -#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ -#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_OFCFGR1 register ***************/ -#define ADC_OFCFGR1_POSOFF_Pos (24UL) -#define ADC_OFCFGR1_POSOFF_Msk (0x01UL << ADC_OFCFGR1_POSOFF_Pos) /*!< 0x01000000 */ -#define ADC_OFCFGR1_POSOFF ADC_OFCFGR1_POSOFF_Msk /*!< ADC offset instance 1 positive offset enable */ - -#define ADC_OFCFGR1_USAT_Pos (25UL) -#define ADC_OFCFGR1_USAT_Msk (0x01UL << ADC_OFCFGR1_USAT_Pos) /*!< 0x02000000 */ -#define ADC_OFCFGR1_USAT ADC_OFCFGR1_USAT_Msk /*!< ADC offset instance 1 unsigned saturation value */ - -#define ADC_OFCFGR1_SSAT_Pos (26UL) -#define ADC_OFCFGR1_SSAT_Msk (0x01UL << ADC_OFCFGR1_SSAT_Pos) /*!< 0x04000000 */ -#define ADC_OFCFGR1_SSAT ADC_OFCFGR1_SSAT_Msk /*!< ADC offset instance 1 signed satuaration enable */ - -#define ADC_OFCFGR1_OFFSET_CH_Pos (27UL) -#define ADC_OFCFGR1_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0xF8000000 */ -#define ADC_OFCFGR1_OFFSET_CH ADC_OFCFGR1_OFFSET_CH_Msk /*!< ADC offset instance 1 channel selection */ -#define ADC_OFCFGR1_OFFSET_CH_0 (0x01UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFCFGR1_OFFSET_CH_1 (0x02UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFCFGR1_OFFSET_CH_2 (0x03UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFCFGR1_OFFSET_CH_3 (0x04UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFCFGR1_OFFSET_CH_4 (0x05UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_OFCFGR2 register ***************/ -#define ADC_OFCFGR2_POSOFF_Pos (24UL) -#define ADC_OFCFGR2_POSOFF_Msk (0x01UL << ADC_OFCFGR2_POSOFF_Pos) /*!< 0x01000000 */ -#define ADC_OFCFGR2_POSOFF ADC_OFCFGR2_POSOFF_Msk /*!< ADC offset instance 2 positive offset enable */ - -#define ADC_OFCFGR2_USAT_Pos (25UL) -#define ADC_OFCFGR2_USAT_Msk (0x01UL << ADC_OFCFGR2_USAT_Pos) /*!< 0x02000000 */ -#define ADC_OFCFGR2_USAT ADC_OFCFGR2_USAT_Msk /*!< ADC offset instance 2 unsigned saturation value */ - -#define ADC_OFCFGR2_SSAT_Pos (26UL) -#define ADC_OFCFGR2_SSAT_Msk (0x01UL << ADC_OFCFGR2_SSAT_Pos) /*!< 0x04000000 */ -#define ADC_OFCFGR2_SSAT ADC_OFCFGR2_SSAT_Msk /*!< ADC offset instance 2 signed satuaration enable */ - -#define ADC_OFCFGR2_OFFSET_CH_Pos (27UL) -#define ADC_OFCFGR2_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0xF8000000 */ -#define ADC_OFCFGR2_OFFSET_CH ADC_OFCFGR2_OFFSET_CH_Msk /*!< ADC offset instance 2 channel selection */ -#define ADC_OFCFGR2_OFFSET_CH_0 (0x01UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFCFGR2_OFFSET_CH_1 (0x02UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFCFGR2_OFFSET_CH_2 (0x03UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFCFGR2_OFFSET_CH_3 (0x04UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFCFGR2_OFFSET_CH_4 (0x05UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_OFCFGR3 register ***************/ -#define ADC_OFCFGR3_POSOFF_Pos (24UL) -#define ADC_OFCFGR3_POSOFF_Msk (0x01UL << ADC_OFCFGR3_POSOFF_Pos) /*!< 0x01000000 */ -#define ADC_OFCFGR3_POSOFF ADC_OFCFGR3_POSOFF_Msk /*!< ADC offset instance 3 positive offset enable */ - -#define ADC_OFCFGR3_USAT_Pos (25UL) -#define ADC_OFCFGR3_USAT_Msk (0x01UL << ADC_OFCFGR3_USAT_Pos) /*!< 0x02000000 */ -#define ADC_OFCFGR3_USAT ADC_OFCFGR3_USAT_Msk /*!< ADC offset instance 3 unsigned saturation value */ - -#define ADC_OFCFGR3_SSAT_Pos (26UL) -#define ADC_OFCFGR3_SSAT_Msk (0x01UL << ADC_OFCFGR3_SSAT_Pos) /*!< 0x04000000 */ -#define ADC_OFCFGR3_SSAT ADC_OFCFGR3_SSAT_Msk /*!< ADC offset instance 3 signed satuaration enable */ - -#define ADC_OFCFGR3_OFFSET_CH_Pos (27UL) -#define ADC_OFCFGR3_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0xF8000000 */ -#define ADC_OFCFGR3_OFFSET_CH ADC_OFCFGR3_OFFSET_CH_Msk /*!< ADC offset instance 3 channel selection for the data offset */ -#define ADC_OFCFGR3_OFFSET_CH_0 (0x01UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFCFGR3_OFFSET_CH_1 (0x02UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFCFGR3_OFFSET_CH_2 (0x03UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFCFGR3_OFFSET_CH_3 (0x04UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFCFGR3_OFFSET_CH_4 (0x05UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_OFCFGR4 register ***************/ -#define ADC_OFCFGR4_POSOFF_Pos (24UL) -#define ADC_OFCFGR4_POSOFF_Msk (0x01UL << ADC_OFCFGR4_POSOFF_Pos) /*!< 0x01000000 */ -#define ADC_OFCFGR4_POSOFF ADC_OFCFGR4_POSOFF_Msk /*!< ADC offset instance 4 positive offset enable */ - -#define ADC_OFCFGR4_USAT_Pos (25UL) -#define ADC_OFCFGR4_USAT_Msk (0x01UL << ADC_OFCFGR4_USAT_Pos) /*!< 0x02000000 */ -#define ADC_OFCFGR4_USAT ADC_OFCFGR4_USAT_Msk /*!< ADC offset instance 4 unsigned saturation value */ - -#define ADC_OFCFGR4_SSAT_Pos (26UL) -#define ADC_OFCFGR4_SSAT_Msk (0x01UL << ADC_OFCFGR4_SSAT_Pos) /*!< 0x04000000 */ -#define ADC_OFCFGR4_SSAT ADC_OFCFGR4_SSAT_Msk /*!< ADC offset instance 4 signed satuaration enable */ - -#define ADC_OFCFGR4_OFFSET_CH_Pos (27UL) -#define ADC_OFCFGR4_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0xF8000000 */ -#define ADC_OFCFGR4_OFFSET_CH ADC_OFCFGR4_OFFSET_CH_Msk /*!< ADC offset instance 4 channel selection for the data offset */ -#define ADC_OFCFGR4_OFFSET_CH_0 (0x01UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFCFGR4_OFFSET_CH_1 (0x02UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFCFGR4_OFFSET_CH_2 (0x03UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFCFGR4_OFFSET_CH_3 (0x04UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFCFGR4_OFFSET_CH_4 (0x05UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_OFR1 register ******************/ -#define ADC_OFR1_OFFSET_Pos (0UL) -#define ADC_OFR1_OFFSET_Msk (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos) /*!< 0x003FFFFF */ -#define ADC_OFR1_OFFSET ADC_OFR1_OFFSET_Msk /*!< ADC offset instance 1 offset level */ -#define ADC_OFR1_OFFSET_0 (0x0000001UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000001 */ -#define ADC_OFR1_OFFSET_1 (0x0000002UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000002 */ -#define ADC_OFR1_OFFSET_2 (0x0000004UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000004 */ -#define ADC_OFR1_OFFSET_3 (0x0000008UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000008 */ -#define ADC_OFR1_OFFSET_4 (0x0000010UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000010 */ -#define ADC_OFR1_OFFSET_5 (0x0000020UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000020 */ -#define ADC_OFR1_OFFSET_6 (0x0000040UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000040 */ -#define ADC_OFR1_OFFSET_7 (0x0000080UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000080 */ -#define ADC_OFR1_OFFSET_8 (0x0000100UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000100 */ -#define ADC_OFR1_OFFSET_9 (0x0000200UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000200 */ -#define ADC_OFR1_OFFSET_10 (0x0000400UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000400 */ -#define ADC_OFR1_OFFSET_11 (0x0000800UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000800 */ -#define ADC_OFR1_OFFSET_12 (0x0001000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00001000 */ -#define ADC_OFR1_OFFSET_13 (0x0002000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00002000 */ -#define ADC_OFR1_OFFSET_14 (0x0004000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00004000 */ -#define ADC_OFR1_OFFSET_15 (0x0008000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00008000 */ -#define ADC_OFR1_OFFSET_16 (0x0010000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00010000 */ -#define ADC_OFR1_OFFSET_17 (0x0020000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00020000 */ -#define ADC_OFR1_OFFSET_18 (0x0040000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00040000 */ -#define ADC_OFR1_OFFSET_19 (0x0080000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00080000 */ -#define ADC_OFR1_OFFSET_20 (0x0100000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00100000 */ -#define ADC_OFR1_OFFSET_21 (0x0200000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00200000 */ - -/******************** Bit definition for ADC_OFR2 register ******************/ -#define ADC_OFR2_OFFSET_Pos (0UL) -#define ADC_OFR2_OFFSET_Msk (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos) /*!< 0x003FFFFF */ -#define ADC_OFR2_OFFSET ADC_OFR2_OFFSET_Msk /*!< ADC offset instance 2 offset level */ -#define ADC_OFR2_OFFSET_0 (0x0000001UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000001 */ -#define ADC_OFR2_OFFSET_1 (0x0000002UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000002 */ -#define ADC_OFR2_OFFSET_2 (0x0000004UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000004 */ -#define ADC_OFR2_OFFSET_3 (0x0000008UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000008 */ -#define ADC_OFR2_OFFSET_4 (0x0000010UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000010 */ -#define ADC_OFR2_OFFSET_5 (0x0000020UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000020 */ -#define ADC_OFR2_OFFSET_6 (0x0000040UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000040 */ -#define ADC_OFR2_OFFSET_7 (0x0000080UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000080 */ -#define ADC_OFR2_OFFSET_8 (0x0000100UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000100 */ -#define ADC_OFR2_OFFSET_9 (0x0000200UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000200 */ -#define ADC_OFR2_OFFSET_10 (0x0000400UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000400 */ -#define ADC_OFR2_OFFSET_11 (0x0000800UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000800 */ -#define ADC_OFR2_OFFSET_12 (0x0001000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00001000 */ -#define ADC_OFR2_OFFSET_13 (0x0002000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00002000 */ -#define ADC_OFR2_OFFSET_14 (0x0004000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00004000 */ -#define ADC_OFR2_OFFSET_15 (0x0008000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00008000 */ -#define ADC_OFR2_OFFSET_16 (0x0010000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00010000 */ -#define ADC_OFR2_OFFSET_17 (0x0020000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00020000 */ -#define ADC_OFR2_OFFSET_18 (0x0040000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00040000 */ -#define ADC_OFR2_OFFSET_19 (0x0080000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00080000 */ -#define ADC_OFR2_OFFSET_20 (0x0100000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00100000 */ -#define ADC_OFR2_OFFSET_21 (0x0200000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00200000 */ - -/******************** Bit definition for ADC_OFR3 register ******************/ -#define ADC_OFR3_OFFSET_Pos (0UL) -#define ADC_OFR3_OFFSET_Msk (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos) /*!< 0x003FFFFF */ -#define ADC_OFR3_OFFSET ADC_OFR3_OFFSET_Msk /*!< ADC offset instance 3 offset level */ -#define ADC_OFR3_OFFSET_0 (0x0000001UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000001 */ -#define ADC_OFR3_OFFSET_1 (0x0000002UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000002 */ -#define ADC_OFR3_OFFSET_2 (0x0000004UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000004 */ -#define ADC_OFR3_OFFSET_3 (0x0000008UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000008 */ -#define ADC_OFR3_OFFSET_4 (0x0000010UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000010 */ -#define ADC_OFR3_OFFSET_5 (0x0000020UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000020 */ -#define ADC_OFR3_OFFSET_6 (0x0000040UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000040 */ -#define ADC_OFR3_OFFSET_7 (0x0000080UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000080 */ -#define ADC_OFR3_OFFSET_8 (0x0000100UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000100 */ -#define ADC_OFR3_OFFSET_9 (0x0000200UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000200 */ -#define ADC_OFR3_OFFSET_10 (0x0000400UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000400 */ -#define ADC_OFR3_OFFSET_11 (0x0000800UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000800 */ -#define ADC_OFR3_OFFSET_12 (0x0001000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00001000 */ -#define ADC_OFR3_OFFSET_13 (0x0002000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00002000 */ -#define ADC_OFR3_OFFSET_14 (0x0004000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00004000 */ -#define ADC_OFR3_OFFSET_15 (0x0008000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00008000 */ -#define ADC_OFR3_OFFSET_16 (0x0010000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00010000 */ -#define ADC_OFR3_OFFSET_17 (0x0020000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00020000 */ -#define ADC_OFR3_OFFSET_18 (0x0040000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00040000 */ -#define ADC_OFR3_OFFSET_19 (0x0080000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00080000 */ -#define ADC_OFR3_OFFSET_20 (0x0100000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00100000 */ -#define ADC_OFR3_OFFSET_21 (0x0200000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00200000 */ - -/******************** Bit definition for ADC_OFR4 register ******************/ -#define ADC_OFR4_OFFSET_Pos (0UL) -#define ADC_OFR4_OFFSET_Msk (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos) /*!< 0x003FFFFF */ -#define ADC_OFR4_OFFSET ADC_OFR4_OFFSET_Msk /*!< ADC offset instance 4 offset level */ -#define ADC_OFR4_OFFSET_0 (0x0000001UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000001 */ -#define ADC_OFR4_OFFSET_1 (0x0000002UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000002 */ -#define ADC_OFR4_OFFSET_2 (0x0000004UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000004 */ -#define ADC_OFR4_OFFSET_3 (0x0000008UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000008 */ -#define ADC_OFR4_OFFSET_4 (0x0000010UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000010 */ -#define ADC_OFR4_OFFSET_5 (0x0000020UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000020 */ -#define ADC_OFR4_OFFSET_6 (0x0000040UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000040 */ -#define ADC_OFR4_OFFSET_7 (0x0000080UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000080 */ -#define ADC_OFR4_OFFSET_8 (0x0000100UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000100 */ -#define ADC_OFR4_OFFSET_9 (0x0000200UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000200 */ -#define ADC_OFR4_OFFSET_10 (0x0000400UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000400 */ -#define ADC_OFR4_OFFSET_11 (0x0000800UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000800 */ -#define ADC_OFR4_OFFSET_12 (0x0001000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00001000 */ -#define ADC_OFR4_OFFSET_13 (0x0002000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00002000 */ -#define ADC_OFR4_OFFSET_14 (0x0004000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00004000 */ -#define ADC_OFR4_OFFSET_15 (0x0008000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00008000 */ -#define ADC_OFR4_OFFSET_16 (0x0010000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00010000 */ -#define ADC_OFR4_OFFSET_17 (0x0020000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00020000 */ -#define ADC_OFR4_OFFSET_18 (0x0040000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00040000 */ -#define ADC_OFR4_OFFSET_19 (0x0080000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00080000 */ -#define ADC_OFR4_OFFSET_20 (0x0100000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00100000 */ -#define ADC_OFR4_OFFSET_21 (0x0200000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00200000 */ - -/******************** Bit definition for ADC_GCOMP register *****************/ -#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) -#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ -#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ -#define ADC_GCOMP_GCOMPCOEFF_0 (0x0001UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000001 */ -#define ADC_GCOMP_GCOMPCOEFF_1 (0x0002UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000002 */ -#define ADC_GCOMP_GCOMPCOEFF_2 (0x0004UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000004 */ -#define ADC_GCOMP_GCOMPCOEFF_3 (0x0008UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000008 */ -#define ADC_GCOMP_GCOMPCOEFF_4 (0x0010UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000010 */ -#define ADC_GCOMP_GCOMPCOEFF_5 (0x0020UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000020 */ -#define ADC_GCOMP_GCOMPCOEFF_6 (0x0040UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000040 */ -#define ADC_GCOMP_GCOMPCOEFF_7 (0x0080UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000080 */ -#define ADC_GCOMP_GCOMPCOEFF_8 (0x0100UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000100 */ -#define ADC_GCOMP_GCOMPCOEFF_9 (0x0200UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000200 */ -#define ADC_GCOMP_GCOMPCOEFF_10 (0x0400UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000400 */ -#define ADC_GCOMP_GCOMPCOEFF_11 (0x0800UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000800 */ -#define ADC_GCOMP_GCOMPCOEFF_12 (0x1000UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00001000 */ -#define ADC_GCOMP_GCOMPCOEFF_13 (0x2000UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00002000 */ - -#define ADC_GCOMP_GCOMP_Pos (31UL) -#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ -#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ - -/******************** Bit definition for ADC_JDR1 register ******************/ -#define ADC_JDR1_JDATA_Pos (0UL) -#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ -#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ -#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ -#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ -#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ -#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ -#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ -#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ -#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ -#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ -#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ -#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ -#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ -#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ -#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ -#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ -#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ -#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_JDR2 register ********************/ -#define ADC_JDR2_JDATA_Pos (0UL) -#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ -#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ -#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ -#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ -#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ -#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ -#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ -#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ -#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ -#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ -#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ -#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ -#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ -#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ -#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ -#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ -#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ -#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_JDR3 register ********************/ -#define ADC_JDR3_JDATA_Pos (0UL) -#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ -#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ -#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ -#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ -#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ -#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ -#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ -#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ -#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ -#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ -#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ -#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ -#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ -#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ -#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ -#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ -#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ -#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_JDR4 register ********************/ -#define ADC_JDR4_JDATA_Pos (0UL) -#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ -#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ -#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ -#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ -#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ -#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ -#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ -#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ -#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ -#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ -#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ -#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ -#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ -#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ -#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ -#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ -#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ -#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_AWD2CR register ****************/ -#define ADC_AWD2CR_AWD2CH_Pos (0UL) -#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ -#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for ADC_AWD3CR register ****************/ -#define ADC_AWD3CR_AWD3CH_Pos (0UL) -#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ -#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for ADC_AWD1TR_LT register *************/ -#define ADC_AWD1LTR_LTR_Pos (0UL) -#define ADC_AWD1LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ -#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_AWD1LTR_LTR_0 (0x000001UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ -#define ADC_AWD1LTR_LTR_1 (0x000002UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ -#define ADC_AWD1LTR_LTR_2 (0x000004UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ -#define ADC_AWD1LTR_LTR_3 (0x000008UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ -#define ADC_AWD1LTR_LTR_4 (0x000010UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ -#define ADC_AWD1LTR_LTR_5 (0x000020UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ -#define ADC_AWD1LTR_LTR_6 (0x000040UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ -#define ADC_AWD1LTR_LTR_7 (0x000080UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ -#define ADC_AWD1LTR_LTR_8 (0x000100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ -#define ADC_AWD1LTR_LTR_9 (0x000200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ -#define ADC_AWD1LTR_LTR_10 (0x000400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ -#define ADC_AWD1LTR_LTR_11 (0x000800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ -#define ADC_AWD1LTR_LTR_12 (0x001000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ -#define ADC_AWD1LTR_LTR_13 (0x002000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ -#define ADC_AWD1LTR_LTR_14 (0x004000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ -#define ADC_AWD1LTR_LTR_15 (0x008000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ -#define ADC_AWD1LTR_LTR_16 (0x010000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ -#define ADC_AWD1LTR_LTR_17 (0x020000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ -#define ADC_AWD1LTR_LTR_18 (0x040000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ -#define ADC_AWD1LTR_LTR_19 (0x080000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ -#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ -#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ -#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ - -/******************** Bit definition for ADC_AWD1TR_HT register *******************/ -#define ADC_AWD1HTR_HTR_Pos (0UL) -#define ADC_AWD1HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ -#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< ADC analog watchdog 1 threshold high */ -#define ADC_AWD1HTR_HTR_0 (0x000001UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ -#define ADC_AWD1HTR_HTR_1 (0x000002UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ -#define ADC_AWD1HTR_HTR_2 (0x000004UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ -#define ADC_AWD1HTR_HTR_3 (0x000008UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ -#define ADC_AWD1HTR_HTR_4 (0x000010UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ -#define ADC_AWD1HTR_HTR_5 (0x000020UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ -#define ADC_AWD1HTR_HTR_6 (0x000040UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ -#define ADC_AWD1HTR_HTR_7 (0x000080UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ -#define ADC_AWD1HTR_HTR_8 (0x000100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ -#define ADC_AWD1HTR_HTR_9 (0x000200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ -#define ADC_AWD1HTR_HTR_10 (0x000400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ -#define ADC_AWD1HTR_HTR_11 (0x000800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ -#define ADC_AWD1HTR_HTR_12 (0x001000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ -#define ADC_AWD1HTR_HTR_13 (0x002000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ -#define ADC_AWD1HTR_HTR_14 (0x004000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ -#define ADC_AWD1HTR_HTR_15 (0x008000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ -#define ADC_AWD1HTR_HTR_16 (0x010000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ -#define ADC_AWD1HTR_HTR_17 (0x020000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ -#define ADC_AWD1HTR_HTR_18 (0x040000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ -#define ADC_AWD1HTR_HTR_19 (0x080000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ -#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ -#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ -#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ - -#define ADC_AWD1HTR_AWDFILT_Pos (29UL) -#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000007 */ -#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< ADC analog watchdog 1 filtering */ -#define ADC_AWD1HTR_AWDFILT_0 (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */ -#define ADC_AWD1HTR_AWDFILT_1 (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */ -#define ADC_AWD1HTR_AWDFILT_2 (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for ADC_AWD2TR_LT register *******************/ -#define ADC_AWD2LTR_LTR_Pos (0UL) -#define ADC_AWD2LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ -#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_AWD2LTR_LTR_0 (0x000001UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ -#define ADC_AWD2LTR_LTR_1 (0x000002UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ -#define ADC_AWD2LTR_LTR_2 (0x000004UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ -#define ADC_AWD2LTR_LTR_3 (0x000008UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ -#define ADC_AWD2LTR_LTR_4 (0x000010UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ -#define ADC_AWD2LTR_LTR_5 (0x000020UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ -#define ADC_AWD2LTR_LTR_6 (0x000040UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ -#define ADC_AWD2LTR_LTR_7 (0x000080UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ -#define ADC_AWD2LTR_LTR_8 (0x000100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ -#define ADC_AWD2LTR_LTR_9 (0x000200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ -#define ADC_AWD2LTR_LTR_10 (0x000400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ -#define ADC_AWD2LTR_LTR_11 (0x000800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ -#define ADC_AWD2LTR_LTR_12 (0x001000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ -#define ADC_AWD2LTR_LTR_13 (0x002000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ -#define ADC_AWD2LTR_LTR_14 (0x004000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ -#define ADC_AWD2LTR_LTR_15 (0x008000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ -#define ADC_AWD2LTR_LTR_16 (0x010000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ -#define ADC_AWD2LTR_LTR_17 (0x020000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ -#define ADC_AWD2LTR_LTR_18 (0x040000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ -#define ADC_AWD2LTR_LTR_19 (0x080000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ -#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ -#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ -#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ - -/******************** Bit definition for ADC_AWD2TR_HT register *******************/ -#define ADC_AWD2HTR_HTR_Pos (0UL) -#define ADC_AWD2HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ -#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_AWD2HTR_HTR_0 (0x000001UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ -#define ADC_AWD2HTR_HTR_1 (0x000002UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ -#define ADC_AWD2HTR_HTR_2 (0x000004UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ -#define ADC_AWD2HTR_HTR_3 (0x000008UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ -#define ADC_AWD2HTR_HTR_4 (0x000010UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ -#define ADC_AWD2HTR_HTR_5 (0x000020UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ -#define ADC_AWD2HTR_HTR_6 (0x000040UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ -#define ADC_AWD2HTR_HTR_7 (0x000080UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ -#define ADC_AWD2HTR_HTR_8 (0x000100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ -#define ADC_AWD2HTR_HTR_9 (0x000200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ -#define ADC_AWD2HTR_HTR_10 (0x000400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ -#define ADC_AWD2HTR_HTR_11 (0x000800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ -#define ADC_AWD2HTR_HTR_12 (0x001000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ -#define ADC_AWD2HTR_HTR_13 (0x002000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ -#define ADC_AWD2HTR_HTR_14 (0x004000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ -#define ADC_AWD2HTR_HTR_15 (0x008000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ -#define ADC_AWD2HTR_HTR_16 (0x010000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ -#define ADC_AWD2HTR_HTR_17 (0x020000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ -#define ADC_AWD2HTR_HTR_18 (0x040000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ -#define ADC_AWD2HTR_HTR_19 (0x080000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ -#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ -#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ -#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ - -/******************** Bit definition for ADC_AWD3TR_LT register *******************/ -#define ADC_AWD3LTR_LTR_Pos (0UL) -#define ADC_AWD3LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ -#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_AWD3LTR_LTR_0 (0x000001UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ -#define ADC_AWD3LTR_LTR_1 (0x000002UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ -#define ADC_AWD3LTR_LTR_2 (0x000004UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ -#define ADC_AWD3LTR_LTR_3 (0x000008UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ -#define ADC_AWD3LTR_LTR_4 (0x000010UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ -#define ADC_AWD3LTR_LTR_5 (0x000020UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ -#define ADC_AWD3LTR_LTR_6 (0x000040UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ -#define ADC_AWD3LTR_LTR_7 (0x000080UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ -#define ADC_AWD3LTR_LTR_8 (0x000100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ -#define ADC_AWD3LTR_LTR_9 (0x000200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ -#define ADC_AWD3LTR_LTR_10 (0x000400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ -#define ADC_AWD3LTR_LTR_11 (0x000800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ -#define ADC_AWD3LTR_LTR_12 (0x001000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ -#define ADC_AWD3LTR_LTR_13 (0x002000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ -#define ADC_AWD3LTR_LTR_14 (0x004000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ -#define ADC_AWD3LTR_LTR_15 (0x008000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ -#define ADC_AWD3LTR_LTR_16 (0x010000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ -#define ADC_AWD3LTR_LTR_17 (0x020000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ -#define ADC_AWD3LTR_LTR_18 (0x040000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ -#define ADC_AWD3LTR_LTR_19 (0x080000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ -#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ -#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ -#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ - -/******************** Bit definition for ADC_AWD3TR_HT register *******************/ -#define ADC_AWD3HTR_HTR_Pos (0UL) -#define ADC_AWD3HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ -#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_AWD3HTR_HTR_0 (0x000001UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ -#define ADC_AWD3HTR_HTR_1 (0x000002UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ -#define ADC_AWD3HTR_HTR_2 (0x000004UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ -#define ADC_AWD3HTR_HTR_3 (0x000008UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ -#define ADC_AWD3HTR_HTR_4 (0x000010UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ -#define ADC_AWD3HTR_HTR_5 (0x000020UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ -#define ADC_AWD3HTR_HTR_6 (0x000040UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ -#define ADC_AWD3HTR_HTR_7 (0x000080UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ -#define ADC_AWD3HTR_HTR_8 (0x000100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ -#define ADC_AWD3HTR_HTR_9 (0x000200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ -#define ADC_AWD3HTR_HTR_10 (0x000400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ -#define ADC_AWD3HTR_HTR_11 (0x000800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ -#define ADC_AWD3HTR_HTR_12 (0x001000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ -#define ADC_AWD3HTR_HTR_13 (0x002000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ -#define ADC_AWD3HTR_HTR_14 (0x004000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ -#define ADC_AWD3HTR_HTR_15 (0x008000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ -#define ADC_AWD3HTR_HTR_16 (0x010000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ -#define ADC_AWD3HTR_HTR_17 (0x020000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ -#define ADC_AWD3HTR_HTR_18 (0x040000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ -#define ADC_AWD3HTR_HTR_19 (0x080000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ -#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ -#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ -#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ - -/******************** Bit definition for ADC_CALFACT register ***************/ - -#define ADC_CALFACT_CALFACT_Pos (0UL) -#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ -#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ -#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ -#define ADC_CALFACT_CALFACT_7 (0x80UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000080 */ -#define ADC_CALFACT_CALFACT_8 (0x100UL<< ADC_CALFACT_CALFACT_Pos) /*!< 0x00000100 */ -#define ADC_CALFACT_CALFACT_9 (0x200UL<< ADC_CALFACT_CALFACT_Pos) /*!< 0x00000200 */ - - -/******************** Bit definition for ADC_OR option register ***************/ -#define ADC_OR_VDDCOREEN_Pos (0UL) -#define ADC_OR_VDDCOREEN_Msk (0x1UL << ADC_OR_VDDCOREEN_Pos) /*!< 0x00000004 */ -#define ADC_OR_VDDCOREEN ADC_OR_VDDCOREEN_Msk /*!< ADC internal path to VDDCORE */ - -/************************* ADC Common registers *****************************/ -/******************** Bit definition for ADC_CSR register *******************/ -#define ADC_CSR_ADRDY_MST_Pos (0UL) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ -#define ADC_CSR_EOSMP_MST_Pos (1UL) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ -#define ADC_CSR_EOC_MST_Pos (2UL) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ -#define ADC_CSR_EOS_MST_Pos (3UL) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ -#define ADC_CSR_OVR_MST_Pos (4UL) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ -#define ADC_CSR_JEOC_MST_Pos (5UL) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ -#define ADC_CSR_JEOS_MST_Pos (6UL) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ -#define ADC_CSR_AWD1_MST_Pos (7UL) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ -#define ADC_CSR_AWD2_MST_Pos (8UL) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ -#define ADC_CSR_AWD3_MST_Pos (9UL) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ -#define ADC_CSR_JQOVF_MST_Pos (10UL) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ -#define ADC_CSR_LDORDY_MST_Pos (12UL) -#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ -#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< ADC multimode master internal voltage regulator output ready flag */ - -#define ADC_CSR_ADRDY_SLV_Pos (16UL) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ -#define ADC_CSR_EOSMP_SLV_Pos (17UL) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ -#define ADC_CSR_EOC_SLV_Pos (18UL) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ -#define ADC_CSR_EOS_SLV_Pos (19UL) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ -#define ADC_CSR_OVR_SLV_Pos (20UL) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ -#define ADC_CSR_JEOC_SLV_Pos (21UL) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ -#define ADC_CSR_JEOS_SLV_Pos (22UL) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ -#define ADC_CSR_AWD1_SLV_Pos (23UL) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ -#define ADC_CSR_AWD2_SLV_Pos (24UL) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ -#define ADC_CSR_AWD3_SLV_Pos (25UL) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ -#define ADC_CSR_JQOVF_SLV_Pos (26UL) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ -#define ADC_CSR_LDORDY_SLV_Pos (28UL) -#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ -#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< ADC multimode slave internal voltage regulator output ready flag */ - -/******************** Bit definition for ADC_CCR register *******************/ -#define ADC_CCR_DUAL_Pos (0UL) -#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ -#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ -#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ -#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ -#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ -#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ -#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ - -#define ADC_CCR_DELAY_Pos (8UL) -#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ -#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ -#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ -#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ -#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ -#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ - -#define ADC_CCR_DAMDF_Pos (14UL) -#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ -#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< ADC multimode data format */ -#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ -#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ - -#define ADC_CCR_PRESC_Pos (18UL) -#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ -#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler */ -#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ -#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ -#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ -#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ - -#define ADC_CCR_VREFEN_Pos (22UL) -#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ -#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ - -#define ADC_CCR_TSEN_Pos (23UL) -#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to Temperature sensor voltage enable */ - -#define ADC_CCR_VBATEN_Pos (24UL) -#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ -#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ - -/******************** Bit definition for ADC_CDR register *******************/ -#define ADC_CDR_RDATA_MST_Pos (0UL) -#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ -#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ - -#define ADC_CDR_RDATA_SLV_Pos (16UL) -#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ -#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ - -/******************** Bit definition for ADC_CDR2 register ******************/ -#define ADC_CDR2_RDATA_ALT_Pos (0UL) -#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ -#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< ADC multimode master or slave (alternated) group regular conversion data */ - -/******************************************************************************/ -/* */ -/* CRC calculation unit */ -/* */ -/******************************************************************************/ -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR_Pos (0UL) -#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ -#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR_Pos (0UL) -#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ -#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET_Pos (0UL) -#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ -#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE_Pos (3UL) -#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ -#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ -#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ -#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ -#define CRC_CR_REV_IN_Pos (5UL) -#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ -#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ -#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ -#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ -#define CRC_CR_REV_OUT_Pos (7UL) -#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ -#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ -#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ -#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ -#define CRC_CR_RTYPE_IN_Pos (9UL) -#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ -#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< RTYPE_IN Reverse Type Input bit */ -#define CRC_CR_RTYPE_OUT_Pos (10UL) -#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ -#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< RTYPE_OUT Reverse Type Output bit */ - -/******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT_Pos (0UL) -#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ -#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ - -/******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL_Pos (0UL) -#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ -#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ - -/******************************************************************************/ -/* */ -/* CRS Clock Recovery System */ -/******************************************************************************/ -/******************* Bit definition for CRS_CR register *********************/ -#define CRS_CR_SYNCOKIE_Pos (0UL) -#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ -#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ -#define CRS_CR_SYNCWARNIE_Pos (1UL) -#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ -#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ -#define CRS_CR_ERRIE_Pos (2UL) -#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ -#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ -#define CRS_CR_ESYNCIE_Pos (3UL) -#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ -#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ -#define CRS_CR_CEN_Pos (5UL) -#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ -#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ -#define CRS_CR_AUTOTRIMEN_Pos (6UL) -#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ -#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ -#define CRS_CR_SWSYNC_Pos (7UL) -#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ -#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ -#define CRS_CR_TRIM_Pos (8UL) -#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ -#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ - -/******************* Bit definition for CRS_CFGR register *********************/ -#define CRS_CFGR_RELOAD_Pos (0UL) -#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ -#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ -#define CRS_CFGR_FELIM_Pos (16UL) -#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ -#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ -#define CRS_CFGR_SYNCDIV_Pos (24UL) -#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ -#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ -#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ -#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ -#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ -#define CRS_CFGR_SYNCSRC_Pos (28UL) -#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ -#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ -#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ -#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ -#define CRS_CFGR_SYNCPOL_Pos (31UL) -#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ -#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ - -/******************* Bit definition for CRS_ISR register *********************/ -#define CRS_ISR_SYNCOKF_Pos (0UL) -#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ -#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ -#define CRS_ISR_SYNCWARNF_Pos (1UL) -#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ -#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ -#define CRS_ISR_ERRF_Pos (2UL) -#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ -#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ -#define CRS_ISR_ESYNCF_Pos (3UL) -#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ -#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ -#define CRS_ISR_SYNCERR_Pos (8UL) -#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ -#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ -#define CRS_ISR_SYNCMISS_Pos (9UL) -#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ -#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ -#define CRS_ISR_TRIMOVF_Pos (10UL) -#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ -#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ -#define CRS_ISR_FEDIR_Pos (15UL) -#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ -#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ -#define CRS_ISR_FECAP_Pos (16UL) -#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ -#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ - -/******************* Bit definition for CRS_ICR register *********************/ -#define CRS_ICR_SYNCOKC_Pos (0UL) -#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ -#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ -#define CRS_ICR_SYNCWARNC_Pos (1UL) -#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ -#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ -#define CRS_ICR_ERRC_Pos (2UL) -#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ -#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ -#define CRS_ICR_ESYNCC_Pos (3UL) -#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ -#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ - -/******************************************************************************/ -/* */ -/* Analog Comparators (COMP) */ -/* */ -/******************************************************************************/ -/*!< ****************** Bit definition for COMPx_CSR register ********************/ -#define COMP_CSR_EN_Pos (0UL) -#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ -#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< COMPx enable bit */ -#define COMP_CSR_INMSEL_Pos (4UL) -#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00070000 */ -#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< COMPx input minus selection bit */ -#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00010000 */ -#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00020000 */ -#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00040000 */ -#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00080000 */ -#define COMP_CSR_INPSEL_Pos (8UL) -#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00100000 */ -#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< COMPx input plus selection bit */ -#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) -#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) -#define COMP_CSR_WINMODE_Pos (11UL) -#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000010 */ -#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< COMPx Windows mode selection bit */ -#define COMP_CSR_WINOUT_Pos (14UL) -#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00000008 */ -#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< COMPx polarity selection bit */ -#define COMP_CSR_POLARITY_Pos (15UL) -#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00000008 */ -#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< COMPx polarity selection bit */ -#define COMP_CSR_HYST_Pos (16UL) -#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00000300 */ -#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< COMPx hysteresis selection bits */ -#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00000100 */ -#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00000200 */ -#define COMP_CSR_PWRMODE_Pos (18UL) -#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00003000 */ -#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */ -#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00001000 */ -#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00002000 */ -#define COMP_CSR_BLANKSEL_Pos (20UL) -#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x0F000000 */ -#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< COMPx blanking source selection bits */ -#define COMP_CSR_BLANKSEL_0 (0x1UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ -#define COMP_CSR_BLANKSEL_1 (0x2UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x02000000 */ -#define COMP_CSR_BLANKSEL_2 (0x4UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x04000000 */ -#define COMP_CSR_BLANKSEL_3 (0x8UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x08000000 */ -#define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ -#define COMP2_CSR_BLANKSEL_2 COMP_CSR_BLANKSEL_2 /*!< COMP2 blanking source selection bit 2 */ -#define COMP_CSR_VALUE_Pos (30UL) -#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x00000001 */ -#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< COMPx enable bit */ -#define COMP_CSR_LOCK_Pos (31UL) -#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ -#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< COMPx Lock Bit */ - -/******************************************************************************/ -/* */ -/* Digital to Analog Converter */ -/* */ -/******************************************************************************/ -#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ - -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1_Pos (0UL) -#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ -#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14UL) -#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ -#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16UL) -#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ -#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30UL) -#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ -#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ -#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!(1)) */ - -#define HSP_ITFENR_TRGOEN_Pos (12UL) -#define HSP_ITFENR_TRGOEN_Msk (0x1UL << HSP_ITFENR_TRGOEN_Pos) /*!< 0x00001000 */ -#define HSP_ITFENR_TRGOEN HSP_ITFENR_TRGOEN_Msk /*!< TRGOEN (TRGO enable bit (1)) */ - -#define HSP_ITFENR_TRGI0EN_Pos (16UL) -#define HSP_ITFENR_TRGI0EN_Msk (0x1UL << HSP_ITFENR_TRGI0EN_Pos) /*!< 0x00010000 */ -#define HSP_ITFENR_TRGI0EN HSP_ITFENR_TRGI0EN_Msk /*!< TRGI0EN (TRGIN0 enable bit (1)) */ - -#define HSP_ITFENR_TRGI1EN_Pos (17UL) -#define HSP_ITFENR_TRGI1EN_Msk (0x1UL << HSP_ITFENR_TRGI1EN_Pos) /*!< 0x00020000 */ -#define HSP_ITFENR_TRGI1EN HSP_ITFENR_TRGI1EN_Msk /*!< TRGI1EN (TRGIN1 enable bit (1)) */ - -#define HSP_ITFENR_TRGI2EN_Pos (18UL) -#define HSP_ITFENR_TRGI2EN_Msk (0x1UL << HSP_ITFENR_TRGI2EN_Pos) /*!< 0x00040000 */ -#define HSP_ITFENR_TRGI2EN HSP_ITFENR_TRGI2EN_Msk /*!< TRGI2EN (TRGIN2 enable bit (1)) */ - -#define HSP_ITFENR_TRGI3EN_Pos (19UL) -#define HSP_ITFENR_TRGI3EN_Msk (0x1UL << HSP_ITFENR_TRGI3EN_Pos) /*!< 0x00080000 */ -#define HSP_ITFENR_TRGI3EN HSP_ITFENR_TRGI3EN_Msk /*!< TRGI3EN (TRGIN3 enable bit (1)) */ - -#define HSP_ITFENR_TRGI4EN_Pos (20UL) -#define HSP_ITFENR_TRGI4EN_Msk (0x1UL << HSP_ITFENR_TRGI4EN_Pos) /*!< 0x00100000 */ -#define HSP_ITFENR_TRGI4EN HSP_ITFENR_TRGI4EN_Msk /*!< TRGI4EN (TRGIN4 enable bit (1)) */ - -#define HSP_ITFENR_TRGI5EN_Pos (21UL) -#define HSP_ITFENR_TRGI5EN_Msk (0x1UL << HSP_ITFENR_TRGI5EN_Pos) /*!< 0x00200000 */ -#define HSP_ITFENR_TRGI5EN HSP_ITFENR_TRGI5EN_Msk /*!< TRGI5EN (TRGIN5 enable bit (1)) */ - -#define HSP_ITFENR_TRGI6EN_Pos (22UL) -#define HSP_ITFENR_TRGI6EN_Msk (0x1UL << HSP_ITFENR_TRGI6EN_Pos) /*!< 0x00400000 */ -#define HSP_ITFENR_TRGI6EN HSP_ITFENR_TRGI6EN_Msk /*!< TRGI6EN (TRGIN6 enable bit (1)) */ - -#define HSP_ITFENR_TRGI7EN_Pos (23UL) -#define HSP_ITFENR_TRGI7EN_Msk (0x1UL << HSP_ITFENR_TRGI7EN_Pos) /*!< 0x00800000 */ -#define HSP_ITFENR_TRGI7EN HSP_ITFENR_TRGI7EN_Msk /*!< TRGI7EN (TRGIN7 enable bit (1)) */ - -#define HSP_ITFENR_TRGI8EN_Pos (24UL) -#define HSP_ITFENR_TRGI8EN_Msk (0x1UL << HSP_ITFENR_TRGI8EN_Pos) /*!< 0x01000000 */ -#define HSP_ITFENR_TRGI8EN HSP_ITFENR_TRGI8EN_Msk /*!< TRGI8EN (TRGIN8 enable bit (1)) */ - -#define HSP_ITFENR_TRGI9EN_Pos (25UL) -#define HSP_ITFENR_TRGI9EN_Msk (0x1UL << HSP_ITFENR_TRGI9EN_Pos) /*!< 0x02000000 */ -#define HSP_ITFENR_TRGI9EN HSP_ITFENR_TRGI9EN_Msk /*!< TRGI9EN (TRGIN9 enable bit (1)) */ - -#define HSP_ITFENR_DCMDDIS_Pos (27UL) -#define HSP_ITFENR_DCMDDIS_Msk (0x1UL << HSP_ITFENR_DCMDDIS_Pos) /*!< 0x08000000 */ -#define HSP_ITFENR_DCMDDIS HSP_ITFENR_DCMDDIS_Msk /*!< DCMDDIS (Direct command interface disable bit ) */ - -#define HSP_ITFENR_CSEGEN_Pos (28UL) -#define HSP_ITFENR_CSEGEN_Msk (0x1UL << HSP_ITFENR_CSEGEN_Pos) /*!< 0x10000000 */ -#define HSP_ITFENR_CSEGEN HSP_ITFENR_CSEGEN_Msk /*!< CSEGEN (CSEG interface enable bit (1)) */ - -#define HSP_ITFENR_CDEGEN_Pos (29UL) -#define HSP_ITFENR_CDEGEN_Msk (0x1UL << HSP_ITFENR_CDEGEN_Pos) /*!< 0x20000000 */ -#define HSP_ITFENR_CDEGEN HSP_ITFENR_CDEGEN_Msk /*!< CDEGEN (CDEG interface enable bit ) */ - -#define HSP_ITFENR_HSEGEN_Pos (30UL) -#define HSP_ITFENR_HSEGEN_Msk (0x1UL << HSP_ITFENR_HSEGEN_Pos) /*!< 0x40000000 */ -#define HSP_ITFENR_HSEGEN HSP_ITFENR_HSEGEN_Msk /*!< HSEGEN (HSEG interface enable bit ) */ - -#define HSP_ITFENR_HDEGEN_Pos (31UL) -#define HSP_ITFENR_HDEGEN_Msk (0x1UL << HSP_ITFENR_HDEGEN_Pos) /*!< 0x80000000 */ -#define HSP_ITFENR_HDEGEN HSP_ITFENR_HDEGEN_Msk /*!< HDEGEN (HDEG interface enable bit ) */ - -/******************** Bit definition for HSP_EVTSRC0R register ********************/ -#define HSP_EVTSRC0R_EVT1SRC_Pos (0UL) -#define HSP_EVTSRC0R_EVT1SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000007 */ -#define HSP_EVTSRC0R_EVT1SRC HSP_EVTSRC0R_EVT1SRC_Msk /*!< EVT1SRC[2:0] bits (Event source selection for priority encoder input 1) */ -#define HSP_EVTSRC0R_EVT1SRC_0 (0x1UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000001 */ -#define HSP_EVTSRC0R_EVT1SRC_1 (0x2UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000002 */ -#define HSP_EVTSRC0R_EVT1SRC_2 (0x4UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000004 */ - -#define HSP_EVTSRC0R_EVT2SRC_Pos (4UL) -#define HSP_EVTSRC0R_EVT2SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000070 */ -#define HSP_EVTSRC0R_EVT2SRC HSP_EVTSRC0R_EVT2SRC_Msk /*!< EVT2SRC[2:0] bits (Event source selection for priority encoder input 2) */ -#define HSP_EVTSRC0R_EVT2SRC_0 (0x1UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000010 */ -#define HSP_EVTSRC0R_EVT2SRC_1 (0x2UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000020 */ -#define HSP_EVTSRC0R_EVT2SRC_2 (0x4UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000040 */ - -#define HSP_EVTSRC0R_EVT3SRC_Pos (8UL) -#define HSP_EVTSRC0R_EVT3SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000700 */ -#define HSP_EVTSRC0R_EVT3SRC HSP_EVTSRC0R_EVT3SRC_Msk /*!< EVT3SRC[2:0] bits (Event source selection for priority encoder input 3) */ -#define HSP_EVTSRC0R_EVT3SRC_0 (0x1UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000100 */ -#define HSP_EVTSRC0R_EVT3SRC_1 (0x2UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000200 */ -#define HSP_EVTSRC0R_EVT3SRC_2 (0x4UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000400 */ - -#define HSP_EVTSRC0R_EVT4SRC_Pos (12UL) -#define HSP_EVTSRC0R_EVT4SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00007000 */ -#define HSP_EVTSRC0R_EVT4SRC HSP_EVTSRC0R_EVT4SRC_Msk /*!< EVT4SRC[2:0] bits (Event source selection for priority encoder input 4) */ -#define HSP_EVTSRC0R_EVT4SRC_0 (0x1UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00001000 */ -#define HSP_EVTSRC0R_EVT4SRC_1 (0x2UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00002000 */ -#define HSP_EVTSRC0R_EVT4SRC_2 (0x4UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00004000 */ - -#define HSP_EVTSRC0R_EVT5SRC_Pos (16UL) -#define HSP_EVTSRC0R_EVT5SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00070000 */ -#define HSP_EVTSRC0R_EVT5SRC HSP_EVTSRC0R_EVT5SRC_Msk /*!< EVT5SRC[2:0] bits (Event source selection for priority encoder input 5) */ -#define HSP_EVTSRC0R_EVT5SRC_0 (0x1UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00010000 */ -#define HSP_EVTSRC0R_EVT5SRC_1 (0x2UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00020000 */ -#define HSP_EVTSRC0R_EVT5SRC_2 (0x4UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00040000 */ - -#define HSP_EVTSRC0R_EVT6SRC_Pos (20UL) -#define HSP_EVTSRC0R_EVT6SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00700000 */ -#define HSP_EVTSRC0R_EVT6SRC HSP_EVTSRC0R_EVT6SRC_Msk /*!< EVT6SRC[2:0] bits (Event source selection for priority encoder input 6) */ -#define HSP_EVTSRC0R_EVT6SRC_0 (0x1UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00100000 */ -#define HSP_EVTSRC0R_EVT6SRC_1 (0x2UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00200000 */ -#define HSP_EVTSRC0R_EVT6SRC_2 (0x4UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00400000 */ - -#define HSP_EVTSRC0R_EVT7SRC_Pos (24UL) -#define HSP_EVTSRC0R_EVT7SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x07000000 */ -#define HSP_EVTSRC0R_EVT7SRC HSP_EVTSRC0R_EVT7SRC_Msk /*!< EVT7SRC[2:0] bits (Event source selection for priority encoder input 7) */ -#define HSP_EVTSRC0R_EVT7SRC_0 (0x1UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x01000000 */ -#define HSP_EVTSRC0R_EVT7SRC_1 (0x2UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x02000000 */ -#define HSP_EVTSRC0R_EVT7SRC_2 (0x4UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x04000000 */ - -#define HSP_EVTSRC0R_EVT8SRC_Pos (28UL) -#define HSP_EVTSRC0R_EVT8SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x70000000 */ -#define HSP_EVTSRC0R_EVT8SRC HSP_EVTSRC0R_EVT8SRC_Msk /*!< EVT8SRC[2:0] bits (Event source selection for priority encoder input 8) */ -#define HSP_EVTSRC0R_EVT8SRC_0 (0x1UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x10000000 */ -#define HSP_EVTSRC0R_EVT8SRC_1 (0x2UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x20000000 */ -#define HSP_EVTSRC0R_EVT8SRC_2 (0x4UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for HSP_EVTSRC1R register ********************/ -#define HSP_EVTSRC1R_EVT9SRC_Pos (0UL) -#define HSP_EVTSRC1R_EVT9SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000007 */ -#define HSP_EVTSRC1R_EVT9SRC HSP_EVTSRC1R_EVT9SRC_Msk /*!< EVT9SRC[2:0] bits (Event source selection for priority encoder input 9) */ -#define HSP_EVTSRC1R_EVT9SRC_0 (0x1UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000001 */ -#define HSP_EVTSRC1R_EVT9SRC_1 (0x2UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000002 */ -#define HSP_EVTSRC1R_EVT9SRC_2 (0x4UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000004 */ - -#define HSP_EVTSRC1R_EVT10SRC_Pos (4UL) -#define HSP_EVTSRC1R_EVT10SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000070 */ -#define HSP_EVTSRC1R_EVT10SRC HSP_EVTSRC1R_EVT10SRC_Msk /*!< EVT10SRC[2:0] bits (Event source selection for priority encoder input 10) */ -#define HSP_EVTSRC1R_EVT10SRC_0 (0x1UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000010 */ -#define HSP_EVTSRC1R_EVT10SRC_1 (0x2UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000020 */ -#define HSP_EVTSRC1R_EVT10SRC_2 (0x4UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000040 */ - -#define HSP_EVTSRC1R_EVT11SRC_Pos (8UL) -#define HSP_EVTSRC1R_EVT11SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000700 */ -#define HSP_EVTSRC1R_EVT11SRC HSP_EVTSRC1R_EVT11SRC_Msk /*!< EVT11SRC[2:0] bits (Event source selection for priority encoder input 11) */ -#define HSP_EVTSRC1R_EVT11SRC_0 (0x1UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000100 */ -#define HSP_EVTSRC1R_EVT11SRC_1 (0x2UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000200 */ -#define HSP_EVTSRC1R_EVT11SRC_2 (0x4UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000400 */ - -#define HSP_EVTSRC1R_EVT12SRC_Pos (12UL) -#define HSP_EVTSRC1R_EVT12SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00007000 */ -#define HSP_EVTSRC1R_EVT12SRC HSP_EVTSRC1R_EVT12SRC_Msk /*!< EVT12SRC[2:0] bits (Event source selection for priority encoder input 12) */ -#define HSP_EVTSRC1R_EVT12SRC_0 (0x1UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00001000 */ -#define HSP_EVTSRC1R_EVT12SRC_1 (0x2UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00002000 */ -#define HSP_EVTSRC1R_EVT12SRC_2 (0x4UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00004000 */ - -#define HSP_EVTSRC1R_EVT13SRC_Pos (16UL) -#define HSP_EVTSRC1R_EVT13SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00070000 */ -#define HSP_EVTSRC1R_EVT13SRC HSP_EVTSRC1R_EVT13SRC_Msk /*!< EVT13SRC[2:0] bits (Event source selection for priority encoder input 13) */ -#define HSP_EVTSRC1R_EVT13SRC_0 (0x1UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00010000 */ -#define HSP_EVTSRC1R_EVT13SRC_1 (0x2UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00020000 */ -#define HSP_EVTSRC1R_EVT13SRC_2 (0x4UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00040000 */ - -#define HSP_EVTSRC1R_EVT14SRC_Pos (20UL) -#define HSP_EVTSRC1R_EVT14SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00700000 */ -#define HSP_EVTSRC1R_EVT14SRC HSP_EVTSRC1R_EVT14SRC_Msk /*!< EVT14SRC[2:0] bits (Event source selection for priority encoder input 14) */ -#define HSP_EVTSRC1R_EVT14SRC_0 (0x1UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00100000 */ -#define HSP_EVTSRC1R_EVT14SRC_1 (0x2UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00200000 */ -#define HSP_EVTSRC1R_EVT14SRC_2 (0x4UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00400000 */ - -#define HSP_EVTSRC1R_EVT15SRC_Pos (24UL) -#define HSP_EVTSRC1R_EVT15SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x07000000 */ -#define HSP_EVTSRC1R_EVT15SRC HSP_EVTSRC1R_EVT15SRC_Msk /*!< EVT15SRC[2:0] bits (Event source selection for priority encoder input 15) */ -#define HSP_EVTSRC1R_EVT15SRC_0 (0x1UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x01000000 */ -#define HSP_EVTSRC1R_EVT15SRC_1 (0x2UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x02000000 */ -#define HSP_EVTSRC1R_EVT15SRC_2 (0x4UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x04000000 */ - -#define HSP_EVTSRC1R_EVT16SRC_Pos (28UL) -#define HSP_EVTSRC1R_EVT16SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x70000000 */ -#define HSP_EVTSRC1R_EVT16SRC HSP_EVTSRC1R_EVT16SRC_Msk /*!< EVT16SRC[2:0] bits (Event source selection for priority encoder input 16) */ -#define HSP_EVTSRC1R_EVT16SRC_0 (0x1UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x10000000 */ -#define HSP_EVTSRC1R_EVT16SRC_1 (0x2UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x20000000 */ -#define HSP_EVTSRC1R_EVT16SRC_2 (0x4UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for HSP_EVTSRC2R register ********************/ -#define HSP_EVTSRC2R_EVT17SRC_Pos (0UL) -#define HSP_EVTSRC2R_EVT17SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000007 */ -#define HSP_EVTSRC2R_EVT17SRC HSP_EVTSRC2R_EVT17SRC_Msk /*!< EVT17SRC[2:0] bits (Event source selection for priority encoder input 17) */ -#define HSP_EVTSRC2R_EVT17SRC_0 (0x1UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000001 */ -#define HSP_EVTSRC2R_EVT17SRC_1 (0x2UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000002 */ -#define HSP_EVTSRC2R_EVT17SRC_2 (0x4UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000004 */ - -#define HSP_EVTSRC2R_EVT18SRC_Pos (4UL) -#define HSP_EVTSRC2R_EVT18SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000070 */ -#define HSP_EVTSRC2R_EVT18SRC HSP_EVTSRC2R_EVT18SRC_Msk /*!< EVT18SRC[2:0] bits (Event source selection for priority encoder input 18) */ -#define HSP_EVTSRC2R_EVT18SRC_0 (0x1UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000010 */ -#define HSP_EVTSRC2R_EVT18SRC_1 (0x2UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000020 */ -#define HSP_EVTSRC2R_EVT18SRC_2 (0x4UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000040 */ - -#define HSP_EVTSRC2R_EVT19SRC_Pos (8UL) -#define HSP_EVTSRC2R_EVT19SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000700 */ -#define HSP_EVTSRC2R_EVT19SRC HSP_EVTSRC2R_EVT19SRC_Msk /*!< EVT19SRC[2:0] bits (Event source selection for priority encoder input 19) */ -#define HSP_EVTSRC2R_EVT19SRC_0 (0x1UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000100 */ -#define HSP_EVTSRC2R_EVT19SRC_1 (0x2UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000200 */ -#define HSP_EVTSRC2R_EVT19SRC_2 (0x4UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000400 */ - -#define HSP_EVTSRC2R_EVT20SRC_Pos (12UL) -#define HSP_EVTSRC2R_EVT20SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00007000 */ -#define HSP_EVTSRC2R_EVT20SRC HSP_EVTSRC2R_EVT20SRC_Msk /*!< EVT20SRC[2:0] bits (Event source selection for priority encoder input 20) */ -#define HSP_EVTSRC2R_EVT20SRC_0 (0x1UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00001000 */ -#define HSP_EVTSRC2R_EVT20SRC_1 (0x2UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00002000 */ -#define HSP_EVTSRC2R_EVT20SRC_2 (0x4UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00004000 */ - -#define HSP_EVTSRC2R_EVT21SRC_Pos (16UL) -#define HSP_EVTSRC2R_EVT21SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00070000 */ -#define HSP_EVTSRC2R_EVT21SRC HSP_EVTSRC2R_EVT21SRC_Msk /*!< EVT21SRC[2:0] bits (Event source selection for priority encoder input 21) */ -#define HSP_EVTSRC2R_EVT21SRC_0 (0x1UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00010000 */ -#define HSP_EVTSRC2R_EVT21SRC_1 (0x2UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00020000 */ -#define HSP_EVTSRC2R_EVT21SRC_2 (0x4UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00040000 */ - -#define HSP_EVTSRC2R_EVT22SRC_Pos (20UL) -#define HSP_EVTSRC2R_EVT22SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00700000 */ -#define HSP_EVTSRC2R_EVT22SRC HSP_EVTSRC2R_EVT22SRC_Msk /*!< EVT22SRC[2:0] bits (Event source selection for priority encoder input 22) */ -#define HSP_EVTSRC2R_EVT22SRC_0 (0x1UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00100000 */ -#define HSP_EVTSRC2R_EVT22SRC_1 (0x2UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00200000 */ -#define HSP_EVTSRC2R_EVT22SRC_2 (0x4UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00400000 */ - -/******************** Bit definition for HSP_BUFFCFGR register ********************/ -#define HSP_BUFFCFGR_BUFF0DIR_Pos (0UL) -#define HSP_BUFFCFGR_BUFF0DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF0DIR_Pos) /*!< 0x00000001 */ -#define HSP_BUFFCFGR_BUFF0DIR HSP_BUFFCFGR_BUFF0DIR_Msk /*!< BUFF0DIR (Direction selection of BUFF0 (1)) */ - -#define HSP_BUFFCFGR_BUFF1DIR_Pos (1UL) -#define HSP_BUFFCFGR_BUFF1DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF1DIR_Pos) /*!< 0x00000002 */ -#define HSP_BUFFCFGR_BUFF1DIR HSP_BUFFCFGR_BUFF1DIR_Msk /*!< BUFF1DIR (Direction selection of BUFF1 (1)) */ - -#define HSP_BUFFCFGR_BUFF2DIR_Pos (2UL) -#define HSP_BUFFCFGR_BUFF2DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF2DIR_Pos) /*!< 0x00000004 */ -#define HSP_BUFFCFGR_BUFF2DIR HSP_BUFFCFGR_BUFF2DIR_Msk /*!< BUFF2DIR (Direction selection of BUFF2 (1)) */ - -#define HSP_BUFFCFGR_BUFF3DIR_Pos (3UL) -#define HSP_BUFFCFGR_BUFF3DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF3DIR_Pos) /*!< 0x00000008 */ -#define HSP_BUFFCFGR_BUFF3DIR HSP_BUFFCFGR_BUFF3DIR_Msk /*!< BUFF3DIR (Direction selection of BUFF3 (1)) */ - -#define HSP_BUFFCFGR_I2FEN_Pos (8UL) -#define HSP_BUFFCFGR_I2FEN_Msk (0x1UL << HSP_BUFFCFGR_I2FEN_Pos) /*!< 0x00000100 */ -#define HSP_BUFFCFGR_I2FEN HSP_BUFFCFGR_I2FEN_Msk /*!< I2FEN (integer to float32 conversion (1)) */ - -#define HSP_BUFFCFGR_COMB0_Pos (16UL) -#define HSP_BUFFCFGR_COMB0_Msk (0x1UL << HSP_BUFFCFGR_COMB0_Pos) /*!< 0x00010000 */ -#define HSP_BUFFCFGR_COMB0 HSP_BUFFCFGR_COMB0_Msk /*!< COMB0 (BUFCMB control for buff_evt[0] (1)) */ - -#define HSP_BUFFCFGR_COMB1_Pos (17UL) -#define HSP_BUFFCFGR_COMB1_Msk (0x1UL << HSP_BUFFCFGR_COMB1_Pos) /*!< 0x00020000 */ -#define HSP_BUFFCFGR_COMB1 HSP_BUFFCFGR_COMB1_Msk /*!< COMB1 (BUFCMB control for buff_evt[1] (1)) */ - -#define HSP_BUFFCFGR_COMB2_Pos (18UL) -#define HSP_BUFFCFGR_COMB2_Msk (0x1UL << HSP_BUFFCFGR_COMB2_Pos) /*!< 0x00040000 */ -#define HSP_BUFFCFGR_COMB2 HSP_BUFFCFGR_COMB2_Msk /*!< COMB2 (BUFCMB control for buff_evt[2] ) */ - -/******************** Bit definition for HSP_BUFFxDR register ********************/ -#define HSP_BUFFDR_BUFFDAT_Pos (0UL) -#define HSP_BUFFDR_BUFFDAT_Msk (0xFFFFFFFFUL << HSP_BUFFDR_BUFFDAT_Pos) /*!< 0xFFFFFFFF */ -#define HSP_BUFFDR_BUFFDAT HSP_BUFFDR_BUFFDAT_Msk /*!< BUFFDAT[31:0] bits (Data buffer) */ - -/******************** Bit definition for HSP_TRGINCFGR register ********************/ -#define HSP_TRGINCFGR_TRG0POL_Pos (0UL) -#define HSP_TRGINCFGR_TRG0POL_Msk (0x1UL << HSP_TRGINCFGR_TRG0POL_Pos) /*!< 0x00000001 */ -#define HSP_TRGINCFGR_TRG0POL HSP_TRGINCFGR_TRG0POL_Msk /*!< TRG0POL (Polarity selection for TRGIN0) */ - -#define HSP_TRGINCFGR_TRG1POL_Pos (1UL) -#define HSP_TRGINCFGR_TRG1POL_Msk (0x1UL << HSP_TRGINCFGR_TRG1POL_Pos) /*!< 0x00000002 */ -#define HSP_TRGINCFGR_TRG1POL HSP_TRGINCFGR_TRG1POL_Msk /*!< TRG1POL (Polarity selection for TRGIN1) */ - -#define HSP_TRGINCFGR_TRG2POL_Pos (2UL) -#define HSP_TRGINCFGR_TRG2POL_Msk (0x1UL << HSP_TRGINCFGR_TRG2POL_Pos) /*!< 0x00000004 */ -#define HSP_TRGINCFGR_TRG2POL HSP_TRGINCFGR_TRG2POL_Msk /*!< TRG2POL (Polarity selection for TRGIN2) */ - -#define HSP_TRGINCFGR_TRG3POL_Pos (3UL) -#define HSP_TRGINCFGR_TRG3POL_Msk (0x1UL << HSP_TRGINCFGR_TRG3POL_Pos) /*!< 0x00000008 */ -#define HSP_TRGINCFGR_TRG3POL HSP_TRGINCFGR_TRG3POL_Msk /*!< TRG3POL (Polarity selection for TRGIN3) */ - -#define HSP_TRGINCFGR_TRG4POL_Pos (4UL) -#define HSP_TRGINCFGR_TRG4POL_Msk (0x1UL << HSP_TRGINCFGR_TRG4POL_Pos) /*!< 0x00000010 */ -#define HSP_TRGINCFGR_TRG4POL HSP_TRGINCFGR_TRG4POL_Msk /*!< TRG4POL (Polarity selection for TRGIN4) */ - -#define HSP_TRGINCFGR_TRG5POL_Pos (5UL) -#define HSP_TRGINCFGR_TRG5POL_Msk (0x1UL << HSP_TRGINCFGR_TRG5POL_Pos) /*!< 0x00000020 */ -#define HSP_TRGINCFGR_TRG5POL HSP_TRGINCFGR_TRG5POL_Msk /*!< TRG5POL (Polarity selection for TRGIN5) */ - -#define HSP_TRGINCFGR_TRG6POL_Pos (6UL) -#define HSP_TRGINCFGR_TRG6POL_Msk (0x1UL << HSP_TRGINCFGR_TRG6POL_Pos) /*!< 0x00000040 */ -#define HSP_TRGINCFGR_TRG6POL HSP_TRGINCFGR_TRG6POL_Msk /*!< TRG6POL (Polarity selection for TRGIN6) */ - -#define HSP_TRGINCFGR_TRG7POL_Pos (7UL) -#define HSP_TRGINCFGR_TRG7POL_Msk (0x1UL << HSP_TRGINCFGR_TRG7POL_Pos) /*!< 0x00000080 */ -#define HSP_TRGINCFGR_TRG7POL HSP_TRGINCFGR_TRG7POL_Msk /*!< TRG7POL (Polarity selection for TRGIN7) */ - -#define HSP_TRGINCFGR_TRG8POL_Pos (8UL) -#define HSP_TRGINCFGR_TRG8POL_Msk (0x1UL << HSP_TRGINCFGR_TRG8POL_Pos) /*!< 0x00000100 */ -#define HSP_TRGINCFGR_TRG8POL HSP_TRGINCFGR_TRG8POL_Msk /*!< TRG8POL (Polarity selection for TRGIN8) */ - -#define HSP_TRGINCFGR_TRG9POL_Pos (9UL) -#define HSP_TRGINCFGR_TRG9POL_Msk (0x1UL << HSP_TRGINCFGR_TRG9POL_Pos) /*!< 0x00000200 */ -#define HSP_TRGINCFGR_TRG9POL HSP_TRGINCFGR_TRG9POL_Msk /*!< TRG9POL (Polarity selection for TRGIN9) */ - -/******************** Bit definition for HSP_TRGOCFGR register ********************/ -#define HSP_TRGOCFGR_TRGO0SRC_Pos (0UL) -#define HSP_TRGOCFGR_TRGO0SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000003 */ -#define HSP_TRGOCFGR_TRGO0SRC HSP_TRGOCFGR_TRGO0SRC_Msk /*!< TRGO0SRC[1:0] bits (Trigger source selection for hsp_trg_out[0] (1)) */ -#define HSP_TRGOCFGR_TRGO0SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000001 */ -#define HSP_TRGOCFGR_TRGO0SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000002 */ - -#define HSP_TRGOCFGR_TRGO1SRC_Pos (2UL) -#define HSP_TRGOCFGR_TRGO1SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x0000000C */ -#define HSP_TRGOCFGR_TRGO1SRC HSP_TRGOCFGR_TRGO1SRC_Msk /*!< TRGO1SRC[1:0] bits (Trigger source selection for hsp_trg_out[1] (1)) */ -#define HSP_TRGOCFGR_TRGO1SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x00000004 */ -#define HSP_TRGOCFGR_TRGO1SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x00000008 */ - -#define HSP_TRGOCFGR_TRGO2SRC_Pos (4UL) -#define HSP_TRGOCFGR_TRGO2SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000030 */ -#define HSP_TRGOCFGR_TRGO2SRC HSP_TRGOCFGR_TRGO2SRC_Msk /*!< TRGO2SRC[1:0] bits (Trigger source selection for hsp_trg_out[2] (1)) */ -#define HSP_TRGOCFGR_TRGO2SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000010 */ -#define HSP_TRGOCFGR_TRGO2SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000020 */ - -#define HSP_TRGOCFGR_TRGO3SRC_Pos (6UL) -#define HSP_TRGOCFGR_TRGO3SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x000000C0 */ -#define HSP_TRGOCFGR_TRGO3SRC HSP_TRGOCFGR_TRGO3SRC_Msk /*!< TRGO3SRC[1:0] bits (Trigger source selection for hsp_trg_out[3] ) */ -#define HSP_TRGOCFGR_TRGO3SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x00000040 */ -#define HSP_TRGOCFGR_TRGO3SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x00000080 */ - -/******************** Bit definition for HSP_CSEGR register ********************/ -#define HSP_CSEGR_CSEVT_Pos (1UL) -#define HSP_CSEGR_CSEVT_Msk (0x3FFFFFUL << HSP_CSEGR_CSEVT_Pos) /*!< 0x007FFFFE */ -#define HSP_CSEGR_CSEVT HSP_CSEGR_CSEVT_Msk /*!< CSEVT[21:0] bits (CPU Shared Software Event ) */ -#define HSP_CSEGR_CSEVT_0 (0x0001UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000002 */ -#define HSP_CSEGR_CSEVT_1 (0x0002UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000004 */ -#define HSP_CSEGR_CSEVT_2 (0x0004UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000008 */ -#define HSP_CSEGR_CSEVT_3 (0x0008UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000010 */ -#define HSP_CSEGR_CSEVT_4 (0x0010UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000020 */ -#define HSP_CSEGR_CSEVT_5 (0x0020UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000040 */ -#define HSP_CSEGR_CSEVT_6 (0x0040UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000080 */ -#define HSP_CSEGR_CSEVT_7 (0x0080UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000100 */ -#define HSP_CSEGR_CSEVT_8 (0x0100UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000200 */ -#define HSP_CSEGR_CSEVT_9 (0x0200UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000400 */ -#define HSP_CSEGR_CSEVT_10 (0x0400UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000800 */ -#define HSP_CSEGR_CSEVT_11 (0x0800UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00001000 */ -#define HSP_CSEGR_CSEVT_12 (0x1000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00002000 */ -#define HSP_CSEGR_CSEVT_13 (0x2000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00004000 */ -#define HSP_CSEGR_CSEVT_14 (0x4000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00008000 */ -#define HSP_CSEGR_CSEVT_15 (0x8000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00010000 */ -#define HSP_CSEGR_CSEVT_16 (0x10000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00020000 */ -#define HSP_CSEGR_CSEVT_17 (0x20000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00040000 */ -#define HSP_CSEGR_CSEVT_18 (0x40000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00080000 */ -#define HSP_CSEGR_CSEVT_19 (0x80000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00100000 */ -#define HSP_CSEGR_CSEVT_20 (0x100000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00200000 */ -#define HSP_CSEGR_CSEVT_21 (0x200000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00400000 */ - -/******************** Bit definition for HSP_CDEGR register ********************/ -#define HSP_CDEGR_CTSKN_Pos (0UL) -#define HSP_CDEGR_CTSKN_Msk (0x3FUL << HSP_CDEGR_CTSKN_Pos) /*!< 0x0000003F */ -#define HSP_CDEGR_CTSKN HSP_CDEGR_CTSKN_Msk /*!< CTSKN[5:0] bits (CPU Task number) */ - -#define HSP_CDEGR_CDEGBSY_Pos (31UL) -#define HSP_CDEGR_CDEGBSY_Msk (0x1UL << HSP_CDEGR_CDEGBSY_Pos) /*!< 0x80000000 */ -#define HSP_CDEGR_CDEGBSY HSP_CDEGR_CDEGBSY_Msk /*!< CDEGBSY (CPU dedicated event generator busy) */ - -/******************** Bit definition for HSP_TRGINSELR0 register ********************/ -#define HSP_TRGINSELR0_TRG0SEL_Pos (0UL) -#define HSP_TRGINSELR0_TRG0SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x0000003F */ -#define HSP_TRGINSELR0_TRG0SEL HSP_TRGINSELR0_TRG0SEL_Msk /*!< TRG0SEL[5:0] bits (Input trigger selection for TRGIN0) */ -#define HSP_TRGINSELR0_TRG0SEL_0 (0x01UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000001 */ -#define HSP_TRGINSELR0_TRG0SEL_1 (0x02UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000002 */ -#define HSP_TRGINSELR0_TRG0SEL_2 (0x04UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000004 */ -#define HSP_TRGINSELR0_TRG0SEL_3 (0x08UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000008 */ -#define HSP_TRGINSELR0_TRG0SEL_4 (0x10UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000010 */ -#define HSP_TRGINSELR0_TRG0SEL_5 (0x20UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000020 */ - -#define HSP_TRGINSELR0_TRG1SEL_Pos (8UL) -#define HSP_TRGINSELR0_TRG1SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00003F00 */ -#define HSP_TRGINSELR0_TRG1SEL HSP_TRGINSELR0_TRG1SEL_Msk /*!< TRG1SEL[5:0] bits (Input trigger selection for TRGIN1) */ -#define HSP_TRGINSELR0_TRG1SEL_0 (0x01UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000100 */ -#define HSP_TRGINSELR0_TRG1SEL_1 (0x02UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000200 */ -#define HSP_TRGINSELR0_TRG1SEL_2 (0x04UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000400 */ -#define HSP_TRGINSELR0_TRG1SEL_3 (0x08UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000800 */ -#define HSP_TRGINSELR0_TRG1SEL_4 (0x10UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00001000 */ -#define HSP_TRGINSELR0_TRG1SEL_5 (0x20UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00002000 */ - -#define HSP_TRGINSELR0_TRG2SEL_Pos (16UL) -#define HSP_TRGINSELR0_TRG2SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x003F0000 */ -#define HSP_TRGINSELR0_TRG2SEL HSP_TRGINSELR0_TRG2SEL_Msk /*!< TRG2SEL[5:0] bits (Input trigger selection for TRGIN2) */ -#define HSP_TRGINSELR0_TRG2SEL_0 (0x01UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00010000 */ -#define HSP_TRGINSELR0_TRG2SEL_1 (0x02UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00020000 */ -#define HSP_TRGINSELR0_TRG2SEL_2 (0x04UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00040000 */ -#define HSP_TRGINSELR0_TRG2SEL_3 (0x08UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00080000 */ -#define HSP_TRGINSELR0_TRG2SEL_4 (0x10UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00100000 */ -#define HSP_TRGINSELR0_TRG2SEL_5 (0x20UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00200000 */ - -#define HSP_TRGINSELR0_TRG3SEL_Pos (24UL) -#define HSP_TRGINSELR0_TRG3SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x3F000000 */ -#define HSP_TRGINSELR0_TRG3SEL HSP_TRGINSELR0_TRG3SEL_Msk /*!< TRG3SEL[5:0] bits (Input trigger selection for TRGIN3) */ -#define HSP_TRGINSELR0_TRG3SEL_0 (0x01UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x01000000 */ -#define HSP_TRGINSELR0_TRG3SEL_1 (0x02UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x02000000 */ -#define HSP_TRGINSELR0_TRG3SEL_2 (0x04UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x04000000 */ -#define HSP_TRGINSELR0_TRG3SEL_3 (0x08UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x08000000 */ -#define HSP_TRGINSELR0_TRG3SEL_4 (0x10UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x10000000 */ -#define HSP_TRGINSELR0_TRG3SEL_5 (0x20UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x20000000 */ - -/******************** Bit definition for HSP_TRGINSELR1 register ********************/ -#define HSP_TRGINSELR1_TRG4SEL_Pos (0UL) -#define HSP_TRGINSELR1_TRG4SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x0000003F */ -#define HSP_TRGINSELR1_TRG4SEL HSP_TRGINSELR1_TRG4SEL_Msk /*!< TRG4SEL[5:0] bits (Input trigger selection for TRGIN4) */ -#define HSP_TRGINSELR1_TRG4SEL_0 (0x01UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000001 */ -#define HSP_TRGINSELR1_TRG4SEL_1 (0x02UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000002 */ -#define HSP_TRGINSELR1_TRG4SEL_2 (0x04UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000004 */ -#define HSP_TRGINSELR1_TRG4SEL_3 (0x08UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000008 */ -#define HSP_TRGINSELR1_TRG4SEL_4 (0x10UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000010 */ -#define HSP_TRGINSELR1_TRG4SEL_5 (0x20UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000020 */ - -#define HSP_TRGINSELR1_TRG5SEL_Pos (8UL) -#define HSP_TRGINSELR1_TRG5SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00003F00 */ -#define HSP_TRGINSELR1_TRG5SEL HSP_TRGINSELR1_TRG5SEL_Msk /*!< TRG5SEL[5:0] bits (Input trigger selection for TRGIN5) */ -#define HSP_TRGINSELR1_TRG5SEL_0 (0x01UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000100 */ -#define HSP_TRGINSELR1_TRG5SEL_1 (0x02UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000200 */ -#define HSP_TRGINSELR1_TRG5SEL_2 (0x04UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000400 */ -#define HSP_TRGINSELR1_TRG5SEL_3 (0x08UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000800 */ -#define HSP_TRGINSELR1_TRG5SEL_4 (0x10UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00001000 */ -#define HSP_TRGINSELR1_TRG5SEL_5 (0x20UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00002000 */ - -#define HSP_TRGINSELR1_TRG6SEL_Pos (16UL) -#define HSP_TRGINSELR1_TRG6SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x003F0000 */ -#define HSP_TRGINSELR1_TRG6SEL HSP_TRGINSELR1_TRG6SEL_Msk /*!< TRG6SEL[5:0] bits (Input trigger selection for TRGIN6) */ -#define HSP_TRGINSELR1_TRG6SEL_0 (0x01UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00010000 */ -#define HSP_TRGINSELR1_TRG6SEL_1 (0x02UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00020000 */ -#define HSP_TRGINSELR1_TRG6SEL_2 (0x04UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00040000 */ -#define HSP_TRGINSELR1_TRG6SEL_3 (0x08UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00080000 */ -#define HSP_TRGINSELR1_TRG6SEL_4 (0x10UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00100000 */ -#define HSP_TRGINSELR1_TRG6SEL_5 (0x20UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00200000 */ - -#define HSP_TRGINSELR1_TRG7SEL_Pos (24UL) -#define HSP_TRGINSELR1_TRG7SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x3F000000 */ -#define HSP_TRGINSELR1_TRG7SEL HSP_TRGINSELR1_TRG7SEL_Msk /*!< TRG7SEL[5:0] bits (Input trigger selection for TRGIN7) */ -#define HSP_TRGINSELR1_TRG7SEL_0 (0x01UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x01000000 */ -#define HSP_TRGINSELR1_TRG7SEL_1 (0x02UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x02000000 */ -#define HSP_TRGINSELR1_TRG7SEL_2 (0x04UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x04000000 */ -#define HSP_TRGINSELR1_TRG7SEL_3 (0x08UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x08000000 */ -#define HSP_TRGINSELR1_TRG7SEL_4 (0x10UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x10000000 */ -#define HSP_TRGINSELR1_TRG7SEL_5 (0x20UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x20000000 */ - -/******************** Bit definition for HSP_TRGINSELR2 register ********************/ -#define HSP_TRGINSELR2_TRG8SEL_Pos (0UL) -#define HSP_TRGINSELR2_TRG8SEL_Msk (0x3FUL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x0000003F */ -#define HSP_TRGINSELR2_TRG8SEL HSP_TRGINSELR2_TRG8SEL_Msk /*!< TRG8SEL[5:0] bits (Input trigger selection for TRGIN8) */ -#define HSP_TRGINSELR2_TRG8SEL_0 (0x01UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000001 */ -#define HSP_TRGINSELR2_TRG8SEL_1 (0x02UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000002 */ -#define HSP_TRGINSELR2_TRG8SEL_2 (0x04UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000004 */ -#define HSP_TRGINSELR2_TRG8SEL_3 (0x08UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000008 */ -#define HSP_TRGINSELR2_TRG8SEL_4 (0x10UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000010 */ -#define HSP_TRGINSELR2_TRG8SEL_5 (0x20UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000020 */ - -#define HSP_TRGINSELR2_TRG9SEL_Pos (8UL) -#define HSP_TRGINSELR2_TRG9SEL_Msk (0x3FUL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00003F00 */ -#define HSP_TRGINSELR2_TRG9SEL HSP_TRGINSELR2_TRG9SEL_Msk /*!< TRG9SEL[5:0] bits (Input trigger selection for TRGIN9) */ -#define HSP_TRGINSELR2_TRG9SEL_0 (0x01UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000100 */ -#define HSP_TRGINSELR2_TRG9SEL_1 (0x02UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000200 */ -#define HSP_TRGINSELR2_TRG9SEL_2 (0x04UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000400 */ -#define HSP_TRGINSELR2_TRG9SEL_3 (0x08UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000800 */ -#define HSP_TRGINSELR2_TRG9SEL_4 (0x10UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00001000 */ -#define HSP_TRGINSELR2_TRG9SEL_5 (0x20UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00002000 */ - -/******************** Bit definition for HSP_BKOxCFGR register ********************/ -#define HSP_BKOCFGR_ACCEREN_Pos (0U) -#define HSP_BKOCFGR_ACCEREN_Msk (0x1UL << HSP_BKOCFGR_ACCEREN_Pos) /*!< 0x00000001 */ -#define HSP_BKOCFGR_ACCEREN HSP_BKOCFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ - -#define HSP_BKOCFGR_FPUEREN_Pos (1U) -#define HSP_BKOCFGR_FPUEREN_Msk (0x1UL << HSP_BKOCFGR_FPUEREN_Pos) /*!< 0x00000002 */ -#define HSP_BKOCFGR_FPUEREN HSP_BKOCFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ - -#define HSP_BKOCFGR_OPCEREN_Pos (2U) -#define HSP_BKOCFGR_OPCEREN_Msk (0x1UL << HSP_BKOCFGR_OPCEREN_Pos) /*!< 0x00000004 */ -#define HSP_BKOCFGR_OPCEREN HSP_BKOCFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ - -#define HSP_BKOCFGR_PFCT28EN_Pos (4U) -#define HSP_BKOCFGR_PFCT28EN_Msk (0x1UL << HSP_BKOCFGR_PFCT28EN_Pos) /*!< 0x00000010 */ -#define HSP_BKOCFGR_PFCT28EN HSP_BKOCFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ - -#define HSP_BKOCFGR_PFCT29EN_Pos (5U) -#define HSP_BKOCFGR_PFCT29EN_Msk (0x1UL << HSP_BKOCFGR_PFCT29EN_Pos) /*!< 0x00000020 */ -#define HSP_BKOCFGR_PFCT29EN HSP_BKOCFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ - -#define HSP_BKOCFGR_PFCT30EN_Pos (6U) -#define HSP_BKOCFGR_PFCT30EN_Msk (0x1UL << HSP_BKOCFGR_PFCT30EN_Pos) /*!< 0x00000040 */ -#define HSP_BKOCFGR_PFCT30EN HSP_BKOCFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ - -#define HSP_BKOCFGR_PFCT31EN_Pos (7U) -#define HSP_BKOCFGR_PFCT31EN_Msk (0x1UL << HSP_BKOCFGR_PFCT31EN_Pos) /*!< 0x00000080 */ -#define HSP_BKOCFGR_PFCT31EN HSP_BKOCFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ - -#define HSP_BKOCFGR_FWEREN_Pos (12U) -#define HSP_BKOCFGR_FWEREN_Msk (0x1UL << HSP_BKOCFGR_FWEREN_Pos) /*!< 0x00001000 */ -#define HSP_BKOCFGR_FWEREN HSP_BKOCFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ - -#define HSP_BKOCFGR_HDEGOVEN_Pos (13U) -#define HSP_BKOCFGR_HDEGOVEN_Msk (0x1UL << HSP_BKOCFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ -#define HSP_BKOCFGR_HDEGOVEN HSP_BKOCFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ - -/******************** Bit definition for HSP_BKICFGR register ********************/ -#define HSP_BKICFGR_ACCEREN_Pos (0UL) -#define HSP_BKICFGR_ACCEREN_Msk (0x1UL << HSP_BKICFGR_ACCEREN_Pos) /*!< 0x00000001 */ -#define HSP_BKICFGR_ACCEREN HSP_BKICFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ - -#define HSP_BKICFGR_FPUEREN_Pos (1UL) -#define HSP_BKICFGR_FPUEREN_Msk (0x1UL << HSP_BKICFGR_FPUEREN_Pos) /*!< 0x00000002 */ -#define HSP_BKICFGR_FPUEREN HSP_BKICFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ - -#define HSP_BKICFGR_OPCEREN_Pos (2UL) -#define HSP_BKICFGR_OPCEREN_Msk (0x1UL << HSP_BKICFGR_OPCEREN_Pos) /*!< 0x00000004 */ -#define HSP_BKICFGR_OPCEREN HSP_BKICFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ - -#define HSP_BKICFGR_PFCT28EN_Pos (4UL) -#define HSP_BKICFGR_PFCT28EN_Msk (0x1UL << HSP_BKICFGR_PFCT28EN_Pos) /*!< 0x00000010 */ -#define HSP_BKICFGR_PFCT28EN HSP_BKICFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ - -#define HSP_BKICFGR_PFCT29EN_Pos (5UL) -#define HSP_BKICFGR_PFCT29EN_Msk (0x1UL << HSP_BKICFGR_PFCT29EN_Pos) /*!< 0x00000020 */ -#define HSP_BKICFGR_PFCT29EN HSP_BKICFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ - -#define HSP_BKICFGR_PFCT30EN_Pos (6UL) -#define HSP_BKICFGR_PFCT30EN_Msk (0x1UL << HSP_BKICFGR_PFCT30EN_Pos) /*!< 0x00000040 */ -#define HSP_BKICFGR_PFCT30EN HSP_BKICFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ - -#define HSP_BKICFGR_PFCT31EN_Pos (7UL) -#define HSP_BKICFGR_PFCT31EN_Msk (0x1UL << HSP_BKICFGR_PFCT31EN_Pos) /*!< 0x00000080 */ -#define HSP_BKICFGR_PFCT31EN HSP_BKICFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ - -#define HSP_BKICFGR_FWEREN_Pos (12UL) -#define HSP_BKICFGR_FWEREN_Msk (0x1UL << HSP_BKICFGR_FWEREN_Pos) /*!< 0x00001000 */ -#define HSP_BKICFGR_FWEREN HSP_BKICFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ - -#define HSP_BKICFGR_HDEGOVEN_Pos (13UL) -#define HSP_BKICFGR_HDEGOVEN_Msk (0x1UL << HSP_BKICFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ -#define HSP_BKICFGR_HDEGOVEN HSP_BKICFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ - -#define HSP_BKICFGR_FSATEN_Pos (14UL) -#define HSP_BKICFGR_FSATEN_Msk (0x1UL << HSP_BKICFGR_FSATEN_Pos) /*!< 0x00004000 */ -#define HSP_BKICFGR_FSATEN HSP_BKICFGR_FSATEN_Msk /*!< FSATEN (FPU saturation break enable for FPUSATF (1)) */ - -#define HSP_BKICFGR_SSEN_Pos (17UL) -#define HSP_BKICFGR_SSEN_Msk (0x1UL << HSP_BKICFGR_SSEN_Pos) /*!< 0x00020000 */ -#define HSP_BKICFGR_SSEN HSP_BKICFGR_SSEN_Msk /*!< SSEN (Single step enable (1)) */ - -/******************** Bit definition for HSP_FWERR register ********************/ -#define HSP_FWERR_FWERRN_Pos (0UL) -#define HSP_FWERR_FWERRN_Msk (0x3FFUL << HSP_FWERR_FWERRN_Pos) /*!< 0x000003FF */ -#define HSP_FWERR_FWERRN HSP_FWERR_FWERRN_Msk /*!< FWERRN[9:0] bits (Firmware error number) */ - -/******************** Bit definition for HSP_PARAMR0 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR0_PARAM_Pos (0UL) -#define HSP_PARAMR0_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR0_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR0_PARAM HSP_PARAMR0_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR1 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR1_PARAM_Pos (0UL) -#define HSP_PARAMR1_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR1_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR1_PARAM HSP_PARAMR1_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR2 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR2_PARAM_Pos (0UL) -#define HSP_PARAMR2_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR2_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR2_PARAM HSP_PARAMR2_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR3 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR3_PARAM_Pos (0UL) -#define HSP_PARAMR3_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR3_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR3_PARAM HSP_PARAMR3_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR4 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR4_PARAM_Pos (0UL) -#define HSP_PARAMR4_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR4_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR4_PARAM HSP_PARAMR4_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR5 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR5_PARAM_Pos (0UL) -#define HSP_PARAMR5_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR5_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR5_PARAM HSP_PARAMR5_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR6 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR6_PARAM_Pos (0UL) -#define HSP_PARAMR6_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR6_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR6_PARAM HSP_PARAMR6_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR7 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR7_PARAM_Pos (0UL) -#define HSP_PARAMR7_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR7_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR7_PARAM HSP_PARAMR7_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR8 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR8_PARAM_Pos (0UL) -#define HSP_PARAMR8_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR8_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR8_PARAM HSP_PARAMR8_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR9 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR9_PARAM_Pos (0UL) -#define HSP_PARAMR9_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR9_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR9_PARAM HSP_PARAMR9_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR10 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR10_PARAM_Pos (0UL) -#define HSP_PARAMR10_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR10_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR10_PARAM HSP_PARAMR10_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR11 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR11_PARAM_Pos (0UL) -#define HSP_PARAMR11_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR11_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR11_PARAM HSP_PARAMR11_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR12 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR12_PARAM_Pos (0UL) -#define HSP_PARAMR12_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR12_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR12_PARAM HSP_PARAMR12_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR13 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR13_PARAM_Pos (0UL) -#define HSP_PARAMR13_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR13_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR13_PARAM HSP_PARAMR13_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR14 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR14_PARAM_Pos (0UL) -#define HSP_PARAMR14_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR14_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR14_PARAM HSP_PARAMR14_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR15 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR15_PARAM_Pos (0UL) -#define HSP_PARAMR15_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR15_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR15_PARAM HSP_PARAMR15_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_SPE_IER register ********************/ -#define HSP_SPE_IER_C2HMRDYIE_Pos (0UL) -#define HSP_SPE_IER_C2HMRDYIE_Msk (0x1UL << HSP_SPE_IER_C2HMRDYIE_Pos) /*!< 0x00000001 */ -#define HSP_SPE_IER_C2HMRDYIE HSP_SPE_IER_C2HMRDYIE_Msk /*!< C2HMRDYIE (CPU to SPE message ready interrupt enable) */ - -#define HSP_SPE_IER_H2CMFREEIE_Pos (1UL) -#define HSP_SPE_IER_H2CMFREEIE_Msk (0x1UL << HSP_SPE_IER_H2CMFREEIE_Pos) /*!< 0x00000002 */ -#define HSP_SPE_IER_H2CMFREEIE HSP_SPE_IER_H2CMFREEIE_Msk /*!< H2CMFREEIE (SPE to CPU message free interrupt enable) */ - -/******************** Bit definition for HSP_SPE_ISR register ********************/ -#define HSP_SPE_ISR_C2HMRDYF_Pos (0UL) -#define HSP_SPE_ISR_C2HMRDYF_Msk (0x1UL << HSP_SPE_ISR_C2HMRDYF_Pos) /*!< 0x00000001 */ -#define HSP_SPE_ISR_C2HMRDYF HSP_SPE_ISR_C2HMRDYF_Msk /*!< C2HMRDYF (CPU to SPE message box status) */ - -#define HSP_SPE_ISR_H2CMFREEF_Pos (1UL) -#define HSP_SPE_ISR_H2CMFREEF_Msk (0x1UL << HSP_SPE_ISR_H2CMFREEF_Pos) /*!< 0x00000002 */ -#define HSP_SPE_ISR_H2CMFREEF HSP_SPE_ISR_H2CMFREEF_Msk /*!< H2CMFREEF (SPE to CPU message box status) */ - -#define HSP_SPE_ISR_RSTREQF_Pos (4UL) -#define HSP_SPE_ISR_RSTREQF_Msk (0x1UL << HSP_SPE_ISR_RSTREQF_Pos) /*!< 0x00000010 */ -#define HSP_SPE_ISR_RSTREQF HSP_SPE_ISR_RSTREQF_Msk /*!< RSTREQF (HSP reset request) */ - -#define HSP_SPE_ISR_BUF0EVTF_Pos (12UL) -#define HSP_SPE_ISR_BUF0EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF0EVTF_Pos) /*!< 0x00001000 */ -#define HSP_SPE_ISR_BUF0EVTF HSP_SPE_ISR_BUF0EVTF_Msk /*!< BUF0EVTF (BUF0 status) */ - -#define HSP_SPE_ISR_BUF1EVTF_Pos (13UL) -#define HSP_SPE_ISR_BUF1EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF1EVTF_Pos) /*!< 0x00002000 */ -#define HSP_SPE_ISR_BUF1EVTF HSP_SPE_ISR_BUF1EVTF_Msk /*!< BUF1EVTF (BUF1 status) */ - -#define HSP_SPE_ISR_BUF2EVTF_Pos (14UL) -#define HSP_SPE_ISR_BUF2EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF2EVTF_Pos) /*!< 0x00004000 */ -#define HSP_SPE_ISR_BUF2EVTF HSP_SPE_ISR_BUF2EVTF_Msk /*!< BUF2EVTF (BUF2 status) */ - -#define HSP_SPE_ISR_BUF3EVTF_Pos (15UL) -#define HSP_SPE_ISR_BUF3EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF3EVTF_Pos) /*!< 0x00008000 */ -#define HSP_SPE_ISR_BUF3EVTF HSP_SPE_ISR_BUF3EVTF_Msk /*!< BUF3EVTF (BUF3 status) */ - -/******************** Bit definition for HSP_TCUCFGR register ********************/ -#define HSP_TCUCFGR_TSKCMP0_Pos (0UL) -#define HSP_TCUCFGR_TSKCMP0_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x0000003F */ -#define HSP_TCUCFGR_TSKCMP0 HSP_TCUCFGR_TSKCMP0_Msk /*!< TSKCMP0[5:0] bits (Task compare 0 (1)) */ -#define HSP_TCUCFGR_TSKCMP0_0 (0x01UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000001 */ -#define HSP_TCUCFGR_TSKCMP0_1 (0x02UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000002 */ -#define HSP_TCUCFGR_TSKCMP0_2 (0x04UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000004 */ -#define HSP_TCUCFGR_TSKCMP0_3 (0x08UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000008 */ -#define HSP_TCUCFGR_TSKCMP0_4 (0x10UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000010 */ -#define HSP_TCUCFGR_TSKCMP0_5 (0x20UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000020 */ - -#define HSP_TCUCFGR_TC0EN_Pos (7UL) -#define HSP_TCUCFGR_TC0EN_Msk (0x1UL << HSP_TCUCFGR_TC0EN_Pos) /*!< 0x00000080 */ -#define HSP_TCUCFGR_TC0EN HSP_TCUCFGR_TC0EN_Msk /*!< TC0EN (Task comparator 0 enable (1)) */ - -#define HSP_TCUCFGR_TSKCMP1_Pos (8UL) -#define HSP_TCUCFGR_TSKCMP1_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00003F00 */ -#define HSP_TCUCFGR_TSKCMP1 HSP_TCUCFGR_TSKCMP1_Msk /*!< TSKCMP1[5:0] bits (Task compare 1 (1)) */ -#define HSP_TCUCFGR_TSKCMP1_0 (0x01UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000100 */ -#define HSP_TCUCFGR_TSKCMP1_1 (0x02UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000200 */ -#define HSP_TCUCFGR_TSKCMP1_2 (0x04UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000400 */ -#define HSP_TCUCFGR_TSKCMP1_3 (0x08UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000800 */ -#define HSP_TCUCFGR_TSKCMP1_4 (0x10UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00001000 */ -#define HSP_TCUCFGR_TSKCMP1_5 (0x20UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00002000 */ - -#define HSP_TCUCFGR_TC1EN_Pos (15UL) -#define HSP_TCUCFGR_TC1EN_Msk (0x1UL << HSP_TCUCFGR_TC1EN_Pos) /*!< 0x00008000 */ -#define HSP_TCUCFGR_TC1EN HSP_TCUCFGR_TC1EN_Msk /*!< TC1EN (Task comparator 1 enable (1)) */ - -#define HSP_TCUCFGR_TSKCMP2_Pos (16UL) -#define HSP_TCUCFGR_TSKCMP2_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x003F0000 */ -#define HSP_TCUCFGR_TSKCMP2 HSP_TCUCFGR_TSKCMP2_Msk /*!< TSKCMP2[5:0] bits (Task compare 2 (1)) */ -#define HSP_TCUCFGR_TSKCMP2_0 (0x01UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00010000 */ -#define HSP_TCUCFGR_TSKCMP2_1 (0x02UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00020000 */ -#define HSP_TCUCFGR_TSKCMP2_2 (0x04UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00040000 */ -#define HSP_TCUCFGR_TSKCMP2_3 (0x08UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00080000 */ -#define HSP_TCUCFGR_TSKCMP2_4 (0x10UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00100000 */ -#define HSP_TCUCFGR_TSKCMP2_5 (0x20UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00200000 */ - -#define HSP_TCUCFGR_TC2EN_Pos (23UL) -#define HSP_TCUCFGR_TC2EN_Msk (0x1UL << HSP_TCUCFGR_TC2EN_Pos) /*!< 0x00800000 */ -#define HSP_TCUCFGR_TC2EN HSP_TCUCFGR_TC2EN_Msk /*!< TC2EN (Task comparator 2 enable (1)) */ - -#define HSP_TCUCFGR_TSKCMP3_Pos (24UL) -#define HSP_TCUCFGR_TSKCMP3_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x3F000000 */ -#define HSP_TCUCFGR_TSKCMP3 HSP_TCUCFGR_TSKCMP3_Msk /*!< TSKCMP3[5:0] bits (Task compare 3 (1)) */ -#define HSP_TCUCFGR_TSKCMP3_0 (0x01UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x01000000 */ -#define HSP_TCUCFGR_TSKCMP3_1 (0x02UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x02000000 */ -#define HSP_TCUCFGR_TSKCMP3_2 (0x04UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x04000000 */ -#define HSP_TCUCFGR_TSKCMP3_3 (0x08UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x08000000 */ -#define HSP_TCUCFGR_TSKCMP3_4 (0x10UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x10000000 */ -#define HSP_TCUCFGR_TSKCMP3_5 (0x20UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x20000000 */ - -#define HSP_TCUCFGR_TC3EN_Pos (31UL) -#define HSP_TCUCFGR_TC3EN_Msk (0x1UL << HSP_TCUCFGR_TC3EN_Pos) /*!< 0x80000000 */ -#define HSP_TCUCFGR_TC3EN HSP_TCUCFGR_TC3EN_Msk /*!< TC3EN (Task comparator 3 enable ) */ - -/******************** Bit definition for HSP_TOVLPCR register ********************/ -#define HSP_TOVLPCR_TOVLPEN_Pos (0UL) -#define HSP_TOVLPCR_TOVLPEN_Msk (0x1UL << HSP_TOVLPCR_TOVLPEN_Pos) /*!< 0x00000001 */ -#define HSP_TOVLPCR_TOVLPEN HSP_TOVLPCR_TOVLPEN_Msk /*!< TOVLPEN (Task overlap enable (1)) */ - -#define HSP_TOVLPCR_LTNB_Pos (8UL) -#define HSP_TOVLPCR_LTNB_Msk (0x3FUL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00003F00 */ -#define HSP_TOVLPCR_LTNB HSP_TOVLPCR_LTNB_Msk /*!< LTNB[5:0] bits (Lower task number value (1)) */ - -#define HSP_TOVLPCR_HTNB_Pos (16UL) -#define HSP_TOVLPCR_HTNB_Msk (0x3FUL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x003F0000 */ -#define HSP_TOVLPCR_HTNB HSP_TOVLPCR_HTNB_Msk /*!< HTNB[5:0] bits (Higher task number value ) */ - -/******************** Bit definition for HSP_SNPR register ********************/ -#define HSP_SNPR_SNPSELA_Pos (0UL) -#define HSP_SNPR_SNPSELA_Msk (0x7UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000007 */ -#define HSP_SNPR_SNPSELA HSP_SNPR_SNPSELA_Msk /*!< SNPSELA[2:0] bits (Snoop group A signal selection) */ -#define HSP_SNPR_SNPSELA_0 (0x1UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000001 */ -#define HSP_SNPR_SNPSELA_1 (0x2UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000002 */ -#define HSP_SNPR_SNPSELA_2 (0x4UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000004 */ - -#define HSP_SNPR_SNPSELB_Pos (4UL) -#define HSP_SNPR_SNPSELB_Msk (0x7UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000070 */ -#define HSP_SNPR_SNPSELB HSP_SNPR_SNPSELB_Msk /*!< SNPSELB[2:0] bits (Snoop group B signal selection) */ -#define HSP_SNPR_SNPSELB_0 (0x1UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000010 */ -#define HSP_SNPR_SNPSELB_1 (0x2UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000020 */ -#define HSP_SNPR_SNPSELB_2 (0x4UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000040 */ - -/******************** Bit definition for HSP_CCNTR register ********************/ -#define HSP_CCNTR_CCNTR_Pos (0UL) -#define HSP_CCNTR_CCNTR_Msk (0xFFFFFFFFUL << HSP_CCNTR_CCNTR_Pos) /*!< 0xFFFFFFFF */ -#define HSP_CCNTR_CCNTR HSP_CCNTR_CCNTR_Msk /*!< CCNTR[31:0] bits (Conflict counter) */ - -/****************** Bit definition for HSP_CAPDR register *******************/ -#define HSP_CAPDR_TSTAMP_Pos (0UL) -#define HSP_CAPDR_TSTAMP_Msk (0x3FFFUL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00003FFF */ -#define HSP_CAPDR_TSTAMP HSP_CAPDR_TSTAMP_Msk /*!< Time-stamp value */ -#define HSP_CAPDR_IFHIST_Pos (14UL) -#define HSP_CAPDR_IFHIST_Msk (0xFFUL << HSP_CAPDR_IFHIST_Pos) /*!< 0x003FC000 */ -#define HSP_CAPDR_IFHIST HSP_CAPDR_IFHIST_Msk /*!< IF condition history */ -#define HSP_CAPDR_IFCNT_Pos (22UL) -#define HSP_CAPDR_IFCNT_Msk (0xFUL << HSP_CAPDR_IFCNT_Pos) /*!< 0x03C00000 */ -#define HSP_CAPDR_IFCNT HSP_CAPDR_IFCNT_Msk /*!< IF instruction counter */ -#define HSP_CAPDR_TSKNB_Pos (26UL) -#define HSP_CAPDR_TSKNB_Msk (0x3FUL << HSP_CAPDR_TSKNB_Pos) /*!< 0xFC000000 */ -#define HSP_CAPDR_TSKNB HSP_CAPDR_TSKNB_Msk /*!< Last captured task number */ - -#define HSP_CAPDR_ALT_IFHIST_Pos (0UL) -#define HSP_CAPDR_ALT_IFHIST_Msk (0x7FFFUL << HSP_CAPDR_ALT_IFHIST_Pos) /*!< 0x00007FFF */ -#define HSP_CAPDR_ALT_IFHIST HSP_CAPDR_IFHIST_Msk /*!< IF condition history */ -#define HSP_CAPDR_ALT_PFCTNB_Pos (16UL) -#define HSP_CAPDR_ALT_PFCTNB_Msk (0x3FUL << HSP_CAPDR_ALT_PFCTNB_Pos) /*!< 0x0003F0000 */ -#define HSP_CAPDR_ALT_PFCTNB HSP_CAPDR_TSTAMP_Msk /*!< Processing Function Number */ -#define HSP_CAPDR_ALT_IFCNT_Pos (22UL) -#define HSP_CAPDR_ALT_IFCNT_Msk (0xFUL << HSP_CAPDR_ALT_IFCNT_Pos) /*!< 0x03C00000 */ -#define HSP_CAPDR_ALT_IFCNT HSP_CAPDR_IFCNT_Msk /*!< IF instruction counter */ -#define HSP_CAPDR_ALT_TSKNB_Pos (26UL) -#define HSP_CAPDR_ALT_TSKNB_Msk (0x3FUL << HSP_CAPDR_ALT_TSKNB_Pos) /*!< 0xFC000000 */ -#define HSP_CAPDR_ALT_TSKNB HSP_CAPDR_TSKNB_Msk /*!< Last captured task number */ - -/******************** Bit definition for HSP_CAPCR register ********************/ -#define HSP_CAPCR_CAPMOD_Pos (0UL) -#define HSP_CAPCR_CAPMOD_Msk (0x3UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000003 */ -#define HSP_CAPCR_CAPMOD HSP_CAPCR_CAPMOD_Msk /*!< CAPMOD[1:0] bits (Capture mode ) */ -#define HSP_CAPCR_CAPMOD_0 (0x1UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000001 */ -#define HSP_CAPCR_CAPMOD_1 (0x2UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000002 */ - -#define HSP_CAPCR_FRCNTEN_Pos (2UL) -#define HSP_CAPCR_FRCNTEN_Msk (0x1UL << HSP_CAPCR_FRCNTEN_Pos) /*!< 0x00000004 */ -#define HSP_CAPCR_FRCNTEN HSP_CAPCR_FRCNTEN_Msk /*!< FRCNTEN (Free-running counter enable ) */ - -#define HSP_CAPCR_PRESC_Pos (4UL) -#define HSP_CAPCR_PRESC_Msk (0x1FUL << HSP_CAPCR_PRESC_Pos) /*!< 0x000001F0 */ -#define HSP_CAPCR_PRESC HSP_CAPCR_PRESC_Msk /*!< PRESC[4:0] bits (Time-stamp prescaler value ) */ -#define HSP_CAPCR_PRESC_0 (0x01UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000010 */ -#define HSP_CAPCR_PRESC_1 (0x02UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000020 */ -#define HSP_CAPCR_PRESC_2 (0x04UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000040 */ -#define HSP_CAPCR_PRESC_3 (0x08UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000080 */ -#define HSP_CAPCR_PRESC_4 (0x10UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000100 */ - -#define HSP_CAPCR_TSKFLT_Pos (12UL) -#define HSP_CAPCR_TSKFLT_Msk (0x1UL << HSP_CAPCR_TSKFLT_Pos) /*!< 0x00001000 */ -#define HSP_CAPCR_TSKFLT HSP_CAPCR_TSKFLT_Msk /*!< TSKFLT (Task filter enable (1)) */ - -#define HSP_CAPCR_CCNTREN_Pos (16UL) -#define HSP_CAPCR_CCNTREN_Msk (0x1UL << HSP_CAPCR_CCNTREN_Pos) /*!< 0x00010000 */ -#define HSP_CAPCR_CCNTREN HSP_CAPCR_CCNTREN_Msk /*!< CCNTREN (Conflict counter enable ) */ - -/******************** Bit definition for HSP_ERR_IER register ********************/ -#define HSP_ERR_IER_TRGIOVRIE_Pos (8UL) -#define HSP_ERR_IER_TRGIOVRIE_Msk (0x1UL << HSP_ERR_IER_TRGIOVRIE_Pos) /*!< 0x00000100 */ -#define HSP_ERR_IER_TRGIOVRIE HSP_ERR_IER_TRGIOVRIE_Msk /*!< TRGIOVRIE (TRGITF overrun interrupt enable) */ - -#define HSP_ERR_IER_B0ERRIE_Pos (12UL) -#define HSP_ERR_IER_B0ERRIE_Msk (0x1UL << HSP_ERR_IER_B0ERRIE_Pos) /*!< 0x00001000 */ -#define HSP_ERR_IER_B0ERRIE HSP_ERR_IER_B0ERRIE_Msk /*!< B0ERRIE (H2CBUFF0 underrun or C2HBUFF0 overrun interrupt enable) */ - -#define HSP_ERR_IER_B1ERRIE_Pos (13UL) -#define HSP_ERR_IER_B1ERRIE_Msk (0x1UL << HSP_ERR_IER_B1ERRIE_Pos) /*!< 0x00002000 */ -#define HSP_ERR_IER_B1ERRIE HSP_ERR_IER_B1ERRIE_Msk /*!< B1ERRIE (H2CBUFF1 underrun or C2HBUFF1 overrun interrupt enable) */ - -#define HSP_ERR_IER_B2ERRIE_Pos (14UL) -#define HSP_ERR_IER_B2ERRIE_Msk (0x1UL << HSP_ERR_IER_B2ERRIE_Pos) /*!< 0x00004000 */ -#define HSP_ERR_IER_B2ERRIE HSP_ERR_IER_B2ERRIE_Msk /*!< B2ERRIE (H2CBUFF2 underrun or C2HBUFF2 overrun interrupt enable) */ - -#define HSP_ERR_IER_B3ERRIE_Pos (15UL) -#define HSP_ERR_IER_B3ERRIE_Msk (0x1UL << HSP_ERR_IER_B3ERRIE_Pos) /*!< 0x00008000 */ -#define HSP_ERR_IER_B3ERRIE HSP_ERR_IER_B3ERRIE_Msk /*!< B3ERRIE (H2CBUFF3 underrun or C2HBUFF3 overrun interrupt enable) */ - -#define HSP_ERR_IER_CAPOVRIE_Pos (16UL) -#define HSP_ERR_IER_CAPOVRIE_Msk (0x1UL << HSP_ERR_IER_CAPOVRIE_Pos) /*!< 0x00010000 */ -#define HSP_ERR_IER_CAPOVRIE HSP_ERR_IER_CAPOVRIE_Msk /*!< CAPOVRIE (Capture register overrun interrupt enable) */ - -#define HSP_ERR_IER_FWERRIE_Pos (17UL) -#define HSP_ERR_IER_FWERRIE_Msk (0x1UL << HSP_ERR_IER_FWERRIE_Pos) /*!< 0x00020000 */ -#define HSP_ERR_IER_FWERRIE HSP_ERR_IER_FWERRIE_Msk /*!< FWERRIE (Firmware error interrupt enable) */ - -#define HSP_ERR_IER_SCHERRIE_Pos (18UL) -#define HSP_ERR_IER_SCHERRIE_Msk (0x1UL << HSP_ERR_IER_SCHERRIE_Pos) /*!< 0x00040000 */ -#define HSP_ERR_IER_SCHERRIE HSP_ERR_IER_SCHERRIE_Msk /*!< SCHERRIE (Scheduler error interrupt enable) */ - -#define HSP_ERR_IER_BKINIE_Pos (19UL) -#define HSP_ERR_IER_BKINIE_Msk (0x1UL << HSP_ERR_IER_BKINIE_Pos) /*!< 0x00080000 */ -#define HSP_ERR_IER_BKINIE HSP_ERR_IER_BKINIE_Msk /*!< BKINIE (Break input interrupt enable) */ - -#define HSP_ERR_IER_HDEGOVRIE_Pos (20UL) -#define HSP_ERR_IER_HDEGOVRIE_Msk (0x1UL << HSP_ERR_IER_HDEGOVRIE_Pos) /*!< 0x00100000 */ -#define HSP_ERR_IER_HDEGOVRIE HSP_ERR_IER_HDEGOVRIE_Msk /*!< HDEGOVRIE (SPE event overrun interrupt enable) */ - -#define HSP_ERR_IER_OPCOERRIE_Pos (22UL) -#define HSP_ERR_IER_OPCOERRIE_Msk (0x1UL << HSP_ERR_IER_OPCOERRIE_Pos) /*!< 0x00400000 */ -#define HSP_ERR_IER_OPCOERRIE HSP_ERR_IER_OPCOERRIE_Msk /*!< OPCOERRIE (Invalid Op. code error interrupt enable) */ - -#define HSP_ERR_IER_ACCERRIE_Pos (23UL) -#define HSP_ERR_IER_ACCERRIE_Msk (0x1UL << HSP_ERR_IER_ACCERRIE_Pos) /*!< 0x00800000 */ -#define HSP_ERR_IER_ACCERRIE HSP_ERR_IER_ACCERRIE_Msk /*!< ACCERRIE (SPE access error interrupt enable) */ - -#define HSP_ERR_IER_UDFIE_Pos (24UL) -#define HSP_ERR_IER_UDFIE_Msk (0x1UL << HSP_ERR_IER_UDFIE_Pos) /*!< 0x01000000 */ -#define HSP_ERR_IER_UDFIE HSP_ERR_IER_UDFIE_Msk /*!< UDFIE (FPU Underflow exception interrupt enable) */ - -#define HSP_ERR_IER_OVFIE_Pos (25UL) -#define HSP_ERR_IER_OVFIE_Msk (0x1UL << HSP_ERR_IER_OVFIE_Pos) /*!< 0x02000000 */ -#define HSP_ERR_IER_OVFIE HSP_ERR_IER_OVFIE_Msk /*!< OVFIE (FPU Overflow exception interrupt enable) */ - -#define HSP_ERR_IER_DBZIE_Pos (26UL) -#define HSP_ERR_IER_DBZIE_Msk (0x1UL << HSP_ERR_IER_DBZIE_Pos) /*!< 0x04000000 */ -#define HSP_ERR_IER_DBZIE HSP_ERR_IER_DBZIE_Msk /*!< DBZIE (FPU division-by-zero exception interrupt enable) */ - -#define HSP_ERR_IER_INVIE_Pos (27UL) -#define HSP_ERR_IER_INVIE_Msk (0x1UL << HSP_ERR_IER_INVIE_Pos) /*!< 0x08000000 */ -#define HSP_ERR_IER_INVIE HSP_ERR_IER_INVIE_Msk /*!< INVIE (FPU Invalid exception interrupt enable) */ - -#define HSP_ERR_IER_DENORMIE_Pos (28UL) -#define HSP_ERR_IER_DENORMIE_Msk (0x1UL << HSP_ERR_IER_DENORMIE_Pos) /*!< 0x10000000 */ -#define HSP_ERR_IER_DENORMIE HSP_ERR_IER_DENORMIE_Msk /*!< DENORMIE (FPU denormal interrupt enable) */ - -/******************** Bit definition for HSP_EVT_IER register ********************/ -#define HSP_EVT_IER_H2CMRDYIE_Pos (0UL) -#define HSP_EVT_IER_H2CMRDYIE_Msk (0x1UL << HSP_EVT_IER_H2CMRDYIE_Pos) /*!< 0x00000001 */ -#define HSP_EVT_IER_H2CMRDYIE HSP_EVT_IER_H2CMRDYIE_Msk /*!< H2CMRDYIE (HSP to CPU message ready interrupt enable) */ - -#define HSP_EVT_IER_C2HMFREEIE_Pos (1UL) -#define HSP_EVT_IER_C2HMFREEIE_Msk (0x1UL << HSP_EVT_IER_C2HMFREEIE_Pos) /*!< 0x00000002 */ -#define HSP_EVT_IER_C2HMFREEIE HSP_EVT_IER_C2HMFREEIE_Msk /*!< C2HMFREEIE (CPU to HSP message box free interrupt enable) */ - -#define HSP_EVT_IER_DCDONEIE_Pos (2UL) -#define HSP_EVT_IER_DCDONEIE_Msk (0x1UL << HSP_EVT_IER_DCDONEIE_Pos) /*!< 0x00000004 */ -#define HSP_EVT_IER_DCDONEIE HSP_EVT_IER_DCDONEIE_Msk /*!< DCDONEIE (Direct command done interrupt enable) */ - -#define HSP_EVT_IER_CAPRDYIE_Pos (4UL) -#define HSP_EVT_IER_CAPRDYIE_Msk (0x1UL << HSP_EVT_IER_CAPRDYIE_Pos) /*!< 0x00000010 */ -#define HSP_EVT_IER_CAPRDYIE HSP_EVT_IER_CAPRDYIE_Msk /*!< CAPRDYIE (Capture buffer data ready interrupt enable) */ - -#define HSP_EVT_IER_CDEGRDYIE_Pos (7UL) -#define HSP_EVT_IER_CDEGRDYIE_Msk (0x1UL << HSP_EVT_IER_CDEGRDYIE_Pos) /*!< 0x00000080 */ -#define HSP_EVT_IER_CDEGRDYIE HSP_EVT_IER_CDEGRDYIE_Msk /*!< CDEGRDYIE (CPU Dedicated event generator ready interrupt enable) */ - -#define HSP_EVT_IER_SOFWFEIE_Pos (8UL) -#define HSP_EVT_IER_SOFWFEIE_Msk (0x1UL << HSP_EVT_IER_SOFWFEIE_Pos) /*!< 0x00000100 */ -#define HSP_EVT_IER_SOFWFEIE HSP_EVT_IER_SOFWFEIE_Msk /*!< SOFWFEIE (Start of WFE interrupt enable) */ - -#define HSP_EVT_IER_EOFWFEIE_Pos (9UL) -#define HSP_EVT_IER_EOFWFEIE_Msk (0x1UL << HSP_EVT_IER_EOFWFEIE_Pos) /*!< 0x00000200 */ -#define HSP_EVT_IER_EOFWFEIE HSP_EVT_IER_EOFWFEIE_Msk /*!< EOFWFEIE (End of WFE interrupt enable) */ - -#define HSP_EVT_IER_B0EVTIE_Pos (12UL) -#define HSP_EVT_IER_B0EVTIE_Msk (0x1UL << HSP_EVT_IER_B0EVTIE_Pos) /*!< 0x00001000 */ -#define HSP_EVT_IER_B0EVTIE HSP_EVT_IER_B0EVTIE_Msk /*!< B0EVTIE (BUFF0 event interrupt enable) */ - -#define HSP_EVT_IER_B1EVTIE_Pos (13UL) -#define HSP_EVT_IER_B1EVTIE_Msk (0x1UL << HSP_EVT_IER_B1EVTIE_Pos) /*!< 0x00002000 */ -#define HSP_EVT_IER_B1EVTIE HSP_EVT_IER_B1EVTIE_Msk /*!< B1EVTIE (BUFF1 event interrupt enable) */ - -#define HSP_EVT_IER_B2EVTIE_Pos (14UL) -#define HSP_EVT_IER_B2EVTIE_Msk (0x1UL << HSP_EVT_IER_B2EVTIE_Pos) /*!< 0x00004000 */ -#define HSP_EVT_IER_B2EVTIE HSP_EVT_IER_B2EVTIE_Msk /*!< B2EVTIE (BUFF2 event interrupt enable) */ - -#define HSP_EVT_IER_B3EVTIE_Pos (15UL) -#define HSP_EVT_IER_B3EVTIE_Msk (0x1UL << HSP_EVT_IER_B3EVTIE_Pos) /*!< 0x00008000 */ -#define HSP_EVT_IER_B3EVTIE HSP_EVT_IER_B3EVTIE_Msk /*!< B3EVTIE (BUFF3 event interrupt enable) */ - -#define HSP_EVT_IER_SOTECP0IE_Pos (16UL) -#define HSP_EVT_IER_SOTECP0IE_Msk (0x1UL << HSP_EVT_IER_SOTECP0IE_Pos) /*!< 0x00010000 */ -#define HSP_EVT_IER_SOTECP0IE HSP_EVT_IER_SOTECP0IE_Msk /*!< SOTECP0IE (Start of task generated by event comparator 0 interrupt enable) */ - -#define HSP_EVT_IER_SOTECP1IE_Pos (17UL) -#define HSP_EVT_IER_SOTECP1IE_Msk (0x1UL << HSP_EVT_IER_SOTECP1IE_Pos) /*!< 0x00020000 */ -#define HSP_EVT_IER_SOTECP1IE HSP_EVT_IER_SOTECP1IE_Msk /*!< SOTECP1IE (Start of task generated by event comparator 1 interrupt enable) */ - -#define HSP_EVT_IER_SOTECP2IE_Pos (18UL) -#define HSP_EVT_IER_SOTECP2IE_Msk (0x1UL << HSP_EVT_IER_SOTECP2IE_Pos) /*!< 0x00040000 */ -#define HSP_EVT_IER_SOTECP2IE HSP_EVT_IER_SOTECP2IE_Msk /*!< SOTECP2IE (Start of task generated by event comparator 2 interrupt enable) */ - -#define HSP_EVT_IER_SOTECP3IE_Pos (19UL) -#define HSP_EVT_IER_SOTECP3IE_Msk (0x1UL << HSP_EVT_IER_SOTECP3IE_Pos) /*!< 0x00080000 */ -#define HSP_EVT_IER_SOTECP3IE HSP_EVT_IER_SOTECP3IE_Msk /*!< SOTECP3IE (Start of task generated by event comparator 3 interrupt enable) */ - -#define HSP_EVT_IER_EOTECP0IE_Pos (20UL) -#define HSP_EVT_IER_EOTECP0IE_Msk (0x1UL << HSP_EVT_IER_EOTECP0IE_Pos) /*!< 0x00100000 */ -#define HSP_EVT_IER_EOTECP0IE HSP_EVT_IER_EOTECP0IE_Msk /*!< EOTECP0IE (End of task generated by event comparator 0 interrupt enable) */ - -#define HSP_EVT_IER_EOTECP1IE_Pos (21UL) -#define HSP_EVT_IER_EOTECP1IE_Msk (0x1UL << HSP_EVT_IER_EOTECP1IE_Pos) /*!< 0x00200000 */ -#define HSP_EVT_IER_EOTECP1IE HSP_EVT_IER_EOTECP1IE_Msk /*!< EOTECP1IE (End of task generated by event comparator 1 interrupt enable) */ - -#define HSP_EVT_IER_EOTECP2IE_Pos (22UL) -#define HSP_EVT_IER_EOTECP2IE_Msk (0x1UL << HSP_EVT_IER_EOTECP2IE_Pos) /*!< 0x00400000 */ -#define HSP_EVT_IER_EOTECP2IE HSP_EVT_IER_EOTECP2IE_Msk /*!< EOTECP2IE (End of task generated by event comparator 2 interrupt enable) */ - -#define HSP_EVT_IER_EOTECP3IE_Pos (23UL) -#define HSP_EVT_IER_EOTECP3IE_Msk (0x1UL << HSP_EVT_IER_EOTECP3IE_Pos) /*!< 0x00800000 */ -#define HSP_EVT_IER_EOTECP3IE HSP_EVT_IER_EOTECP3IE_Msk /*!< EOTECP3IE (End of task generated by event comparator 3 interrupt enable) */ - -#define HSP_EVT_IER_TOVLPIE_Pos (28UL) -#define HSP_EVT_IER_TOVLPIE_Msk (0x1UL << HSP_EVT_IER_TOVLPIE_Pos) /*!< 0x10000000 */ -#define HSP_EVT_IER_TOVLPIE HSP_EVT_IER_TOVLPIE_Msk /*!< TOVLPIE (Task overlap flag interrupt enable) */ - -#define HSP_EVT_IER_FPUSATIE_Pos (31UL) -#define HSP_EVT_IER_FPUSATIE_Msk (0x1UL << HSP_EVT_IER_FPUSATIE_Pos) /*!< 0x80000000 */ -#define HSP_EVT_IER_FPUSATIE HSP_EVT_IER_FPUSATIE_Msk /*!< FPUSATIE (Saturation flag interrupt enable) */ - -/******************** Bit definition for HSP_PFCTEVT_IER register ********************/ -#define HSP_PFCTEVT_IER_PFCTIE_Pos (0UL) -#define HSP_PFCTEVT_IER_PFCTIE_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PFCTEVT_IER_PFCTIE HSP_PFCTEVT_IER_PFCTIE_Msk /*!< PFCTIE[31:0] bits (Processing function flags interrupt enable) */ -#define HSP_PFCTEVT_IER_PFCTIE_0 (0x00001UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000001 */ -#define HSP_PFCTEVT_IER_PFCTIE_1 (0x00002UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000002 */ -#define HSP_PFCTEVT_IER_PFCTIE_2 (0x00004UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000004 */ -#define HSP_PFCTEVT_IER_PFCTIE_3 (0x00008UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000008 */ -#define HSP_PFCTEVT_IER_PFCTIE_4 (0x00010UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000010 */ -#define HSP_PFCTEVT_IER_PFCTIE_5 (0x00020UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000020 */ -#define HSP_PFCTEVT_IER_PFCTIE_6 (0x00040UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000040 */ -#define HSP_PFCTEVT_IER_PFCTIE_7 (0x00080UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000080 */ -#define HSP_PFCTEVT_IER_PFCTIE_8 (0x00100UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000100 */ -#define HSP_PFCTEVT_IER_PFCTIE_9 (0x00200UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000200 */ -#define HSP_PFCTEVT_IER_PFCTIE_10 (0x00400UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000400 */ -#define HSP_PFCTEVT_IER_PFCTIE_11 (0x00800UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000800 */ -#define HSP_PFCTEVT_IER_PFCTIE_12 (0x01000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00001000 */ -#define HSP_PFCTEVT_IER_PFCTIE_13 (0x02000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00002000 */ -#define HSP_PFCTEVT_IER_PFCTIE_14 (0x04000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00004000 */ -#define HSP_PFCTEVT_IER_PFCTIE_15 (0x08000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00008000 */ -#define HSP_PFCTEVT_IER_PFCTIE_16 (0x10000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00010000 */ -#define HSP_PFCTEVT_IER_PFCTIE_17 (0x20000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00020000 */ -#define HSP_PFCTEVT_IER_PFCTIE_18 (0x40000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00040000 */ -#define HSP_PFCTEVT_IER_PFCTIE_19 (0x80000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00080000 */ -#define HSP_PFCTEVT_IER_PFCTIE_20 (0x100000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00100000 */ -#define HSP_PFCTEVT_IER_PFCTIE_21 (0x200000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00200000 */ -#define HSP_PFCTEVT_IER_PFCTIE_22 (0x400000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00400000 */ -#define HSP_PFCTEVT_IER_PFCTIE_23 (0x800000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00800000 */ -#define HSP_PFCTEVT_IER_PFCTIE_24 (0x1000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x01000000 */ -#define HSP_PFCTEVT_IER_PFCTIE_25 (0x2000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x02000000 */ -#define HSP_PFCTEVT_IER_PFCTIE_26 (0x4000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x04000000 */ -#define HSP_PFCTEVT_IER_PFCTIE_27 (0x8000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x08000000 */ -#define HSP_PFCTEVT_IER_PFCTIE_28 (0x10000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x10000000 */ -#define HSP_PFCTEVT_IER_PFCTIE_29 (0x20000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x20000000 */ -#define HSP_PFCTEVT_IER_PFCTIE_30 (0x40000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x40000000 */ -#define HSP_PFCTEVT_IER_PFCTIE_31 (0x80000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_ERR_ISR register ********************/ -#define HSP_ERR_ISR_TRGIOVRF_Pos (8UL) -#define HSP_ERR_ISR_TRGIOVRF_Msk (0x1UL << HSP_ERR_ISR_TRGIOVRF_Pos) /*!< 0x00000100 */ -#define HSP_ERR_ISR_TRGIOVRF HSP_ERR_ISR_TRGIOVRF_Msk /*!< TRGIOVRF (TRGITF overrun flag) */ - -#define HSP_ERR_ISR_B0ERRF_Pos (12UL) -#define HSP_ERR_ISR_B0ERRF_Msk (0x1UL << HSP_ERR_ISR_B0ERRF_Pos) /*!< 0x00001000 */ -#define HSP_ERR_ISR_B0ERRF HSP_ERR_ISR_B0ERRF_Msk /*!< B0ERRF (H2CBUFF0 underrun or C2HBUFF0 overrun flag) */ - -#define HSP_ERR_ISR_B1ERRF_Pos (13UL) -#define HSP_ERR_ISR_B1ERRF_Msk (0x1UL << HSP_ERR_ISR_B1ERRF_Pos) /*!< 0x00002000 */ -#define HSP_ERR_ISR_B1ERRF HSP_ERR_ISR_B1ERRF_Msk /*!< B1ERRF (H2CBUFF1 underrun or C2HBUFF1 overrun flag) */ - -#define HSP_ERR_ISR_B2ERRF_Pos (14UL) -#define HSP_ERR_ISR_B2ERRF_Msk (0x1UL << HSP_ERR_ISR_B2ERRF_Pos) /*!< 0x00004000 */ -#define HSP_ERR_ISR_B2ERRF HSP_ERR_ISR_B2ERRF_Msk /*!< B2ERRF (H2CBUFF2 underrun or C2HBUFF2 overrun flag) */ - -#define HSP_ERR_ISR_B3ERRF_Pos (15UL) -#define HSP_ERR_ISR_B3ERRF_Msk (0x1UL << HSP_ERR_ISR_B3ERRF_Pos) /*!< 0x00008000 */ -#define HSP_ERR_ISR_B3ERRF HSP_ERR_ISR_B3ERRF_Msk /*!< B3ERRF (H2CBUFF3 underrun or C2HBUFF3 overrun flag) */ - -#define HSP_ERR_ISR_CAPOVRF_Pos (16UL) -#define HSP_ERR_ISR_CAPOVRF_Msk (0x1UL << HSP_ERR_ISR_CAPOVRF_Pos) /*!< 0x00010000 */ -#define HSP_ERR_ISR_CAPOVRF HSP_ERR_ISR_CAPOVRF_Msk /*!< CAPOVRF (Capture register overrun flag) */ - -#define HSP_ERR_ISR_FWERRF_Pos (17UL) -#define HSP_ERR_ISR_FWERRF_Msk (0x1UL << HSP_ERR_ISR_FWERRF_Pos) /*!< 0x00020000 */ -#define HSP_ERR_ISR_FWERRF HSP_ERR_ISR_FWERRF_Msk /*!< FWERRF (Firmware error flag) */ - -#define HSP_ERR_ISR_SCHERRF_Pos (18UL) -#define HSP_ERR_ISR_SCHERRF_Msk (0x1UL << HSP_ERR_ISR_SCHERRF_Pos) /*!< 0x00040000 */ -#define HSP_ERR_ISR_SCHERRF HSP_ERR_ISR_SCHERRF_Msk /*!< SCHERRF (Scheduler error flag) */ - -#define HSP_ERR_ISR_BKINF_Pos (19UL) -#define HSP_ERR_ISR_BKINF_Msk (0x1UL << HSP_ERR_ISR_BKINF_Pos) /*!< 0x00080000 */ -#define HSP_ERR_ISR_BKINF HSP_ERR_ISR_BKINF_Msk /*!< BKINF (Break input flag) */ - -#define HSP_ERR_ISR_HDEGOVRF_Pos (20UL) -#define HSP_ERR_ISR_HDEGOVRF_Msk (0x1UL << HSP_ERR_ISR_HDEGOVRF_Pos) /*!< 0x00100000 */ -#define HSP_ERR_ISR_HDEGOVRF HSP_ERR_ISR_HDEGOVRF_Msk /*!< HDEGOVRF (SPE event overrun flag) */ - -#define HSP_ERR_ISR_OPCOERRF_Pos (22UL) -#define HSP_ERR_ISR_OPCOERRF_Msk (0x1UL << HSP_ERR_ISR_OPCOERRF_Pos) /*!< 0x00400000 */ -#define HSP_ERR_ISR_OPCOERRF HSP_ERR_ISR_OPCOERRF_Msk /*!< OPCOERRF (Invalid OpCode error flag) */ - -#define HSP_ERR_ISR_ACCERRF_Pos (23UL) -#define HSP_ERR_ISR_ACCERRF_Msk (0x1UL << HSP_ERR_ISR_ACCERRF_Pos) /*!< 0x00800000 */ -#define HSP_ERR_ISR_ACCERRF HSP_ERR_ISR_ACCERRF_Msk /*!< ACCERRF (SPE Access error flag) */ - -#define HSP_ERR_ISR_FPUERRF_Pos (24UL) -#define HSP_ERR_ISR_FPUERRF_Msk (0x1UL << HSP_ERR_ISR_FPUERRF_Pos) /*!< 0x01000000 */ -#define HSP_ERR_ISR_FPUERRF HSP_ERR_ISR_FPUERRF_Msk /*!< FPUERRF (Computation error flag) */ - -/******************** Bit definition for HSP_EVT_ISR register ********************/ -#define HSP_EVT_ISR_H2CMRDYF_Pos (0UL) -#define HSP_EVT_ISR_H2CMRDYF_Msk (0x1UL << HSP_EVT_ISR_H2CMRDYF_Pos) /*!< 0x00000001 */ -#define HSP_EVT_ISR_H2CMRDYF HSP_EVT_ISR_H2CMRDYF_Msk /*!< H2CMRDYF (HSP to CPU message ready flag) */ - -#define HSP_EVT_ISR_C2HMFREEF_Pos (1UL) -#define HSP_EVT_ISR_C2HMFREEF_Msk (0x1UL << HSP_EVT_ISR_C2HMFREEF_Pos) /*!< 0x00000002 */ -#define HSP_EVT_ISR_C2HMFREEF HSP_EVT_ISR_C2HMFREEF_Msk /*!< C2HMFREEF (CPU to HSP message box free flag) */ - -#define HSP_EVT_ISR_DCDONEF_Pos (2UL) -#define HSP_EVT_ISR_DCDONEF_Msk (0x1UL << HSP_EVT_ISR_DCDONEF_Pos) /*!< 0x00000004 */ -#define HSP_EVT_ISR_DCDONEF HSP_EVT_ISR_DCDONEF_Msk /*!< DCDONEF (Direct command done flag) */ - -#define HSP_EVT_ISR_CAPRDYF_Pos (4UL) -#define HSP_EVT_ISR_CAPRDYF_Msk (0x1UL << HSP_EVT_ISR_CAPRDYF_Pos) /*!< 0x00000010 */ -#define HSP_EVT_ISR_CAPRDYF HSP_EVT_ISR_CAPRDYF_Msk /*!< CAPRDYF (Capture buffer data ready flag) */ - -#define HSP_EVT_ISR_CDEGRDYF_Pos (7UL) -#define HSP_EVT_ISR_CDEGRDYF_Msk (0x1UL << HSP_EVT_ISR_CDEGRDYF_Pos) /*!< 0x00000080 */ -#define HSP_EVT_ISR_CDEGRDYF HSP_EVT_ISR_CDEGRDYF_Msk /*!< CDEGRDYF (CPU Dedicated event generator ready flag) */ - -#define HSP_EVT_ISR_SOFWFEF_Pos (8UL) -#define HSP_EVT_ISR_SOFWFEF_Msk (0x1UL << HSP_EVT_ISR_SOFWFEF_Pos) /*!< 0x00000100 */ -#define HSP_EVT_ISR_SOFWFEF HSP_EVT_ISR_SOFWFEF_Msk /*!< SOFWFEF (Start of WFE flag) */ - -#define HSP_EVT_ISR_EOFWFEF_Pos (9UL) -#define HSP_EVT_ISR_EOFWFEF_Msk (0x1UL << HSP_EVT_ISR_EOFWFEF_Pos) /*!< 0x00000200 */ -#define HSP_EVT_ISR_EOFWFEF HSP_EVT_ISR_EOFWFEF_Msk /*!< EOFWFEF (End of WFE flag) */ - -#define HSP_EVT_ISR_B0EVTF_Pos (12UL) -#define HSP_EVT_ISR_B0EVTF_Msk (0x1UL << HSP_EVT_ISR_B0EVTF_Pos) /*!< 0x00001000 */ -#define HSP_EVT_ISR_B0EVTF HSP_EVT_ISR_B0EVTF_Msk /*!< B0EVTF (BUFF0 event flag) */ - -#define HSP_EVT_ISR_B1EVTF_Pos (13UL) -#define HSP_EVT_ISR_B1EVTF_Msk (0x1UL << HSP_EVT_ISR_B1EVTF_Pos) /*!< 0x00002000 */ -#define HSP_EVT_ISR_B1EVTF HSP_EVT_ISR_B1EVTF_Msk /*!< B1EVTF (BUFF1 event flag) */ - -#define HSP_EVT_ISR_B2EVTF_Pos (14UL) -#define HSP_EVT_ISR_B2EVTF_Msk (0x1UL << HSP_EVT_ISR_B2EVTF_Pos) /*!< 0x00004000 */ -#define HSP_EVT_ISR_B2EVTF HSP_EVT_ISR_B2EVTF_Msk /*!< B2EVTF (BUFF2 event flag) */ - -#define HSP_EVT_ISR_B3EVTF_Pos (15UL) -#define HSP_EVT_ISR_B3EVTF_Msk (0x1UL << HSP_EVT_ISR_B3EVTF_Pos) /*!< 0x00008000 */ -#define HSP_EVT_ISR_B3EVTF HSP_EVT_ISR_B3EVTF_Msk /*!< B3EVTF (BUFF3 event flag) */ - -#define HSP_EVT_ISR_SOTECP0F_Pos (16UL) -#define HSP_EVT_ISR_SOTECP0F_Msk (0x1UL << HSP_EVT_ISR_SOTECP0F_Pos) /*!< 0x00010000 */ -#define HSP_EVT_ISR_SOTECP0F HSP_EVT_ISR_SOTECP0F_Msk /*!< SOTECP0F (Start of task flag, for event comparator 0) */ - -#define HSP_EVT_ISR_SOTECP1F_Pos (17UL) -#define HSP_EVT_ISR_SOTECP1F_Msk (0x1UL << HSP_EVT_ISR_SOTECP1F_Pos) /*!< 0x00020000 */ -#define HSP_EVT_ISR_SOTECP1F HSP_EVT_ISR_SOTECP1F_Msk /*!< SOTECP1F (Start of task flag, for event comparator 1) */ - -#define HSP_EVT_ISR_SOTECP2F_Pos (18UL) -#define HSP_EVT_ISR_SOTECP2F_Msk (0x1UL << HSP_EVT_ISR_SOTECP2F_Pos) /*!< 0x00040000 */ -#define HSP_EVT_ISR_SOTECP2F HSP_EVT_ISR_SOTECP2F_Msk /*!< SOTECP2F (Start of task flag, for event comparator 2) */ - -#define HSP_EVT_ISR_SOTECP3F_Pos (19UL) -#define HSP_EVT_ISR_SOTECP3F_Msk (0x1UL << HSP_EVT_ISR_SOTECP3F_Pos) /*!< 0x00080000 */ -#define HSP_EVT_ISR_SOTECP3F HSP_EVT_ISR_SOTECP3F_Msk /*!< SOTECP3F (Start of task flag, for event comparator 3) */ - -#define HSP_EVT_ISR_EOTECP0F_Pos (20UL) -#define HSP_EVT_ISR_EOTECP0F_Msk (0x1UL << HSP_EVT_ISR_EOTECP0F_Pos) /*!< 0x00100000 */ -#define HSP_EVT_ISR_EOTECP0F HSP_EVT_ISR_EOTECP0F_Msk /*!< EOTECP0F (End of task flag, for event comparator 0) */ - -#define HSP_EVT_ISR_EOTECP1F_Pos (21UL) -#define HSP_EVT_ISR_EOTECP1F_Msk (0x1UL << HSP_EVT_ISR_EOTECP1F_Pos) /*!< 0x00200000 */ -#define HSP_EVT_ISR_EOTECP1F HSP_EVT_ISR_EOTECP1F_Msk /*!< EOTECP1F (End of task flag, for event comparator 1) */ - -#define HSP_EVT_ISR_EOTECP2F_Pos (22UL) -#define HSP_EVT_ISR_EOTECP2F_Msk (0x1UL << HSP_EVT_ISR_EOTECP2F_Pos) /*!< 0x00400000 */ -#define HSP_EVT_ISR_EOTECP2F HSP_EVT_ISR_EOTECP2F_Msk /*!< EOTECP2F (End of task flag, for event comparator 2) */ - -#define HSP_EVT_ISR_EOTECP3F_Pos (23UL) -#define HSP_EVT_ISR_EOTECP3F_Msk (0x1UL << HSP_EVT_ISR_EOTECP3F_Pos) /*!< 0x00800000 */ -#define HSP_EVT_ISR_EOTECP3F HSP_EVT_ISR_EOTECP3F_Msk /*!< EOTECP3F (End of task flag, for event comparator 3) */ - -#define HSP_EVT_ISR_TOVLPF_Pos (28UL) -#define HSP_EVT_ISR_TOVLPF_Msk (0x1UL << HSP_EVT_ISR_TOVLPF_Pos) /*!< 0x10000000 */ -#define HSP_EVT_ISR_TOVLPF HSP_EVT_ISR_TOVLPF_Msk /*!< TOVLPF (Task overlap flag) */ - -#define HSP_EVT_ISR_FPUSATF_Pos (31UL) -#define HSP_EVT_ISR_FPUSATF_Msk (0x1UL << HSP_EVT_ISR_FPUSATF_Pos) /*!< 0x80000000 */ -#define HSP_EVT_ISR_FPUSATF HSP_EVT_ISR_FPUSATF_Msk /*!< FPUSATF (FPU saturation flag) */ - -/******************** Bit definition for HSP_PFCTEVT_ISR register ********************/ -#define HSP_PFCTEVT_ISR_PFCTF_Pos (0UL) -#define HSP_PFCTEVT_ISR_PFCTF_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PFCTEVT_ISR_PFCTF HSP_PFCTEVT_ISR_PFCTF_Msk /*!< PFCTF[31:0] bits (Flags generated by SPE processing functions ) */ -#define HSP_PFCTEVT_ISR_PFCTF_0 (0x00001UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000001 */ -#define HSP_PFCTEVT_ISR_PFCTF_1 (0x00002UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000002 */ -#define HSP_PFCTEVT_ISR_PFCTF_2 (0x00004UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000004 */ -#define HSP_PFCTEVT_ISR_PFCTF_3 (0x00008UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000008 */ -#define HSP_PFCTEVT_ISR_PFCTF_4 (0x00010UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000010 */ -#define HSP_PFCTEVT_ISR_PFCTF_5 (0x00020UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000020 */ -#define HSP_PFCTEVT_ISR_PFCTF_6 (0x00040UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000040 */ -#define HSP_PFCTEVT_ISR_PFCTF_7 (0x00080UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000080 */ -#define HSP_PFCTEVT_ISR_PFCTF_8 (0x00100UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000100 */ -#define HSP_PFCTEVT_ISR_PFCTF_9 (0x00200UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000200 */ -#define HSP_PFCTEVT_ISR_PFCTF_10 (0x00400UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000400 */ -#define HSP_PFCTEVT_ISR_PFCTF_11 (0x00800UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000800 */ -#define HSP_PFCTEVT_ISR_PFCTF_12 (0x01000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00001000 */ -#define HSP_PFCTEVT_ISR_PFCTF_13 (0x02000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00002000 */ -#define HSP_PFCTEVT_ISR_PFCTF_14 (0x04000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00004000 */ -#define HSP_PFCTEVT_ISR_PFCTF_15 (0x08000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00008000 */ -#define HSP_PFCTEVT_ISR_PFCTF_16 (0x10000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00010000 */ -#define HSP_PFCTEVT_ISR_PFCTF_17 (0x20000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00020000 */ -#define HSP_PFCTEVT_ISR_PFCTF_18 (0x40000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00040000 */ -#define HSP_PFCTEVT_ISR_PFCTF_19 (0x80000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00080000 */ -#define HSP_PFCTEVT_ISR_PFCTF_20 (0x100000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00100000 */ -#define HSP_PFCTEVT_ISR_PFCTF_21 (0x200000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00200000 */ -#define HSP_PFCTEVT_ISR_PFCTF_22 (0x400000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00400000 */ -#define HSP_PFCTEVT_ISR_PFCTF_23 (0x800000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00800000 */ -#define HSP_PFCTEVT_ISR_PFCTF_24 (0x1000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x01000000 */ -#define HSP_PFCTEVT_ISR_PFCTF_25 (0x2000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x02000000 */ -#define HSP_PFCTEVT_ISR_PFCTF_26 (0x4000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x04000000 */ -#define HSP_PFCTEVT_ISR_PFCTF_27 (0x8000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x08000000 */ -#define HSP_PFCTEVT_ISR_PFCTF_28 (0x10000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x10000000 */ -#define HSP_PFCTEVT_ISR_PFCTF_29 (0x20000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x20000000 */ -#define HSP_PFCTEVT_ISR_PFCTF_30 (0x40000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x40000000 */ -#define HSP_PFCTEVT_ISR_PFCTF_31 (0x80000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_ERRINFR register ********************/ -#define HSP_ERRINFR_INEXACT_Pos (0UL) -#define HSP_ERRINFR_INEXACT_Msk (0x1UL << HSP_ERRINFR_INEXACT_Pos) /*!< 0x00000001 */ -#define HSP_ERRINFR_INEXACT HSP_ERRINFR_INEXACT_Msk /*!< INEXACT (INEXACT exception flag) */ - -#define HSP_ERRINFR_UDFLOW_Pos (1UL) -#define HSP_ERRINFR_UDFLOW_Msk (0x1UL << HSP_ERRINFR_UDFLOW_Pos) /*!< 0x00000002 */ -#define HSP_ERRINFR_UDFLOW HSP_ERRINFR_UDFLOW_Msk /*!< UDFLOW (UNDERFLOW exception flag) */ - -#define HSP_ERRINFR_OVFLOW_Pos (2UL) -#define HSP_ERRINFR_OVFLOW_Msk (0x1UL << HSP_ERRINFR_OVFLOW_Pos) /*!< 0x00000004 */ -#define HSP_ERRINFR_OVFLOW HSP_ERRINFR_OVFLOW_Msk /*!< OVFLOW (OVERFLOW exception flag) */ - -#define HSP_ERRINFR_DIVZERO_Pos (3UL) -#define HSP_ERRINFR_DIVZERO_Msk (0x1UL << HSP_ERRINFR_DIVZERO_Pos) /*!< 0x00000008 */ -#define HSP_ERRINFR_DIVZERO HSP_ERRINFR_DIVZERO_Msk /*!< DIVZERO (Division by zero exception flag) */ - -#define HSP_ERRINFR_INVALID_Pos (4UL) -#define HSP_ERRINFR_INVALID_Msk (0x1UL << HSP_ERRINFR_INVALID_Pos) /*!< 0x00000010 */ -#define HSP_ERRINFR_INVALID HSP_ERRINFR_INVALID_Msk /*!< INVALID (INVALID exception flag) */ - -#define HSP_ERRINFR_DENORM_Pos (5UL) -#define HSP_ERRINFR_DENORM_Msk (0x1UL << HSP_ERRINFR_DENORM_Pos) /*!< 0x00000020 */ -#define HSP_ERRINFR_DENORM HSP_ERRINFR_DENORM_Msk /*!< DENORM (DENORMAL exception flag) */ - -#define HSP_ERRINFR_CMERR_Pos (8UL) -#define HSP_ERRINFR_CMERR_Msk (0x1UL << HSP_ERRINFR_CMERR_Pos) /*!< 0x00000100 */ -#define HSP_ERRINFR_CMERR HSP_ERRINFR_CMERR_Msk /*!< CMERR (Code memory access error flag) */ - -#define HSP_ERRINFR_DMERR_Pos (9UL) -#define HSP_ERRINFR_DMERR_Msk (0x1UL << HSP_ERRINFR_DMERR_Pos) /*!< 0x00000200 */ -#define HSP_ERRINFR_DMERR HSP_ERRINFR_DMERR_Msk /*!< DMERR (Data memory access error flag) */ - -#define HSP_ERRINFR_MAHBERR_Pos (11UL) -#define HSP_ERRINFR_MAHBERR_Msk (0x1UL << HSP_ERRINFR_MAHBERR_Pos) /*!< 0x00000800 */ -#define HSP_ERRINFR_MAHBERR HSP_ERRINFR_MAHBERR_Msk /*!< MAHBERR (Internal AHB access error flag) */ - -#define HSP_ERRINFR_SAHBERR_Pos (12UL) -#define HSP_ERRINFR_SAHBERR_Msk (0x1UL << HSP_ERRINFR_SAHBERR_Pos) /*!< 0x00001000 */ -#define HSP_ERRINFR_SAHBERR HSP_ERRINFR_SAHBERR_Msk /*!< SAHBERR (Slave AHB access error flag) */ - -#define HSP_ERRINFR_TRGIERR_Pos (16UL) -#define HSP_ERRINFR_TRGIERR_Msk (0x3FFUL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x03FF0000 */ -#define HSP_ERRINFR_TRGIERR HSP_ERRINFR_TRGIERR_Msk /*!< TRGIERR[9:0] bits (TRGIN error information) */ -#define HSP_ERRINFR_TRGIERR_0 (0x001UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00010000 */ -#define HSP_ERRINFR_TRGIERR_1 (0x002UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00020000 */ -#define HSP_ERRINFR_TRGIERR_2 (0x004UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00040000 */ -#define HSP_ERRINFR_TRGIERR_3 (0x008UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00080000 */ -#define HSP_ERRINFR_TRGIERR_4 (0x010UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00100000 */ -#define HSP_ERRINFR_TRGIERR_5 (0x020UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00200000 */ -#define HSP_ERRINFR_TRGIERR_6 (0x040UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00400000 */ -#define HSP_ERRINFR_TRGIERR_7 (0x080UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00800000 */ -#define HSP_ERRINFR_TRGIERR_8 (0x100UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x01000000 */ -#define HSP_ERRINFR_TRGIERR_9 (0x200UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x02000000 */ - -/******************** Bit definition for HSP_ERR_ICR register ********************/ -#define HSP_ERR_ICR_TRGIOVRC_Pos (8UL) -#define HSP_ERR_ICR_TRGIOVRC_Msk (0x1UL << HSP_ERR_ICR_TRGIOVRC_Pos) /*!< 0x00000100 */ -#define HSP_ERR_ICR_TRGIOVRC HSP_ERR_ICR_TRGIOVRC_Msk /*!< TRGIOVRC (Clear TRGIOVRF flag) */ - -#define HSP_ERR_ICR_B0ERRC_Pos (12UL) -#define HSP_ERR_ICR_B0ERRC_Msk (0x1UL << HSP_ERR_ICR_B0ERRC_Pos) /*!< 0x00001000 */ -#define HSP_ERR_ICR_B0ERRC HSP_ERR_ICR_B0ERRC_Msk /*!< B0ERRC (Clear B0ERRF flag) */ - -#define HSP_ERR_ICR_B1ERRC_Pos (13UL) -#define HSP_ERR_ICR_B1ERRC_Msk (0x1UL << HSP_ERR_ICR_B1ERRC_Pos) /*!< 0x00002000 */ -#define HSP_ERR_ICR_B1ERRC HSP_ERR_ICR_B1ERRC_Msk /*!< B1ERRC (Clear B1ERRF flag) */ - -#define HSP_ERR_ICR_B2ERRC_Pos (14UL) -#define HSP_ERR_ICR_B2ERRC_Msk (0x1UL << HSP_ERR_ICR_B2ERRC_Pos) /*!< 0x00004000 */ -#define HSP_ERR_ICR_B2ERRC HSP_ERR_ICR_B2ERRC_Msk /*!< B2ERRC (Clear B2ERRF flag) */ - -#define HSP_ERR_ICR_B3ERRC_Pos (15UL) -#define HSP_ERR_ICR_B3ERRC_Msk (0x1UL << HSP_ERR_ICR_B3ERRC_Pos) /*!< 0x00008000 */ -#define HSP_ERR_ICR_B3ERRC HSP_ERR_ICR_B3ERRC_Msk /*!< B3ERRC (Clear B3ERRF flag) */ - -#define HSP_ERR_ICR_CAPOVRC_Pos (16UL) -#define HSP_ERR_ICR_CAPOVRC_Msk (0x1UL << HSP_ERR_ICR_CAPOVRC_Pos) /*!< 0x00010000 */ -#define HSP_ERR_ICR_CAPOVRC HSP_ERR_ICR_CAPOVRC_Msk /*!< CAPOVRC (Clear CAPOVRF flag) */ - -#define HSP_ERR_ICR_FWERRC_Pos (17UL) -#define HSP_ERR_ICR_FWERRC_Msk (0x1UL << HSP_ERR_ICR_FWERRC_Pos) /*!< 0x00020000 */ -#define HSP_ERR_ICR_FWERRC HSP_ERR_ICR_FWERRC_Msk /*!< FWERRC (Clear FWERRF flag) */ - -#define HSP_ERR_ICR_SCHERRC_Pos (18UL) -#define HSP_ERR_ICR_SCHERRC_Msk (0x1UL << HSP_ERR_ICR_SCHERRC_Pos) /*!< 0x00040000 */ -#define HSP_ERR_ICR_SCHERRC HSP_ERR_ICR_SCHERRC_Msk /*!< SCHERRC (Clear SCHERRF flag) */ - -#define HSP_ERR_ICR_BKINC_Pos (19UL) -#define HSP_ERR_ICR_BKINC_Msk (0x1UL << HSP_ERR_ICR_BKINC_Pos) /*!< 0x00080000 */ -#define HSP_ERR_ICR_BKINC HSP_ERR_ICR_BKINC_Msk /*!< BKINC (Clear BKINF flag) */ - -#define HSP_ERR_ICR_HDEGOVRC_Pos (20UL) -#define HSP_ERR_ICR_HDEGOVRC_Msk (0x1UL << HSP_ERR_ICR_HDEGOVRC_Pos) /*!< 0x00100000 */ -#define HSP_ERR_ICR_HDEGOVRC HSP_ERR_ICR_HDEGOVRC_Msk /*!< HDEGOVRC (Clear HDEGOVRF flag) */ - -#define HSP_ERR_ICR_OPCOERRC_Pos (22UL) -#define HSP_ERR_ICR_OPCOERRC_Msk (0x1UL << HSP_ERR_ICR_OPCOERRC_Pos) /*!< 0x00400000 */ -#define HSP_ERR_ICR_OPCOERRC HSP_ERR_ICR_OPCOERRC_Msk /*!< OPCOERRC (Clear OPCOERRF flag) */ - -#define HSP_ERR_ICR_ACCERRC_Pos (23UL) -#define HSP_ERR_ICR_ACCERRC_Msk (0x1UL << HSP_ERR_ICR_ACCERRC_Pos) /*!< 0x00800000 */ -#define HSP_ERR_ICR_ACCERRC HSP_ERR_ICR_ACCERRC_Msk /*!< ACCERRC (Clear ACCERRF flag) */ - -#define HSP_ERR_ICR_FPUERRC_Pos (24UL) -#define HSP_ERR_ICR_FPUERRC_Msk (0x1UL << HSP_ERR_ICR_FPUERRC_Pos) /*!< 0x01000000 */ -#define HSP_ERR_ICR_FPUERRC HSP_ERR_ICR_FPUERRC_Msk /*!< FPUERRC (Clear FPUERRF flag) */ - -/******************** Bit definition for HSP_EVT_ICR register ********************/ -#define HSP_EVT_ICR_H2CMRDYC_Pos (0UL) -#define HSP_EVT_ICR_H2CMRDYC_Msk (0x1UL << HSP_EVT_ICR_H2CMRDYC_Pos) /*!< 0x00000001 */ -#define HSP_EVT_ICR_H2CMRDYC HSP_EVT_ICR_H2CMRDYC_Msk /*!< H2CMRDYC (Clear H2CMRDYF flag) */ - -#define HSP_EVT_ICR_C2HMFREEC_Pos (1UL) -#define HSP_EVT_ICR_C2HMFREEC_Msk (0x1UL << HSP_EVT_ICR_C2HMFREEC_Pos) /*!< 0x00000002 */ -#define HSP_EVT_ICR_C2HMFREEC HSP_EVT_ICR_C2HMFREEC_Msk /*!< C2HMFREEC (Clear C2HMFREEF flag) */ - -#define HSP_EVT_ICR_DCDONEC_Pos (2UL) -#define HSP_EVT_ICR_DCDONEC_Msk (0x1UL << HSP_EVT_ICR_DCDONEC_Pos) /*!< 0x00000004 */ -#define HSP_EVT_ICR_DCDONEC HSP_EVT_ICR_DCDONEC_Msk /*!< DCDONEC (Clear DCDONEF flag) */ - -#define HSP_EVT_ICR_CDEGRDYC_Pos (7UL) -#define HSP_EVT_ICR_CDEGRDYC_Msk (0x1UL << HSP_EVT_ICR_CDEGRDYC_Pos) /*!< 0x00000080 */ -#define HSP_EVT_ICR_CDEGRDYC HSP_EVT_ICR_CDEGRDYC_Msk /*!< CDEGRDYC (Clear of CDEGRDYF flag) */ - -#define HSP_EVT_ICR_SOFWFEC_Pos (8UL) -#define HSP_EVT_ICR_SOFWFEC_Msk (0x1UL << HSP_EVT_ICR_SOFWFEC_Pos) /*!< 0x00000100 */ -#define HSP_EVT_ICR_SOFWFEC HSP_EVT_ICR_SOFWFEC_Msk /*!< SOFWFEC (Clear of SOFWFEF flag) */ - -#define HSP_EVT_ICR_EOFWFEC_Pos (9UL) -#define HSP_EVT_ICR_EOFWFEC_Msk (0x1UL << HSP_EVT_ICR_EOFWFEC_Pos) /*!< 0x00000200 */ -#define HSP_EVT_ICR_EOFWFEC HSP_EVT_ICR_EOFWFEC_Msk /*!< EOFWFEC (Clear of EOFWFEF flag) */ - -#define HSP_EVT_ICR_SOTECP0C_Pos (16UL) -#define HSP_EVT_ICR_SOTECP0C_Msk (0x1UL << HSP_EVT_ICR_SOTECP0C_Pos) /*!< 0x00010000 */ -#define HSP_EVT_ICR_SOTECP0C HSP_EVT_ICR_SOTECP0C_Msk /*!< SOTECP0C (Clear SOTECP0F flag) */ - -#define HSP_EVT_ICR_SOTECP1C_Pos (17UL) -#define HSP_EVT_ICR_SOTECP1C_Msk (0x1UL << HSP_EVT_ICR_SOTECP1C_Pos) /*!< 0x00020000 */ -#define HSP_EVT_ICR_SOTECP1C HSP_EVT_ICR_SOTECP1C_Msk /*!< SOTECP1C (Clear SOTECP1F flag) */ - -#define HSP_EVT_ICR_SOTECP2C_Pos (18UL) -#define HSP_EVT_ICR_SOTECP2C_Msk (0x1UL << HSP_EVT_ICR_SOTECP2C_Pos) /*!< 0x00040000 */ -#define HSP_EVT_ICR_SOTECP2C HSP_EVT_ICR_SOTECP2C_Msk /*!< SOTECP2C (Clear SOTECP2F flag) */ - -#define HSP_EVT_ICR_SOTECP3C_Pos (19UL) -#define HSP_EVT_ICR_SOTECP3C_Msk (0x1UL << HSP_EVT_ICR_SOTECP3C_Pos) /*!< 0x00080000 */ -#define HSP_EVT_ICR_SOTECP3C HSP_EVT_ICR_SOTECP3C_Msk /*!< SOTECP3C (Clear SOTECP3F flag) */ - -#define HSP_EVT_ICR_EOTECP0C_Pos (20UL) -#define HSP_EVT_ICR_EOTECP0C_Msk (0x1UL << HSP_EVT_ICR_EOTECP0C_Pos) /*!< 0x00100000 */ -#define HSP_EVT_ICR_EOTECP0C HSP_EVT_ICR_EOTECP0C_Msk /*!< EOTECP0C (Clear EOTECP0F flag) */ - -#define HSP_EVT_ICR_EOTECP1C_Pos (21UL) -#define HSP_EVT_ICR_EOTECP1C_Msk (0x1UL << HSP_EVT_ICR_EOTECP1C_Pos) /*!< 0x00200000 */ -#define HSP_EVT_ICR_EOTECP1C HSP_EVT_ICR_EOTECP1C_Msk /*!< EOTECP1C (Clear EOTECP1F flag) */ - -#define HSP_EVT_ICR_EOTECP2C_Pos (22UL) -#define HSP_EVT_ICR_EOTECP2C_Msk (0x1UL << HSP_EVT_ICR_EOTECP2C_Pos) /*!< 0x00400000 */ -#define HSP_EVT_ICR_EOTECP2C HSP_EVT_ICR_EOTECP2C_Msk /*!< EOTECP2C (Clear EOTECP2F flag) */ - -#define HSP_EVT_ICR_EOTECP3C_Pos (23UL) -#define HSP_EVT_ICR_EOTECP3C_Msk (0x1UL << HSP_EVT_ICR_EOTECP3C_Pos) /*!< 0x00800000 */ -#define HSP_EVT_ICR_EOTECP3C HSP_EVT_ICR_EOTECP3C_Msk /*!< EOTECP3C (Clear EOTECP3F flag) */ - -#define HSP_EVT_ICR_TOVLPC_Pos (28UL) -#define HSP_EVT_ICR_TOVLPC_Msk (0x1UL << HSP_EVT_ICR_TOVLPC_Pos) /*!< 0x10000000 */ -#define HSP_EVT_ICR_TOVLPC HSP_EVT_ICR_TOVLPC_Msk /*!< TOVLPC (Clear TOVLPF flag) */ - -#define HSP_EVT_ICR_FPUSATC_Pos (31UL) -#define HSP_EVT_ICR_FPUSATC_Msk (0x1UL << HSP_EVT_ICR_FPUSATC_Pos) /*!< 0x80000000 */ -#define HSP_EVT_ICR_FPUSATC HSP_EVT_ICR_FPUSATC_Msk /*!< FPUSATC (Clear FPUSATF flag) */ - -/******************** Bit definition for HSP_PFCTEVT_ICR register ********************/ -#define HSP_PFCTEVT_ICR_PFCTC_Pos (0UL) -#define HSP_PFCTEVT_ICR_PFCTC_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PFCTEVT_ICR_PFCTC HSP_PFCTEVT_ICR_PFCTC_Msk /*!< PFCTC[31:0] bits (Clear PFCTF[31:0] flag) */ -#define HSP_PFCTEVT_ICR_PFCTC_0 (0x00001UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000001 */ -#define HSP_PFCTEVT_ICR_PFCTC_1 (0x00002UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000002 */ -#define HSP_PFCTEVT_ICR_PFCTC_2 (0x00004UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000004 */ -#define HSP_PFCTEVT_ICR_PFCTC_3 (0x00008UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000008 */ -#define HSP_PFCTEVT_ICR_PFCTC_4 (0x00010UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000010 */ -#define HSP_PFCTEVT_ICR_PFCTC_5 (0x00020UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000020 */ -#define HSP_PFCTEVT_ICR_PFCTC_6 (0x00040UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000040 */ -#define HSP_PFCTEVT_ICR_PFCTC_7 (0x00080UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000080 */ -#define HSP_PFCTEVT_ICR_PFCTC_8 (0x00100UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000100 */ -#define HSP_PFCTEVT_ICR_PFCTC_9 (0x00200UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000200 */ -#define HSP_PFCTEVT_ICR_PFCTC_10 (0x00400UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000400 */ -#define HSP_PFCTEVT_ICR_PFCTC_11 (0x00800UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000800 */ -#define HSP_PFCTEVT_ICR_PFCTC_12 (0x01000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00001000 */ -#define HSP_PFCTEVT_ICR_PFCTC_13 (0x02000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00002000 */ -#define HSP_PFCTEVT_ICR_PFCTC_14 (0x04000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00004000 */ -#define HSP_PFCTEVT_ICR_PFCTC_15 (0x08000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00008000 */ -#define HSP_PFCTEVT_ICR_PFCTC_16 (0x10000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00010000 */ -#define HSP_PFCTEVT_ICR_PFCTC_17 (0x20000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00020000 */ -#define HSP_PFCTEVT_ICR_PFCTC_18 (0x40000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00040000 */ -#define HSP_PFCTEVT_ICR_PFCTC_19 (0x80000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00080000 */ -#define HSP_PFCTEVT_ICR_PFCTC_20 (0x100000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00100000 */ -#define HSP_PFCTEVT_ICR_PFCTC_21 (0x200000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00200000 */ -#define HSP_PFCTEVT_ICR_PFCTC_22 (0x400000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00400000 */ -#define HSP_PFCTEVT_ICR_PFCTC_23 (0x800000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00800000 */ -#define HSP_PFCTEVT_ICR_PFCTC_24 (0x1000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x01000000 */ -#define HSP_PFCTEVT_ICR_PFCTC_25 (0x2000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x02000000 */ -#define HSP_PFCTEVT_ICR_PFCTC_26 (0x4000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x04000000 */ -#define HSP_PFCTEVT_ICR_PFCTC_27 (0x8000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x08000000 */ -#define HSP_PFCTEVT_ICR_PFCTC_28 (0x10000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x10000000 */ -#define HSP_PFCTEVT_ICR_PFCTC_29 (0x20000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x20000000 */ -#define HSP_PFCTEVT_ICR_PFCTC_30 (0x40000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x40000000 */ -#define HSP_PFCTEVT_ICR_PFCTC_31 (0x80000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_FWVERR register ********************/ -#define HSP_FWVERR_CRAMINREV_Pos (0UL) -#define HSP_FWVERR_CRAMINREV_Msk (0xFFUL << HSP_FWVERR_CRAMINREV_Pos) /*!< 0x000000FF */ -#define HSP_FWVERR_CRAMINREV HSP_FWVERR_CRAMINREV_Msk /*!< CRAMINREV[7:0] bits (Code RAM Minor revision) */ - -#define HSP_FWVERR_CRAMAJREV_Pos (8UL) -#define HSP_FWVERR_CRAMAJREV_Msk (0xFUL << HSP_FWVERR_CRAMAJREV_Pos) /*!< 0x00000F00 */ -#define HSP_FWVERR_CRAMAJREV HSP_FWVERR_CRAMAJREV_Msk /*!< CRAMAJREV[3:0] bits (Code RAM Major revision) */ - -#define HSP_FWVERR_CROMINREV_Pos (12UL) -#define HSP_FWVERR_CROMINREV_Msk (0xFFUL << HSP_FWVERR_CROMINREV_Pos) /*!< 0x000FF000 */ -#define HSP_FWVERR_CROMINREV HSP_FWVERR_CROMINREV_Msk /*!< CROMINREV[7:0] bits (Code ROM Minor revision) */ - -#define HSP_FWVERR_CROMAJREV_Pos (20UL) -#define HSP_FWVERR_CROMAJREV_Msk (0xFUL << HSP_FWVERR_CROMAJREV_Pos) /*!< 0x000F0000 */ -#define HSP_FWVERR_CROMAJREV HSP_FWVERR_CROMAJREV_Msk /*!< CROMAJREV[3:0] bits (Code ROM Major revision) */ - -#define HSP_FWVERR_DROMINREV_Pos (24UL) -#define HSP_FWVERR_DROMINREV_Msk (0xFUL << HSP_FWVERR_DROMINREV_Pos) /*!< 0x00F00000 */ -#define HSP_FWVERR_DROMINREV HSP_FWVERR_DROMINREV_Msk /*!< DROMINREV[3:0] bits (Data ROM Minor revision) */ - -#define HSP_FWVERR_DROMAJREV_Pos (28UL) -#define HSP_FWVERR_DROMAJREV_Msk (0xFUL << HSP_FWVERR_DROMAJREV_Pos) /*!< 0x0F000000 */ -#define HSP_FWVERR_DROMAJREV HSP_FWVERR_DROMAJREV_Msk /*!< DROMAJREV[3:0] bits (Data ROM Major revision) */ - -/******************************************************************************/ -/* */ -/* Inter-integrated Circuit Interface (I2C) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for I2C_CR1 register *******************/ -#define I2C_CR1_PE_Pos (0UL) -#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ -#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ -#define I2C_CR1_TXIE_Pos (1UL) -#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ -#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ -#define I2C_CR1_RXIE_Pos (2UL) -#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ -#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ -#define I2C_CR1_ADDRIE_Pos (3UL) -#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ -#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ -#define I2C_CR1_NACKIE_Pos (4UL) -#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ -#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ -#define I2C_CR1_STOPIE_Pos (5UL) -#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ -#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ -#define I2C_CR1_TCIE_Pos (6UL) -#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ -#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ -#define I2C_CR1_ERRIE_Pos (7UL) -#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ -#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ -#define I2C_CR1_DNF_Pos (8UL) -#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ -#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ -#define I2C_CR1_ANFOFF_Pos (12UL) -#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ -#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST_Pos (13UL) -#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ -#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ -#define I2C_CR1_TXDMAEN_Pos (14UL) -#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ -#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ -#define I2C_CR1_RXDMAEN_Pos (15UL) -#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ -#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ -#define I2C_CR1_SBC_Pos (16UL) -#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ -#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ -#define I2C_CR1_NOSTRETCH_Pos (17UL) -#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ -#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ -#define I2C_CR1_WUPEN_Pos (18UL) -#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ -#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ -#define I2C_CR1_GCEN_Pos (19UL) -#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ -#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ -#define I2C_CR1_SMBHEN_Pos (20UL) -#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ -#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ -#define I2C_CR1_SMBDEN_Pos (21UL) -#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ -#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ -#define I2C_CR1_ALERTEN_Pos (22UL) -#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ -#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ -#define I2C_CR1_PECEN_Pos (23UL) -#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ -#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ -#define I2C_CR1_FMP_Pos (24UL) -#define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ -#define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< FMP enable */ -#define I2C_CR1_ADDRACLR_Pos (30UL) -#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ -#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ -#define I2C_CR1_STOPFACLR_Pos (31UL) -#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ -#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ - -/****************** Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_SADD_Pos (0UL) -#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ -#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ -#define I2C_CR2_RD_WRN_Pos (10UL) -#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ -#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ -#define I2C_CR2_ADD10_Pos (11UL) -#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ -#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ -#define I2C_CR2_HEAD10R_Pos (12UL) -#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ -#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ -#define I2C_CR2_START_Pos (13UL) -#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ -#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ -#define I2C_CR2_STOP_Pos (14UL) -#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ -#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ -#define I2C_CR2_NACK_Pos (15UL) -#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ -#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ -#define I2C_CR2_NBYTES_Pos (16UL) -#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ -#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ -#define I2C_CR2_RELOAD_Pos (24UL) -#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ -#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ -#define I2C_CR2_AUTOEND_Pos (25UL) -#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ -#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ -#define I2C_CR2_PECBYTE_Pos (26UL) -#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ -#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ - -/******************* Bit definition for I2C_OAR1 register ******************/ -#define I2C_OAR1_OA1_Pos (0UL) -#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ -#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ -#define I2C_OAR1_OA1MODE_Pos (10UL) -#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ -#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ -#define I2C_OAR1_OA1EN_Pos (15UL) -#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ -#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ - -/******************* Bit definition for I2C_OAR2 register ******************/ -#define I2C_OAR2_OA2_Pos (1UL) -#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ -#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ -#define I2C_OAR2_OA2MSK_Pos (8UL) -#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ -#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ -#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ -#define I2C_OAR2_OA2MASK01_Pos (8UL) -#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ -#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ -#define I2C_OAR2_OA2MASK02_Pos (9UL) -#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ -#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ -#define I2C_OAR2_OA2MASK03_Pos (8UL) -#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ -#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ -#define I2C_OAR2_OA2MASK04_Pos (10UL) -#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ -#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ -#define I2C_OAR2_OA2MASK05_Pos (8UL) -#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ -#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ -#define I2C_OAR2_OA2MASK06_Pos (9UL) -#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ -#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ -#define I2C_OAR2_OA2MASK07_Pos (8UL) -#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ -#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ -#define I2C_OAR2_OA2EN_Pos (15UL) -#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ -#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ - -/******************* Bit definition for I2C_TIMINGR register *******************/ -#define I2C_TIMINGR_SCLL_Pos (0UL) -#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ -#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ -#define I2C_TIMINGR_SCLH_Pos (8UL) -#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ -#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ -#define I2C_TIMINGR_SDADEL_Pos (16UL) -#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ -#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ -#define I2C_TIMINGR_SCLDEL_Pos (20UL) -#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ -#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ -#define I2C_TIMINGR_PRESC_Pos (28UL) -#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ -#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ - -/******************* Bit definition for I2C_TIMEOUTR register *******************/ -#define I2C_TIMEOUTR_TIMEOUTA_Pos (0UL) -#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ -#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ -#define I2C_TIMEOUTR_TIDLE_Pos (12UL) -#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ -#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ -#define I2C_TIMEOUTR_TIMOUTEN_Pos (15UL) -#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ -#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ -#define I2C_TIMEOUTR_TIMEOUTB_Pos (16UL) -#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ -#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ -#define I2C_TIMEOUTR_TEXTEN_Pos (31UL) -#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ -#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ - -/****************** Bit definition for I2C_ISR register *********************/ -#define I2C_ISR_TXE_Pos (0UL) -#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ -#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ -#define I2C_ISR_TXIS_Pos (1UL) -#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ -#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ -#define I2C_ISR_RXNE_Pos (2UL) -#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ -#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ -#define I2C_ISR_ADDR_Pos (3UL) -#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ -#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ -#define I2C_ISR_NACKF_Pos (4UL) -#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ -#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ -#define I2C_ISR_STOPF_Pos (5UL) -#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ -#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ -#define I2C_ISR_TC_Pos (6UL) -#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ -#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ -#define I2C_ISR_TCR_Pos (7UL) -#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ -#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ -#define I2C_ISR_BERR_Pos (8UL) -#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ -#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ -#define I2C_ISR_ARLO_Pos (9UL) -#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ -#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ -#define I2C_ISR_OVR_Pos (10UL) -#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ -#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ -#define I2C_ISR_PECERR_Pos (11UL) -#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ -#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ -#define I2C_ISR_TIMEOUT_Pos (12UL) -#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ -#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ -#define I2C_ISR_ALERT_Pos (13UL) -#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ -#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ -#define I2C_ISR_BUSY_Pos (15UL) -#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ -#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ -#define I2C_ISR_DIR_Pos (16UL) -#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ -#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ -#define I2C_ISR_ADDCODE_Pos (17UL) -#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ -#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ - -/****************** Bit definition for I2C_ICR register *********************/ -#define I2C_ICR_ADDRCF_Pos (3UL) -#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ -#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ -#define I2C_ICR_NACKCF_Pos (4UL) -#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ -#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ -#define I2C_ICR_STOPCF_Pos (5UL) -#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ -#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ -#define I2C_ICR_BERRCF_Pos (8UL) -#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ -#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ -#define I2C_ICR_ARLOCF_Pos (9UL) -#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ -#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ -#define I2C_ICR_OVRCF_Pos (10UL) -#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ -#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ -#define I2C_ICR_PECCF_Pos (11UL) -#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ -#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ -#define I2C_ICR_TIMOUTCF_Pos (12UL) -#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ -#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ -#define I2C_ICR_ALERTCF_Pos (13UL) -#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ -#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ - -/****************** Bit definition for I2C_PECR register *********************/ -#define I2C_PECR_PEC_Pos (0UL) -#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ -#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ - -/****************** Bit definition for I2C_RXDR register *********************/ -#define I2C_RXDR_RXDATA_Pos (0UL) -#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ -#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ - -/****************** Bit definition for I2C_TXDR register *********************/ -#define I2C_TXDR_TXDATA_Pos (0UL) -#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ -#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ - -/****************** Bit definition for I2C_AUTOCR register ********************/ -#define I2C_AUTOCR_TCDMAEN_Pos (6UL) -#define I2C_AUTOCR_TCDMAEN_Msk (0x1UL << I2C_AUTOCR_TCDMAEN_Pos) /*!< 0x00000040 */ -#define I2C_AUTOCR_TCDMAEN I2C_AUTOCR_TCDMAEN_Msk /*!< DMA request enable on Transfer Complete event */ -#define I2C_AUTOCR_TCRDMAEN_Pos (7UL) -#define I2C_AUTOCR_TCRDMAEN_Msk (0x1UL << I2C_AUTOCR_TCRDMAEN_Pos) /*!< 0x00000080 */ -#define I2C_AUTOCR_TCRDMAEN I2C_AUTOCR_TCRDMAEN_Msk /*!< DMA request enable on Transfer Complete Reload event */ -#define I2C_AUTOCR_TRIGSEL_Pos (16UL) -#define I2C_AUTOCR_TRIGSEL_Msk (0xFUL << I2C_AUTOCR_TRIGSEL_Pos) /*!< 0x000F0000 */ -#define I2C_AUTOCR_TRIGSEL I2C_AUTOCR_TRIGSEL_Msk /*!< Trigger selection */ -#define I2C_AUTOCR_TRIGPOL_Pos (20UL) -#define I2C_AUTOCR_TRIGPOL_Msk (0x1UL << I2C_AUTOCR_TRIGPOL_Pos) /*!< 0x000100000 */ -#define I2C_AUTOCR_TRIGPOL I2C_AUTOCR_TRIGPOL_Msk /*!< Trigger polarity */ -#define I2C_AUTOCR_TRIGEN_Pos (21UL) -#define I2C_AUTOCR_TRIGEN_Msk (0x1UL << I2C_AUTOCR_TRIGEN_Pos) /*!< 0x000200000 */ -#define I2C_AUTOCR_TRIGEN I2C_AUTOCR_TRIGEN_Msk /*!< Trigger enable */ - -/******************************************************************************/ -/* */ -/* Improved Inter-integrated Circuit Interface (I3C) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for I3C_CR register *********************/ -#define I3C_CR_DCNT_Pos (0UL) -#define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ -#define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ -#define I3C_CR_RNW_Pos (16UL) -#define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ -#define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ -#define I3C_CR_CCC_Pos (16UL) -#define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ -#define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ -#define I3C_CR_ADD_Pos (17UL) -#define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ -#define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ -#define I3C_CR_MTYPE_Pos (27UL) -#define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ -#define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ -#define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ -#define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ -#define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ -#define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ -#define I3C_CR_MEND_Pos (31UL) -#define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ -#define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ - -/******************* Bit definition for I3C_CFGR register *******************/ -#define I3C_CFGR_EN_Pos (0UL) -#define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ -#define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ -#define I3C_CFGR_CRINIT_Pos (1UL) -#define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ -#define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ -#define I3C_CFGR_NOARBH_Pos (2UL) -#define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ -#define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ -#define I3C_CFGR_RSTPTRN_Pos (3UL) -#define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ -#define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ -#define I3C_CFGR_EXITPTRN_Pos (4UL) -#define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ -#define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ -#define I3C_CFGR_HKSDAEN_Pos (5UL) -#define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ -#define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ -#define I3C_CFGR_HJACK_Pos (7UL) -#define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ -#define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ -#define I3C_CFGR_RXDMAEN_Pos (8UL) -#define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ -#define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ -#define I3C_CFGR_RXFLUSH_Pos (9UL) -#define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ -#define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ -#define I3C_CFGR_RXTHRES_Pos (10UL) -#define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ -#define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ -#define I3C_CFGR_TXDMAEN_Pos (12UL) -#define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ -#define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ -#define I3C_CFGR_TXFLUSH_Pos (13UL) -#define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ -#define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ -#define I3C_CFGR_TXTHRES_Pos (14UL) -#define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ -#define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ -#define I3C_CFGR_SDMAEN_Pos (16UL) -#define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ -#define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ -#define I3C_CFGR_SFLUSH_Pos (17UL) -#define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ -#define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ -#define I3C_CFGR_SMODE_Pos (18UL) -#define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ -#define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ -#define I3C_CFGR_TMODE_Pos (19UL) -#define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ -#define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ -#define I3C_CFGR_CDMAEN_Pos (20UL) -#define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ -#define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ -#define I3C_CFGR_CFLUSH_Pos (21UL) -#define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ -#define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ -#define I3C_CFGR_FCFDIS_Pos (23UL) -#define I3C_CFGR_FCFDIS_Msk (0x1UL << I3C_CFGR_FCFDIS_Pos) /*!< 0x00800000 */ -#define I3C_CFGR_FCFDIS I3C_CFGR_FCFDIS_Msk /*!< FCF generation disable */ -#define I3C_CFGR_TRIGSEL_Pos (24UL) -#define I3C_CFGR_TRIGSEL_Msk (0xFUL << I3C_CFGR_TRIGSEL_Pos) /*!< 0x0F000000 */ -#define I3C_CFGR_TRIGSEL I3C_CFGR_TRIGSEL_Msk /*!< Trigger selection */ -#define I3C_CFGR_TRIGPOL_Pos (28UL) -#define I3C_CFGR_TRIGPOL_Msk (0x1UL << I3C_CFGR_TRIGPOL_Pos) /*!< 0x10000000 */ -#define I3C_CFGR_TRIGPOL I3C_CFGR_TRIGPOL_Msk /*!< Trigger polarity */ -#define I3C_CFGR_TRIGHWEN_Pos (29UL) -#define I3C_CFGR_TRIGHWEN_Msk (0x1UL << I3C_CFGR_TRIGHWEN_Pos) /*!< 0x20000000 */ -#define I3C_CFGR_TRIGHWEN I3C_CFGR_TRIGHWEN_Msk /*!< Trigger enable */ -#define I3C_CFGR_TSFSET_Pos (30UL) -#define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ -#define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ - -/******************* Bit definition for I3C_RDR register ********************/ -#define I3C_RDR_RDB0_Pos (0UL) -#define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ -#define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ - -/****************** Bit definition for I3C_RDWR register ********************/ -#define I3C_RDWR_RDBx_Pos (0UL) -#define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ -#define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ -#define I3C_RDWR_RDB0_Pos (0UL) -#define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ -#define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ -#define I3C_RDWR_RDB1_Pos (8UL) -#define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ -#define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ -#define I3C_RDWR_RDB2_Pos (16UL) -#define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ -#define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ -#define I3C_RDWR_RDB3_Pos (24UL) -#define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ -#define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ - -/******************* Bit definition for I3C_TDR register ********************/ -#define I3C_TDR_TDB0_Pos (0UL) -#define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ -#define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ - -/****************** Bit definition for I3C_TDWR register ********************/ -#define I3C_TDWR_TDBx_Pos (0UL) -#define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ -#define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ -#define I3C_TDWR_TDB0_Pos (0UL) -#define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ -#define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ -#define I3C_TDWR_TDB1_Pos (8UL) -#define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ -#define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ -#define I3C_TDWR_TDB2_Pos (16UL) -#define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ -#define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ -#define I3C_TDWR_TDB3_Pos (24UL) -#define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ -#define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ - -/******************* Bit definition for I3C_IBIDR register ******************/ -#define I3C_IBIDR_IBIDBx_Pos (0UL) -#define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ -#define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ -#define I3C_IBIDR_IBIDB0_Pos (0UL) -#define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ -#define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ -#define I3C_IBIDR_IBIDB1_Pos (8UL) -#define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ -#define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ -#define I3C_IBIDR_IBIDB2_Pos (16UL) -#define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ -#define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ -#define I3C_IBIDR_IBIDB3_Pos (24UL) -#define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ -#define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ - -/****************** Bit definition for I3C_TGTTDR register ******************/ -#define I3C_TGTTDR_TGTTDCNT_Pos (0UL) -#define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ -#define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ -#define I3C_TGTTDR_PRELOAD_Pos (16UL) -#define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ -#define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ - -/******************* Bit definition for I3C_SR register *********************/ -#define I3C_SR_XDCNT_Pos (0UL) -#define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ -#define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ -#define I3C_SR_ABT_Pos (17UL) -#define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ -#define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ -#define I3C_SR_DIR_Pos (18UL) -#define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ -#define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ -#define I3C_SR_MID_Pos (24UL) -#define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ -#define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ - -/******************* Bit definition for I3C_SER register ********************/ -#define I3C_SER_CODERR_Pos (0UL) -#define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ -#define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ -#define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ -#define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ -#define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ -#define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ -#define I3C_SER_PERR_Pos (4UL) -#define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ -#define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ -#define I3C_SER_STALL_Pos (5UL) -#define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ -#define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ -#define I3C_SER_DOVR_Pos (6UL) -#define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ -#define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ -#define I3C_SER_COVR_Pos (7UL) -#define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ -#define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ -#define I3C_SER_ANACK_Pos (8UL) -#define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ -#define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ -#define I3C_SER_DNACK_Pos (9UL) -#define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ -#define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ -#define I3C_SER_DERR_Pos (10UL) -#define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ -#define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ - -/******************* Bit definition for I3C_RMR register ********************/ -#define I3C_RMR_IBIRDCNT_Pos (0UL) -#define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ -#define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ -#define I3C_RMR_RCODE_Pos (8UL) -#define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ -#define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ -#define I3C_RMR_RADD_Pos (17UL) -#define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ -#define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ - -/******************* Bit definition for I3C_EVR register ********************/ -#define I3C_EVR_CFEF_Pos (0UL) -#define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ -#define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ -#define I3C_EVR_TXFEF_Pos (1UL) -#define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ -#define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ -#define I3C_EVR_CFNFF_Pos (2UL) -#define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ -#define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ -#define I3C_EVR_SFNEF_Pos (3UL) -#define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ -#define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ -#define I3C_EVR_TXFNFF_Pos (4UL) -#define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ -#define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ -#define I3C_EVR_RXFNEF_Pos (5UL) -#define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ -#define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ -#define I3C_EVR_TXLASTF_Pos (6UL) -#define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ -#define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ -#define I3C_EVR_RXLASTF_Pos (7UL) -#define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ -#define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ -#define I3C_EVR_FCF_Pos (9UL) -#define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ -#define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ -#define I3C_EVR_RXTGTENDF_Pos (10UL) -#define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ -#define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ -#define I3C_EVR_ERRF_Pos (11UL) -#define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ -#define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ -#define I3C_EVR_IBIF_Pos (15UL) -#define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ -#define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ -#define I3C_EVR_IBIENDF_Pos (16UL) -#define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ -#define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ -#define I3C_EVR_CRF_Pos (17UL) -#define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ -#define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ -#define I3C_EVR_CRUPDF_Pos (18UL) -#define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ -#define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ -#define I3C_EVR_HJF_Pos (19UL) -#define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ -#define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ -#define I3C_EVR_WKPF_Pos (21UL) -#define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ -#define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ -#define I3C_EVR_GETF_Pos (22UL) -#define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ -#define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ -#define I3C_EVR_STAF_Pos (23UL) -#define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ -#define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ -#define I3C_EVR_DAUPDF_Pos (24UL) -#define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ -#define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ -#define I3C_EVR_MWLUPDF_Pos (25UL) -#define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ -#define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ -#define I3C_EVR_MRLUPDF_Pos (26UL) -#define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ -#define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ -#define I3C_EVR_RSTF_Pos (27UL) -#define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ -#define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ -#define I3C_EVR_ASUPDF_Pos (28UL) -#define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ -#define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ -#define I3C_EVR_INTUPDF_Pos (29UL) -#define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ -#define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ -#define I3C_EVR_DEFF_Pos (30UL) -#define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ -#define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ -#define I3C_EVR_GRPF_Pos (31UL) -#define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ -#define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ - -/******************* Bit definition for I3C_IER register ********************/ -#define I3C_IER_CFNFIE_Pos (2UL) -#define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ -#define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ -#define I3C_IER_SFNEIE_Pos (3UL) -#define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ -#define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ -#define I3C_IER_TXFNFIE_Pos (4UL) -#define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ -#define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ -#define I3C_IER_RXFNEIE_Pos (5UL) -#define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ -#define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ -#define I3C_IER_FCIE_Pos (9UL) -#define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ -#define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ -#define I3C_IER_RXTGTENDIE_Pos (10UL) -#define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ -#define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ -#define I3C_IER_ERRIE_Pos (11UL) -#define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ -#define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ -#define I3C_IER_IBIIE_Pos (15UL) -#define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ -#define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ -#define I3C_IER_IBIENDIE_Pos (16UL) -#define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ -#define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ -#define I3C_IER_CRIE_Pos (17UL) -#define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ -#define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ -#define I3C_IER_CRUPDIE_Pos (18UL) -#define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ -#define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ -#define I3C_IER_HJIE_Pos (19UL) -#define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ -#define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ -#define I3C_IER_WKPIE_Pos (21UL) -#define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ -#define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ -#define I3C_IER_GETIE_Pos (22UL) -#define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ -#define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ -#define I3C_IER_STAIE_Pos (23UL) -#define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ -#define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ -#define I3C_IER_DAUPDIE_Pos (24UL) -#define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ -#define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ -#define I3C_IER_MWLUPDIE_Pos (25UL) -#define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ -#define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ -#define I3C_IER_MRLUPDIE_Pos (26UL) -#define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ -#define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ -#define I3C_IER_RSTIE_Pos (27UL) -#define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ -#define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ -#define I3C_IER_ASUPDIE_Pos (28UL) -#define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ -#define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ -#define I3C_IER_INTUPDIE_Pos (29UL) -#define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ -#define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ -#define I3C_IER_DEFIE_Pos (30UL) -#define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ -#define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ -#define I3C_IER_GRPIE_Pos (31UL) -#define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ -#define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ - -/******************* Bit definition for I3C_CEVR register *******************/ -#define I3C_CEVR_CFCF_Pos (9UL) -#define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ -#define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ -#define I3C_CEVR_CRXTGTENDF_Pos (10UL) -#define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ -#define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ -#define I3C_CEVR_CERRF_Pos (11UL) -#define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ -#define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ -#define I3C_CEVR_CIBIF_Pos (15UL) -#define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ -#define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ -#define I3C_CEVR_CIBIENDF_Pos (16UL) -#define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ -#define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ -#define I3C_CEVR_CCRF_Pos (17UL) -#define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ -#define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ -#define I3C_CEVR_CCRUPDF_Pos (18UL) -#define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ -#define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ -#define I3C_CEVR_CHJF_Pos (19UL) -#define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ -#define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ -#define I3C_CEVR_CWKPF_Pos (21UL) -#define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ -#define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ -#define I3C_CEVR_CGETF_Pos (22UL) -#define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ -#define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ -#define I3C_CEVR_CSTAF_Pos (23UL) -#define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ -#define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ -#define I3C_CEVR_CDAUPDF_Pos (24UL) -#define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ -#define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ -#define I3C_CEVR_CMWLUPDF_Pos (25UL) -#define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ -#define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ -#define I3C_CEVR_CMRLUPDF_Pos (26UL) -#define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ -#define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ -#define I3C_CEVR_CRSTF_Pos (27UL) -#define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ -#define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ -#define I3C_CEVR_CASUPDF_Pos (28UL) -#define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ -#define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ -#define I3C_CEVR_CINTUPDF_Pos (29UL) -#define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ -#define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ -#define I3C_CEVR_CDEFF_Pos (30UL) -#define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ -#define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ -#define I3C_CEVR_CGRPF_Pos (31UL) -#define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ -#define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ - -/******************* Bit definition for I3C_MISR register *******************/ -#define I3C_MISR_CFNFMIS_Pos (2UL) -#define I3C_MISR_CFNFMIS_Msk (0x1UL << I3C_MISR_CFNFMIS_Pos) /*!< 0x00000004 */ -#define I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS_Msk /*!< Control FIFO Not Full Mask Interrupt Status */ -#define I3C_MISR_SFNEMIS_Pos (3UL) -#define I3C_MISR_SFNEMIS_Msk (0x1UL << I3C_MISR_SFNEMIS_Pos) /*!< 0x00000008 */ -#define I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS_Msk /*!< Status FIFO Not Empty Mask Interrupt Status */ -#define I3C_MISR_TXFNFMIS_Pos (4UL) -#define I3C_MISR_TXFNFMIS_Msk (0x1UL << I3C_MISR_TXFNFMIS_Pos) /*!< 0x00000010 */ -#define I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS_Msk /*!< TX FIFO Not Full Mask Interrupt Status */ -#define I3C_MISR_RXFNEMIS_Pos (5UL) -#define I3C_MISR_RXFNEMIS_Msk (0x1UL << I3C_MISR_RXFNEMIS_Pos) /*!< 0x00000020 */ -#define I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS_Msk /*!< RX FIFO Not Empty Mask Interrupt Status */ -#define I3C_MISR_FCMIS_Pos (9UL) -#define I3C_MISR_FCMIS_Msk (0x1UL << I3C_MISR_FCMIS_Pos) /*!< 0x00000200 */ -#define I3C_MISR_FCMIS I3C_MISR_FCMIS_Msk /*!< Frame Complete Mask Interrupt Status */ -#define I3C_MISR_RXTGTENDMIS_Pos (10UL) -#define I3C_MISR_RXTGTENDMIS_Msk (0x1UL << I3C_MISR_RXTGTENDMIS_Pos) /*!< 0x00000400 */ -#define I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS_Msk /*!< Reception Target End Mask Interrupt Status */ -#define I3C_MISR_ERRMIS_Pos (11UL) -#define I3C_MISR_ERRMIS_Msk (0x1UL << I3C_MISR_ERRMIS_Pos) /*!< 0x00000800 */ -#define I3C_MISR_ERRMIS I3C_MISR_ERRMIS_Msk /*!< Error Mask Interrupt Status */ -#define I3C_MISR_IBIMIS_Pos (15UL) -#define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ -#define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Mask Interrupt Status */ -#define I3C_MISR_IBIENDMIS_Pos (16UL) -#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ -#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Mask Interrupt Status */ -#define I3C_MISR_CRMIS_Pos (17UL) -#define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ -#define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Mask Interrupt Status */ -#define I3C_MISR_CRUPDMIS_Pos (18UL) -#define I3C_MISR_CRUPDMIS_Msk (0x1UL << I3C_MISR_CRUPDMIS_Pos) /*!< 0x00040000 */ -#define I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS_Msk /*!< Controller-role Update Mask Interrupt Status */ -#define I3C_MISR_HJMIS_Pos (19UL) -#define I3C_MISR_HJMIS_Msk (0x1UL << I3C_MISR_HJMIS_Pos) /*!< 0x00080000 */ -#define I3C_MISR_HJMIS I3C_MISR_HJMIS_Msk /*!< Hot Join Mask Interrupt Status */ -#define I3C_MISR_WKPMIS_Pos (21UL) -#define I3C_MISR_WKPMIS_Msk (0x1UL << I3C_MISR_WKPMIS_Pos) /*!< 0x00200000 */ -#define I3C_MISR_WKPMIS I3C_MISR_WKPMIS_Msk /*!< Wake Up Mask Interrupt Status */ -#define I3C_MISR_GETMIS_Pos (22UL) -#define I3C_MISR_GETMIS_Msk (0x1UL << I3C_MISR_GETMIS_Pos) /*!< 0x00400000 */ -#define I3C_MISR_GETMIS I3C_MISR_GETMIS_Msk /*!< Get type CCC received Mask Interrupt Status */ -#define I3C_MISR_STAMIS_Pos (23UL) -#define I3C_MISR_STAMIS_Msk (0x1UL << I3C_MISR_STAMIS_Pos) /*!< 0x00800000 */ -#define I3C_MISR_STAMIS I3C_MISR_STAMIS_Msk /*!< Get Status Mask Interrupt Status */ -#define I3C_MISR_DAUPDMIS_Pos (24UL) -#define I3C_MISR_DAUPDMIS_Msk (0x1UL << I3C_MISR_DAUPDMIS_Pos) /*!< 0x01000000 */ -#define I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS_Msk /*!< Dynamic Address Update Mask Interrupt Status */ -#define I3C_MISR_MWLUPDMIS_Pos (25UL) -#define I3C_MISR_MWLUPDMIS_Msk (0x1UL << I3C_MISR_MWLUPDMIS_Pos) /*!< 0x02000000 */ -#define I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS_Msk /*!< Max Write Length Update Mask Interrupt Status */ -#define I3C_MISR_MRLUPDMIS_Pos (26UL) -#define I3C_MISR_MRLUPDMIS_Msk (0x1UL << I3C_MISR_MRLUPDMIS_Pos) /*!< 0x04000000 */ -#define I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS_Msk /*!< Max Read Length Update Mask Interrupt Status */ -#define I3C_MISR_RSTMIS_Pos (27UL) -#define I3C_MISR_RSTMIS_Msk (0x1UL << I3C_MISR_RSTMIS_Pos) /*!< 0x08000000 */ -#define I3C_MISR_RSTMIS I3C_MISR_RSTMIS_Msk /*!< Reset Mask Interrupt Status, due to Reset pattern received */ -#define I3C_MISR_ASUPDMIS_Pos (28UL) -#define I3C_MISR_ASUPDMIS_Msk (0x1UL << I3C_MISR_ASUPDMIS_Pos) /*!< 0x10000000 */ -#define I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS_Msk /*!< Activity State Mask Interrupt Status */ -#define I3C_MISR_INTUPDMIS_Pos (29UL) -#define I3C_MISR_INTUPDMIS_Msk (0x1UL << I3C_MISR_INTUPDMIS_Pos) /*!< 0x20000000 */ -#define I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS_Msk /*!< Interrupt Update Mask Interrupt Status */ -#define I3C_MISR_DEFMIS_Pos (30UL) -#define I3C_MISR_DEFMIS_Msk (0x1UL << I3C_MISR_DEFMIS_Pos) /*!< 0x40000000 */ -#define I3C_MISR_DEFMIS I3C_MISR_DEFMIS_Msk /*!< List of Targets Command Received Mask Interrupt Status */ -#define I3C_MISR_GRPMIS_Pos (31UL) -#define I3C_MISR_GRPMIS_Msk (0x1UL << I3C_MISR_GRPMIS_Pos) /*!< 0x80000000 */ -#define I3C_MISR_GRPMIS I3C_MISR_GRPMIS_Msk /*!< List of Group Addresses Command Received Mask Interrupt Status */ - -/****************** Bit definition for I3C_DEVR0 register *******************/ -#define I3C_DEVR0_DAVAL_Pos (0UL) -#define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ -#define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ -#define I3C_DEVR0_DA_Pos (1UL) -#define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ -#define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ -#define I3C_DEVR0_IBIEN_Pos (16UL) -#define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ -#define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ -#define I3C_DEVR0_CREN_Pos (17UL) -#define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ -#define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ -#define I3C_DEVR0_HJEN_Pos (19UL) -#define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ -#define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ -#define I3C_DEVR0_AS_Pos (20UL) -#define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ -#define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ -#define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ -#define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ -#define I3C_DEVR0_RSTACT_Pos (22UL) -#define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ -#define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ -#define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ -#define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ -#define I3C_DEVR0_RSTVAL_Pos (24UL) -#define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ -#define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ - -/****************** Bit definition for I3C_DEVRX register *******************/ -#define I3C_DEVRX_DA_Pos (1UL) -#define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ -#define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ -#define I3C_DEVRX_IBIACK_Pos (16UL) -#define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ -#define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ -#define I3C_DEVRX_CRACK_Pos (17UL) -#define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ -#define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ -#define I3C_DEVRX_IBIDEN_Pos (18UL) -#define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ -#define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ -#define I3C_DEVRX_SUSP_Pos (19UL) -#define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ -#define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ -#define I3C_DEVRX_DIS_Pos (31UL) -#define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ -#define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ - -/****************** Bit definition for I3C_MAXRLR register ******************/ -#define I3C_MAXRLR_MRL_Pos (0UL) -#define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ -#define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ -#define I3C_MAXRLR_IBIP_Pos (16UL) -#define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ -#define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ -#define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ -#define I3C_MAXRLR_IBIP_1 (0x2UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00020000 */ -#define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ - -/****************** Bit definition for I3C_MAXWLR register ******************/ -#define I3C_MAXWLR_MWL_Pos (0UL) -#define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ -#define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ - -/**************** Bit definition for I3C_TIMINGR0 register ******************/ -#define I3C_TIMINGR0_SCLL_PP_Pos (0UL) -#define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ -#define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ -#define I3C_TIMINGR0_SCLH_I3C_Pos (8UL) -#define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ -#define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ -#define I3C_TIMINGR0_SCLL_OD_Pos (16UL) -#define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ -#define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ -#define I3C_TIMINGR0_SCLH_I2C_Pos (24UL) -#define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ -#define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ - -/**************** Bit definition for I3C_TIMINGR1 register ******************/ -#define I3C_TIMINGR1_AVAL_Pos (0UL) -#define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ -#define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ -#define I3C_TIMINGR1_ASNCR_Pos (8UL) -#define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ -#define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ -#define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ -#define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ -#define I3C_TIMINGR1_FREE_Pos (16UL) -#define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ -#define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ -#define I3C_TIMINGR1_SDA_HD_Pos (28UL) -#define I3C_TIMINGR1_SDA_HD_Msk (0x3UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x30000000 */ -#define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ -#define I3C_TIMINGR1_SDA_HD_0 (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x10000000 */ -#define I3C_TIMINGR1_SDA_HD_1 (0x2UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x20000000 */ - -/**************** Bit definition for I3C_TIMINGR2 register ******************/ -#define I3C_TIMINGR2_STALLT_Pos (0UL) -#define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ -#define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ -#define I3C_TIMINGR2_STALLD_Pos (1UL) -#define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ -#define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ -#define I3C_TIMINGR2_STALLC_Pos (2UL) -#define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ -#define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ -#define I3C_TIMINGR2_STALLA_Pos (3UL) -#define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ -#define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ -#define I3C_TIMINGR2_STALLR_Pos (4UL) -#define I3C_TIMINGR2_STALLR_Msk (0x1UL << I3C_TIMINGR2_STALLR_Pos) /*!< 0x00000010 */ -#define I3C_TIMINGR2_STALLR I3C_TIMINGR2_STALLR_Msk /*!< Stall on I2C Read ACK bit */ -#define I3C_TIMINGR2_STALLS_Pos (5UL) -#define I3C_TIMINGR2_STALLS_Msk (0x1UL << I3C_TIMINGR2_STALLS_Pos) /*!< 0x00000020 */ -#define I3C_TIMINGR2_STALLS I3C_TIMINGR2_STALLS_Msk /*!< Stall on I2C Write ACK bit */ -#define I3C_TIMINGR2_STALLL_Pos (6UL) -#define I3C_TIMINGR2_STALLL_Msk (0x1UL << I3C_TIMINGR2_STALLL_Pos) /*!< 0x00000040 */ -#define I3C_TIMINGR2_STALLL I3C_TIMINGR2_STALLL_Msk /*!< Stall on I2C Address ACK bit */ -#define I3C_TIMINGR2_STALL_Pos (8UL) -#define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ -#define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ - -/******************* Bit definition for I3C_BCR register ********************/ -#define I3C_BCR_BCR_Pos (0UL) -#define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ -#define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ -#define I3C_BCR_BCR0_Pos (0UL) -#define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ -#define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ -#define I3C_BCR_BCR1_Pos (1UL) -#define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ -#define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ -#define I3C_BCR_BCR2_Pos (2UL) -#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ -#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ -#define I3C_BCR_BCR3_Pos (3UL) -#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */ -#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */ -#define I3C_BCR_BCR4_Pos (4UL) -#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */ -#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */ -#define I3C_BCR_BCR5_Pos (5UL) -#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */ -#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */ -#define I3C_BCR_BCR6_Pos (6UL) -#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ -#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ - -/******************* Bit definition for I3C_DCR register ********************/ -#define I3C_DCR_DCR_Pos (0UL) -#define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ -#define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ - -/***************** Bit definition for I3C_GETCAPR register ******************/ -#define I3C_GETCAPR_CAPPEND_Pos (14UL) -#define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ -#define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ - -/***************** Bit definition for I3C_CRCAPR register *******************/ -#define I3C_CRCAPR_CAPDHOFF_Pos (3UL) -#define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ -#define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ -#define I3C_CRCAPR_CAPGRP_Pos (9UL) -#define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ -#define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ - -/**************** Bit definition for I3C_GETMXDSR register ******************/ -#define I3C_GETMXDSR_HOFFAS_Pos (0UL) -#define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ -#define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ -#define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ -#define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ -#define I3C_GETMXDSR_FMT_Pos (8UL) -#define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ -#define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ -#define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ -#define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ -#define I3C_GETMXDSR_RDTURN_Pos (16UL) -#define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ -#define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ -#define I3C_GETMXDSR_TSCO_Pos (24UL) -#define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ -#define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ - -/****************** Bit definition for I3C_EPIDR register *******************/ -#define I3C_EPIDR_MIPIID_Pos (12UL) -#define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ -#define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ -#define I3C_EPIDR_IDTSEL_Pos (16UL) -#define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ -#define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ -#define I3C_EPIDR_MIPIMID_Pos (17UL) -#define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ -#define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ - -/******************************************************************************/ -/* */ -/* ICACHE */ -/* */ -/******************************************************************************/ -/****************** Bit definition for ICACHE_CR register *******************/ -#define ICACHE_CR_EN_Pos (0UL) -#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ -#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< Enable */ -#define ICACHE_CR_CACHEINV_Pos (1UL) -#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ -#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ -#define ICACHE_CR_WAYSEL_Pos (2UL) -#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ -#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< Ways selection */ -#define ICACHE_CR_HITMEN_Pos (16UL) -#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ -#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< Hit monitor enable */ -#define ICACHE_CR_MISSMEN_Pos (17UL) -#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ -#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< Miss monitor enable */ -#define ICACHE_CR_HITMRST_Pos (18UL) -#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ -#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< Hit monitor reset */ -#define ICACHE_CR_MISSMRST_Pos (19UL) -#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ -#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< Miss monitor reset */ - -/****************** Bit definition for ICACHE_SR register *******************/ -#define ICACHE_SR_BUSYF_Pos (0UL) -#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ -#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< Busy flag */ -#define ICACHE_SR_BSYENDF_Pos (1UL) -#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ -#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< Busy end flag */ -#define ICACHE_SR_ERRF_Pos (2UL) -#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ -#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< Cache error flag */ - -/****************** Bit definition for ICACHE_IER register ******************/ -#define ICACHE_IER_BSYENDIE_Pos (1UL) -#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ -#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ -#define ICACHE_IER_ERRIE_Pos (2UL) -#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ -#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ - -/****************** Bit definition for ICACHE_FCR register ******************/ -#define ICACHE_FCR_CBSYENDF_Pos (1UL) -#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ -#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ -#define ICACHE_FCR_CERRF_Pos (2UL) -#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ -#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ - -/****************** Bit definition for ICACHE_HMONR register ****************/ -#define ICACHE_HMONR_HITMON_Pos (0UL) -#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ -#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< Cache hit monitor register */ - -/****************** Bit definition for ICACHE_MMONR register ****************/ -#define ICACHE_MMONR_MISSMON_Pos (0UL) -#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ -#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< Cache miss monitor register */ - -/****************** Bit definition for ICACHE_CRRx register *****************/ -#define ICACHE_CRRx_BASEADDR_Pos (0UL) -#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ -#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< Base address of region X to remap */ -#define ICACHE_CRRx_RSIZE_Pos (9UL) -#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ -#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< Region X size */ -#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ -#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ -#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ -#define ICACHE_CRRx_REN_Pos (15UL) -#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ -#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< Region X enable */ -#define ICACHE_CRRx_REMAPADDR_Pos (16UL) -#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ -#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< Remap address of Region X to be remapped */ -#define ICACHE_CRRx_MSTSEL_Pos (28UL) -#define ICACHE_CRRx_MSTSEL_Msk (0x1UL << ICACHE_CRRx_MSTSEL_Pos) /*!< 0x10000000 */ -#define ICACHE_CRRx_MSTSEL ICACHE_CRRx_MSTSEL_Msk /*!< Region X AHB cache master selection */ -#define ICACHE_CRRx_HBURST_Pos (31UL) -#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ -#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< Region X output burst type */ - -/******************************************************************************/ -/* */ -/* Independent WATCHDOG */ -/* */ -/******************************************************************************/ -/******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY_Pos (0UL) -#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ -#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! */ - -/******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0UL) -#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ -#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk -#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ -#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ -#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ -#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4UL) -#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ -#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk -#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ -#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ -#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7UL) -#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ -#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8UL) -#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ -#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk -#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ -#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ -#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ -#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12UL) -#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ -#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk -#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ -#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ -#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15UL) -#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ -#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16UL) -#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ -#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk -#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ -#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ -#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ -#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20UL) -#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ -#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk -#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ -#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22UL) -#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ -#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23UL) -#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ -#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24UL) -#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ -#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk -#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ -#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ -#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ -#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28UL) -#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ -#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk -#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ -#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30UL) -#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ -#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31UL) -#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ -#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk - -/******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0UL) -#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ -#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24UL) -#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ -#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk -#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ -#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ -#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ -#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ -#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31UL) -#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ -#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk - -/******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0UL) -#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ -#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk -#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ -#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ -#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ -#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4UL) -#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ -#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk -#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ -#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ -#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7UL) -#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ -#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8UL) -#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ -#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk -#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ -#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ -#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ -#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12UL) -#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ -#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk -#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ -#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ -#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15UL) -#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ -#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16UL) -#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ -#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk -#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ -#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ -#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ -#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20UL) -#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ -#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk -#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ -#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22UL) -#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ -#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23UL) -#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ -#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24UL) -#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ -#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk -#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ -#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ -#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ -#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28UL) -#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ -#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk -#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ -#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30UL) -#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ -#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31UL) -#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ -#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk - -/******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0UL) -#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ -#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24UL) -#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ -#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk -#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ -#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ -#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ -#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ -#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31UL) -#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ -#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk - -/******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0UL) -#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ -#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1UL) -#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ -#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2UL) -#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ -#define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3UL) -#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ -#define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4UL) -#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ -#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5UL) -#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ -#define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6UL) -#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ -#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk - -/******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0UL) -#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ -#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1UL) -#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ -#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2UL) -#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ -#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3UL) -#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ -#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4UL) -#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ -#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5UL) -#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ -#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6UL) -#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ -#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk - -/******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0UL) -#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ -#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1UL) -#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ -#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2UL) -#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ -#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3UL) -#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ -#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4UL) -#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ -#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5UL) -#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ -#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6UL) -#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ -#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk - -/******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0UL) -#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ -#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1UL) -#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ -#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2UL) -#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ -#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3UL) -#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ -#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4UL) -#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ -#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5UL) -#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ -#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6UL) -#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ -#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk - -/******************** Bits definition for RTC_TAMPTSCR register ******************/ -#define RTC_TAMPTSCR_TAMP1TS_Pos (0UL) -#define RTC_TAMPTSCR_TAMP1TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP1TS_Pos) /*!< 0x00000001 */ -#define RTC_TAMPTSCR_TAMP1TS RTC_TAMPTSCR_TAMP1TS_Msk -#define RTC_TAMPTSCR_TAMP2TS_Pos (1UL) -#define RTC_TAMPTSCR_TAMP2TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP2TS_Pos) /*!< 0x00000002 */ -#define RTC_TAMPTSCR_TAMP2TS RTC_TAMPTSCR_TAMP2TS_Msk -#define RTC_TAMPTSCR_TAMP3TS_Pos (2UL) -#define RTC_TAMPTSCR_TAMP3TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP3TS_Pos) /*!< 0x00000004 */ -#define RTC_TAMPTSCR_TAMP3TS RTC_TAMPTSCR_TAMP3TS_Msk -#define RTC_TAMPTSCR_TAMP4TS_Pos (3UL) -#define RTC_TAMPTSCR_TAMP4TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP4TS_Pos) /*!< 0x00000008 */ -#define RTC_TAMPTSCR_TAMP4TS RTC_TAMPTSCR_TAMP4TS_Msk -#define RTC_TAMPTSCR_TAMP5TS_Pos (4UL) -#define RTC_TAMPTSCR_TAMP5TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP5TS_Pos) /*!< 0x00000010 */ -#define RTC_TAMPTSCR_TAMP5TS RTC_TAMPTSCR_TAMP5TS_Msk -#define RTC_TAMPTSCR_ITAMPTS_Pos (16UL) -#define RTC_TAMPTSCR_ITAMPTS_Msk (0x1UL << RTC_TAMPTSCR_ITAMPTS_Pos) /*!< 0x00010000 */ -#define RTC_TAMPTSCR_ITAMPTS RTC_TAMPTSCR_ITAMPTS_Msk - -/******************** Bits definition for RTC_TSIDR register ******************/ -#define RTC_TSIDR_TSID_Pos (0UL) -#define RTC_TSIDR_TSID_Msk (0x3FUL << RTC_TSIDR_TSID_Pos) /*!< 0x0000003F */ -#define RTC_TSIDR_TSID RTC_TSIDR_TSID_Msk -#define RTC_TSIDR_TSID_0 (0x1UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000001 */ -#define RTC_TSIDR_TSID_1 (0x2UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000002 */ -#define RTC_TSIDR_TSID_2 (0x4UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000004 */ -#define RTC_TSIDR_TSID_3 (0x8UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000008 */ -#define RTC_TSIDR_TSID_4 (0x10UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000010 */ -#define RTC_TSIDR_TSID_5 (0x20UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000020 */ - -/******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0UL) -#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ -#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk - -/******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0UL) -#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ -#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk - -/******************************************************************************/ -/* */ -/* Serial Audio Interface */ -/* */ -/******************************************************************************/ -/******************* Bit definition for SAI_xCR1 register *******************/ -#define SAI_xCR1_MODE_Pos (0UL) -#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ -#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!>2) /*!< Input modulus number of bits */ -#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ - -/* Compute Montgomery parameter output data */ -#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ - -/* Compute modular exponentiation input data */ -#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ -#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ -#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ -#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ -#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ -#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ -#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ -#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ -#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ - -/* Compute modular exponentiation output data */ -#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ -#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ -#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ -#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ - -/* Compute ECC scalar multiplication input data */ -#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ -#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ -#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ -#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ -#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ -#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ - -/* Compute ECC scalar multiplication output data */ -#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ -#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ -#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ - -/* Point check input data */ -#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ -#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ -#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ -#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ - -/* Point check output data */ -#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ - -/* ECDSA signature input data */ -#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ -#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ -#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ -#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ -#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ -#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ -#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ -#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ - -/* ECDSA signature output data */ -#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ -#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ -#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ -#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ -#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ - -/* ECDSA verification input data */ -#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ -#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ -#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ -#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ -#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ -#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ -#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ -#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ -#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ - -/* ECDSA verification output data */ -#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* RSA CRT exponentiation input data */ -#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ -#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ -#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ -#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ -#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ -#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ -#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ - -/* RSA CRT exponentiation output data */ -#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Modular reduction input data */ -#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ -#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ -#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ -#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ - -/* Modular reduction output data */ -#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Arithmetic addition input data */ -#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ - -/* Arithmetic addition output data */ -#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Arithmetic subtraction input data */ -#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ - -/* Arithmetic subtraction output data */ -#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Arithmetic multiplication input data */ -#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ - -/* Arithmetic multiplication output data */ -#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Comparison input data */ -#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ - -/* Comparison output data */ -#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Modular addition input data */ -#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ - -/* Modular addition output data */ -#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Modular inversion input data */ -#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ - -/* Modular inversion output data */ -#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Modular subtraction input data */ -#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ - -/* Modular subtraction output data */ -#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Montgomery multiplication input data */ -#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ - -/* Montgomery multiplication output data */ -#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Generic Arithmetic input data */ -#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ - -/* Generic Arithmetic output data */ -#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ - -/* Compute ECC complete addition input data */ -#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ -#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ -#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ - -/* Compute ECC complete addition output data */ -#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ -#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ -#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ - -/* Compute ECC double base ladder input data */ -#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ -#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ -#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ -#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ -#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ - -/* Compute ECC double base ladder output data */ -#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ -#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ -#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ - -/* Compute ECC projective to affine conversion input data */ -#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ -#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ -#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ -#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ -#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ - -/* Compute ECC projective to affine conversion output data */ -#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ -#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ -#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ - - -/******************************************************************************/ -/* */ -/* VREFBUF */ -/* */ -/******************************************************************************/ -/******************* Bit definition for VREFBUF_CSR register ****************/ -#define VREFBUF_CSR_ENVR_Pos (0UL) -#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ -#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - -/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ -#define __CM33_REV 0x0000U /* Core revision r0p4 */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __DSP_PRESENT 1U /* DSP extension present */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ -#include "system_stm32u3xx.h" /*!< STM32U3xx System */ - - -/* ================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================================================== */ -/** @addtogroup STM32U3xx_peripherals - * @{ - */ - -/** - * @brief ADC Analog to Digital Converter - */ -typedef struct -{ - __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ - __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ - __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ - __IO uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x1C */ - uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x20 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ - uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x44 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ - __IO uint32_t OFCFGR1; /*!< ADC offset configuration register 1, Address offset: 0x50 */ - __IO uint32_t OFCFGR2; /*!< ADC offset configuration register 2, Address offset: 0x54 */ - __IO uint32_t OFCFGR3; /*!< ADC offset configuration register 3, Address offset: 0x58 */ - __IO uint32_t OFCFGR4; /*!< ADC offset configuration register 4, Address offset: 0x5C */ - __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ - __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ - __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ - __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ - __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ - uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x74 */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ - uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x90 */ - __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ - __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ - __IO uint32_t AWD1LTR; /*!< ADC analog watchdog 1 low threshold register, Address offset: 0xA8 */ - __IO uint32_t AWD1HTR; /*!< ADC analog watchdog 1 high threshold register, Address offset: 0xAC */ - __IO uint32_t AWD2LTR; /*!< ADC analog watchdog 2 low threshold register, Address offset: 0xB0 */ - __IO uint32_t AWD2HTR; /*!< ADC analog watchdog 2 high threshold register, Address offset: 0xB4 */ - __IO uint32_t AWD3LTR; /*!< ADC analog watchdog 3 low threshold register, Address offset: 0xB8 */ - __IO uint32_t AWD3HTR; /*!< ADC analog watchdog 3 high threshold register, Address offset: 0xBC */ - uint32_t RESERVED5; /*!< Reserved, Address offset: 0xC0 */ - __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xC4 */ - uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0xC8 */ - __IO uint32_t OR; /*!< ADC option register, Address offset: 0xD0 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for dual mode 32-bit, Address offset: 0x310 */ -} ADC_Common_TypeDef; - -/** - * @brief AES hardware accelerator - */ -typedef struct -{ - __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ - __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ - __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ - __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ - __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ - __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ - __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ - __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ - __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ - __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ - __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ - __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ - __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ - __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ - __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ - __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ - __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ - __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ - __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ - __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ - __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ - __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ - __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ - uint32_t RESERVED1[168]; /*!< Reserved, 0x60 -- 0x2FC */ - __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ - __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ - __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ -} AES_TypeDef; - -/** - * @brief Coupling and chaining bridge (CCB) - */ -typedef struct -{ - __IO uint32_t CR; /*!< CCB ccontrol register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< CCB status register, Address offset: 0x04 */ - uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08 */ - __IO uint32_t REFTAGR[4]; /*!< CCB reference tag register, Address offset: 0x10 */ -} CCB_TypeDef; - -/** - * @brief Comparator - */ -typedef struct -{ - __IO uint32_t CSR; /*!< Comparator control/status register , Address offset: 0x00 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ - __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ -} COMP_Common_TypeDef; - -/** - * @brief CRC calculation unit - */ -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief DAC - */ -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ - __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ - __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ - __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ - __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ - __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ - __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ - __IO uint32_t RESERVED[1]; - __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1LFZR; /*!< Debug MCU APB1L freeze register, Address offset: 0x08 */ - __IO uint32_t APB1HFZR; /*!< Debug MCU APB1H freeze register, Address offset: 0x0C */ - __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ - __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x20 */ - __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ - uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xFC */ - __IO uint32_t SR; /*!< Debug MCU status register, Address offset: 0xFC */ - __IO uint32_t DGB_AUTH_HOST; /*!< Debug MCU debug host authentication register, Address offset: 0x100 */ - __IO uint32_t DGB_AUTH_DEVICE; /*!< Debug MCU debug device authentication register, Address offset: 0x104 */ - uint32_t RESERVED3[946]; /*!< Reserved, 0x108 - 0xFD0 */ - __IO uint32_t PIDR4; /*!< Debug MCU CoreSight peripheral identity register 4, Address offset: 0xFD0 */ - __IO uint32_t PIDR0; /*!< Debug MCU CoreSight peripheral identity register 0, Address offset: 0xFE0 */ - __IO uint32_t PIDR1; /*!< Debug MCU CoreSight peripheral identity register 1, Address offset: 0xFE4 */ - __IO uint32_t PIDR2; /*!< Debug MCU CoreSight peripheral identity register 2, Address offset: 0xFE8 */ - __IO uint32_t PIDR3; /*!< Debug MCU CoreSight peripheral identity register 3, Address offset: 0xFEC */ - __IO uint32_t CIDR0; /*!< Debug MCU CoreSight component identity register 0, Address offset: 0xFF0 */ - __IO uint32_t CIDR1; /*!< Debug MCU CoreSight component identity register 1, Address offset: 0xFF4 */ - __IO uint32_t CIDR2; /*!< Debug MCU CoreSight component identity register 2, Address offset: 0xFF8 */ - __IO uint32_t CIDR3; /*!< Debug MCU CoreSight component identity register 3, Address offset: 0xFFC */ -} DBGMCU_TypeDef; - -/** - * @ brief Delay Block - */ -typedef struct -{ - __IO uint32_t CR; /*!< Delay Block Control Register, Address offset: 0x00 */ - __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */ -} DLYB_TypeDef; - -/** - * @brief DMA Controller - */ -typedef struct -{ - __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ - __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ - __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ - __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ - __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ - uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ - __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ - __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ - __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ - uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ - __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ - __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ - __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ - __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ - __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ - __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ - __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ - uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ - __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ -} DMA_Channel_TypeDef; - -/** - * @brief Asynch Interrupt/Event Controller (EXTI) - */ -typedef struct -{ - __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ - __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ - __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ - __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ - __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ - __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ - __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ - uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ - __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ - __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ - uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ - __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ - __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ -} EXTI_TypeDef; - -/** - * @brief FD Controller Area Network - */ -typedef struct -{ - __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ - __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ - uint32_t RESERVED1; /*!< Reserved, 0x008 */ - __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ - __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ - __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ - __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ - __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ - __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ - __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ - __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ - __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ - uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ - __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ - __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ - __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ - uint32_t RESERVED3; /*!< Reserved, 0x04C */ - __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ - __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ - __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ - __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ - uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ - __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ - __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ - __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ - uint32_t RESERVED5; /*!< Reserved, 0x08C */ - __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ - __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ - __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ - __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ - uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ - __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ - __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ - __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ - __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ - __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ - __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ - __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ - __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ - __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ - __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ - __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ -} FDCAN_GlobalTypeDef; - -/** - * @brief FD Controller Area Network Configuration - */ -typedef struct -{ - __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ - uint32_t RESERVED1[128]; /*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ - __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ - uint32_t RESERVED2[58]; /*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ - __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ - __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ - __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ - __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ -} FDCAN_Config_TypeDef; - -/** - * @brief FLASH Registers - */ -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x04 */ - __IO uint32_t KEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ - __IO uint32_t SKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x14 */ - __IO uint32_t PDKEY1R; /*!< FLASH bank 1 power-down key register, Address offset: 0x18 */ - __IO uint32_t PDKEY2R; /*!< FLASH bank 2 power-down key register, Address offset: 0x1C */ - __IO uint32_t SR; /*!< FLASH non-secure status register, Address offset: 0x20 */ - __IO uint32_t SSR; /*!< FLASH secure status register, Address offset: 0x24 */ - __IO uint32_t CR; /*!< FLASH non-secure control register, Address offset: 0x28 */ - __IO uint32_t SCR; /*!< FLASH secure control register, Address offset: 0x2C */ - __IO uint32_t ECCCR; /*!< FLASH ECC correction register, Address offset: 0x30 */ - __IO uint32_t ECCDR; /*!< FLASH ECC detection register, Address offset: 0x34 */ - __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x38 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x3C */ - __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ - __IO uint32_t BOOT0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ - __IO uint32_t BOOT1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ - __IO uint32_t SBOOT0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ - __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ - __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ - __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ - __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ - __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ - __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ - __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ - __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ - uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x70-0x7C */ - __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ - __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ - __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ - __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ - uint32_t RESERVED5[4]; /*!< Reserved, Address offset: 0x90-0x9C */ - __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ - __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ - __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ - __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ - uint32_t RESERVED6[4]; /*!< Reserved, Address offset: 0xB0-0xBC */ - __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ - __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ - __IO uint32_t SECHDPEXTR; /*!< FLASH HDP extension register, Address offset: 0xC8 */ - uint32_t RESERVED7; /*!< Reserved, Address offset: 0xCC */ - __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ - __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ - __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ - __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ - uint32_t RESERVED8[4]; /*!< Reserved, Address offset: 0xE0-0xEC */ - __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ - __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ - __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ - __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ - uint32_t RESERVED9[4]; /*!< Reserved, Address offset: 0x100-0x10C */ - __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x110 */ - __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x114 */ - __IO uint32_t OEM1KEYR3; /*!< FLASH OEM1 key register 3, Address offset: 0x118 */ - __IO uint32_t OEM1KEYR4; /*!< FLASH OEM1 key register 4, Address offset: 0x11C */ - __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x120 */ - __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x124 */ - __IO uint32_t OEM2KEYR3; /*!< FLASH OEM2 key register 3, Address offset: 0x128 */ - __IO uint32_t OEM2KEYR4; /*!< FLASH OEM2 key register 4, Address offset: 0x12C */ - __IO uint32_t OEMKEYSR; /*!< FLASH OEM key status register, Address offset: 0x130 */ -} FLASH_TypeDef; - -/** - * @brief General Purpose I/O - */ -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ - __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ -} GPIO_TypeDef; - -typedef struct -{ - __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ - __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ - __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ - __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ - __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ - __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ - __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ - __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ - __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ - __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ - __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ - __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ -} GTZC_TZIC_TypeDef; - -typedef struct -{ - __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ - uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ - __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register, Address offset: 0x10 */ - uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ - __IO uint32_t SECCFGR[12]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x12C */ - uint32_t RESERVED3[52]; /*!< Reserved3, Address offset: 0x130-0x200 */ - __IO uint32_t PRIVCFGR[12]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x22C */ -} GTZC_MPCBB_TypeDef; - -/** - * @brief Global TrustZone Controller - */ -typedef struct -{ - __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ - uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ - __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ - __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ - __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ - uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ - __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ - __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ - __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ -} GTZC_TZSC_TypeDef; - -/** - * @brief HASH - */ -typedef struct -{ - __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ - __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ - __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ - __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ - __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ - __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ - __IO uint32_t SHA3CFGR; /*!< HASH SHA-3 configuration register, Address offset: 0x28 */ - uint32_t RESERVED[51]; /*!< Reserved, 0x2C-0xF4 */ - __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ -} HASH_TypeDef; - -/** - * @brief HASH_DIGEST - */ -typedef struct -{ - __IO uint32_t HR[50]; /*!< HASH digest registers, Address offset: 0x310-0x3D4 */ -} HASH_DIGEST_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ - __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ - __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ - __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ - __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ - __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ - __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ - __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ - __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ - __IO uint32_t AUTOCR; /*!< I2C Autonomous mode control register, Address offset: 0x2C */ -} I2C_TypeDef; - -/** - * @brief Improved Inter-integrated Circuit Interface - */ -typedef struct -{ - __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ - __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ - uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ - __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ - __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ - __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ - __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ - __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ - __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ - uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ - __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ - uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ - __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ - uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ - __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ - __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ - __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ - __IO uint32_t MISR; /*!< I3C Masked Interrupt Status register, Address offset: 0x5C */ - __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ - __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ - uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ - __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ - __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ - uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ - __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ - __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ - __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ - uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ - __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ - __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ - __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ - __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ - __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ - __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ -} I3C_TypeDef; - -/** - * @brief Instruction Cache - */ -typedef struct -{ - __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ - __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ - __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ - __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ - __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x018-0x01C */ - __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ - __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ - __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ - __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ -} ICACHE_TypeDef; - -/** - * @brief IWDG - */ -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ - __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ - __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ -} IWDG_TypeDef; - -/** - * @brief LCD - */ -typedef struct -{ - __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ - __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ - __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ - __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ -} LCD_TypeDef; - -/** - * @brief LPTIMER - */ -typedef struct -{ - __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ - __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ - __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ - __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ - __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ - __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ - __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ - __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ - __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ - __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ - __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ -} LPTIM_TypeDef; - -/** - * @brief MDF/ADF - */ -typedef struct -{ - __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ - __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ - uint32_t RESERVED0[6]; /*!< Reserved, 0x08-0x1C */ - __IO uint32_t TRGISELR; /*!< MDF Trigger Input Selection Register, Address offset: 0x20 */ -} MDF_TypeDef; - -/** - * @brief MDF/ADF filter - */ -typedef struct -{ - __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ - __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ - __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ - __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ - __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ - uint32_t RESERVED0[4]; /*!< Reserved, 0x94-0xA0 */ - __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ - uint32_t RESERVED1[1]; /*!< Reserved, 0xA8 */ - __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ - __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ - uint32_t RESERVED2[1]; /*!< Reserved, 0xB4 */ - __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ - __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ - __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ - __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ - uint32_t RESERVED3[10]; /*!< Reserved, 0xC8-0xEC */ - __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ -} MDF_Filter_TypeDef; - -/** - * @brief Operational Amplifier (OPAMP) - */ -typedef struct -{ - __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ - __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ - __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ -} OPAMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to - several OPAMP instances, Address offset: 0x00 */ -} OPAMP_Common_TypeDef; - -/** - * @brief PKA - */ -typedef struct -{ - __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ - __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ - uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ - __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ -} PKA_TypeDef; - -/** - * @brief Power Control - */ -typedef struct -{ - __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ - __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ - __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ - __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ - __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ - __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ - __IO uint32_t BDCR; /*!< Power backup domain control register, Address offset: 0x24 */ - __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x2C */ - __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ - __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ - __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ - __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */ - __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ - __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ - __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ - __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ - __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ - __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ - __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ - __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ - __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ - __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ - __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ - __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ - __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ - __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ - __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ - __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ - __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ - __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ - __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ - uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x90 -> 0xAC */ - __IO uint32_t I3CPUCR1; /*!< Power I3C pull-up control register 1, Address offset: 0xB0 */ - __IO uint32_t I3CPUCR2; /*!< Power I3C pull-up control register 2, Address offset: 0xB4 */ -} PWR_TypeDef; - -/** - * @brief SRAMs configuration controller - */ -typedef struct -{ - __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< Interrupt enable register, Address offset: 0x04 */ - __IO uint32_t ISR; /*!< Interrupt status register, Address offset: 0x08 */ - uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ - __IO uint32_t PEAR; /*!< Parity error address register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< Interrupt clear register, Address offset: 0x14 */ - __IO uint32_t WPR1; /*!< Write protection register 1, Address offset: 0x18 */ - __IO uint32_t WPR2; /*!< Write protection register 2, Address offset: 0x1C */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ - __IO uint32_t PARKEYR; /*!< Parity key register, Address offset: 0x24 */ - __IO uint32_t ERKEYR; /*!< Erase key register, Address offset: 0x28 */ -}RAMCFG_TypeDef; - -/** - * @brief Reset and Clock Control - */ -typedef struct -{ - __IO uint32_t CR; /*!< RCC Clock Control Register Address offset: 0x000 */ - uint32_t RESERVED0; /*!< Reserved Address offset: 0x004 */ - __IO uint32_t ICSCR1; /*!< RCC Internal Clock Sources Calibration Register 1 Address offset: 0x008 */ - __IO uint32_t ICSCR2; /*!< RCC Internal Clock Sources Calibration Register 2 Address offset: 0x00C */ - __IO uint32_t ICSCR3; /*!< RCC Internal Clock Sources Calibration Register 3 Address offset: 0x010 */ - __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x014 */ - uint32_t RESERVED1; /*!< Reserved Address offset: 0x018 */ - __IO uint32_t CFGR1; /*!< RCC Clock Configuration Register 1 Address offset: 0x01C */ - __IO uint32_t CFGR2; /*!< RCC Clock Configuration Register 2 Address offset: 0x020 */ - __IO uint32_t CFGR3; /*!< RCC Clock Configuration Register 3 Address offset: 0x024 */ - __IO uint32_t CFGR4; /*!< RCC Clock Configuration Register 4 Address offset: 0x028 */ - uint32_t RESERVED2[9]; /*!< Reserved Address offset: 0x02C */ - __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x050 */ - __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x054 */ - __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x058 */ - uint32_t RESERVED3; /*!< Reserved Address offset: 0x05C */ - __IO uint32_t AHB1RSTR1; /*!< AHB1 Peripherals Reset Register 1 Address offset: 0x060 */ - __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x064 */ - __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x068 */ - uint32_t RESERVED4[2]; /*!< Reserved Address offset: 0x06C */ - __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x074 */ - __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x078 */ - __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x07C */ - __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x080 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x084 */ - __IO uint32_t AHB1ENR1; /*!< AHB1 Peripherals Clock Enable Register 1 Address offset: 0x088 */ - __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x08C */ - __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x090 */ - __IO uint32_t AHB1ENR2; /*!< AHB1 Peripherals Clock Enable Register 2 Address offset: 0x094 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x098 */ - __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x09C */ - __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0x0A0 */ - __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0x0A4 */ - __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0x0A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x0AC */ - __IO uint32_t AHB1SLPENR1; /*!< AHB1 Peripherals Clock Enable in Sleep Mode Register 1 Address offset: 0x0B0 */ - __IO uint32_t AHB2SLPENR1; /*!< AHB2 Peripherals Clock Enable in Sleep Mode Register 1 Address offset: 0x0B4 */ - __IO uint32_t AHB2SLPENR2; /*!< AHB2 Peripherals Clock Enable in Sleep Mode Register 2 Address offset: 0x0B8 */ - __IO uint32_t AHB1SLPENR2; /*!< AHB1 Peripherals Clock Enable in Sleep Mode Register 2 Address offset: 0x0BC */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x0C0 */ - __IO uint32_t APB1SLPENR1; /*!< APB1 Peripherals Clock Enable in Sleep Mode Register 1 Address offset: 0x0C4 */ - __IO uint32_t APB1SLPENR2; /*!< APB1 Peripherals Clock Enable in Sleep Mode Register 2 Address offset: 0x0C8 */ - __IO uint32_t APB2SLPENR; /*!< APB2 Peripherals Clock Enable in Sleep Mode Register Address offset: 0x0CC */ - __IO uint32_t APB3SLPENR; /*!< APB3 Peripherals Clock Enable in Sleep Mode Register Address offset: 0x0D0 */ - uint32_t RESERVED9; /*!< Reserved Address offset: 0x0D4 */ - __IO uint32_t AHB1STPENR1; /*!< AHB1 Peripherals Clock Enable in Stop Mode Register 1 Address offset: 0x0D8 */ - __IO uint32_t AHB2STPENR1; /*!< AHB2 Peripherals Clock Enable in Stop Mode Register 1 Address offset: 0x0DC */ - uint32_t RESERVED10[3]; /*!< Reserved Address offset: 0x0E0 */ - __IO uint32_t APB1STPENR1; /*!< APB1 Peripherals Clock Enable in Stop Mode Register 1 Address offset: 0x0EC */ - __IO uint32_t APB1STPENR2; /*!< APB1 Peripherals Clock Enable in Stop Mode Register 2 Address offset: 0x0F0 */ - __IO uint32_t APB2STPENR; /*!< APB2 Peripherals Clock Enable in Stop Mode Register Address offset: 0x0F4 */ - __IO uint32_t APB3STPENR; /*!< APB3 Peripherals Clock Enable in Stop Mode Register Address offset: 0x0F8 */ - uint32_t RESERVED11; /*!< Reserved Address offset: 0x0FC */ - __IO uint32_t CCIPR1; /*!< Peripherals Independent Clocks Configuration Register 1 Address offset: 0x100 */ - __IO uint32_t CCIPR2; /*!< Peripherals Independent Clocks Configuration Register 2 Address offset: 0x104 */ - __IO uint32_t CCIPR3; /*!< Peripherals Independent Clocks Configuration Register 3 Address offset: 0x108 */ - uint32_t RESERVED12; /*!< Reserved Address offset: 0x10C */ - __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0x110 */ - __IO uint32_t CSR; /*!< Control & Status Register Address offset: 0x114 */ - uint32_t RESERVED13[6]; /*!< Reserved Address offset: 0x118 */ - __IO uint32_t SECCFGR; /*!< RCC Secure Configuration Register Address offset: 0x130 */ - __IO uint32_t PRIVCFGR; /*!< RCC Privilege Configuration Register Address offset: 0x134 */ -} RCC_TypeDef; - -/** - * @brief RNG - */ -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ -} RNG_TypeDef; - -/** - * @brief Real-Time Clock - */ -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ - __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x60 */ - __IO uint32_t TAMPTSCR; /*!< RTC timestamp on tamper control register, Address offset: 0x64 */ - __IO uint32_t TSIDR; /*!< RTC timestamp status register, Address offset: 0x68 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x6C */ - __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ - __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ -} RTC_TypeDef; - -/** - * @brief Serial Audio Interface - */ -typedef struct -{ - uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ - __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ - __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ -} SAI_TypeDef; - -typedef struct -{ - __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ - __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ - __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ - __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ - __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ - __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ -} SAI_Block_TypeDef; - -/** - * @brief Secure digital input/output Interface - */ -typedef struct -{ - __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ - __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ - uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ - __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ - __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ - __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ - __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ - __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ - uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ -} SDMMC_TypeDef; - -/** - * @brief SPI - */ -typedef struct -{ - __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ - __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ - __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ - __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ - __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ - __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ - __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ - __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ - uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ - __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ - uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ - __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ - __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ - __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ - __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ -} SPI_TypeDef; - -/** - * @brief System configuration controller - */ -typedef struct -{ - __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ - __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ - __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ - __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ - __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ - __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ - __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ - uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x28 */ - __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ -} SYSCFG_TypeDef; - -/** - * @brief Tamper and backup registers - */ -typedef struct -{ - __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ - __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - uint32_t RESERVED1[4]; /*!< Reserved, 0x10 -- 0x1C */ - __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ - __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ - uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ - __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ - __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ - __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ - __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ - __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ - __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ - uint32_t RESERVED2[4]; /*!< Reserved, 0x44 -- 0x50 */ - __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ - uint32_t RESERVED3[42]; /*!< Reserved, 0x58 -- 0xFC */ - __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ - __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ - __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ - __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ - __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ - __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ - __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ - __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ - __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ - __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ - __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ - __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ - __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ - __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ - __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ - __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ - __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ - __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ - __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ - __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ - __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ - __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ - __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ - __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ - __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ - __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ - __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ - __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ - __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ - __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ - __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ - __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ -} TAMP_TypeDef; - -/** - * @brief Touch Sensing Controller (TSC) - */ -typedef struct -{ - __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ - __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ - __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ - __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ - __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ - __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ - __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ - __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, 0x34-0x4C */ -} TSC_TypeDef; - -/** - * @brief TIM - */ -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ - __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ - __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ - __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ - __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ - __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ - __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ - __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ - __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ - uint32_t RESERVED0[220]; /*!< Reserved, Address offset: 0x6C */ - __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ - __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ -typedef struct -{ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ - __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ - __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ - __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ -} USART_TypeDef; - -/** - * @brief Universal Serial Bus Full Speed Dual Role Device - */ -typedef struct -{ - __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ - __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ - __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ - __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ - __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ - __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ - __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ - __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ - __IO uint32_t RESERVED0[8]; /*!< Reserved, */ - __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ - __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ - __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ - __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ - __IO uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ - __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ -} USB_DRD_TypeDef; - -/** - * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table - */ -typedef struct -{ - __IO uint32_t TXBD; /*!= 6010050) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* ================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* ================================================================================================================== */ -/** @addtogroup STM32U3xx_Peripheral_peripheralAddr - * @{ - */ - -/*!< Flash, Peripheral and internal SRAMs base addresses - Non secure */ -#define FLASH_BASE_NS 0x08000000UL /*!< FLASH non-secure base address */ -#define SYSTEM_FLASH_BASE_NS 0x0BF80000UL /*!< System FLASH non-secure base address */ -#define SRAM1_BASE_NS 0x20000000UL /*!< SRAM1 non-secure base address */ -#define SRAM2_BASE_NS 0x20018000UL /*!< SRAM2 non-secure base address */ -#define SRAM3_BASE_NS 0x20028000UL /*!< SRAM3 non-secure base address */ -#define SRAM4_BASE_NS 0x20068000UL /*!< SRAM4 non-secure base address */ - -#define PERIPH_BASE_NS 0x40000000UL /*!< Peripheral non-secure base address */ -#define EXTRAM_BASE_NS 0x90000000UL /*!< External RAM base address */ -#define EPPB_BASE 0xE0040000UL /*!< External Private Peripheral Bus */ - -/*!< OTP, Engineering bytes, Option bytes defines */ -#define FLASH_OTP_BASE (SYSTEM_FLASH_BASE_NS + 0x00020000UL) /*!< FLASH OTP (one-time programmable) base address */ -#define FLASH_OTP_SIZE 0x00000200U /*!< 512 bytes OTP (one-time programmable) */ -#define FLASH_ENGY_BASE (SYSTEM_FLASH_BASE_NS + 0x00020500UL) -#define PACKAGE_BASE (FLASH_ENGY_BASE) /*!< Package data register base address */ -#define UID_BASE (FLASH_ENGY_BASE + 0x00000200UL) /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE (FLASH_ENGY_BASE + 0x000002A0UL) /*!< Flash size data register base address */ -#define UID64_BASE (FLASH_ENGY_BASE + 0x00000500UL) /*!< 64-bit Unique device Identification */ - -/*!< Memory sizes */ -/* Internal Flash size */ -#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x180000U : \ - ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x180000U : \ - (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) - -/*!< Internal SRAMs size */ -#define SRAM1_SIZE 0x00018000UL /*!< SRAM1=96k */ -#define SRAM2_SIZE 0x00010000UL /*!< SRAM2=64k */ -#define SRAM3_SIZE 0x00040000UL /*!< SRAM3=256k */ -#define SRAM4_SIZE 0x00010000UL /*!< SRAM4=64k */ - -/*!< Peripheral memory map - Non secure */ -#define APB1PERIPH_BASE_NS PERIPH_BASE_NS -#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) -#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) -#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00040000UL) -#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) - -/*!< APB1 Non secure peripherals */ -#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x00000000UL) -#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x00000400UL) -#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x00000800UL) -#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x00001000UL) -#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x00001400UL) -#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x00002000UL) -#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x00002C00UL) -#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x00003000UL) -#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x00003800UL) -#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x00004400UL) -#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x00004800UL) -#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x00004C00UL) -#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x00005000UL) -#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x00005400UL) -#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x00005800UL) -#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x00005C00UL) -#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x00006000UL) -#define OPAMP1_BASE_NS (APB1PERIPH_BASE_NS + 0x00007000UL) -#define OPAMP2_BASE_NS (OPAMP1_BASE_NS + 0x0000010UL) -#define VREFBUF_BASE_NS (APB1PERIPH_BASE_NS + 0x00007400UL) -#define RTC_BASE_NS (APB1PERIPH_BASE_NS + 0x00007800UL) -#define TAMP_BASE_NS (APB1PERIPH_BASE_NS + 0x00007C00UL) -#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x00009400UL) -#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0x0000A400UL) -#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0x0000A500UL) -#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0x0000AC00UL) - -/*!< APB2 Non secure peripherals */ -#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x00002C00UL) -#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x00003000UL) -#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x00003400UL) -#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x00003800UL) -#define TIM12_BASE_NS (APB2PERIPH_BASE_NS + 0x00003C00UL) -#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x00004000UL) -#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x00004400UL) -#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x00004800UL) -#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x00005400UL) -#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x0000004UL) -#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x0000024UL) -#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x00006000UL) -#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x00006400UL) -#define I3C2_BASE_NS (APB2PERIPH_BASE_NS + 0x00006C00UL) - -/*!< AHB1 Non secure peripherals */ -#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) -#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x00000050UL) -#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x000000D0UL) -#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x00000150UL) -#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x000001D0UL) -#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x00000250UL) -#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x000002D0UL) -#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x00000350UL) -#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x000003D0UL) -#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x00000450UL) -#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x000004D0UL) -#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x00000550UL) -#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x000005D0UL) -#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x00002000UL) -#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x00003000UL) -#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x00004000UL) -#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x00006000UL) -#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) -#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x00000040UL) -#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x00000080UL) -#define HSP1_BASE_NS (AHB1PERIPH_BASE_NS + 0x0000C000UL) -#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x00010400UL) -#define PWR_BASE_NS (AHB1PERIPH_BASE_NS + 0x00010800UL) -#define RCC_BASE_NS (AHB1PERIPH_BASE_NS + 0x00010C00UL) -#define EXTI_BASE_NS (AHB1PERIPH_BASE_NS + 0x00012000UL) -#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x00012400UL) -#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x00012C00UL) -#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x00013000UL) -#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x00013400UL) -#define GTZC_MPCBB4_BASE_NS (AHB1PERIPH_BASE_NS + 0x00013800UL) -#define ADF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x00014000UL) -#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x00000080UL) - -/*!< APB3 Non secure peripherals */ -#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x00000400UL) -#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x00002400UL) -#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x00002800UL) -#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x00004400UL) -#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x00004800UL) -#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x00004C00UL) -#define COMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x00005400UL) -#define COMP2_BASE_NS (COMP1_BASE_NS + 0x00000004UL) -#define LCD_BASE_NS (APB3PERIPH_BASE_NS + 0x00008000UL) - -/*!< AHB2 Non secure peripherals */ -#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000000UL) -#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000400UL) -#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000800UL) -#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000C00UL) -#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001000UL) -#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001400UL) -#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001800UL) -#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x00001C00UL) -#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008000UL) -#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008100UL) -#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008300UL) -#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x00008400UL) -#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0000UL) -#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0400UL) -#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0710UL) -#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0800UL) -#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A0C00UL) -#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A2000UL) -#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A2400UL) -#define CCB_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A7C00UL) -#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A8000UL) -#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000A8400UL) -#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0x000AF000UL) -#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0x000B1400UL) - -#if defined(CPU_IN_SECURE_STATE) -/*!< Flash, Peripheral and internal SRAMs base addresses - secure */ -#define FLASH_BASE_S 0x0C000000UL /*!< FLASH secure base address */ -#define SYSTEM_FLASH_BASE_S 0x0FF80000UL /*!< System FLASH secure base address */ -#define SRAM1_BASE_S 0x30000000UL /*!< SRAM1 secure base address */ -#define SRAM2_BASE_S 0x30018000UL /*!< SRAM2 secure base address */ -#define SRAM3_BASE_S 0x30028000UL /*!< SRAM3 secure base address */ -#define SRAM4_BASE_S 0x30068000UL /*!< SRAM4 secure base address */ -#define PERIPH_BASE_S 0x50000000UL /*!< Peripheral secure base address */ - -/*!< Peripheral memory map - secure */ -#define APB1PERIPH_BASE_S PERIPH_BASE_S -#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) -#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) -#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x00040000UL) -#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) - -/*!< APB1 secure peripherals */ -#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x00000000UL) -#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x00000400UL) -#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x00000800UL) -#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x00001000UL) -#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x00001400UL) -#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x00002000UL) -#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x00002C00UL) -#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x00003000UL) -#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x00003800UL) -#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x00004400UL) -#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x00004800UL) -#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x00004C00UL) -#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x00005000UL) -#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x00005400UL) -#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x00005800UL) -#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x00005C00UL) -#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x00006000UL) -#define OPAMP1_BASE_S (APB1PERIPH_BASE_S + 0x00007000UL) -#define OPAMP2_BASE_S (OPAMP1_BASE_S + 0x0000010UL) -#define VREFBUF_BASE_S (APB1PERIPH_BASE_S + 0x00007400UL) -#define RTC_BASE_S (APB1PERIPH_BASE_S + 0x00007800UL) -#define TAMP_BASE_S (APB1PERIPH_BASE_S + 0x00007C00UL) -#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x00009400UL) -#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0x0000A400UL) -#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0x0000A500UL) -#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0x0000AC00UL) - -/*!< APB2 secure peripherals */ -#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x00002C00UL) -#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x00003000UL) -#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x00003400UL) -#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x00003800UL) -#define TIM12_BASE_S (APB2PERIPH_BASE_S + 0x00003C00UL) -#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x00004000UL) -#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x00004400UL) -#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x00004800UL) -#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x00005400UL) -#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x0000004UL) -#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x0000024UL) -#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x00006000UL) -#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x00006400UL) -#define I3C2_BASE_S (APB2PERIPH_BASE_S + 0x00006C00UL) - -/*!< AHB1 secure peripherals */ -#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) -#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x00000050UL) -#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x000000D0UL) -#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x00000150UL) -#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x000001D0UL) -#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x00000250UL) -#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x000002D0UL) -#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x00000350UL) -#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x000003D0UL) -#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x00000450UL) -#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x000004D0UL) -#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x00000550UL) -#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x000005D0UL) -#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x00002000UL) -#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x00003000UL) -#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x00004000UL) -#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x00006000UL) -#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) -#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x00000040UL) -#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x00000080UL) -#define HSP1_BASE_S (AHB1PERIPH_BASE_S + 0x0000C000UL) -#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x00010400UL) -#define PWR_BASE_S (AHB1PERIPH_BASE_S + 0x00010800UL) -#define RCC_BASE_S (AHB1PERIPH_BASE_S + 0x00010C00UL) -#define EXTI_BASE_S (AHB1PERIPH_BASE_S + 0x00012000UL) -#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x00012400UL) -#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x00012800UL) -#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x00012C00UL) -#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x00013000UL) -#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x00013400UL) -#define GTZC_MPCBB4_BASE_S (AHB1PERIPH_BASE_S + 0x00013800UL) -#define ADF1_BASE_S (AHB1PERIPH_BASE_S + 0x00014000UL) -#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x00000080UL) - -/*!< APB3 secure peripherals */ -#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x00000400UL) -#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x00002400UL) -#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x00002800UL) -#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x00004400UL) -#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x00004800UL) -#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x00004C00UL) -#define COMP1_BASE_S (APB3PERIPH_BASE_S + 0x00005400UL) -#define COMP2_BASE_S (COMP1_BASE_S + 0x00000004UL) -#define LCD_BASE_S (APB3PERIPH_BASE_S + 0x00008000UL) - -/*!< AHB2 secure peripherals */ -#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000000UL) -#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00000400UL) -#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00000800UL) -#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00000C00UL) -#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x00001000UL) -#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x00001400UL) -#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x00001800UL) -#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x00001C00UL) -#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x00008000UL) -#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x00008100UL) -#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x00008300UL) -#define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x00008400UL) -#define AES_BASE_S (AHB2PERIPH_BASE_S + 0x000A0000UL) -#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0x000A0400UL) -#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0x000A0710UL) -#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0x000A0800UL) -#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0x000A0C00UL) -#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0x000A2000UL) -#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0x000A2400UL) -#define CCB_BASE_S (AHB2PERIPH_BASE_S + 0x000A7C00UL) -#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0x000A8000UL) -#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0x000A8400UL) -#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0x000AF000UL) -#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0x000B1400UL) -#endif /* CPU_IN_SECURE_STATE */ - -/*!< External memories base addresses - Not aliased */ -#define OCTOSPI1_BASE EXTRAM_BASE_NS - -/*!< DBGMCU base addresses - Not aliased */ -#define DBGMCU_BASE (EPPB_BASE + 0x00004000UL) - -/*!< USB PMA SIZE */ -#define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */ - -/*!< Root Secure Service Library */ -/************ RSSLIB SAU system Flash region definition constants *************/ -#define RSSLIB_SYS_FLASH_NS_PFUNC_START 0x0BF99040UL -#define RSSLIB_SYS_FLASH_NS_PFUNC_END 0x0BF990FFUL - -/************ RSSLIB function return constants ********************************/ -#define RSSLIB_ERROR 0xF5F5F5F5UL -#define RSSLIB_SUCCESS 0xEAEAEAEAUL - -/*!< RSSLIB pointer function structure address definition */ -#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START -#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) - -/*!< HDP Area constant definition */ -#define RSSLIB_HDP_AREA_Pos 0UL -#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) -#define RSSLIB_HDP_AREA1_Pos 0UL -#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) -#define RSSLIB_HDP_AREA2_Pos 1UL -#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) -#define RSSLIB_HDPEXT_CLOSE_BOUNDARY_OPEN 0xC9C9C9C9UL /* Access to HDPx extension area and HDPx area denied but HDPx_EXT (in FLASH_HDPEXTR) increment allowed at any time */ -#define RSSLIB_HDPEXT_CLOSE_BOUNDARY_LOCK 0xD6D6D6D6UL /* Access to HDPx extension area and HDPx area denied. Update of HDPx_EXT size is not possible anymore */ - -/** - * @brief Prototype of RSSLIB Close and exit HDP Function - * @detail This function close the requested hdp area passed in input - * parameter and jump to the reset handler present within the - * Vector table. The function does not return on successful execution. - * @param HdpArea notifies which hdp area to close, can be a combination of - * hdpa area 1 and hdp area 2 - * @param VectorTableAddr pointer on the vector table containing the reset handler the function - * jumps to. - * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. - */ -typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); - -/** - * @brief Prototype of RSSLIB Close and exit HDP extension Function - * @detail This function close the requested hdp extension area passed in input - * parameter and jump to the reset handler present within the - * Vector table. The function does not return on successful execution. - * @param HdpExtArea notifies which hdp extension area to close, can be a combination of - * hdp extension area 1 and hdp extension area 2 - * @param VectorTableAddr pointer on the vector table containing the reset handler the function - * jumps to. - * @param CloseBound notifies if the HDP extension area should be closed with - * HDPx_EXT increment allowed or not - * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. - */ -typedef uint32_t ( *RSSLIB_S_CloseExitHDPExt_TypeDef)( uint32_t HdpExtArea, uint32_t VectorTableAddr, uint32_t CloseBound ); - - -/** - * @brief RSSLib non-secure callable function pointer structure - */ -typedef struct -{ - __IM uint32_t Reserved[8]; -}NSC_pFuncTypeDef; - -/** - * @brief RSSLib secure callable function pointer structure - */ -typedef struct -{ - __IM uint32_t Reserved2[2]; - __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ - __IM RSSLIB_S_CloseExitHDPExt_TypeDef CloseExitHDPExt; /*!< RSSLIB Bootloader Close and exit HDP extension Address offset: 0x2C */ -}S_pFuncTypeDef; - -/** - * @brief RSSLib function pointer structure - */ -typedef struct -{ - NSC_pFuncTypeDef NSC; - S_pFuncTypeDef S; -}RSSLIB_pFunc_TypeDef; - -/* - * Certificate address description - */ -#define CERT_CHIP_PACK1_ADDR (0x0BF9FE00U) -#define CERT_CHIP_PACK1_SIZE (0x200U) -#define CERT_CHIP_PACK2_ADDR (0x0BF9FC00U) -#define CERT_CHIP_PACK2_SIZE (0x200U) - -#define CERT_CHIP_PACK_ADDR (CERT_CHIP_PACK2_ADDR) -#define CERT_CHIP_PACK_SIZE (CERT_CHIP_PACK1_SIZE + CERT_CHIP_PACK2_SIZE) - -#define CERT_ST_DUA_USER_FU_PUB_KEY_OFFSET (12U) -#define CERT_ST_DUA_USER_FU_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_PUB_KEY_OFFSET) -#define CERT_ST_DUA_USER_FU_SIGN_OFFSET (76U) -#define CERT_ST_DUA_USER_FU_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_SIGN_OFFSET) -#define CERT_ST_DUA_USER_FU_SERIAL_OFFSET (140U) -#define CERT_ST_DUA_USER_FU_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_SERIAL_OFFSET) - -#define CERT_ST_DUA_USER_LU_PUB_KEY_OFFSET (162U) -#define CERT_ST_DUA_USER_LU_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_PUB_KEY_OFFSET) -#define CERT_ST_DUA_USER_LU_SIGN_OFFSET (226U) -#define CERT_ST_DUA_USER_LU_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_SIGN_OFFSET) -#define CERT_ST_DUA_USER_LU_SERIAL_OFFSET (290U) -#define CERT_ST_DUA_USER_LU_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_SERIAL_OFFSET) -/** @} */ /* End of group STM32U3xx_Peripheral_peripheralAddr */ - - -/* ================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* ================================================================================================================== */ -/** @addtogroup STM32U3xx_Peripheral_declaration - * @{ - */ -#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) -#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) -#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) -#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) -#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) -#define AES_NS ((AES_TypeDef *) AES_BASE_NS) -#define CCB_NS ((CCB_TypeDef *) CCB_BASE_NS) -#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) -#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) -#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) -#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) -#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) -#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) -#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) -#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) -#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) -#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) -#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) -#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) -#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) -#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) -#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) -#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) -#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) -#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) -#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) -#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) -#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) -#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) -#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) -#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) -#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) -#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) -#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) -#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) -#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) -#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) -#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) -#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) -#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) -#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) -#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) -#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) -#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) -#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) -#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) -#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) -#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) -#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) -#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) -#define I3C1_NS ((I3C_TypeDef *) I3C1_BASE_NS) -#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) -#define HSP1_NS ((HSP_TypeDef *) HSP1_BASE_NS) -#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) -#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) -#define LCD_NS ((LCD_TypeDef *) LCD_BASE_NS) -#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) -#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) -#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) -#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) -#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) -#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) -#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) -#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) -#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) -#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) -#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) -#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) -#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) -#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) -#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) -#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) -#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) -#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) -#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) -#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) -#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) -#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) -#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) -#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) -#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) -#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) -#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) -#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) -#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) -#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) -#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) -#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) -#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) -#define TIM12_NS ((TIM_TypeDef *) TIM12_BASE_NS) -#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) -#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) -#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) -#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) -#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) -#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) -#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) -#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) -#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) -#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) -#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) -#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) -#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) -#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) - -/*!< DBGMCU peripheral */ -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -#if defined (CPU_IN_SECURE_STATE) -#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) -#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) -#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) -#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) -#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) -#define AES_S ((AES_TypeDef *) AES_BASE_S) -#define CCB_S ((CCB_TypeDef *) CCB_BASE_S) -#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) -#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) -#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) -#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) -#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) -#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) -#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) -#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) -#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) -#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) -#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) -#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) -#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) -#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) -#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) -#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) -#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) -#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) -#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) -#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) -#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) -#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) -#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) -#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) -#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) -#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) -#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) -#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) -#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) -#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) -#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) -#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) -#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) -#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) -#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) -#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) -#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) -#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) -#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) -#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) -#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) -#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) -#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) -#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) -#define I3C1_S ((I3C_TypeDef *) I3C1_BASE_S) -#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) -#define HSP1_S ((HSP_TypeDef *) HSP1_BASE_S) -#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) -#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) -#define LCD_S ((LCD_TypeDef *) LCD_BASE_S) -#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) -#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) -#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) -#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) -#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) -#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) -#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) -#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) -#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) -#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) -#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) -#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) -#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) -#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) -#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) -#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) -#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) -#define SAES_S ((AES_TypeDef *) SAES_BASE_S) -#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) -#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) -#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) -#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) -#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) -#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) -#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) -#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) -#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) -#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) -#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) -#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) -#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) -#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) -#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) -#define TIM12_S ((TIM_TypeDef *) TIM12_BASE_S) -#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) -#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) -#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) -#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) -#define UART4_S ((USART_TypeDef *) UART4_BASE_S) -#define UART5_S ((USART_TypeDef *) UART5_BASE_S) -#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) -#define USART1_S ((USART_TypeDef *) USART1_BASE_S) -#define USART2_S ((USART_TypeDef *) USART2_BASE_S) -#define USART3_S ((USART_TypeDef *) USART3_BASE_S) -#define USB_DRD_FS_S ((USB_DRD_TypeDef *) USB_DRD_BASE_S) -#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) -#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) -#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) - -/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ -/*!< Memory base addresses for Secure peripherals */ -#define FLASH_BASE FLASH_BASE_S -#define SRAM1_BASE SRAM1_BASE_S -#define SRAM2_BASE SRAM2_BASE_S -#define SRAM3_BASE SRAM3_BASE_S -#define SRAM4_BASE SRAM4_BASE_S - -/*!< Instance aliases and base addresses for Secure peripherals */ -#define ADC12_COMMON ADC12_COMMON_S -#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S -#define ADC1 ADC1_S -#define ADC1_BASE ADC1_BASE_S -#define ADC2 ADC2_S -#define ADC2_BASE ADC2_BASE_S -#define ADF1 ADF1_S -#define ADF1_BASE ADF1_BASE_S -#define ADF1_Filter0 ADF1_Filter0_S -#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S -#define AES AES_S -#define AES_BASE AES_BASE_S -#define CCB CCB_S -#define CCB_BASE CCB_BASE_S -#define COMP1 COMP1_S -#define COMP1_BASE COMP1_BASE_S -#define COMP2 COMP2_S -#define COMP2_BASE COMP2_BASE_S -#define COMP12_COMMON COMP12_COMMON_S -#define COMP12_COMMON_BASE COMP12_BASE_S -#define CRC CRC_S -#define CRC_BASE CRC_BASE_S -#define CRS CRS_S -#define CRS_BASE CRS_BASE_S -#define DAC1 DAC1_S -#define DAC1_BASE DAC1_BASE_S -#define DLYB_SDMMC1 DLYB_SDMMC1_S -#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S -#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S -#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S -#define EXTI EXTI_S -#define EXTI_BASE EXTI_BASE_S -#define FDCAN1 FDCAN1_S -#define FDCAN1_BASE FDCAN1_BASE_S -#define FDCAN_CONFIG FDCAN_CONFIG_S -#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S -#define FLASH FLASH_S -#define FLASH_R_BASE FLASH_R_BASE_S -#define GPDMA1 GPDMA1_S -#define GPDMA1_BASE GPDMA1_BASE_S -#define GPDMA1_Channel0 GPDMA1_Channel0_S -#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S -#define GPDMA1_Channel1 GPDMA1_Channel1_S -#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S -#define GPDMA1_Channel2 GPDMA1_Channel2_S -#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S -#define GPDMA1_Channel3 GPDMA1_Channel3_S -#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S -#define GPDMA1_Channel4 GPDMA1_Channel4_S -#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S -#define GPDMA1_Channel5 GPDMA1_Channel5_S -#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S -#define GPDMA1_Channel6 GPDMA1_Channel6_S -#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S -#define GPDMA1_Channel7 GPDMA1_Channel7_S -#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S -#define GPDMA1_Channel8 GPDMA1_Channel8_S -#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S -#define GPDMA1_Channel9 GPDMA1_Channel9_S -#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S -#define GPDMA1_Channel10 GPDMA1_Channel10_S -#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S -#define GPDMA1_Channel11 GPDMA1_Channel11_S -#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S -#define GPIOA GPIOA_S -#define GPIOA_BASE GPIOA_BASE_S -#define GPIOB GPIOB_S -#define GPIOB_BASE GPIOB_BASE_S -#define GPIOC GPIOC_S -#define GPIOC_BASE GPIOC_BASE_S -#define GPIOD GPIOD_S -#define GPIOD_BASE GPIOD_BASE_S -#define GPIOE GPIOE_S -#define GPIOE_BASE GPIOE_BASE_S -#define GPIOF GPIOF_S -#define GPIOF_BASE GPIOF_BASE_S -#define GPIOG GPIOG_S -#define GPIOG_BASE GPIOG_BASE_S -#define GPIOH GPIOH_S -#define GPIOH_BASE GPIOH_BASE_S -#define GTZC_MPCBB1 GTZC_MPCBB1_S -#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S -#define GTZC_MPCBB2 GTZC_MPCBB2_S -#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S -#define GTZC_MPCBB3 GTZC_MPCBB3_S -#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S -#define GTZC_MPCBB4 GTZC_MPCBB4_S -#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S -#define GTZC_TZSC1 GTZC_TZSC1_S -#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S -#define GTZC_TZIC1 GTZC_TZIC1_S -#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S -#define HASH HASH_S -#define HASH_BASE HASH_BASE_S -#define HASH_DIGEST HASH_DIGEST_S -#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S -#define I2C1 I2C1_S -#define I2C1_BASE I2C1_BASE_S -#define I2C2 I2C2_S -#define I2C2_BASE I2C2_BASE_S -#define I2C3 I2C3_S -#define I2C3_BASE I2C3_BASE_S -#define I3C1 I3C1_S -#define I3C1_BASE I3C1_BASE_S -#define I3C2 I3C2_S -#define I3C2_BASE I3C2_BASE_S -#define HSP1 HSP1_S -#define HSP1_BASE HSP1_BASE_S -#define ICACHE ICACHE_S -#define ICACHE_BASE ICACHE_BASE_S -#define IWDG IWDG_S -#define IWDG_BASE IWDG_BASE_S -#define LCD LCD_S -#define LCD_BASE LCD_BASE_S -#define LPTIM1 LPTIM1_S -#define LPTIM1_BASE LPTIM1_BASE_S -#define LPTIM2 LPTIM2_S -#define LPTIM2_BASE LPTIM2_BASE_S -#define LPTIM3 LPTIM3_S -#define LPTIM3_BASE LPTIM3_BASE_S -#define LPTIM4 LPTIM4_S -#define LPTIM4_BASE LPTIM4_BASE_S -#define LPUART1 LPUART1_S -#define LPUART1_BASE LPUART1_BASE_S -#define OCTOSPI1 OCTOSPI1_S -#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S -#define OPAMP1 OPAMP1_S -#define OPAMP1_BASE OPAMP1_BASE_S -#define OPAMP2 OPAMP2_S -#define OPAMP2_BASE OPAMP2_BASE_S -#define OPAMP12_COMMON OPAMP12_COMMON_S -#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S -#define PKA PKA_S -#define PKA_BASE PKA_BASE_S -#define PKA_RAM_BASE PKA_RAM_BASE_S -#define PWR PWR_S -#define PWR_BASE PWR_BASE_S -#define RAMCFG_SRAM1 RAMCFG_SRAM1_S -#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S -#define RAMCFG_SRAM2 RAMCFG_SRAM2_S -#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S -#define RAMCFG_SRAM3 RAMCFG_SRAM3_S -#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S -#define RCC RCC_S -#define RCC_BASE RCC_BASE_S -#define RNG RNG_S -#define RNG_BASE RNG_BASE_S -#define RTC RTC_S -#define RTC_BASE RTC_BASE_S -#define SAES SAES_S -#define SAES_BASE SAES_BASE_S -#define SAI1 SAI1_S -#define SAI1_BASE SAI1_BASE_S -#define SAI1_Block_A SAI1_Block_A_S -#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S -#define SAI1_Block_B SAI1_Block_B_S -#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S -#define SDMMC1 SDMMC1_S -#define SDMMC1_BASE SDMMC1_BASE_S -#define SPI1 SPI1_S -#define SPI1_BASE SPI1_BASE_S -#define SPI2 SPI2_S -#define SPI2_BASE SPI2_BASE_S -#define SPI3 SPI3_S -#define SPI3_BASE SPI3_BASE_S -#define SRAMCAN_BASE SRAMCAN_BASE_S -#define SYSCFG SYSCFG_S -#define SYSCFG_BASE SYSCFG_BASE_S -#define TAMP TAMP_S -#define TAMP_BASE TAMP_BASE_S -#define TIM1 TIM1_S -#define TIM1_BASE TIM1_BASE_S -#define TIM2 TIM2_S -#define TIM2_BASE TIM2_BASE_S -#define TIM3 TIM3_S -#define TIM3_BASE TIM3_BASE_S -#define TIM4 TIM4_S -#define TIM4_BASE TIM4_BASE_S -#define TIM6 TIM6_S -#define TIM6_BASE TIM6_BASE_S -#define TIM7 TIM7_S -#define TIM7_BASE TIM7_BASE_S -#define TIM12 TIM12_S -#define TIM12_BASE TIM12_BASE_S -#define TIM15 TIM15_S -#define TIM15_BASE TIM15_BASE_S -#define TIM16 TIM16_S -#define TIM16_BASE TIM16_BASE_S -#define TIM17 TIM17_S -#define TIM17_BASE TIM17_BASE_S -#define TSC TSC_S -#define TSC_BASE TSC_BASE_S -#define UART4 UART4_S -#define UART4_BASE UART4_BASE_S -#define UART5 UART5_S -#define UART5_BASE UART5_BASE_S -#define TIM8 TIM8_S -#define TIM8_BASE TIM8_BASE_S -#define USART1 USART1_S -#define USART1_BASE USART1_BASE_S -#define USART2 USART2_S -#define USART2_BASE USART2_BASE_S -#define USART3 USART3_S -#define USART3_BASE USART3_BASE_S -#define USB_DRD_FS USB_DRD_FS_S -#define USB_DRD_BASE USB_DRD_BASE_S -#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S -#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S -#define VREFBUF VREFBUF_S -#define VREFBUF_BASE VREFBUF_BASE_S -#define WWDG WWDG_S -#define WWDG_BASE WWDG_BASE_S - -#else /* CPU_IN_SECURE_STATE */ -/*!< Memory base addresses for Secure peripherals */ -#define FLASH_BASE FLASH_BASE_NS -#define SRAM1_BASE SRAM1_BASE_NS -#define SRAM2_BASE SRAM2_BASE_NS -#define SRAM3_BASE SRAM3_BASE_NS -#define SRAM4_BASE SRAM4_BASE_NS - -/*!< Instance aliases and base addresses for Secure peripherals */ -#define ADC12_COMMON ADC12_COMMON_NS -#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS -#define ADC1 ADC1_NS -#define ADC1_BASE ADC1_BASE_NS -#define ADC2 ADC2_NS -#define ADC2_BASE ADC2_BASE_NS -#define ADF1 ADF1_NS -#define ADF1_BASE ADF1_BASE_NS -#define ADF1_Filter0 ADF1_Filter0_NS -#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS -#define AES AES_NS -#define AES_BASE AES_BASE_NS -#define CCB CCB_NS -#define CCB_BASE CCB_BASE_NS -#define COMP1 COMP1_NS -#define COMP1_BASE COMP1_BASE_NS -#define COMP2 COMP2_NS -#define COMP2_BASE COMP2_BASE_NS -#define COMP12_COMMON COMP12_COMMON_NS -#define COMP12_COMMON_BASE COMP12_BASE_NS -#define CRC CRC_NS -#define CRC_BASE CRC_BASE_NS -#define CRS CRS_NS -#define CRS_BASE CRS_BASE_NS -#define DAC1 DAC1_NS -#define DAC1_BASE DAC1_BASE_NS -#define DLYB_SDMMC1 DLYB_SDMMC1_NS -#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS -#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS -#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS -#define EXTI EXTI_NS -#define EXTI_BASE EXTI_BASE_NS -#define FDCAN1 FDCAN1_NS -#define FDCAN1_BASE FDCAN1_BASE_NS -#define FDCAN_CONFIG FDCAN_CONFIG_NS -#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS -#define FLASH FLASH_NS -#define FLASH_R_BASE FLASH_R_BASE_NS -#define GPDMA1 GPDMA1_NS -#define GPDMA1_BASE GPDMA1_BASE_NS -#define GPDMA1_Channel0 GPDMA1_Channel0_NS -#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS -#define GPDMA1_Channel1 GPDMA1_Channel1_NS -#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS -#define GPDMA1_Channel2 GPDMA1_Channel2_NS -#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS -#define GPDMA1_Channel3 GPDMA1_Channel3_NS -#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS -#define GPDMA1_Channel4 GPDMA1_Channel4_NS -#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS -#define GPDMA1_Channel5 GPDMA1_Channel5_NS -#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS -#define GPDMA1_Channel6 GPDMA1_Channel6_NS -#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS -#define GPDMA1_Channel7 GPDMA1_Channel7_NS -#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS -#define GPDMA1_Channel8 GPDMA1_Channel8_NS -#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS -#define GPDMA1_Channel9 GPDMA1_Channel9_NS -#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS -#define GPDMA1_Channel10 GPDMA1_Channel10_NS -#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS -#define GPDMA1_Channel11 GPDMA1_Channel11_NS -#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS -#define GPIOA GPIOA_NS -#define GPIOA_BASE GPIOA_BASE_NS -#define GPIOB GPIOB_NS -#define GPIOB_BASE GPIOB_BASE_NS -#define GPIOC GPIOC_NS -#define GPIOC_BASE GPIOC_BASE_NS -#define GPIOD GPIOD_NS -#define GPIOD_BASE GPIOD_BASE_NS -#define GPIOE GPIOE_NS -#define GPIOE_BASE GPIOE_BASE_NS -#define GPIOF GPIOF_NS -#define GPIOF_BASE GPIOF_BASE_NS -#define GPIOG GPIOG_NS -#define GPIOG_BASE GPIOG_BASE_NS -#define GPIOH GPIOH_NS -#define GPIOH_BASE GPIOH_BASE_NS -#define GTZC_MPCBB1 GTZC_MPCBB1_NS -#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS -#define GTZC_MPCBB2 GTZC_MPCBB2_NS -#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS -#define GTZC_MPCBB3 GTZC_MPCBB3_NS -#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS -#define GTZC_MPCBB4 GTZC_MPCBB4_NS -#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS -#define GTZC_TZSC1 GTZC_TZSC1_NS -#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS -#define HASH HASH_NS -#define HASH_BASE HASH_BASE_NS -#define HASH_DIGEST HASH_DIGEST_NS -#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS -#define I2C1 I2C1_NS -#define I2C1_BASE I2C1_BASE_NS -#define I2C2 I2C2_NS -#define I2C2_BASE I2C2_BASE_NS -#define I2C3 I2C3_NS -#define I2C3_BASE I2C3_BASE_NS -#define I3C1 I3C1_NS -#define I3C1_BASE I3C1_BASE_NS -#define I3C2 I3C2_NS -#define I3C2_BASE I3C2_BASE_NS -#define HSP1 HSP1_NS -#define HSP1_BASE HSP1_BASE_NS -#define ICACHE ICACHE_NS -#define ICACHE_BASE ICACHE_BASE_NS -#define IWDG IWDG_NS -#define IWDG_BASE IWDG_BASE_NS -#define LCD LCD_NS -#define LCD_BASE LCD_BASE_NS -#define LPTIM1 LPTIM1_NS -#define LPTIM1_BASE LPTIM1_BASE_NS -#define LPTIM2 LPTIM2_NS -#define LPTIM2_BASE LPTIM2_BASE_NS -#define LPTIM3 LPTIM3_NS -#define LPTIM3_BASE LPTIM3_BASE_NS -#define LPTIM4 LPTIM4_NS -#define LPTIM4_BASE LPTIM4_BASE_NS -#define LPUART1 LPUART1_NS -#define LPUART1_BASE LPUART1_BASE_NS -#define OCTOSPI1 OCTOSPI1_NS -#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS -#define OPAMP1 OPAMP1_NS -#define OPAMP1_BASE OPAMP1_BASE_NS -#define OPAMP2 OPAMP2_NS -#define OPAMP2_BASE OPAMP2_BASE_NS -#define OPAMP12_COMMON OPAMP12_COMMON_NS -#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS -#define PKA PKA_NS -#define PKA_BASE PKA_BASE_NS -#define PKA_RAM_BASE PKA_RAM_BASE_NS -#define PWR PWR_NS -#define PWR_BASE PWR_BASE_NS -#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS -#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS -#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS -#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS -#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS -#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS -#define RCC RCC_NS -#define RCC_BASE RCC_BASE_NS -#define RNG RNG_NS -#define RNG_BASE RNG_BASE_NS -#define RTC RTC_NS -#define RTC_BASE RTC_BASE_NS -#define SAES SAES_NS -#define SAES_BASE SAES_BASE_NS -#define SAI1 SAI1_NS -#define SAI1_BASE SAI1_BASE_NS -#define SAI1_Block_A SAI1_Block_A_NS -#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS -#define SAI1_Block_B SAI1_Block_B_NS -#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS -#define SDMMC1 SDMMC1_NS -#define SDMMC1_BASE SDMMC1_BASE_NS -#define SPI1 SPI1_NS -#define SPI1_BASE SPI1_BASE_NS -#define SPI2 SPI2_NS -#define SPI2_BASE SPI2_BASE_NS -#define SPI3 SPI3_NS -#define SPI3_BASE SPI3_BASE_NS -#define SRAMCAN_BASE SRAMCAN_BASE_NS -#define SYSCFG SYSCFG_NS -#define SYSCFG_BASE SYSCFG_BASE_NS -#define TAMP TAMP_NS -#define TAMP_BASE TAMP_BASE_NS -#define TIM1 TIM1_NS -#define TIM1_BASE TIM1_BASE_NS -#define TIM2 TIM2_NS -#define TIM2_BASE TIM2_BASE_NS -#define TIM3 TIM3_NS -#define TIM3_BASE TIM3_BASE_NS -#define TIM4 TIM4_NS -#define TIM4_BASE TIM4_BASE_NS -#define TIM6 TIM6_NS -#define TIM6_BASE TIM6_BASE_NS -#define TIM7 TIM7_NS -#define TIM7_BASE TIM7_BASE_NS -#define TIM12 TIM12_NS -#define TIM12_BASE TIM12_BASE_NS -#define TIM15 TIM15_NS -#define TIM15_BASE TIM15_BASE_NS -#define TIM16 TIM16_NS -#define TIM16_BASE TIM16_BASE_NS -#define TIM17 TIM17_NS -#define TIM17_BASE TIM17_BASE_NS -#define TSC TSC_NS -#define TSC_BASE TSC_BASE_NS -#define UART4 UART4_NS -#define UART4_BASE UART4_BASE_NS -#define UART5 UART5_NS -#define UART5_BASE UART5_BASE_NS -#define TIM8 TIM8_NS -#define TIM8_BASE TIM8_BASE_NS -#define USART1 USART1_NS -#define USART1_BASE USART1_BASE_NS -#define USART2 USART2_NS -#define USART2_BASE USART2_BASE_NS -#define USART3 USART3_NS -#define USART3_BASE USART3_BASE_NS -#define USB_DRD_FS USB_DRD_FS_NS -#define USB_DRD_BASE USB_DRD_BASE_NS -#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS -#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS -#define VREFBUF VREFBUF_NS -#define VREFBUF_BASE VREFBUF_BASE_NS -#define WWDG WWDG_NS -#define WWDG_BASE WWDG_BASE_NS -#endif /* CPU_IN_SECURE_STATE */ - -/** @addtogroup Exported_constants - * @{ - */ - -/** @addtogroup Hardware_Constant_Definition - * @{ - */ -#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ -/** - * @} - */ - -/** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter (ADC) */ -/* */ -/******************************************************************************/ - -/* Specific device feature definitions */ -#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ - -/******************** Bit definition for ADC_ISR register *******************/ -#define ADC_ISR_ADRDY_Pos (0UL) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ -#define ADC_ISR_EOSMP_Pos (1UL) -#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ -#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ -#define ADC_ISR_EOC_Pos (2UL) -#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ -#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ -#define ADC_ISR_EOS_Pos (3UL) -#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ -#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_ISR_OVR_Pos (4UL) -#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ -#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ -#define ADC_ISR_JEOC_Pos (5UL) -#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ -#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ -#define ADC_ISR_JEOS_Pos (6UL) -#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ -#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_ISR_AWD1_Pos (7UL) -#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ -#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8UL) -#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ -#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9UL) -#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ -#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ -#define ADC_ISR_JQOVF_Pos (10UL) -#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ -#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ -#define ADC_ISR_LDORDY_Pos (12UL) -#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ -#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready flag */ - -/******************** Bit definition for ADC_IER register *******************/ -#define ADC_IER_ADRDYIE_Pos (0UL) -#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ -#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ -#define ADC_IER_EOSMPIE_Pos (1UL) -#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ -#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ -#define ADC_IER_EOCIE_Pos (2UL) -#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ -#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ -#define ADC_IER_EOSIE_Pos (3UL) -#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ -#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_IER_OVRIE_Pos (4UL) -#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ -#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ -#define ADC_IER_JEOCIE_Pos (5UL) -#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ -#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ -#define ADC_IER_JEOSIE_Pos (6UL) -#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ -#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_IER_AWD1IE_Pos (7UL) -#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ -#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_IER_AWD2IE_Pos (8UL) -#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ -#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ -#define ADC_IER_AWD3IE_Pos (9UL) -#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ -#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ -#define ADC_IER_JQOVFIE_Pos (10UL) -#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ -#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ -#define ADC_IER_LDORDYIE_Pos (12UL) -#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ -#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt*/ - -/******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0UL) -#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ -#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ -#define ADC_CR_ADDIS_Pos (1UL) -#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ -#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ -#define ADC_CR_ADSTART_Pos (2UL) -#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ -#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR_JADSTART_Pos (3UL) -#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ -#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR_ADSTP_Pos (4UL) -#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ -#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ -#define ADC_CR_JADSTP_Pos (5UL) -#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ -#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ -#define ADC_CR_ADVREGEN_Pos (28UL) -#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ -#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator */ -#define ADC_CR_DEEPPWD_Pos (29UL) -#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ -#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ -#define ADC_CR_ADCAL_Pos (31UL) -#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ -#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ - -/******************** Bit definition for ADC_CFGR1 register ******************/ -#define ADC_CFGR1_DMNGT_Pos (0UL) -#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ -#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC data management configuration */ -#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ -#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ - -#define ADC_CFGR1_RES_Pos (2UL) -#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ -#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ -#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ -#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ - -#define ADC_CFGR1_EXTSEL_Pos (5UL) -#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ -#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ - -#define ADC_CFGR1_EXTEN_Pos (10UL) -#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ -#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ -#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ - -#define ADC_CFGR1_OVRMOD_Pos (12UL) -#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ -#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ -#define ADC_CFGR1_CONT_Pos (13UL) -#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ -#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CFGR1_AUTDLY_Pos (14UL) -#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ -#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC low power auto wait */ - -#define ADC_CFGR1_DISCEN_Pos (16UL) -#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ -#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ - -#define ADC_CFGR1_DISCNUM_Pos (17UL) -#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ -#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ -#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ -#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ - -#define ADC_CFGR1_JDISCEN_Pos (20UL) -#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ -#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ - -#define ADC_CFGR1_JQM_Pos (21UL) -#define ADC_CFGR1_JQM_Msk (0x1UL << ADC_CFGR1_JQM_Pos) /*!< 0x00200000 */ -#define ADC_CFGR1_JQM ADC_CFGR1_JQM_Msk /*!< ADC group injected contexts queue mode */ - -#define ADC_CFGR1_AWD1SGL_Pos (22UL) -#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ -#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CFGR1_AWD1EN_Pos (23UL) -#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ -#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ -#define ADC_CFGR1_JAWD1EN_Pos (24UL) -#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ -#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CFGR1_JAUTO_Pos (25UL) -#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ -#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ - -#define ADC_CFGR1_AWD1CH_Pos (26UL) -#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ -#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ -#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ -#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ -#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ -#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ - -#define ADC_CFGR1_JQDIS_Pos (31UL) -#define ADC_CFGR1_JQDIS_Msk (0x1UL << ADC_CFGR1_JQDIS_Pos) /*!< 0x80000000 */ -#define ADC_CFGR1_JQDIS ADC_CFGR1_JQDIS_Msk /*!< ADC group injected contexts queue disable */ - -/******************** Bit definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_ROVSE_Pos (0UL) -#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ -#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ -#define ADC_CFGR2_JOVSE_Pos (1UL) -#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ -#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ - -#define ADC_CFGR2_OVSS_Pos (5UL) -#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ -#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ -#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ -#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ -#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ -#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ - -#define ADC_CFGR2_TROVS_Pos (9UL) -#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ -#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ -#define ADC_CFGR2_ROVSM_Pos (10UL) -#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ -#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ - -#define ADC_CFGR2_BULB_Pos (13UL) -#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ -#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC bulb sampling mode */ - -#define ADC_CFGR2_SWTRIG_Pos (14UL) -#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ -#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC software trigger bit for sampling time control trigger mode */ - -#define ADC_CFGR2_SMPTRIG_Pos (15UL) -#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ -#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC sampling time control trigger mode */ - -#define ADC_CFGR2_OVSR_Pos (16UL) -#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ -#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ - -#define ADC_CFGR2_LFTRIG_Pos (27UL) -#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ -#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low-frequency trigge */ - -#define ADC_CFGR2_LSHIFT_Pos (28UL) -#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ -#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC left shift factor */ -#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ -#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ -#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ -#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_SMPR1 register *****************/ -#define ADC_SMPR1_SMP0_Pos (0UL) -#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ -#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR1_SMP1_Pos (3UL) -#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ -#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR1_SMP2_Pos (6UL) -#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR1_SMP3_Pos (9UL) -#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR1_SMP4_Pos (12UL) -#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ -#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR1_SMP5_Pos (15UL) -#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ -#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR1_SMP6_Pos (18UL) -#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR1_SMP7_Pos (21UL) -#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ - -#define ADC_SMPR1_SMP8_Pos (24UL) -#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ -#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ - -#define ADC_SMPR1_SMP9_Pos (27UL) -#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ -#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ - -/******************** Bit definition for ADC_SMPR2 register *****************/ -#define ADC_SMPR2_SMP10_Pos (0UL) -#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ -#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR2_SMP11_Pos (3UL) -#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ -#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR2_SMP12_Pos (6UL) -#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR2_SMP13_Pos (9UL) -#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR2_SMP14_Pos (12UL) -#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ -#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR2_SMP15_Pos (15UL) -#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ -#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR2_SMP16_Pos (18UL) -#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR2_SMP17_Pos (21UL) -#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ - -#define ADC_SMPR2_SMP18_Pos (24UL) -#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ -#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ - -#define ADC_SMPR2_SMP19_Pos (27UL) -#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ -#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ -#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ -#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ -#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ - -/******************** Bit definition for ADC_PCSEL register *****************/ -#define ADC_PCSEL_PCSEL_Pos (0UL) -#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ -#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC channel preselection */ -#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ -#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ -#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ -#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ -#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ -#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ -#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ -#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ -#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ -#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ -#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ -#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ -#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ -#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ -#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ -#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ -#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ -#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ -#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for ADC_SQR1 register ******************/ -#define ADC_SQR1_L_Pos (0UL) -#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ -#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ - -#define ADC_SQR1_SQ1_Pos (6UL) -#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ -#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ - -#define ADC_SQR1_SQ2_Pos (12UL) -#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ -#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ - -#define ADC_SQR1_SQ3_Pos (18UL) -#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ -#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ - -#define ADC_SQR1_SQ4_Pos (24UL) -#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ -#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ -#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ -#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ -#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ -#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR2 register ******************/ -#define ADC_SQR2_SQ5_Pos (0UL) -#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ -#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ - -#define ADC_SQR2_SQ6_Pos (6UL) -#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ -#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ - -#define ADC_SQR2_SQ7_Pos (12UL) -#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ -#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ - -#define ADC_SQR2_SQ8_Pos (18UL) -#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ -#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ - -#define ADC_SQR2_SQ9_Pos (24UL) -#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ -#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR3 register ******************/ -#define ADC_SQR3_SQ10_Pos (0UL) -#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ -#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ - -#define ADC_SQR3_SQ11_Pos (6UL) -#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ -#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ -#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ - -#define ADC_SQR3_SQ12_Pos (12UL) -#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ -#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ - -#define ADC_SQR3_SQ13_Pos (18UL) -#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ -#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ - -#define ADC_SQR3_SQ14_Pos (24UL) -#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ -#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR4 register ******************/ -#define ADC_SQR4_SQ15_Pos (0UL) -#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ -#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ -#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ -#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ -#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ -#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ - -#define ADC_SQR4_SQ16_Pos (6UL) -#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ -#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ -#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ -#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ -#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ -#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_RDATA_Pos (0UL) -#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_RDATA_0 (0x00000001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ -#define ADC_DR_RDATA_1 (0x00000002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ -#define ADC_DR_RDATA_2 (0x00000004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ -#define ADC_DR_RDATA_3 (0x00000008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ -#define ADC_DR_RDATA_4 (0x00000010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ -#define ADC_DR_RDATA_5 (0x00000020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ -#define ADC_DR_RDATA_6 (0x00000040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ -#define ADC_DR_RDATA_7 (0x00000080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ -#define ADC_DR_RDATA_8 (0x00000100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ -#define ADC_DR_RDATA_9 (0x00000200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ -#define ADC_DR_RDATA_10 (0x00000400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ -#define ADC_DR_RDATA_11 (0x00000800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ -#define ADC_DR_RDATA_12 (0x00001000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ -#define ADC_DR_RDATA_13 (0x00002000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ -#define ADC_DR_RDATA_14 (0x00004000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ -#define ADC_DR_RDATA_15 (0x00008000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ -#define ADC_DR_RDATA_16 (0x00010000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ -#define ADC_DR_RDATA_17 (0x00020000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ -#define ADC_DR_RDATA_18 (0x00040000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ -#define ADC_DR_RDATA_19 (0x00080000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ -#define ADC_DR_RDATA_20 (0x00100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ -#define ADC_DR_RDATA_21 (0x00200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ -#define ADC_DR_RDATA_22 (0x00400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ -#define ADC_DR_RDATA_23 (0x00800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ -#define ADC_DR_RDATA_24 (0x01000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ -#define ADC_DR_RDATA_25 (0x02000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ -#define ADC_DR_RDATA_26 (0x04000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ -#define ADC_DR_RDATA_27 (0x08000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ -#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ -#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ -#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ -#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_JSQR register ******************/ -#define ADC_JSQR_JL_Pos (0UL) -#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ -#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ - -#define ADC_JSQR_JEXTSEL_Pos (2UL) -#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ -#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ -#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ - -#define ADC_JSQR_JEXTEN_Pos (7UL) -#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ -#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ -#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ -#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ - -#define ADC_JSQR_JSQ1_Pos (9UL) -#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ -#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ -#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ - -#define ADC_JSQR_JSQ2_Pos (15UL) -#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ -#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ -#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ - -#define ADC_JSQR_JSQ3_Pos (21UL) -#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ -#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ -#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ - -#define ADC_JSQR_JSQ4_Pos (27UL) -#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ -#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ -#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_OFCFGR1 register ***************/ -#define ADC_OFCFGR1_POSOFF_Pos (24UL) -#define ADC_OFCFGR1_POSOFF_Msk (0x01UL << ADC_OFCFGR1_POSOFF_Pos) /*!< 0x01000000 */ -#define ADC_OFCFGR1_POSOFF ADC_OFCFGR1_POSOFF_Msk /*!< ADC offset instance 1 positive offset enable */ - -#define ADC_OFCFGR1_USAT_Pos (25UL) -#define ADC_OFCFGR1_USAT_Msk (0x01UL << ADC_OFCFGR1_USAT_Pos) /*!< 0x02000000 */ -#define ADC_OFCFGR1_USAT ADC_OFCFGR1_USAT_Msk /*!< ADC offset instance 1 unsigned saturation value */ - -#define ADC_OFCFGR1_SSAT_Pos (26UL) -#define ADC_OFCFGR1_SSAT_Msk (0x01UL << ADC_OFCFGR1_SSAT_Pos) /*!< 0x04000000 */ -#define ADC_OFCFGR1_SSAT ADC_OFCFGR1_SSAT_Msk /*!< ADC offset instance 1 signed satuaration enable */ - -#define ADC_OFCFGR1_OFFSET_CH_Pos (27UL) -#define ADC_OFCFGR1_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0xF8000000 */ -#define ADC_OFCFGR1_OFFSET_CH ADC_OFCFGR1_OFFSET_CH_Msk /*!< ADC offset instance 1 channel selection */ -#define ADC_OFCFGR1_OFFSET_CH_0 (0x01UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFCFGR1_OFFSET_CH_1 (0x02UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFCFGR1_OFFSET_CH_2 (0x03UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFCFGR1_OFFSET_CH_3 (0x04UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFCFGR1_OFFSET_CH_4 (0x05UL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_OFCFGR2 register ***************/ -#define ADC_OFCFGR2_POSOFF_Pos (24UL) -#define ADC_OFCFGR2_POSOFF_Msk (0x01UL << ADC_OFCFGR2_POSOFF_Pos) /*!< 0x01000000 */ -#define ADC_OFCFGR2_POSOFF ADC_OFCFGR2_POSOFF_Msk /*!< ADC offset instance 2 positive offset enable */ - -#define ADC_OFCFGR2_USAT_Pos (25UL) -#define ADC_OFCFGR2_USAT_Msk (0x01UL << ADC_OFCFGR2_USAT_Pos) /*!< 0x02000000 */ -#define ADC_OFCFGR2_USAT ADC_OFCFGR2_USAT_Msk /*!< ADC offset instance 2 unsigned saturation value */ - -#define ADC_OFCFGR2_SSAT_Pos (26UL) -#define ADC_OFCFGR2_SSAT_Msk (0x01UL << ADC_OFCFGR2_SSAT_Pos) /*!< 0x04000000 */ -#define ADC_OFCFGR2_SSAT ADC_OFCFGR2_SSAT_Msk /*!< ADC offset instance 2 signed satuaration enable */ - -#define ADC_OFCFGR2_OFFSET_CH_Pos (27UL) -#define ADC_OFCFGR2_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0xF8000000 */ -#define ADC_OFCFGR2_OFFSET_CH ADC_OFCFGR2_OFFSET_CH_Msk /*!< ADC offset instance 2 channel selection */ -#define ADC_OFCFGR2_OFFSET_CH_0 (0x01UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFCFGR2_OFFSET_CH_1 (0x02UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFCFGR2_OFFSET_CH_2 (0x03UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFCFGR2_OFFSET_CH_3 (0x04UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFCFGR2_OFFSET_CH_4 (0x05UL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_OFCFGR3 register ***************/ -#define ADC_OFCFGR3_POSOFF_Pos (24UL) -#define ADC_OFCFGR3_POSOFF_Msk (0x01UL << ADC_OFCFGR3_POSOFF_Pos) /*!< 0x01000000 */ -#define ADC_OFCFGR3_POSOFF ADC_OFCFGR3_POSOFF_Msk /*!< ADC offset instance 3 positive offset enable */ - -#define ADC_OFCFGR3_USAT_Pos (25UL) -#define ADC_OFCFGR3_USAT_Msk (0x01UL << ADC_OFCFGR3_USAT_Pos) /*!< 0x02000000 */ -#define ADC_OFCFGR3_USAT ADC_OFCFGR3_USAT_Msk /*!< ADC offset instance 3 unsigned saturation value */ - -#define ADC_OFCFGR3_SSAT_Pos (26UL) -#define ADC_OFCFGR3_SSAT_Msk (0x01UL << ADC_OFCFGR3_SSAT_Pos) /*!< 0x04000000 */ -#define ADC_OFCFGR3_SSAT ADC_OFCFGR3_SSAT_Msk /*!< ADC offset instance 3 signed satuaration enable */ - -#define ADC_OFCFGR3_OFFSET_CH_Pos (27UL) -#define ADC_OFCFGR3_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0xF8000000 */ -#define ADC_OFCFGR3_OFFSET_CH ADC_OFCFGR3_OFFSET_CH_Msk /*!< ADC offset instance 3 channel selection for the data offset */ -#define ADC_OFCFGR3_OFFSET_CH_0 (0x01UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFCFGR3_OFFSET_CH_1 (0x02UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFCFGR3_OFFSET_CH_2 (0x03UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFCFGR3_OFFSET_CH_3 (0x04UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFCFGR3_OFFSET_CH_4 (0x05UL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_OFCFGR4 register ***************/ -#define ADC_OFCFGR4_POSOFF_Pos (24UL) -#define ADC_OFCFGR4_POSOFF_Msk (0x01UL << ADC_OFCFGR4_POSOFF_Pos) /*!< 0x01000000 */ -#define ADC_OFCFGR4_POSOFF ADC_OFCFGR4_POSOFF_Msk /*!< ADC offset instance 4 positive offset enable */ - -#define ADC_OFCFGR4_USAT_Pos (25UL) -#define ADC_OFCFGR4_USAT_Msk (0x01UL << ADC_OFCFGR4_USAT_Pos) /*!< 0x02000000 */ -#define ADC_OFCFGR4_USAT ADC_OFCFGR4_USAT_Msk /*!< ADC offset instance 4 unsigned saturation value */ - -#define ADC_OFCFGR4_SSAT_Pos (26UL) -#define ADC_OFCFGR4_SSAT_Msk (0x01UL << ADC_OFCFGR4_SSAT_Pos) /*!< 0x04000000 */ -#define ADC_OFCFGR4_SSAT ADC_OFCFGR4_SSAT_Msk /*!< ADC offset instance 4 signed satuaration enable */ - -#define ADC_OFCFGR4_OFFSET_CH_Pos (27UL) -#define ADC_OFCFGR4_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0xF8000000 */ -#define ADC_OFCFGR4_OFFSET_CH ADC_OFCFGR4_OFFSET_CH_Msk /*!< ADC offset instance 4 channel selection for the data offset */ -#define ADC_OFCFGR4_OFFSET_CH_0 (0x01UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFCFGR4_OFFSET_CH_1 (0x02UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFCFGR4_OFFSET_CH_2 (0x03UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFCFGR4_OFFSET_CH_3 (0x04UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFCFGR4_OFFSET_CH_4 (0x05UL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_OFR1 register ******************/ -#define ADC_OFR1_OFFSET_Pos (0UL) -#define ADC_OFR1_OFFSET_Msk (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos) /*!< 0x003FFFFF */ -#define ADC_OFR1_OFFSET ADC_OFR1_OFFSET_Msk /*!< ADC offset instance 1 offset level */ -#define ADC_OFR1_OFFSET_0 (0x0000001UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000001 */ -#define ADC_OFR1_OFFSET_1 (0x0000002UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000002 */ -#define ADC_OFR1_OFFSET_2 (0x0000004UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000004 */ -#define ADC_OFR1_OFFSET_3 (0x0000008UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000008 */ -#define ADC_OFR1_OFFSET_4 (0x0000010UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000010 */ -#define ADC_OFR1_OFFSET_5 (0x0000020UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000020 */ -#define ADC_OFR1_OFFSET_6 (0x0000040UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000040 */ -#define ADC_OFR1_OFFSET_7 (0x0000080UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000080 */ -#define ADC_OFR1_OFFSET_8 (0x0000100UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000100 */ -#define ADC_OFR1_OFFSET_9 (0x0000200UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000200 */ -#define ADC_OFR1_OFFSET_10 (0x0000400UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000400 */ -#define ADC_OFR1_OFFSET_11 (0x0000800UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000800 */ -#define ADC_OFR1_OFFSET_12 (0x0001000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00001000 */ -#define ADC_OFR1_OFFSET_13 (0x0002000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00002000 */ -#define ADC_OFR1_OFFSET_14 (0x0004000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00004000 */ -#define ADC_OFR1_OFFSET_15 (0x0008000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00008000 */ -#define ADC_OFR1_OFFSET_16 (0x0010000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00010000 */ -#define ADC_OFR1_OFFSET_17 (0x0020000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00020000 */ -#define ADC_OFR1_OFFSET_18 (0x0040000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00040000 */ -#define ADC_OFR1_OFFSET_19 (0x0080000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00080000 */ -#define ADC_OFR1_OFFSET_20 (0x0100000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00100000 */ -#define ADC_OFR1_OFFSET_21 (0x0200000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00200000 */ - -/******************** Bit definition for ADC_OFR2 register ******************/ -#define ADC_OFR2_OFFSET_Pos (0UL) -#define ADC_OFR2_OFFSET_Msk (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos) /*!< 0x003FFFFF */ -#define ADC_OFR2_OFFSET ADC_OFR2_OFFSET_Msk /*!< ADC offset instance 2 offset level */ -#define ADC_OFR2_OFFSET_0 (0x0000001UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000001 */ -#define ADC_OFR2_OFFSET_1 (0x0000002UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000002 */ -#define ADC_OFR2_OFFSET_2 (0x0000004UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000004 */ -#define ADC_OFR2_OFFSET_3 (0x0000008UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000008 */ -#define ADC_OFR2_OFFSET_4 (0x0000010UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000010 */ -#define ADC_OFR2_OFFSET_5 (0x0000020UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000020 */ -#define ADC_OFR2_OFFSET_6 (0x0000040UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000040 */ -#define ADC_OFR2_OFFSET_7 (0x0000080UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000080 */ -#define ADC_OFR2_OFFSET_8 (0x0000100UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000100 */ -#define ADC_OFR2_OFFSET_9 (0x0000200UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000200 */ -#define ADC_OFR2_OFFSET_10 (0x0000400UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000400 */ -#define ADC_OFR2_OFFSET_11 (0x0000800UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000800 */ -#define ADC_OFR2_OFFSET_12 (0x0001000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00001000 */ -#define ADC_OFR2_OFFSET_13 (0x0002000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00002000 */ -#define ADC_OFR2_OFFSET_14 (0x0004000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00004000 */ -#define ADC_OFR2_OFFSET_15 (0x0008000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00008000 */ -#define ADC_OFR2_OFFSET_16 (0x0010000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00010000 */ -#define ADC_OFR2_OFFSET_17 (0x0020000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00020000 */ -#define ADC_OFR2_OFFSET_18 (0x0040000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00040000 */ -#define ADC_OFR2_OFFSET_19 (0x0080000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00080000 */ -#define ADC_OFR2_OFFSET_20 (0x0100000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00100000 */ -#define ADC_OFR2_OFFSET_21 (0x0200000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00200000 */ - -/******************** Bit definition for ADC_OFR3 register ******************/ -#define ADC_OFR3_OFFSET_Pos (0UL) -#define ADC_OFR3_OFFSET_Msk (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos) /*!< 0x003FFFFF */ -#define ADC_OFR3_OFFSET ADC_OFR3_OFFSET_Msk /*!< ADC offset instance 3 offset level */ -#define ADC_OFR3_OFFSET_0 (0x0000001UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000001 */ -#define ADC_OFR3_OFFSET_1 (0x0000002UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000002 */ -#define ADC_OFR3_OFFSET_2 (0x0000004UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000004 */ -#define ADC_OFR3_OFFSET_3 (0x0000008UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000008 */ -#define ADC_OFR3_OFFSET_4 (0x0000010UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000010 */ -#define ADC_OFR3_OFFSET_5 (0x0000020UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000020 */ -#define ADC_OFR3_OFFSET_6 (0x0000040UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000040 */ -#define ADC_OFR3_OFFSET_7 (0x0000080UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000080 */ -#define ADC_OFR3_OFFSET_8 (0x0000100UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000100 */ -#define ADC_OFR3_OFFSET_9 (0x0000200UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000200 */ -#define ADC_OFR3_OFFSET_10 (0x0000400UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000400 */ -#define ADC_OFR3_OFFSET_11 (0x0000800UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000800 */ -#define ADC_OFR3_OFFSET_12 (0x0001000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00001000 */ -#define ADC_OFR3_OFFSET_13 (0x0002000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00002000 */ -#define ADC_OFR3_OFFSET_14 (0x0004000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00004000 */ -#define ADC_OFR3_OFFSET_15 (0x0008000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00008000 */ -#define ADC_OFR3_OFFSET_16 (0x0010000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00010000 */ -#define ADC_OFR3_OFFSET_17 (0x0020000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00020000 */ -#define ADC_OFR3_OFFSET_18 (0x0040000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00040000 */ -#define ADC_OFR3_OFFSET_19 (0x0080000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00080000 */ -#define ADC_OFR3_OFFSET_20 (0x0100000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00100000 */ -#define ADC_OFR3_OFFSET_21 (0x0200000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00200000 */ - -/******************** Bit definition for ADC_OFR4 register ******************/ -#define ADC_OFR4_OFFSET_Pos (0UL) -#define ADC_OFR4_OFFSET_Msk (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos) /*!< 0x003FFFFF */ -#define ADC_OFR4_OFFSET ADC_OFR4_OFFSET_Msk /*!< ADC offset instance 4 offset level */ -#define ADC_OFR4_OFFSET_0 (0x0000001UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000001 */ -#define ADC_OFR4_OFFSET_1 (0x0000002UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000002 */ -#define ADC_OFR4_OFFSET_2 (0x0000004UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000004 */ -#define ADC_OFR4_OFFSET_3 (0x0000008UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000008 */ -#define ADC_OFR4_OFFSET_4 (0x0000010UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000010 */ -#define ADC_OFR4_OFFSET_5 (0x0000020UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000020 */ -#define ADC_OFR4_OFFSET_6 (0x0000040UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000040 */ -#define ADC_OFR4_OFFSET_7 (0x0000080UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000080 */ -#define ADC_OFR4_OFFSET_8 (0x0000100UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000100 */ -#define ADC_OFR4_OFFSET_9 (0x0000200UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000200 */ -#define ADC_OFR4_OFFSET_10 (0x0000400UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000400 */ -#define ADC_OFR4_OFFSET_11 (0x0000800UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000800 */ -#define ADC_OFR4_OFFSET_12 (0x0001000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00001000 */ -#define ADC_OFR4_OFFSET_13 (0x0002000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00002000 */ -#define ADC_OFR4_OFFSET_14 (0x0004000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00004000 */ -#define ADC_OFR4_OFFSET_15 (0x0008000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00008000 */ -#define ADC_OFR4_OFFSET_16 (0x0010000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00010000 */ -#define ADC_OFR4_OFFSET_17 (0x0020000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00020000 */ -#define ADC_OFR4_OFFSET_18 (0x0040000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00040000 */ -#define ADC_OFR4_OFFSET_19 (0x0080000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00080000 */ -#define ADC_OFR4_OFFSET_20 (0x0100000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00100000 */ -#define ADC_OFR4_OFFSET_21 (0x0200000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00200000 */ - -/******************** Bit definition for ADC_GCOMP register *****************/ -#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) -#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ -#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ -#define ADC_GCOMP_GCOMPCOEFF_0 (0x0001UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000001 */ -#define ADC_GCOMP_GCOMPCOEFF_1 (0x0002UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000002 */ -#define ADC_GCOMP_GCOMPCOEFF_2 (0x0004UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000004 */ -#define ADC_GCOMP_GCOMPCOEFF_3 (0x0008UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000008 */ -#define ADC_GCOMP_GCOMPCOEFF_4 (0x0010UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000010 */ -#define ADC_GCOMP_GCOMPCOEFF_5 (0x0020UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000020 */ -#define ADC_GCOMP_GCOMPCOEFF_6 (0x0040UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000040 */ -#define ADC_GCOMP_GCOMPCOEFF_7 (0x0080UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000080 */ -#define ADC_GCOMP_GCOMPCOEFF_8 (0x0100UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000100 */ -#define ADC_GCOMP_GCOMPCOEFF_9 (0x0200UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000200 */ -#define ADC_GCOMP_GCOMPCOEFF_10 (0x0400UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000400 */ -#define ADC_GCOMP_GCOMPCOEFF_11 (0x0800UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00000800 */ -#define ADC_GCOMP_GCOMPCOEFF_12 (0x1000UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00001000 */ -#define ADC_GCOMP_GCOMPCOEFF_13 (0x2000UL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00002000 */ - -#define ADC_GCOMP_GCOMP_Pos (31UL) -#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ -#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ - -/******************** Bit definition for ADC_JDR1 register ******************/ -#define ADC_JDR1_JDATA_Pos (0UL) -#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ -#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ -#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ -#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ -#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ -#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ -#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ -#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ -#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ -#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ -#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ -#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ -#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ -#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ -#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ -#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ -#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ -#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_JDR2 register ********************/ -#define ADC_JDR2_JDATA_Pos (0UL) -#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ -#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ -#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ -#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ -#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ -#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ -#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ -#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ -#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ -#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ -#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ -#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ -#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ -#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ -#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ -#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ -#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ -#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_JDR3 register ********************/ -#define ADC_JDR3_JDATA_Pos (0UL) -#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ -#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ -#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ -#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ -#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ -#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ -#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ -#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ -#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ -#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ -#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ -#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ -#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ -#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ -#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ -#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ -#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ -#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_JDR4 register ********************/ -#define ADC_JDR4_JDATA_Pos (0UL) -#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ -#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ -#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ -#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ -#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ -#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ -#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ -#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ -#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ -#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ -#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ -#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ -#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ -#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ -#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ -#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ -#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ -#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_AWD2CR register ****************/ -#define ADC_AWD2CR_AWD2CH_Pos (0UL) -#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ -#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for ADC_AWD3CR register ****************/ -#define ADC_AWD3CR_AWD3CH_Pos (0UL) -#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ -#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for ADC_AWD1TR_LT register *************/ -#define ADC_AWD1LTR_LTR_Pos (0UL) -#define ADC_AWD1LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ -#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_AWD1LTR_LTR_0 (0x000001UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ -#define ADC_AWD1LTR_LTR_1 (0x000002UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ -#define ADC_AWD1LTR_LTR_2 (0x000004UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ -#define ADC_AWD1LTR_LTR_3 (0x000008UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ -#define ADC_AWD1LTR_LTR_4 (0x000010UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ -#define ADC_AWD1LTR_LTR_5 (0x000020UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ -#define ADC_AWD1LTR_LTR_6 (0x000040UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ -#define ADC_AWD1LTR_LTR_7 (0x000080UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ -#define ADC_AWD1LTR_LTR_8 (0x000100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ -#define ADC_AWD1LTR_LTR_9 (0x000200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ -#define ADC_AWD1LTR_LTR_10 (0x000400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ -#define ADC_AWD1LTR_LTR_11 (0x000800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ -#define ADC_AWD1LTR_LTR_12 (0x001000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ -#define ADC_AWD1LTR_LTR_13 (0x002000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ -#define ADC_AWD1LTR_LTR_14 (0x004000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ -#define ADC_AWD1LTR_LTR_15 (0x008000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ -#define ADC_AWD1LTR_LTR_16 (0x010000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ -#define ADC_AWD1LTR_LTR_17 (0x020000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ -#define ADC_AWD1LTR_LTR_18 (0x040000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ -#define ADC_AWD1LTR_LTR_19 (0x080000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ -#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ -#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ -#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ - -/******************** Bit definition for ADC_AWD1TR_HT register *******************/ -#define ADC_AWD1HTR_HTR_Pos (0UL) -#define ADC_AWD1HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ -#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< ADC analog watchdog 1 threshold high */ -#define ADC_AWD1HTR_HTR_0 (0x000001UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ -#define ADC_AWD1HTR_HTR_1 (0x000002UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ -#define ADC_AWD1HTR_HTR_2 (0x000004UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ -#define ADC_AWD1HTR_HTR_3 (0x000008UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ -#define ADC_AWD1HTR_HTR_4 (0x000010UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ -#define ADC_AWD1HTR_HTR_5 (0x000020UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ -#define ADC_AWD1HTR_HTR_6 (0x000040UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ -#define ADC_AWD1HTR_HTR_7 (0x000080UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ -#define ADC_AWD1HTR_HTR_8 (0x000100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ -#define ADC_AWD1HTR_HTR_9 (0x000200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ -#define ADC_AWD1HTR_HTR_10 (0x000400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ -#define ADC_AWD1HTR_HTR_11 (0x000800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ -#define ADC_AWD1HTR_HTR_12 (0x001000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ -#define ADC_AWD1HTR_HTR_13 (0x002000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ -#define ADC_AWD1HTR_HTR_14 (0x004000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ -#define ADC_AWD1HTR_HTR_15 (0x008000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ -#define ADC_AWD1HTR_HTR_16 (0x010000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ -#define ADC_AWD1HTR_HTR_17 (0x020000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ -#define ADC_AWD1HTR_HTR_18 (0x040000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ -#define ADC_AWD1HTR_HTR_19 (0x080000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ -#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ -#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ -#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ - -#define ADC_AWD1HTR_AWDFILT_Pos (29UL) -#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000007 */ -#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< ADC analog watchdog 1 filtering */ -#define ADC_AWD1HTR_AWDFILT_0 (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */ -#define ADC_AWD1HTR_AWDFILT_1 (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */ -#define ADC_AWD1HTR_AWDFILT_2 (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for ADC_AWD2TR_LT register *******************/ -#define ADC_AWD2LTR_LTR_Pos (0UL) -#define ADC_AWD2LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ -#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_AWD2LTR_LTR_0 (0x000001UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ -#define ADC_AWD2LTR_LTR_1 (0x000002UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ -#define ADC_AWD2LTR_LTR_2 (0x000004UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ -#define ADC_AWD2LTR_LTR_3 (0x000008UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ -#define ADC_AWD2LTR_LTR_4 (0x000010UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ -#define ADC_AWD2LTR_LTR_5 (0x000020UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ -#define ADC_AWD2LTR_LTR_6 (0x000040UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ -#define ADC_AWD2LTR_LTR_7 (0x000080UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ -#define ADC_AWD2LTR_LTR_8 (0x000100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ -#define ADC_AWD2LTR_LTR_9 (0x000200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ -#define ADC_AWD2LTR_LTR_10 (0x000400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ -#define ADC_AWD2LTR_LTR_11 (0x000800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ -#define ADC_AWD2LTR_LTR_12 (0x001000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ -#define ADC_AWD2LTR_LTR_13 (0x002000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ -#define ADC_AWD2LTR_LTR_14 (0x004000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ -#define ADC_AWD2LTR_LTR_15 (0x008000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ -#define ADC_AWD2LTR_LTR_16 (0x010000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ -#define ADC_AWD2LTR_LTR_17 (0x020000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ -#define ADC_AWD2LTR_LTR_18 (0x040000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ -#define ADC_AWD2LTR_LTR_19 (0x080000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ -#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ -#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ -#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ - -/******************** Bit definition for ADC_AWD2TR_HT register *******************/ -#define ADC_AWD2HTR_HTR_Pos (0UL) -#define ADC_AWD2HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ -#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_AWD2HTR_HTR_0 (0x000001UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ -#define ADC_AWD2HTR_HTR_1 (0x000002UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ -#define ADC_AWD2HTR_HTR_2 (0x000004UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ -#define ADC_AWD2HTR_HTR_3 (0x000008UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ -#define ADC_AWD2HTR_HTR_4 (0x000010UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ -#define ADC_AWD2HTR_HTR_5 (0x000020UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ -#define ADC_AWD2HTR_HTR_6 (0x000040UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ -#define ADC_AWD2HTR_HTR_7 (0x000080UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ -#define ADC_AWD2HTR_HTR_8 (0x000100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ -#define ADC_AWD2HTR_HTR_9 (0x000200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ -#define ADC_AWD2HTR_HTR_10 (0x000400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ -#define ADC_AWD2HTR_HTR_11 (0x000800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ -#define ADC_AWD2HTR_HTR_12 (0x001000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ -#define ADC_AWD2HTR_HTR_13 (0x002000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ -#define ADC_AWD2HTR_HTR_14 (0x004000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ -#define ADC_AWD2HTR_HTR_15 (0x008000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ -#define ADC_AWD2HTR_HTR_16 (0x010000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ -#define ADC_AWD2HTR_HTR_17 (0x020000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ -#define ADC_AWD2HTR_HTR_18 (0x040000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ -#define ADC_AWD2HTR_HTR_19 (0x080000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ -#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ -#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ -#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ - -/******************** Bit definition for ADC_AWD3TR_LT register *******************/ -#define ADC_AWD3LTR_LTR_Pos (0UL) -#define ADC_AWD3LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ -#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_AWD3LTR_LTR_0 (0x000001UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ -#define ADC_AWD3LTR_LTR_1 (0x000002UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ -#define ADC_AWD3LTR_LTR_2 (0x000004UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ -#define ADC_AWD3LTR_LTR_3 (0x000008UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ -#define ADC_AWD3LTR_LTR_4 (0x000010UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ -#define ADC_AWD3LTR_LTR_5 (0x000020UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ -#define ADC_AWD3LTR_LTR_6 (0x000040UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ -#define ADC_AWD3LTR_LTR_7 (0x000080UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ -#define ADC_AWD3LTR_LTR_8 (0x000100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ -#define ADC_AWD3LTR_LTR_9 (0x000200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ -#define ADC_AWD3LTR_LTR_10 (0x000400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ -#define ADC_AWD3LTR_LTR_11 (0x000800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ -#define ADC_AWD3LTR_LTR_12 (0x001000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ -#define ADC_AWD3LTR_LTR_13 (0x002000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ -#define ADC_AWD3LTR_LTR_14 (0x004000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ -#define ADC_AWD3LTR_LTR_15 (0x008000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ -#define ADC_AWD3LTR_LTR_16 (0x010000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ -#define ADC_AWD3LTR_LTR_17 (0x020000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ -#define ADC_AWD3LTR_LTR_18 (0x040000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ -#define ADC_AWD3LTR_LTR_19 (0x080000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ -#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ -#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ -#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ - -/******************** Bit definition for ADC_AWD3TR_HT register *******************/ -#define ADC_AWD3HTR_HTR_Pos (0UL) -#define ADC_AWD3HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ -#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_AWD3HTR_HTR_0 (0x000001UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ -#define ADC_AWD3HTR_HTR_1 (0x000002UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ -#define ADC_AWD3HTR_HTR_2 (0x000004UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ -#define ADC_AWD3HTR_HTR_3 (0x000008UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ -#define ADC_AWD3HTR_HTR_4 (0x000010UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ -#define ADC_AWD3HTR_HTR_5 (0x000020UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ -#define ADC_AWD3HTR_HTR_6 (0x000040UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ -#define ADC_AWD3HTR_HTR_7 (0x000080UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ -#define ADC_AWD3HTR_HTR_8 (0x000100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ -#define ADC_AWD3HTR_HTR_9 (0x000200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ -#define ADC_AWD3HTR_HTR_10 (0x000400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ -#define ADC_AWD3HTR_HTR_11 (0x000800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ -#define ADC_AWD3HTR_HTR_12 (0x001000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ -#define ADC_AWD3HTR_HTR_13 (0x002000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ -#define ADC_AWD3HTR_HTR_14 (0x004000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ -#define ADC_AWD3HTR_HTR_15 (0x008000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ -#define ADC_AWD3HTR_HTR_16 (0x010000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ -#define ADC_AWD3HTR_HTR_17 (0x020000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ -#define ADC_AWD3HTR_HTR_18 (0x040000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ -#define ADC_AWD3HTR_HTR_19 (0x080000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ -#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ -#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ -#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ - -/******************** Bit definition for ADC_CALFACT register ***************/ - -#define ADC_CALFACT_CALFACT_Pos (0UL) -#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ -#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ -#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ -#define ADC_CALFACT_CALFACT_7 (0x80UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000080 */ -#define ADC_CALFACT_CALFACT_8 (0x100UL<< ADC_CALFACT_CALFACT_Pos) /*!< 0x00000100 */ -#define ADC_CALFACT_CALFACT_9 (0x200UL<< ADC_CALFACT_CALFACT_Pos) /*!< 0x00000200 */ - - -/******************** Bit definition for ADC_OR option register ***************/ -#define ADC_OR_VDDCOREEN_Pos (0UL) -#define ADC_OR_VDDCOREEN_Msk (0x1UL << ADC_OR_VDDCOREEN_Pos) /*!< 0x00000004 */ -#define ADC_OR_VDDCOREEN ADC_OR_VDDCOREEN_Msk /*!< ADC internal path to VDDCORE */ - -/************************* ADC Common registers *****************************/ -/******************** Bit definition for ADC_CSR register *******************/ -#define ADC_CSR_ADRDY_MST_Pos (0UL) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ -#define ADC_CSR_EOSMP_MST_Pos (1UL) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ -#define ADC_CSR_EOC_MST_Pos (2UL) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ -#define ADC_CSR_EOS_MST_Pos (3UL) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ -#define ADC_CSR_OVR_MST_Pos (4UL) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ -#define ADC_CSR_JEOC_MST_Pos (5UL) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ -#define ADC_CSR_JEOS_MST_Pos (6UL) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ -#define ADC_CSR_AWD1_MST_Pos (7UL) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ -#define ADC_CSR_AWD2_MST_Pos (8UL) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ -#define ADC_CSR_AWD3_MST_Pos (9UL) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ -#define ADC_CSR_JQOVF_MST_Pos (10UL) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ -#define ADC_CSR_LDORDY_MST_Pos (12UL) -#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ -#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< ADC multimode master internal voltage regulator output ready flag */ - -#define ADC_CSR_ADRDY_SLV_Pos (16UL) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ -#define ADC_CSR_EOSMP_SLV_Pos (17UL) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ -#define ADC_CSR_EOC_SLV_Pos (18UL) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ -#define ADC_CSR_EOS_SLV_Pos (19UL) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ -#define ADC_CSR_OVR_SLV_Pos (20UL) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ -#define ADC_CSR_JEOC_SLV_Pos (21UL) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ -#define ADC_CSR_JEOS_SLV_Pos (22UL) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ -#define ADC_CSR_AWD1_SLV_Pos (23UL) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ -#define ADC_CSR_AWD2_SLV_Pos (24UL) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ -#define ADC_CSR_AWD3_SLV_Pos (25UL) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ -#define ADC_CSR_JQOVF_SLV_Pos (26UL) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ -#define ADC_CSR_LDORDY_SLV_Pos (28UL) -#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ -#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< ADC multimode slave internal voltage regulator output ready flag */ - -/******************** Bit definition for ADC_CCR register *******************/ -#define ADC_CCR_DUAL_Pos (0UL) -#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ -#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ -#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ -#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ -#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ -#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ -#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ - -#define ADC_CCR_DELAY_Pos (8UL) -#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ -#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ -#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ -#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ -#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ -#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ - -#define ADC_CCR_DAMDF_Pos (14UL) -#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ -#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< ADC multimode data format */ -#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ -#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ - -#define ADC_CCR_PRESC_Pos (18UL) -#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ -#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler */ -#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ -#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ -#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ -#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ - -#define ADC_CCR_VREFEN_Pos (22UL) -#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ -#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ - -#define ADC_CCR_TSEN_Pos (23UL) -#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to Temperature sensor voltage enable */ - -#define ADC_CCR_VBATEN_Pos (24UL) -#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ -#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ - -/******************** Bit definition for ADC_CDR register *******************/ -#define ADC_CDR_RDATA_MST_Pos (0UL) -#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ -#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ - -#define ADC_CDR_RDATA_SLV_Pos (16UL) -#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ -#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ - -/******************** Bit definition for ADC_CDR2 register ******************/ -#define ADC_CDR2_RDATA_ALT_Pos (0UL) -#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ -#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< ADC multimode master or slave (alternated) group regular conversion data */ - -/******************************************************************************/ -/* */ -/* Advanced Encryption Standard (AES) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for AES_CR register *********************/ -#define AES_CR_EN_Pos (0UL) -#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ -#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ -#define AES_CR_DATATYPE_Pos (1UL) -#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ -#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ -#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ -#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ -#define AES_CR_MODE_Pos (3UL) -#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ -#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ -#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ -#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ -#define AES_CR_CHMOD_Pos (5UL) -#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ -#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ -#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ -#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ -#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ -#define AES_CR_DMAINEN_Pos (11UL) -#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ -#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ -#define AES_CR_DMAOUTEN_Pos (12UL) -#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ -#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ -#define AES_CR_GCMPH_Pos (13UL) -#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ -#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ -#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ -#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ -#define AES_CR_KEYSIZE_Pos (18UL) -#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ -#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ -#define AES_CR_KEYPROT_Pos (19UL) -#define AES_CR_KEYPROT_Msk (0x1UL << AES_CR_KEYPROT_Pos) /*!< 0x00040000 */ -#define AES_CR_KEYPROT AES_CR_KEYPROT_Msk /*!< Key protection */ -#define AES_CR_NPBLB_Pos (20UL) -#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ -#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ -#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ -#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ -#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ -#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ -#define AES_CR_KMOD_Pos (24UL) -#define AES_CR_KMOD_Msk (0x3UL << AES_CR_KMOD_Pos) /*!< 0x03000000 */ -#define AES_CR_KMOD AES_CR_KMOD_Msk /*!< Key mode selection */ -#define AES_CR_KMOD_0 (0x1UL << AES_CR_KMOD_Pos) /*!< 0x01000000 */ -#define AES_CR_KMOD_1 (0x2UL << AES_CR_KMOD_Pos) /*!< 0x02000000 */ -#define AES_CR_KSHAREID_Pos (26UL) -#define AES_CR_KSHAREID_Msk (0x3UL << AES_CR_KSHAREID_Pos) /*!< 0x0C000000 */ -#define AES_CR_KSHAREID AES_CR_KSHAREID_Msk /*!< Key Shared ID */ -#define AES_CR_KEYSEL_Pos (28UL) -#define AES_CR_KEYSEL_Msk (0x7UL << AES_CR_KEYSEL_Pos) /*!< 0x70000000 */ -#define AES_CR_KEYSEL AES_CR_KEYSEL_Msk /*!< Key Selection */ -#define AES_CR_KEYSEL_0 (0x1UL << AES_CR_KEYSEL_Pos) /*!< 0x10000000 */ -#define AES_CR_KEYSEL_1 (0x2UL << AES_CR_KEYSEL_Pos) /*!< 0x20000000 */ -#define AES_CR_KEYSEL_2 (0x4UL << AES_CR_KEYSEL_Pos) /*!< 0x40000000 */ -#define AES_CR_IPRST_Pos (31UL) -#define AES_CR_IPRST_Msk (0x1UL << AES_CR_IPRST_Pos) /*!< 0x80000000 */ -#define AES_CR_IPRST AES_CR_IPRST_Msk /*!< AES IP software reset */ - -/******************* Bit definition for AES_SR register *********************/ -#define AES_SR_CCF_Pos (0UL) -#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ -#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ -#define AES_SR_RDERR_Pos (1UL) -#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ -#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ -#define AES_SR_WRERR_Pos (2UL) -#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ -#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ -#define AES_SR_BUSY_Pos (3UL) -#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ -#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ -#define AES_SR_KEYVALID_Pos (7UL) -#define AES_SR_KEYVALID_Msk (0x1UL << AES_SR_KEYVALID_Pos) /*!< 0x00000080 */ -#define AES_SR_KEYVALID AES_SR_KEYVALID_Msk /*!< KEYVALID Flag */ - -/******************* Bit definition for AES_DINR register *******************/ -#define AES_DINR_Pos (0UL) -#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ -#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ - -/******************* Bit definition for AES_DOUTR register ******************/ -#define AES_DOUTR_Pos (0UL) -#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ -#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ - -/******************* Bit definition for AES_KEYR0 register ******************/ -#define AES_KEYR0_Pos (0UL) -#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ -#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ - -/******************* Bit definition for AES_KEYR1 register ******************/ -#define AES_KEYR1_Pos (0UL) -#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ -#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ - -/******************* Bit definition for AES_KEYR2 register ******************/ -#define AES_KEYR2_Pos (0UL) -#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ -#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ - -/******************* Bit definition for AES_KEYR3 register ******************/ -#define AES_KEYR3_Pos (0UL) -#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ -#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ - -/******************* Bit definition for AES_KEYR4 register ******************/ -#define AES_KEYR4_Pos (0UL) -#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ -#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ - -/******************* Bit definition for AES_KEYR5 register ******************/ -#define AES_KEYR5_Pos (0UL) -#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ -#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ - -/******************* Bit definition for AES_KEYR6 register ******************/ -#define AES_KEYR6_Pos (0UL) -#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ -#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ - -/******************* Bit definition for AES_KEYR7 register ******************/ -#define AES_KEYR7_Pos (0UL) -#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ -#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ - -/******************* Bit definition for AES_IVR0 register ******************/ -#define AES_IVR0_Pos (0UL) -#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ -#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ - -/******************* Bit definition for AES_IVR1 register ******************/ -#define AES_IVR1_Pos (0UL) -#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ -#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ - -/******************* Bit definition for AES_IVR2 register ******************/ -#define AES_IVR2_Pos (0UL) -#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ -#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ - -/******************* Bit definition for AES_IVR3 register ******************/ -#define AES_IVR3_Pos (0UL) -#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ -#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ - -/******************* Bit definition for AES_SUSP0R register ******************/ -#define AES_SUSP0R_Pos (0UL) -#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ -#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ - -/******************* Bit definition for AES_SUSP1R register ******************/ -#define AES_SUSP1R_Pos (0UL) -#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ -#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ - -/******************* Bit definition for AES_SUSP2R register ******************/ -#define AES_SUSP2R_Pos (0UL) -#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ -#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ - -/******************* Bit definition for AES_SUSP3R register ******************/ -#define AES_SUSP3R_Pos (0UL) -#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ -#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ - -/******************* Bit definition for AES_SUSP4R register ******************/ -#define AES_SUSP4R_Pos (0UL) -#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ -#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ - -/******************* Bit definition for AES_SUSP5R register ******************/ -#define AES_SUSP5R_Pos (0UL) -#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ -#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ - -/******************* Bit definition for AES_SUSP6R register ******************/ -#define AES_SUSP6R_Pos (0UL) -#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ -#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ - -/******************* Bit definition for AES_SUSP7R register ******************/ -#define AES_SUSP7R_Pos (0UL) -#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ -#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ - -/******************* Bit definition for AES_IER register ******************/ -#define AES_IER_CCFIE_Pos (0UL) -#define AES_IER_CCFIE_Msk (0x1UL << AES_IER_CCFIE_Pos) /*!< 0x00000001 */ -#define AES_IER_CCFIE AES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ -#define AES_IER_RWEIE_Pos (1UL) -#define AES_IER_RWEIE_Msk (0x1UL << AES_IER_RWEIE_Pos) /*!< 0x00000002 */ -#define AES_IER_RWEIE AES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ -#define AES_IER_KEIE_Pos (2UL) -#define AES_IER_KEIE_Msk (0x1UL << AES_IER_KEIE_Pos) /*!< 0x00000004 */ -#define AES_IER_KEIE AES_IER_KEIE_Msk /*!< Key error interrupt enable */ -#define AES_IER_RNGEIE_Pos (3UL) -#define AES_IER_RNGEIE_Msk (0x1UL << AES_IER_RNGEIE_Pos) /*!< 0x00000008 */ -#define AES_IER_RNGEIE AES_IER_RNGEIE_Msk /*!< Rng error interrupt enable */ - -/******************* Bit definition for AES_ISR register ******************/ -#define AES_ISR_CCF_Pos (0UL) -#define AES_ISR_CCF_Msk (0x1UL << AES_ISR_CCF_Pos) /*!< 0x00000001 */ -#define AES_ISR_CCF AES_ISR_CCF_Msk /*!< Computation complete flag */ -#define AES_ISR_RWEIF_Pos (1UL) -#define AES_ISR_RWEIF_Msk (0x1UL << AES_ISR_RWEIF_Pos) /*!< 0x00000002 */ -#define AES_ISR_RWEIF AES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ -#define AES_ISR_KEIF_Pos (2UL) -#define AES_ISR_KEIF_Msk (0x1UL << AES_ISR_KEIF_Pos) /*!< 0x00000004 */ -#define AES_ISR_KEIF AES_ISR_KEIF_Msk /*!< Key error interrupt flag */ -#define AES_ISR_RNGEIF_Pos (3UL) -#define AES_ISR_RNGEIF_Msk (0x1UL << AES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ -#define AES_ISR_RNGEIF AES_ISR_RNGEIF_Msk /*!< Rng error interrupt flag */ - -/******************* Bit definition for AES_ICR register ******************/ -#define AES_ICR_CCF_Pos (0UL) -#define AES_ICR_CCF_Msk (0x1UL << AES_ICR_CCF_Pos) /*!< 0x00000001 */ -#define AES_ICR_CCF AES_ICR_CCF_Msk /*!< Computation complete flag clear */ -#define AES_ICR_RWEIF_Pos (1UL) -#define AES_ICR_RWEIF_Msk (0x1UL << AES_ICR_RWEIF_Pos) /*!< 0x00000002 */ -#define AES_ICR_RWEIF AES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ -#define AES_ICR_KEIF_Pos (2UL) -#define AES_ICR_KEIF_Msk (0x1UL << AES_ICR_KEIF_Pos) /*!< 0x00000004 */ -#define AES_ICR_KEIF AES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ -#define AES_ICR_RNGEIF_Pos (3UL) -#define AES_ICR_RNGEIF_Msk (0x1UL << AES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ -#define AES_ICR_RNGEIF AES_ICR_RNGEIF_Msk /*!< Rng error interrupt flag clear */ - -/******************************************************************************/ -/* */ -/* Coupling and chaining bridge (CCB) */ -/* */ -/******************************************************************************/ - -/* Specific device feature definitions */ -#define SW_SANITY_CHECK_SUPPORT /*!< CCB feature available only on specific devices: SW Sanity check is available on U3 1M devices */ - -/******************* Bit definition for CCB_CR register ******************/ -#define CCB_CR_CCOP_Pos (0UL) -#define CCB_CR_CCOP_Msk (0xFFUL << CCB_CR_CCOP_Pos) /*!< 0x000000FF */ -#define CCB_CR_CCOP CCB_CR_CCOP_Msk /*!< Coupling and chaining operation */ -#define CCB_CR_IPRST_Pos (31UL) -#define CCB_CR_IPRST_Msk (0x1UL << CCB_CR_IPRST_Pos) /*!< 0x80000000 */ -#define CCB_CR_IPRST CCB_CR_IPRST_Msk /*!< CCB reset */ - -/******************* Bit definition for CCB_SR register ******************/ -#define CCB_SR_OPSTEP_Pos (0UL) -#define CCB_SR_OPSTEP_Msk (0x1FUL << CCB_SR_OPSTEP_Pos) /*!< 0x0000001F */ -#define CCB_SR_OPSTEP CCB_SR_OPSTEP_Msk /*!< Operation step */ -#define CCB_SR_OPERR_Pos (8UL) -#define CCB_SR_OPERR_Msk (0x1FUL << CCB_SR_OPERR_Pos) /*!< 0x00001F00 */ -#define CCB_SR_OPERR CCB_SR_OPERR_Msk /*!< Operation error */ -#define CCB_SR_BUSY_Pos (16UL) -#define CCB_SR_BUSY_Msk (0x1UL << CCB_SR_BUSY_Pos) /*!< 0x00010000 */ -#define CCB_SR_BUSY CCB_SR_BUSY_Msk /*!< CCB busy */ -#define CCB_SR_TAMP_EVT0_Pos (24UL) -#define CCB_SR_TAMP_EVT0_Msk (0x1UL << CCB_SR_TAMP_EVT0_Pos) /*!< 0x01000000 */ -#define CCB_SR_TAMP_EVT0 CCB_SR_TAMP_EVT0_Msk /*!< Tamper event 0 flag */ -#define CCB_SR_TAMP_EVT1_Pos (25UL) -#define CCB_SR_TAMP_EVT1_Msk (0x1UL << CCB_SR_TAMP_EVT1_Pos) /*!< 0x02000000 */ -#define CCB_SR_TAMP_EVT1 CCB_SR_TAMP_EVT1_Msk /*!< Tamper event 1 flag */ -#define CCB_SR_TAMP_EVT2_Pos (26UL) -#define CCB_SR_TAMP_EVT2_Msk (0x1UL << CCB_SR_TAMP_EVT2_Pos) /*!< 0x04000000 */ -#define CCB_SR_TAMP_EVT2 CCB_SR_TAMP_EVT2_Msk /*!< Tamper event 2 flag */ -#define CCB_SR_TAMP_EVT3_Pos (27UL) -#define CCB_SR_TAMP_EVT3_Msk (0x1UL << CCB_SR_TAMP_EVT3_Pos) /*!< 0x08000000 */ -#define CCB_SR_TAMP_EVT3 CCB_SR_TAMP_EVT3_Msk /*!< Tamper event 3 flag */ -#define CCB_SR_TAMP_EVT4_Pos (28UL) -#define CCB_SR_TAMP_EVT4_Msk (0x1UL << CCB_SR_TAMP_EVT4_Pos) /*!< 0x10000000 */ -#define CCB_SR_TAMP_EVT4 CCB_SR_TAMP_EVT4_Msk /*!< Tamper event 4 flag */ - -/******************************************************************************/ -/* */ -/* CRC calculation unit */ -/* */ -/******************************************************************************/ -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR_Pos (0UL) -#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ -#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR_Pos (0UL) -#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ -#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET_Pos (0UL) -#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ -#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE_Pos (3UL) -#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ -#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ -#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ -#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ -#define CRC_CR_REV_IN_Pos (5UL) -#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ -#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ -#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ -#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ -#define CRC_CR_REV_OUT_Pos (7UL) -#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ -#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ -#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ -#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ -#define CRC_CR_RTYPE_IN_Pos (9UL) -#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ -#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< RTYPE_IN Reverse Type Input bit */ -#define CRC_CR_RTYPE_OUT_Pos (10UL) -#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ -#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< RTYPE_OUT Reverse Type Output bit */ - -/******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT_Pos (0UL) -#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ -#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ - -/******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL_Pos (0UL) -#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ -#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ - -/******************************************************************************/ -/* */ -/* CRS Clock Recovery System */ -/******************************************************************************/ -/******************* Bit definition for CRS_CR register *********************/ -#define CRS_CR_SYNCOKIE_Pos (0UL) -#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ -#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ -#define CRS_CR_SYNCWARNIE_Pos (1UL) -#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ -#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ -#define CRS_CR_ERRIE_Pos (2UL) -#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ -#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ -#define CRS_CR_ESYNCIE_Pos (3UL) -#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ -#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ -#define CRS_CR_CEN_Pos (5UL) -#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ -#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ -#define CRS_CR_AUTOTRIMEN_Pos (6UL) -#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ -#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ -#define CRS_CR_SWSYNC_Pos (7UL) -#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ -#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ -#define CRS_CR_TRIM_Pos (8UL) -#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ -#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ - -/******************* Bit definition for CRS_CFGR register *********************/ -#define CRS_CFGR_RELOAD_Pos (0UL) -#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ -#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ -#define CRS_CFGR_FELIM_Pos (16UL) -#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ -#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ -#define CRS_CFGR_SYNCDIV_Pos (24UL) -#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ -#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ -#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ -#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ -#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ -#define CRS_CFGR_SYNCSRC_Pos (28UL) -#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ -#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ -#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ -#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ -#define CRS_CFGR_SYNCPOL_Pos (31UL) -#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ -#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ - -/******************* Bit definition for CRS_ISR register *********************/ -#define CRS_ISR_SYNCOKF_Pos (0UL) -#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ -#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ -#define CRS_ISR_SYNCWARNF_Pos (1UL) -#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ -#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ -#define CRS_ISR_ERRF_Pos (2UL) -#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ -#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ -#define CRS_ISR_ESYNCF_Pos (3UL) -#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ -#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ -#define CRS_ISR_SYNCERR_Pos (8UL) -#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ -#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ -#define CRS_ISR_SYNCMISS_Pos (9UL) -#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ -#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ -#define CRS_ISR_TRIMOVF_Pos (10UL) -#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ -#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ -#define CRS_ISR_FEDIR_Pos (15UL) -#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ -#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ -#define CRS_ISR_FECAP_Pos (16UL) -#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ -#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ - -/******************* Bit definition for CRS_ICR register *********************/ -#define CRS_ICR_SYNCOKC_Pos (0UL) -#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ -#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ -#define CRS_ICR_SYNCWARNC_Pos (1UL) -#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ -#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ -#define CRS_ICR_ERRC_Pos (2UL) -#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ -#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ -#define CRS_ICR_ESYNCC_Pos (3UL) -#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ -#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ - -/******************************************************************************/ -/* */ -/* Analog Comparators (COMP) */ -/* */ -/******************************************************************************/ -/*!< ****************** Bit definition for COMPx_CSR register ********************/ -#define COMP_CSR_EN_Pos (0UL) -#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ -#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< COMPx enable bit */ -#define COMP_CSR_INMSEL_Pos (4UL) -#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00070000 */ -#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< COMPx input minus selection bit */ -#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00010000 */ -#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00020000 */ -#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00040000 */ -#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00080000 */ -#define COMP_CSR_INPSEL_Pos (8UL) -#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00100000 */ -#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< COMPx input plus selection bit */ -#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) -#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) -#define COMP_CSR_WINMODE_Pos (11UL) -#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000010 */ -#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< COMPx Windows mode selection bit */ -#define COMP_CSR_WINOUT_Pos (14UL) -#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00000008 */ -#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< COMPx polarity selection bit */ -#define COMP_CSR_POLARITY_Pos (15UL) -#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00000008 */ -#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< COMPx polarity selection bit */ -#define COMP_CSR_HYST_Pos (16UL) -#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00000300 */ -#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< COMPx hysteresis selection bits */ -#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00000100 */ -#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00000200 */ -#define COMP_CSR_PWRMODE_Pos (18UL) -#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00003000 */ -#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */ -#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00001000 */ -#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00002000 */ -#define COMP_CSR_BLANKSEL_Pos (20UL) -#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x0F000000 */ -#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< COMPx blanking source selection bits */ -#define COMP_CSR_BLANKSEL_0 (0x1UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ -#define COMP_CSR_BLANKSEL_1 (0x2UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x02000000 */ -#define COMP_CSR_BLANKSEL_2 (0x4UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x04000000 */ -#define COMP_CSR_BLANKSEL_3 (0x8UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x08000000 */ -#define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ -#define COMP2_CSR_BLANKSEL_2 COMP_CSR_BLANKSEL_2 /*!< COMP2 blanking source selection bit 2 */ -#define COMP_CSR_VALUE_Pos (30UL) -#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x00000001 */ -#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< COMPx enable bit */ -#define COMP_CSR_LOCK_Pos (31UL) -#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ -#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< COMPx Lock Bit */ - -/******************************************************************************/ -/* */ -/* Digital to Analog Converter */ -/* */ -/******************************************************************************/ -#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ - -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1_Pos (0UL) -#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ -#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14UL) -#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ -#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16UL) -#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ -#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30UL) -#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ -#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ -#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!(1)) */ - -#define HSP_ITFENR_TRGOEN_Pos (12UL) -#define HSP_ITFENR_TRGOEN_Msk (0x1UL << HSP_ITFENR_TRGOEN_Pos) /*!< 0x00001000 */ -#define HSP_ITFENR_TRGOEN HSP_ITFENR_TRGOEN_Msk /*!< TRGOEN (TRGO enable bit (1)) */ - -#define HSP_ITFENR_TRGI0EN_Pos (16UL) -#define HSP_ITFENR_TRGI0EN_Msk (0x1UL << HSP_ITFENR_TRGI0EN_Pos) /*!< 0x00010000 */ -#define HSP_ITFENR_TRGI0EN HSP_ITFENR_TRGI0EN_Msk /*!< TRGI0EN (TRGIN0 enable bit (1)) */ - -#define HSP_ITFENR_TRGI1EN_Pos (17UL) -#define HSP_ITFENR_TRGI1EN_Msk (0x1UL << HSP_ITFENR_TRGI1EN_Pos) /*!< 0x00020000 */ -#define HSP_ITFENR_TRGI1EN HSP_ITFENR_TRGI1EN_Msk /*!< TRGI1EN (TRGIN1 enable bit (1)) */ - -#define HSP_ITFENR_TRGI2EN_Pos (18UL) -#define HSP_ITFENR_TRGI2EN_Msk (0x1UL << HSP_ITFENR_TRGI2EN_Pos) /*!< 0x00040000 */ -#define HSP_ITFENR_TRGI2EN HSP_ITFENR_TRGI2EN_Msk /*!< TRGI2EN (TRGIN2 enable bit (1)) */ - -#define HSP_ITFENR_TRGI3EN_Pos (19UL) -#define HSP_ITFENR_TRGI3EN_Msk (0x1UL << HSP_ITFENR_TRGI3EN_Pos) /*!< 0x00080000 */ -#define HSP_ITFENR_TRGI3EN HSP_ITFENR_TRGI3EN_Msk /*!< TRGI3EN (TRGIN3 enable bit (1)) */ - -#define HSP_ITFENR_TRGI4EN_Pos (20UL) -#define HSP_ITFENR_TRGI4EN_Msk (0x1UL << HSP_ITFENR_TRGI4EN_Pos) /*!< 0x00100000 */ -#define HSP_ITFENR_TRGI4EN HSP_ITFENR_TRGI4EN_Msk /*!< TRGI4EN (TRGIN4 enable bit (1)) */ - -#define HSP_ITFENR_TRGI5EN_Pos (21UL) -#define HSP_ITFENR_TRGI5EN_Msk (0x1UL << HSP_ITFENR_TRGI5EN_Pos) /*!< 0x00200000 */ -#define HSP_ITFENR_TRGI5EN HSP_ITFENR_TRGI5EN_Msk /*!< TRGI5EN (TRGIN5 enable bit (1)) */ - -#define HSP_ITFENR_TRGI6EN_Pos (22UL) -#define HSP_ITFENR_TRGI6EN_Msk (0x1UL << HSP_ITFENR_TRGI6EN_Pos) /*!< 0x00400000 */ -#define HSP_ITFENR_TRGI6EN HSP_ITFENR_TRGI6EN_Msk /*!< TRGI6EN (TRGIN6 enable bit (1)) */ - -#define HSP_ITFENR_TRGI7EN_Pos (23UL) -#define HSP_ITFENR_TRGI7EN_Msk (0x1UL << HSP_ITFENR_TRGI7EN_Pos) /*!< 0x00800000 */ -#define HSP_ITFENR_TRGI7EN HSP_ITFENR_TRGI7EN_Msk /*!< TRGI7EN (TRGIN7 enable bit (1)) */ - -#define HSP_ITFENR_TRGI8EN_Pos (24UL) -#define HSP_ITFENR_TRGI8EN_Msk (0x1UL << HSP_ITFENR_TRGI8EN_Pos) /*!< 0x01000000 */ -#define HSP_ITFENR_TRGI8EN HSP_ITFENR_TRGI8EN_Msk /*!< TRGI8EN (TRGIN8 enable bit (1)) */ - -#define HSP_ITFENR_TRGI9EN_Pos (25UL) -#define HSP_ITFENR_TRGI9EN_Msk (0x1UL << HSP_ITFENR_TRGI9EN_Pos) /*!< 0x02000000 */ -#define HSP_ITFENR_TRGI9EN HSP_ITFENR_TRGI9EN_Msk /*!< TRGI9EN (TRGIN9 enable bit (1)) */ - -#define HSP_ITFENR_DCMDDIS_Pos (27UL) -#define HSP_ITFENR_DCMDDIS_Msk (0x1UL << HSP_ITFENR_DCMDDIS_Pos) /*!< 0x08000000 */ -#define HSP_ITFENR_DCMDDIS HSP_ITFENR_DCMDDIS_Msk /*!< DCMDDIS (Direct command interface disable bit ) */ - -#define HSP_ITFENR_CSEGEN_Pos (28UL) -#define HSP_ITFENR_CSEGEN_Msk (0x1UL << HSP_ITFENR_CSEGEN_Pos) /*!< 0x10000000 */ -#define HSP_ITFENR_CSEGEN HSP_ITFENR_CSEGEN_Msk /*!< CSEGEN (CSEG interface enable bit (1)) */ - -#define HSP_ITFENR_CDEGEN_Pos (29UL) -#define HSP_ITFENR_CDEGEN_Msk (0x1UL << HSP_ITFENR_CDEGEN_Pos) /*!< 0x20000000 */ -#define HSP_ITFENR_CDEGEN HSP_ITFENR_CDEGEN_Msk /*!< CDEGEN (CDEG interface enable bit ) */ - -#define HSP_ITFENR_HSEGEN_Pos (30UL) -#define HSP_ITFENR_HSEGEN_Msk (0x1UL << HSP_ITFENR_HSEGEN_Pos) /*!< 0x40000000 */ -#define HSP_ITFENR_HSEGEN HSP_ITFENR_HSEGEN_Msk /*!< HSEGEN (HSEG interface enable bit ) */ - -#define HSP_ITFENR_HDEGEN_Pos (31UL) -#define HSP_ITFENR_HDEGEN_Msk (0x1UL << HSP_ITFENR_HDEGEN_Pos) /*!< 0x80000000 */ -#define HSP_ITFENR_HDEGEN HSP_ITFENR_HDEGEN_Msk /*!< HDEGEN (HDEG interface enable bit ) */ - -/******************** Bit definition for HSP_EVTSRC0R register ********************/ -#define HSP_EVTSRC0R_EVT1SRC_Pos (0UL) -#define HSP_EVTSRC0R_EVT1SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000007 */ -#define HSP_EVTSRC0R_EVT1SRC HSP_EVTSRC0R_EVT1SRC_Msk /*!< EVT1SRC[2:0] bits (Event source selection for priority encoder input 1) */ -#define HSP_EVTSRC0R_EVT1SRC_0 (0x1UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000001 */ -#define HSP_EVTSRC0R_EVT1SRC_1 (0x2UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000002 */ -#define HSP_EVTSRC0R_EVT1SRC_2 (0x4UL << HSP_EVTSRC0R_EVT1SRC_Pos) /*!< 0x00000004 */ - -#define HSP_EVTSRC0R_EVT2SRC_Pos (4UL) -#define HSP_EVTSRC0R_EVT2SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000070 */ -#define HSP_EVTSRC0R_EVT2SRC HSP_EVTSRC0R_EVT2SRC_Msk /*!< EVT2SRC[2:0] bits (Event source selection for priority encoder input 2) */ -#define HSP_EVTSRC0R_EVT2SRC_0 (0x1UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000010 */ -#define HSP_EVTSRC0R_EVT2SRC_1 (0x2UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000020 */ -#define HSP_EVTSRC0R_EVT2SRC_2 (0x4UL << HSP_EVTSRC0R_EVT2SRC_Pos) /*!< 0x00000040 */ - -#define HSP_EVTSRC0R_EVT3SRC_Pos (8UL) -#define HSP_EVTSRC0R_EVT3SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000700 */ -#define HSP_EVTSRC0R_EVT3SRC HSP_EVTSRC0R_EVT3SRC_Msk /*!< EVT3SRC[2:0] bits (Event source selection for priority encoder input 3) */ -#define HSP_EVTSRC0R_EVT3SRC_0 (0x1UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000100 */ -#define HSP_EVTSRC0R_EVT3SRC_1 (0x2UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000200 */ -#define HSP_EVTSRC0R_EVT3SRC_2 (0x4UL << HSP_EVTSRC0R_EVT3SRC_Pos) /*!< 0x00000400 */ - -#define HSP_EVTSRC0R_EVT4SRC_Pos (12UL) -#define HSP_EVTSRC0R_EVT4SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00007000 */ -#define HSP_EVTSRC0R_EVT4SRC HSP_EVTSRC0R_EVT4SRC_Msk /*!< EVT4SRC[2:0] bits (Event source selection for priority encoder input 4) */ -#define HSP_EVTSRC0R_EVT4SRC_0 (0x1UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00001000 */ -#define HSP_EVTSRC0R_EVT4SRC_1 (0x2UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00002000 */ -#define HSP_EVTSRC0R_EVT4SRC_2 (0x4UL << HSP_EVTSRC0R_EVT4SRC_Pos) /*!< 0x00004000 */ - -#define HSP_EVTSRC0R_EVT5SRC_Pos (16UL) -#define HSP_EVTSRC0R_EVT5SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00070000 */ -#define HSP_EVTSRC0R_EVT5SRC HSP_EVTSRC0R_EVT5SRC_Msk /*!< EVT5SRC[2:0] bits (Event source selection for priority encoder input 5) */ -#define HSP_EVTSRC0R_EVT5SRC_0 (0x1UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00010000 */ -#define HSP_EVTSRC0R_EVT5SRC_1 (0x2UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00020000 */ -#define HSP_EVTSRC0R_EVT5SRC_2 (0x4UL << HSP_EVTSRC0R_EVT5SRC_Pos) /*!< 0x00040000 */ - -#define HSP_EVTSRC0R_EVT6SRC_Pos (20UL) -#define HSP_EVTSRC0R_EVT6SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00700000 */ -#define HSP_EVTSRC0R_EVT6SRC HSP_EVTSRC0R_EVT6SRC_Msk /*!< EVT6SRC[2:0] bits (Event source selection for priority encoder input 6) */ -#define HSP_EVTSRC0R_EVT6SRC_0 (0x1UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00100000 */ -#define HSP_EVTSRC0R_EVT6SRC_1 (0x2UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00200000 */ -#define HSP_EVTSRC0R_EVT6SRC_2 (0x4UL << HSP_EVTSRC0R_EVT6SRC_Pos) /*!< 0x00400000 */ - -#define HSP_EVTSRC0R_EVT7SRC_Pos (24UL) -#define HSP_EVTSRC0R_EVT7SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x07000000 */ -#define HSP_EVTSRC0R_EVT7SRC HSP_EVTSRC0R_EVT7SRC_Msk /*!< EVT7SRC[2:0] bits (Event source selection for priority encoder input 7) */ -#define HSP_EVTSRC0R_EVT7SRC_0 (0x1UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x01000000 */ -#define HSP_EVTSRC0R_EVT7SRC_1 (0x2UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x02000000 */ -#define HSP_EVTSRC0R_EVT7SRC_2 (0x4UL << HSP_EVTSRC0R_EVT7SRC_Pos) /*!< 0x04000000 */ - -#define HSP_EVTSRC0R_EVT8SRC_Pos (28UL) -#define HSP_EVTSRC0R_EVT8SRC_Msk (0x7UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x70000000 */ -#define HSP_EVTSRC0R_EVT8SRC HSP_EVTSRC0R_EVT8SRC_Msk /*!< EVT8SRC[2:0] bits (Event source selection for priority encoder input 8) */ -#define HSP_EVTSRC0R_EVT8SRC_0 (0x1UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x10000000 */ -#define HSP_EVTSRC0R_EVT8SRC_1 (0x2UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x20000000 */ -#define HSP_EVTSRC0R_EVT8SRC_2 (0x4UL << HSP_EVTSRC0R_EVT8SRC_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for HSP_EVTSRC1R register ********************/ -#define HSP_EVTSRC1R_EVT9SRC_Pos (0UL) -#define HSP_EVTSRC1R_EVT9SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000007 */ -#define HSP_EVTSRC1R_EVT9SRC HSP_EVTSRC1R_EVT9SRC_Msk /*!< EVT9SRC[2:0] bits (Event source selection for priority encoder input 9) */ -#define HSP_EVTSRC1R_EVT9SRC_0 (0x1UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000001 */ -#define HSP_EVTSRC1R_EVT9SRC_1 (0x2UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000002 */ -#define HSP_EVTSRC1R_EVT9SRC_2 (0x4UL << HSP_EVTSRC1R_EVT9SRC_Pos) /*!< 0x00000004 */ - -#define HSP_EVTSRC1R_EVT10SRC_Pos (4UL) -#define HSP_EVTSRC1R_EVT10SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000070 */ -#define HSP_EVTSRC1R_EVT10SRC HSP_EVTSRC1R_EVT10SRC_Msk /*!< EVT10SRC[2:0] bits (Event source selection for priority encoder input 10) */ -#define HSP_EVTSRC1R_EVT10SRC_0 (0x1UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000010 */ -#define HSP_EVTSRC1R_EVT10SRC_1 (0x2UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000020 */ -#define HSP_EVTSRC1R_EVT10SRC_2 (0x4UL << HSP_EVTSRC1R_EVT10SRC_Pos) /*!< 0x00000040 */ - -#define HSP_EVTSRC1R_EVT11SRC_Pos (8UL) -#define HSP_EVTSRC1R_EVT11SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000700 */ -#define HSP_EVTSRC1R_EVT11SRC HSP_EVTSRC1R_EVT11SRC_Msk /*!< EVT11SRC[2:0] bits (Event source selection for priority encoder input 11) */ -#define HSP_EVTSRC1R_EVT11SRC_0 (0x1UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000100 */ -#define HSP_EVTSRC1R_EVT11SRC_1 (0x2UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000200 */ -#define HSP_EVTSRC1R_EVT11SRC_2 (0x4UL << HSP_EVTSRC1R_EVT11SRC_Pos) /*!< 0x00000400 */ - -#define HSP_EVTSRC1R_EVT12SRC_Pos (12UL) -#define HSP_EVTSRC1R_EVT12SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00007000 */ -#define HSP_EVTSRC1R_EVT12SRC HSP_EVTSRC1R_EVT12SRC_Msk /*!< EVT12SRC[2:0] bits (Event source selection for priority encoder input 12) */ -#define HSP_EVTSRC1R_EVT12SRC_0 (0x1UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00001000 */ -#define HSP_EVTSRC1R_EVT12SRC_1 (0x2UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00002000 */ -#define HSP_EVTSRC1R_EVT12SRC_2 (0x4UL << HSP_EVTSRC1R_EVT12SRC_Pos) /*!< 0x00004000 */ - -#define HSP_EVTSRC1R_EVT13SRC_Pos (16UL) -#define HSP_EVTSRC1R_EVT13SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00070000 */ -#define HSP_EVTSRC1R_EVT13SRC HSP_EVTSRC1R_EVT13SRC_Msk /*!< EVT13SRC[2:0] bits (Event source selection for priority encoder input 13) */ -#define HSP_EVTSRC1R_EVT13SRC_0 (0x1UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00010000 */ -#define HSP_EVTSRC1R_EVT13SRC_1 (0x2UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00020000 */ -#define HSP_EVTSRC1R_EVT13SRC_2 (0x4UL << HSP_EVTSRC1R_EVT13SRC_Pos) /*!< 0x00040000 */ - -#define HSP_EVTSRC1R_EVT14SRC_Pos (20UL) -#define HSP_EVTSRC1R_EVT14SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00700000 */ -#define HSP_EVTSRC1R_EVT14SRC HSP_EVTSRC1R_EVT14SRC_Msk /*!< EVT14SRC[2:0] bits (Event source selection for priority encoder input 14) */ -#define HSP_EVTSRC1R_EVT14SRC_0 (0x1UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00100000 */ -#define HSP_EVTSRC1R_EVT14SRC_1 (0x2UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00200000 */ -#define HSP_EVTSRC1R_EVT14SRC_2 (0x4UL << HSP_EVTSRC1R_EVT14SRC_Pos) /*!< 0x00400000 */ - -#define HSP_EVTSRC1R_EVT15SRC_Pos (24UL) -#define HSP_EVTSRC1R_EVT15SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x07000000 */ -#define HSP_EVTSRC1R_EVT15SRC HSP_EVTSRC1R_EVT15SRC_Msk /*!< EVT15SRC[2:0] bits (Event source selection for priority encoder input 15) */ -#define HSP_EVTSRC1R_EVT15SRC_0 (0x1UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x01000000 */ -#define HSP_EVTSRC1R_EVT15SRC_1 (0x2UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x02000000 */ -#define HSP_EVTSRC1R_EVT15SRC_2 (0x4UL << HSP_EVTSRC1R_EVT15SRC_Pos) /*!< 0x04000000 */ - -#define HSP_EVTSRC1R_EVT16SRC_Pos (28UL) -#define HSP_EVTSRC1R_EVT16SRC_Msk (0x7UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x70000000 */ -#define HSP_EVTSRC1R_EVT16SRC HSP_EVTSRC1R_EVT16SRC_Msk /*!< EVT16SRC[2:0] bits (Event source selection for priority encoder input 16) */ -#define HSP_EVTSRC1R_EVT16SRC_0 (0x1UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x10000000 */ -#define HSP_EVTSRC1R_EVT16SRC_1 (0x2UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x20000000 */ -#define HSP_EVTSRC1R_EVT16SRC_2 (0x4UL << HSP_EVTSRC1R_EVT16SRC_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for HSP_EVTSRC2R register ********************/ -#define HSP_EVTSRC2R_EVT17SRC_Pos (0UL) -#define HSP_EVTSRC2R_EVT17SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000007 */ -#define HSP_EVTSRC2R_EVT17SRC HSP_EVTSRC2R_EVT17SRC_Msk /*!< EVT17SRC[2:0] bits (Event source selection for priority encoder input 17) */ -#define HSP_EVTSRC2R_EVT17SRC_0 (0x1UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000001 */ -#define HSP_EVTSRC2R_EVT17SRC_1 (0x2UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000002 */ -#define HSP_EVTSRC2R_EVT17SRC_2 (0x4UL << HSP_EVTSRC2R_EVT17SRC_Pos) /*!< 0x00000004 */ - -#define HSP_EVTSRC2R_EVT18SRC_Pos (4UL) -#define HSP_EVTSRC2R_EVT18SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000070 */ -#define HSP_EVTSRC2R_EVT18SRC HSP_EVTSRC2R_EVT18SRC_Msk /*!< EVT18SRC[2:0] bits (Event source selection for priority encoder input 18) */ -#define HSP_EVTSRC2R_EVT18SRC_0 (0x1UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000010 */ -#define HSP_EVTSRC2R_EVT18SRC_1 (0x2UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000020 */ -#define HSP_EVTSRC2R_EVT18SRC_2 (0x4UL << HSP_EVTSRC2R_EVT18SRC_Pos) /*!< 0x00000040 */ - -#define HSP_EVTSRC2R_EVT19SRC_Pos (8UL) -#define HSP_EVTSRC2R_EVT19SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000700 */ -#define HSP_EVTSRC2R_EVT19SRC HSP_EVTSRC2R_EVT19SRC_Msk /*!< EVT19SRC[2:0] bits (Event source selection for priority encoder input 19) */ -#define HSP_EVTSRC2R_EVT19SRC_0 (0x1UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000100 */ -#define HSP_EVTSRC2R_EVT19SRC_1 (0x2UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000200 */ -#define HSP_EVTSRC2R_EVT19SRC_2 (0x4UL << HSP_EVTSRC2R_EVT19SRC_Pos) /*!< 0x00000400 */ - -#define HSP_EVTSRC2R_EVT20SRC_Pos (12UL) -#define HSP_EVTSRC2R_EVT20SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00007000 */ -#define HSP_EVTSRC2R_EVT20SRC HSP_EVTSRC2R_EVT20SRC_Msk /*!< EVT20SRC[2:0] bits (Event source selection for priority encoder input 20) */ -#define HSP_EVTSRC2R_EVT20SRC_0 (0x1UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00001000 */ -#define HSP_EVTSRC2R_EVT20SRC_1 (0x2UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00002000 */ -#define HSP_EVTSRC2R_EVT20SRC_2 (0x4UL << HSP_EVTSRC2R_EVT20SRC_Pos) /*!< 0x00004000 */ - -#define HSP_EVTSRC2R_EVT21SRC_Pos (16UL) -#define HSP_EVTSRC2R_EVT21SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00070000 */ -#define HSP_EVTSRC2R_EVT21SRC HSP_EVTSRC2R_EVT21SRC_Msk /*!< EVT21SRC[2:0] bits (Event source selection for priority encoder input 21) */ -#define HSP_EVTSRC2R_EVT21SRC_0 (0x1UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00010000 */ -#define HSP_EVTSRC2R_EVT21SRC_1 (0x2UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00020000 */ -#define HSP_EVTSRC2R_EVT21SRC_2 (0x4UL << HSP_EVTSRC2R_EVT21SRC_Pos) /*!< 0x00040000 */ - -#define HSP_EVTSRC2R_EVT22SRC_Pos (20UL) -#define HSP_EVTSRC2R_EVT22SRC_Msk (0x7UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00700000 */ -#define HSP_EVTSRC2R_EVT22SRC HSP_EVTSRC2R_EVT22SRC_Msk /*!< EVT22SRC[2:0] bits (Event source selection for priority encoder input 22) */ -#define HSP_EVTSRC2R_EVT22SRC_0 (0x1UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00100000 */ -#define HSP_EVTSRC2R_EVT22SRC_1 (0x2UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00200000 */ -#define HSP_EVTSRC2R_EVT22SRC_2 (0x4UL << HSP_EVTSRC2R_EVT22SRC_Pos) /*!< 0x00400000 */ - -/******************** Bit definition for HSP_BUFFCFGR register ********************/ -#define HSP_BUFFCFGR_BUFF0DIR_Pos (0UL) -#define HSP_BUFFCFGR_BUFF0DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF0DIR_Pos) /*!< 0x00000001 */ -#define HSP_BUFFCFGR_BUFF0DIR HSP_BUFFCFGR_BUFF0DIR_Msk /*!< BUFF0DIR (Direction selection of BUFF0 (1)) */ - -#define HSP_BUFFCFGR_BUFF1DIR_Pos (1UL) -#define HSP_BUFFCFGR_BUFF1DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF1DIR_Pos) /*!< 0x00000002 */ -#define HSP_BUFFCFGR_BUFF1DIR HSP_BUFFCFGR_BUFF1DIR_Msk /*!< BUFF1DIR (Direction selection of BUFF1 (1)) */ - -#define HSP_BUFFCFGR_BUFF2DIR_Pos (2UL) -#define HSP_BUFFCFGR_BUFF2DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF2DIR_Pos) /*!< 0x00000004 */ -#define HSP_BUFFCFGR_BUFF2DIR HSP_BUFFCFGR_BUFF2DIR_Msk /*!< BUFF2DIR (Direction selection of BUFF2 (1)) */ - -#define HSP_BUFFCFGR_BUFF3DIR_Pos (3UL) -#define HSP_BUFFCFGR_BUFF3DIR_Msk (0x1UL << HSP_BUFFCFGR_BUFF3DIR_Pos) /*!< 0x00000008 */ -#define HSP_BUFFCFGR_BUFF3DIR HSP_BUFFCFGR_BUFF3DIR_Msk /*!< BUFF3DIR (Direction selection of BUFF3 (1)) */ - -#define HSP_BUFFCFGR_I2FEN_Pos (8UL) -#define HSP_BUFFCFGR_I2FEN_Msk (0x1UL << HSP_BUFFCFGR_I2FEN_Pos) /*!< 0x00000100 */ -#define HSP_BUFFCFGR_I2FEN HSP_BUFFCFGR_I2FEN_Msk /*!< I2FEN (integer to float32 conversion (1)) */ - -#define HSP_BUFFCFGR_COMB0_Pos (16UL) -#define HSP_BUFFCFGR_COMB0_Msk (0x1UL << HSP_BUFFCFGR_COMB0_Pos) /*!< 0x00010000 */ -#define HSP_BUFFCFGR_COMB0 HSP_BUFFCFGR_COMB0_Msk /*!< COMB0 (BUFCMB control for buff_evt[0] (1)) */ - -#define HSP_BUFFCFGR_COMB1_Pos (17UL) -#define HSP_BUFFCFGR_COMB1_Msk (0x1UL << HSP_BUFFCFGR_COMB1_Pos) /*!< 0x00020000 */ -#define HSP_BUFFCFGR_COMB1 HSP_BUFFCFGR_COMB1_Msk /*!< COMB1 (BUFCMB control for buff_evt[1] (1)) */ - -#define HSP_BUFFCFGR_COMB2_Pos (18UL) -#define HSP_BUFFCFGR_COMB2_Msk (0x1UL << HSP_BUFFCFGR_COMB2_Pos) /*!< 0x00040000 */ -#define HSP_BUFFCFGR_COMB2 HSP_BUFFCFGR_COMB2_Msk /*!< COMB2 (BUFCMB control for buff_evt[2] ) */ - -/******************** Bit definition for HSP_BUFFxDR register ********************/ -#define HSP_BUFFDR_BUFFDAT_Pos (0UL) -#define HSP_BUFFDR_BUFFDAT_Msk (0xFFFFFFFFUL << HSP_BUFFDR_BUFFDAT_Pos) /*!< 0xFFFFFFFF */ -#define HSP_BUFFDR_BUFFDAT HSP_BUFFDR_BUFFDAT_Msk /*!< BUFFDAT[31:0] bits (Data buffer) */ - -/******************** Bit definition for HSP_TRGINCFGR register ********************/ -#define HSP_TRGINCFGR_TRG0POL_Pos (0UL) -#define HSP_TRGINCFGR_TRG0POL_Msk (0x1UL << HSP_TRGINCFGR_TRG0POL_Pos) /*!< 0x00000001 */ -#define HSP_TRGINCFGR_TRG0POL HSP_TRGINCFGR_TRG0POL_Msk /*!< TRG0POL (Polarity selection for TRGIN0) */ - -#define HSP_TRGINCFGR_TRG1POL_Pos (1UL) -#define HSP_TRGINCFGR_TRG1POL_Msk (0x1UL << HSP_TRGINCFGR_TRG1POL_Pos) /*!< 0x00000002 */ -#define HSP_TRGINCFGR_TRG1POL HSP_TRGINCFGR_TRG1POL_Msk /*!< TRG1POL (Polarity selection for TRGIN1) */ - -#define HSP_TRGINCFGR_TRG2POL_Pos (2UL) -#define HSP_TRGINCFGR_TRG2POL_Msk (0x1UL << HSP_TRGINCFGR_TRG2POL_Pos) /*!< 0x00000004 */ -#define HSP_TRGINCFGR_TRG2POL HSP_TRGINCFGR_TRG2POL_Msk /*!< TRG2POL (Polarity selection for TRGIN2) */ - -#define HSP_TRGINCFGR_TRG3POL_Pos (3UL) -#define HSP_TRGINCFGR_TRG3POL_Msk (0x1UL << HSP_TRGINCFGR_TRG3POL_Pos) /*!< 0x00000008 */ -#define HSP_TRGINCFGR_TRG3POL HSP_TRGINCFGR_TRG3POL_Msk /*!< TRG3POL (Polarity selection for TRGIN3) */ - -#define HSP_TRGINCFGR_TRG4POL_Pos (4UL) -#define HSP_TRGINCFGR_TRG4POL_Msk (0x1UL << HSP_TRGINCFGR_TRG4POL_Pos) /*!< 0x00000010 */ -#define HSP_TRGINCFGR_TRG4POL HSP_TRGINCFGR_TRG4POL_Msk /*!< TRG4POL (Polarity selection for TRGIN4) */ - -#define HSP_TRGINCFGR_TRG5POL_Pos (5UL) -#define HSP_TRGINCFGR_TRG5POL_Msk (0x1UL << HSP_TRGINCFGR_TRG5POL_Pos) /*!< 0x00000020 */ -#define HSP_TRGINCFGR_TRG5POL HSP_TRGINCFGR_TRG5POL_Msk /*!< TRG5POL (Polarity selection for TRGIN5) */ - -#define HSP_TRGINCFGR_TRG6POL_Pos (6UL) -#define HSP_TRGINCFGR_TRG6POL_Msk (0x1UL << HSP_TRGINCFGR_TRG6POL_Pos) /*!< 0x00000040 */ -#define HSP_TRGINCFGR_TRG6POL HSP_TRGINCFGR_TRG6POL_Msk /*!< TRG6POL (Polarity selection for TRGIN6) */ - -#define HSP_TRGINCFGR_TRG7POL_Pos (7UL) -#define HSP_TRGINCFGR_TRG7POL_Msk (0x1UL << HSP_TRGINCFGR_TRG7POL_Pos) /*!< 0x00000080 */ -#define HSP_TRGINCFGR_TRG7POL HSP_TRGINCFGR_TRG7POL_Msk /*!< TRG7POL (Polarity selection for TRGIN7) */ - -#define HSP_TRGINCFGR_TRG8POL_Pos (8UL) -#define HSP_TRGINCFGR_TRG8POL_Msk (0x1UL << HSP_TRGINCFGR_TRG8POL_Pos) /*!< 0x00000100 */ -#define HSP_TRGINCFGR_TRG8POL HSP_TRGINCFGR_TRG8POL_Msk /*!< TRG8POL (Polarity selection for TRGIN8) */ - -#define HSP_TRGINCFGR_TRG9POL_Pos (9UL) -#define HSP_TRGINCFGR_TRG9POL_Msk (0x1UL << HSP_TRGINCFGR_TRG9POL_Pos) /*!< 0x00000200 */ -#define HSP_TRGINCFGR_TRG9POL HSP_TRGINCFGR_TRG9POL_Msk /*!< TRG9POL (Polarity selection for TRGIN9) */ - -/******************** Bit definition for HSP_TRGOCFGR register ********************/ -#define HSP_TRGOCFGR_TRGO0SRC_Pos (0UL) -#define HSP_TRGOCFGR_TRGO0SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000003 */ -#define HSP_TRGOCFGR_TRGO0SRC HSP_TRGOCFGR_TRGO0SRC_Msk /*!< TRGO0SRC[1:0] bits (Trigger source selection for hsp_trg_out[0] (1)) */ -#define HSP_TRGOCFGR_TRGO0SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000001 */ -#define HSP_TRGOCFGR_TRGO0SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO0SRC_Pos) /*!< 0x00000002 */ - -#define HSP_TRGOCFGR_TRGO1SRC_Pos (2UL) -#define HSP_TRGOCFGR_TRGO1SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x0000000C */ -#define HSP_TRGOCFGR_TRGO1SRC HSP_TRGOCFGR_TRGO1SRC_Msk /*!< TRGO1SRC[1:0] bits (Trigger source selection for hsp_trg_out[1] (1)) */ -#define HSP_TRGOCFGR_TRGO1SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x00000004 */ -#define HSP_TRGOCFGR_TRGO1SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO1SRC_Pos) /*!< 0x00000008 */ - -#define HSP_TRGOCFGR_TRGO2SRC_Pos (4UL) -#define HSP_TRGOCFGR_TRGO2SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000030 */ -#define HSP_TRGOCFGR_TRGO2SRC HSP_TRGOCFGR_TRGO2SRC_Msk /*!< TRGO2SRC[1:0] bits (Trigger source selection for hsp_trg_out[2] (1)) */ -#define HSP_TRGOCFGR_TRGO2SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000010 */ -#define HSP_TRGOCFGR_TRGO2SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO2SRC_Pos) /*!< 0x00000020 */ - -#define HSP_TRGOCFGR_TRGO3SRC_Pos (6UL) -#define HSP_TRGOCFGR_TRGO3SRC_Msk (0x3UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x000000C0 */ -#define HSP_TRGOCFGR_TRGO3SRC HSP_TRGOCFGR_TRGO3SRC_Msk /*!< TRGO3SRC[1:0] bits (Trigger source selection for hsp_trg_out[3] ) */ -#define HSP_TRGOCFGR_TRGO3SRC_0 (0x1UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x00000040 */ -#define HSP_TRGOCFGR_TRGO3SRC_1 (0x2UL << HSP_TRGOCFGR_TRGO3SRC_Pos) /*!< 0x00000080 */ - -/******************** Bit definition for HSP_CSEGR register ********************/ -#define HSP_CSEGR_CSEVT_Pos (1UL) -#define HSP_CSEGR_CSEVT_Msk (0x3FFFFFUL << HSP_CSEGR_CSEVT_Pos) /*!< 0x007FFFFE */ -#define HSP_CSEGR_CSEVT HSP_CSEGR_CSEVT_Msk /*!< CSEVT[21:0] bits (CPU Shared Software Event ) */ -#define HSP_CSEGR_CSEVT_0 (0x0001UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000002 */ -#define HSP_CSEGR_CSEVT_1 (0x0002UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000004 */ -#define HSP_CSEGR_CSEVT_2 (0x0004UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000008 */ -#define HSP_CSEGR_CSEVT_3 (0x0008UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000010 */ -#define HSP_CSEGR_CSEVT_4 (0x0010UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000020 */ -#define HSP_CSEGR_CSEVT_5 (0x0020UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000040 */ -#define HSP_CSEGR_CSEVT_6 (0x0040UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000080 */ -#define HSP_CSEGR_CSEVT_7 (0x0080UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000100 */ -#define HSP_CSEGR_CSEVT_8 (0x0100UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000200 */ -#define HSP_CSEGR_CSEVT_9 (0x0200UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000400 */ -#define HSP_CSEGR_CSEVT_10 (0x0400UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00000800 */ -#define HSP_CSEGR_CSEVT_11 (0x0800UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00001000 */ -#define HSP_CSEGR_CSEVT_12 (0x1000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00002000 */ -#define HSP_CSEGR_CSEVT_13 (0x2000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00004000 */ -#define HSP_CSEGR_CSEVT_14 (0x4000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00008000 */ -#define HSP_CSEGR_CSEVT_15 (0x8000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00010000 */ -#define HSP_CSEGR_CSEVT_16 (0x10000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00020000 */ -#define HSP_CSEGR_CSEVT_17 (0x20000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00040000 */ -#define HSP_CSEGR_CSEVT_18 (0x40000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00080000 */ -#define HSP_CSEGR_CSEVT_19 (0x80000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00100000 */ -#define HSP_CSEGR_CSEVT_20 (0x100000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00200000 */ -#define HSP_CSEGR_CSEVT_21 (0x200000UL << HSP_CSEGR_CSEVT_Pos) /*!< 0x00400000 */ - -/******************** Bit definition for HSP_CDEGR register ********************/ -#define HSP_CDEGR_CTSKN_Pos (0UL) -#define HSP_CDEGR_CTSKN_Msk (0x3FUL << HSP_CDEGR_CTSKN_Pos) /*!< 0x0000003F */ -#define HSP_CDEGR_CTSKN HSP_CDEGR_CTSKN_Msk /*!< CTSKN[5:0] bits (CPU Task number) */ - -#define HSP_CDEGR_CDEGBSY_Pos (31UL) -#define HSP_CDEGR_CDEGBSY_Msk (0x1UL << HSP_CDEGR_CDEGBSY_Pos) /*!< 0x80000000 */ -#define HSP_CDEGR_CDEGBSY HSP_CDEGR_CDEGBSY_Msk /*!< CDEGBSY (CPU dedicated event generator busy) */ - -/******************** Bit definition for HSP_TRGINSELR0 register ********************/ -#define HSP_TRGINSELR0_TRG0SEL_Pos (0UL) -#define HSP_TRGINSELR0_TRG0SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x0000003F */ -#define HSP_TRGINSELR0_TRG0SEL HSP_TRGINSELR0_TRG0SEL_Msk /*!< TRG0SEL[5:0] bits (Input trigger selection for TRGIN0) */ -#define HSP_TRGINSELR0_TRG0SEL_0 (0x01UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000001 */ -#define HSP_TRGINSELR0_TRG0SEL_1 (0x02UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000002 */ -#define HSP_TRGINSELR0_TRG0SEL_2 (0x04UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000004 */ -#define HSP_TRGINSELR0_TRG0SEL_3 (0x08UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000008 */ -#define HSP_TRGINSELR0_TRG0SEL_4 (0x10UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000010 */ -#define HSP_TRGINSELR0_TRG0SEL_5 (0x20UL << HSP_TRGINSELR0_TRG0SEL_Pos) /*!< 0x00000020 */ - -#define HSP_TRGINSELR0_TRG1SEL_Pos (8UL) -#define HSP_TRGINSELR0_TRG1SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00003F00 */ -#define HSP_TRGINSELR0_TRG1SEL HSP_TRGINSELR0_TRG1SEL_Msk /*!< TRG1SEL[5:0] bits (Input trigger selection for TRGIN1) */ -#define HSP_TRGINSELR0_TRG1SEL_0 (0x01UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000100 */ -#define HSP_TRGINSELR0_TRG1SEL_1 (0x02UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000200 */ -#define HSP_TRGINSELR0_TRG1SEL_2 (0x04UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000400 */ -#define HSP_TRGINSELR0_TRG1SEL_3 (0x08UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00000800 */ -#define HSP_TRGINSELR0_TRG1SEL_4 (0x10UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00001000 */ -#define HSP_TRGINSELR0_TRG1SEL_5 (0x20UL << HSP_TRGINSELR0_TRG1SEL_Pos) /*!< 0x00002000 */ - -#define HSP_TRGINSELR0_TRG2SEL_Pos (16UL) -#define HSP_TRGINSELR0_TRG2SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x003F0000 */ -#define HSP_TRGINSELR0_TRG2SEL HSP_TRGINSELR0_TRG2SEL_Msk /*!< TRG2SEL[5:0] bits (Input trigger selection for TRGIN2) */ -#define HSP_TRGINSELR0_TRG2SEL_0 (0x01UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00010000 */ -#define HSP_TRGINSELR0_TRG2SEL_1 (0x02UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00020000 */ -#define HSP_TRGINSELR0_TRG2SEL_2 (0x04UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00040000 */ -#define HSP_TRGINSELR0_TRG2SEL_3 (0x08UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00080000 */ -#define HSP_TRGINSELR0_TRG2SEL_4 (0x10UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00100000 */ -#define HSP_TRGINSELR0_TRG2SEL_5 (0x20UL << HSP_TRGINSELR0_TRG2SEL_Pos) /*!< 0x00200000 */ - -#define HSP_TRGINSELR0_TRG3SEL_Pos (24UL) -#define HSP_TRGINSELR0_TRG3SEL_Msk (0x3FUL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x3F000000 */ -#define HSP_TRGINSELR0_TRG3SEL HSP_TRGINSELR0_TRG3SEL_Msk /*!< TRG3SEL[5:0] bits (Input trigger selection for TRGIN3) */ -#define HSP_TRGINSELR0_TRG3SEL_0 (0x01UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x01000000 */ -#define HSP_TRGINSELR0_TRG3SEL_1 (0x02UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x02000000 */ -#define HSP_TRGINSELR0_TRG3SEL_2 (0x04UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x04000000 */ -#define HSP_TRGINSELR0_TRG3SEL_3 (0x08UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x08000000 */ -#define HSP_TRGINSELR0_TRG3SEL_4 (0x10UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x10000000 */ -#define HSP_TRGINSELR0_TRG3SEL_5 (0x20UL << HSP_TRGINSELR0_TRG3SEL_Pos) /*!< 0x20000000 */ - -/******************** Bit definition for HSP_TRGINSELR1 register ********************/ -#define HSP_TRGINSELR1_TRG4SEL_Pos (0UL) -#define HSP_TRGINSELR1_TRG4SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x0000003F */ -#define HSP_TRGINSELR1_TRG4SEL HSP_TRGINSELR1_TRG4SEL_Msk /*!< TRG4SEL[5:0] bits (Input trigger selection for TRGIN4) */ -#define HSP_TRGINSELR1_TRG4SEL_0 (0x01UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000001 */ -#define HSP_TRGINSELR1_TRG4SEL_1 (0x02UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000002 */ -#define HSP_TRGINSELR1_TRG4SEL_2 (0x04UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000004 */ -#define HSP_TRGINSELR1_TRG4SEL_3 (0x08UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000008 */ -#define HSP_TRGINSELR1_TRG4SEL_4 (0x10UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000010 */ -#define HSP_TRGINSELR1_TRG4SEL_5 (0x20UL << HSP_TRGINSELR1_TRG4SEL_Pos) /*!< 0x00000020 */ - -#define HSP_TRGINSELR1_TRG5SEL_Pos (8UL) -#define HSP_TRGINSELR1_TRG5SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00003F00 */ -#define HSP_TRGINSELR1_TRG5SEL HSP_TRGINSELR1_TRG5SEL_Msk /*!< TRG5SEL[5:0] bits (Input trigger selection for TRGIN5) */ -#define HSP_TRGINSELR1_TRG5SEL_0 (0x01UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000100 */ -#define HSP_TRGINSELR1_TRG5SEL_1 (0x02UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000200 */ -#define HSP_TRGINSELR1_TRG5SEL_2 (0x04UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000400 */ -#define HSP_TRGINSELR1_TRG5SEL_3 (0x08UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00000800 */ -#define HSP_TRGINSELR1_TRG5SEL_4 (0x10UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00001000 */ -#define HSP_TRGINSELR1_TRG5SEL_5 (0x20UL << HSP_TRGINSELR1_TRG5SEL_Pos) /*!< 0x00002000 */ - -#define HSP_TRGINSELR1_TRG6SEL_Pos (16UL) -#define HSP_TRGINSELR1_TRG6SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x003F0000 */ -#define HSP_TRGINSELR1_TRG6SEL HSP_TRGINSELR1_TRG6SEL_Msk /*!< TRG6SEL[5:0] bits (Input trigger selection for TRGIN6) */ -#define HSP_TRGINSELR1_TRG6SEL_0 (0x01UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00010000 */ -#define HSP_TRGINSELR1_TRG6SEL_1 (0x02UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00020000 */ -#define HSP_TRGINSELR1_TRG6SEL_2 (0x04UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00040000 */ -#define HSP_TRGINSELR1_TRG6SEL_3 (0x08UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00080000 */ -#define HSP_TRGINSELR1_TRG6SEL_4 (0x10UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00100000 */ -#define HSP_TRGINSELR1_TRG6SEL_5 (0x20UL << HSP_TRGINSELR1_TRG6SEL_Pos) /*!< 0x00200000 */ - -#define HSP_TRGINSELR1_TRG7SEL_Pos (24UL) -#define HSP_TRGINSELR1_TRG7SEL_Msk (0x3FUL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x3F000000 */ -#define HSP_TRGINSELR1_TRG7SEL HSP_TRGINSELR1_TRG7SEL_Msk /*!< TRG7SEL[5:0] bits (Input trigger selection for TRGIN7) */ -#define HSP_TRGINSELR1_TRG7SEL_0 (0x01UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x01000000 */ -#define HSP_TRGINSELR1_TRG7SEL_1 (0x02UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x02000000 */ -#define HSP_TRGINSELR1_TRG7SEL_2 (0x04UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x04000000 */ -#define HSP_TRGINSELR1_TRG7SEL_3 (0x08UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x08000000 */ -#define HSP_TRGINSELR1_TRG7SEL_4 (0x10UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x10000000 */ -#define HSP_TRGINSELR1_TRG7SEL_5 (0x20UL << HSP_TRGINSELR1_TRG7SEL_Pos) /*!< 0x20000000 */ - -/******************** Bit definition for HSP_TRGINSELR2 register ********************/ -#define HSP_TRGINSELR2_TRG8SEL_Pos (0UL) -#define HSP_TRGINSELR2_TRG8SEL_Msk (0x3FUL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x0000003F */ -#define HSP_TRGINSELR2_TRG8SEL HSP_TRGINSELR2_TRG8SEL_Msk /*!< TRG8SEL[5:0] bits (Input trigger selection for TRGIN8) */ -#define HSP_TRGINSELR2_TRG8SEL_0 (0x01UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000001 */ -#define HSP_TRGINSELR2_TRG8SEL_1 (0x02UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000002 */ -#define HSP_TRGINSELR2_TRG8SEL_2 (0x04UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000004 */ -#define HSP_TRGINSELR2_TRG8SEL_3 (0x08UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000008 */ -#define HSP_TRGINSELR2_TRG8SEL_4 (0x10UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000010 */ -#define HSP_TRGINSELR2_TRG8SEL_5 (0x20UL << HSP_TRGINSELR2_TRG8SEL_Pos) /*!< 0x00000020 */ - -#define HSP_TRGINSELR2_TRG9SEL_Pos (8UL) -#define HSP_TRGINSELR2_TRG9SEL_Msk (0x3FUL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00003F00 */ -#define HSP_TRGINSELR2_TRG9SEL HSP_TRGINSELR2_TRG9SEL_Msk /*!< TRG9SEL[5:0] bits (Input trigger selection for TRGIN9) */ -#define HSP_TRGINSELR2_TRG9SEL_0 (0x01UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000100 */ -#define HSP_TRGINSELR2_TRG9SEL_1 (0x02UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000200 */ -#define HSP_TRGINSELR2_TRG9SEL_2 (0x04UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000400 */ -#define HSP_TRGINSELR2_TRG9SEL_3 (0x08UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00000800 */ -#define HSP_TRGINSELR2_TRG9SEL_4 (0x10UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00001000 */ -#define HSP_TRGINSELR2_TRG9SEL_5 (0x20UL << HSP_TRGINSELR2_TRG9SEL_Pos) /*!< 0x00002000 */ - -/******************** Bit definition for HSP_BKOxCFGR register ********************/ -#define HSP_BKOCFGR_ACCEREN_Pos (0U) -#define HSP_BKOCFGR_ACCEREN_Msk (0x1UL << HSP_BKOCFGR_ACCEREN_Pos) /*!< 0x00000001 */ -#define HSP_BKOCFGR_ACCEREN HSP_BKOCFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ - -#define HSP_BKOCFGR_FPUEREN_Pos (1U) -#define HSP_BKOCFGR_FPUEREN_Msk (0x1UL << HSP_BKOCFGR_FPUEREN_Pos) /*!< 0x00000002 */ -#define HSP_BKOCFGR_FPUEREN HSP_BKOCFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ - -#define HSP_BKOCFGR_OPCEREN_Pos (2U) -#define HSP_BKOCFGR_OPCEREN_Msk (0x1UL << HSP_BKOCFGR_OPCEREN_Pos) /*!< 0x00000004 */ -#define HSP_BKOCFGR_OPCEREN HSP_BKOCFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ - -#define HSP_BKOCFGR_PFCT28EN_Pos (4U) -#define HSP_BKOCFGR_PFCT28EN_Msk (0x1UL << HSP_BKOCFGR_PFCT28EN_Pos) /*!< 0x00000010 */ -#define HSP_BKOCFGR_PFCT28EN HSP_BKOCFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ - -#define HSP_BKOCFGR_PFCT29EN_Pos (5U) -#define HSP_BKOCFGR_PFCT29EN_Msk (0x1UL << HSP_BKOCFGR_PFCT29EN_Pos) /*!< 0x00000020 */ -#define HSP_BKOCFGR_PFCT29EN HSP_BKOCFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ - -#define HSP_BKOCFGR_PFCT30EN_Pos (6U) -#define HSP_BKOCFGR_PFCT30EN_Msk (0x1UL << HSP_BKOCFGR_PFCT30EN_Pos) /*!< 0x00000040 */ -#define HSP_BKOCFGR_PFCT30EN HSP_BKOCFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ - -#define HSP_BKOCFGR_PFCT31EN_Pos (7U) -#define HSP_BKOCFGR_PFCT31EN_Msk (0x1UL << HSP_BKOCFGR_PFCT31EN_Pos) /*!< 0x00000080 */ -#define HSP_BKOCFGR_PFCT31EN HSP_BKOCFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ - -#define HSP_BKOCFGR_FWEREN_Pos (12U) -#define HSP_BKOCFGR_FWEREN_Msk (0x1UL << HSP_BKOCFGR_FWEREN_Pos) /*!< 0x00001000 */ -#define HSP_BKOCFGR_FWEREN HSP_BKOCFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ - -#define HSP_BKOCFGR_HDEGOVEN_Pos (13U) -#define HSP_BKOCFGR_HDEGOVEN_Msk (0x1UL << HSP_BKOCFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ -#define HSP_BKOCFGR_HDEGOVEN HSP_BKOCFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ - -/******************** Bit definition for HSP_BKICFGR register ********************/ -#define HSP_BKICFGR_ACCEREN_Pos (0UL) -#define HSP_BKICFGR_ACCEREN_Msk (0x1UL << HSP_BKICFGR_ACCEREN_Pos) /*!< 0x00000001 */ -#define HSP_BKICFGR_ACCEREN HSP_BKICFGR_ACCEREN_Msk /*!< ACCEREN (Access error break enable for ACCERRF (1)) */ - -#define HSP_BKICFGR_FPUEREN_Pos (1UL) -#define HSP_BKICFGR_FPUEREN_Msk (0x1UL << HSP_BKICFGR_FPUEREN_Pos) /*!< 0x00000002 */ -#define HSP_BKICFGR_FPUEREN HSP_BKICFGR_FPUEREN_Msk /*!< FPUEREN (FPU error break enable for FPUERRF (1)) */ - -#define HSP_BKICFGR_OPCEREN_Pos (2UL) -#define HSP_BKICFGR_OPCEREN_Msk (0x1UL << HSP_BKICFGR_OPCEREN_Pos) /*!< 0x00000004 */ -#define HSP_BKICFGR_OPCEREN HSP_BKICFGR_OPCEREN_Msk /*!< OPCEREN (Opcode error break enable for OPCOERRF ) */ - -#define HSP_BKICFGR_PFCT28EN_Pos (4UL) -#define HSP_BKICFGR_PFCT28EN_Msk (0x1UL << HSP_BKICFGR_PFCT28EN_Pos) /*!< 0x00000010 */ -#define HSP_BKICFGR_PFCT28EN HSP_BKICFGR_PFCT28EN_Msk /*!< PFCT28EN (Processing function flag break enable for PFCTF[28] (1)) */ - -#define HSP_BKICFGR_PFCT29EN_Pos (5UL) -#define HSP_BKICFGR_PFCT29EN_Msk (0x1UL << HSP_BKICFGR_PFCT29EN_Pos) /*!< 0x00000020 */ -#define HSP_BKICFGR_PFCT29EN HSP_BKICFGR_PFCT29EN_Msk /*!< PFCT29EN (Processing function flag break enable for PFCTF[29] (1)) */ - -#define HSP_BKICFGR_PFCT30EN_Pos (6UL) -#define HSP_BKICFGR_PFCT30EN_Msk (0x1UL << HSP_BKICFGR_PFCT30EN_Pos) /*!< 0x00000040 */ -#define HSP_BKICFGR_PFCT30EN HSP_BKICFGR_PFCT30EN_Msk /*!< PFCT30EN (Processing function flag break enable for PFCTF[30] (1)) */ - -#define HSP_BKICFGR_PFCT31EN_Pos (7UL) -#define HSP_BKICFGR_PFCT31EN_Msk (0x1UL << HSP_BKICFGR_PFCT31EN_Pos) /*!< 0x00000080 */ -#define HSP_BKICFGR_PFCT31EN HSP_BKICFGR_PFCT31EN_Msk /*!< PFCT31EN (Processing function flag break enable for PFCTF[31] (1)) */ - -#define HSP_BKICFGR_FWEREN_Pos (12UL) -#define HSP_BKICFGR_FWEREN_Msk (0x1UL << HSP_BKICFGR_FWEREN_Pos) /*!< 0x00001000 */ -#define HSP_BKICFGR_FWEREN HSP_BKICFGR_FWEREN_Msk /*!< FWEREN (Firmware error break enable for FWERRF (1)) */ - -#define HSP_BKICFGR_HDEGOVEN_Pos (13UL) -#define HSP_BKICFGR_HDEGOVEN_Msk (0x1UL << HSP_BKICFGR_HDEGOVEN_Pos) /*!< 0x00002000 */ -#define HSP_BKICFGR_HDEGOVEN HSP_BKICFGR_HDEGOVEN_Msk /*!< HDEGOVEN (HSP dedicated event generator overrun break enable for HDEGOVRF (1)) */ - -#define HSP_BKICFGR_FSATEN_Pos (14UL) -#define HSP_BKICFGR_FSATEN_Msk (0x1UL << HSP_BKICFGR_FSATEN_Pos) /*!< 0x00004000 */ -#define HSP_BKICFGR_FSATEN HSP_BKICFGR_FSATEN_Msk /*!< FSATEN (FPU saturation break enable for FPUSATF (1)) */ - -#define HSP_BKICFGR_SSEN_Pos (17UL) -#define HSP_BKICFGR_SSEN_Msk (0x1UL << HSP_BKICFGR_SSEN_Pos) /*!< 0x00020000 */ -#define HSP_BKICFGR_SSEN HSP_BKICFGR_SSEN_Msk /*!< SSEN (Single step enable (1)) */ - -/******************** Bit definition for HSP_FWERR register ********************/ -#define HSP_FWERR_FWERRN_Pos (0UL) -#define HSP_FWERR_FWERRN_Msk (0x3FFUL << HSP_FWERR_FWERRN_Pos) /*!< 0x000003FF */ -#define HSP_FWERR_FWERRN HSP_FWERR_FWERRN_Msk /*!< FWERRN[9:0] bits (Firmware error number) */ - -/******************** Bit definition for HSP_PARAMR0 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR0_PARAM_Pos (0UL) -#define HSP_PARAMR0_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR0_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR0_PARAM HSP_PARAMR0_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR1 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR1_PARAM_Pos (0UL) -#define HSP_PARAMR1_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR1_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR1_PARAM HSP_PARAMR1_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR2 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR2_PARAM_Pos (0UL) -#define HSP_PARAMR2_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR2_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR2_PARAM HSP_PARAMR2_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR3 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR3_PARAM_Pos (0UL) -#define HSP_PARAMR3_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR3_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR3_PARAM HSP_PARAMR3_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR4 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR4_PARAM_Pos (0UL) -#define HSP_PARAMR4_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR4_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR4_PARAM HSP_PARAMR4_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR5 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR5_PARAM_Pos (0UL) -#define HSP_PARAMR5_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR5_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR5_PARAM HSP_PARAMR5_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR6 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR6_PARAM_Pos (0UL) -#define HSP_PARAMR6_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR6_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR6_PARAM HSP_PARAMR6_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR7 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR7_PARAM_Pos (0UL) -#define HSP_PARAMR7_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR7_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR7_PARAM HSP_PARAMR7_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR8 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR8_PARAM_Pos (0UL) -#define HSP_PARAMR8_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR8_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR8_PARAM HSP_PARAMR8_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR9 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR9_PARAM_Pos (0UL) -#define HSP_PARAMR9_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR9_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR9_PARAM HSP_PARAMR9_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR10 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR10_PARAM_Pos (0UL) -#define HSP_PARAMR10_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR10_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR10_PARAM HSP_PARAMR10_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR11 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR11_PARAM_Pos (0UL) -#define HSP_PARAMR11_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR11_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR11_PARAM HSP_PARAMR11_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR12 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR12_PARAM_Pos (0UL) -#define HSP_PARAMR12_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR12_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR12_PARAM HSP_PARAMR12_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR13 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR13_PARAM_Pos (0UL) -#define HSP_PARAMR13_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR13_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR13_PARAM HSP_PARAMR13_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR14 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR14_PARAM_Pos (0UL) -#define HSP_PARAMR14_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR14_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR14_PARAM HSP_PARAMR14_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_PARAMR15 register ********************/ -/*!< PARAM configuration */ -#define HSP_PARAMR15_PARAM_Pos (0UL) -#define HSP_PARAMR15_PARAM_Msk (0xFFFFFFFFUL << HSP_PARAMR15_PARAM_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PARAMR15_PARAM HSP_PARAMR15_PARAM_Msk /*!< PARAM[31:0] bits (Parameter value) */ - -/******************** Bit definition for HSP_SPE_IER register ********************/ -#define HSP_SPE_IER_C2HMRDYIE_Pos (0UL) -#define HSP_SPE_IER_C2HMRDYIE_Msk (0x1UL << HSP_SPE_IER_C2HMRDYIE_Pos) /*!< 0x00000001 */ -#define HSP_SPE_IER_C2HMRDYIE HSP_SPE_IER_C2HMRDYIE_Msk /*!< C2HMRDYIE (CPU to SPE message ready interrupt enable) */ - -#define HSP_SPE_IER_H2CMFREEIE_Pos (1UL) -#define HSP_SPE_IER_H2CMFREEIE_Msk (0x1UL << HSP_SPE_IER_H2CMFREEIE_Pos) /*!< 0x00000002 */ -#define HSP_SPE_IER_H2CMFREEIE HSP_SPE_IER_H2CMFREEIE_Msk /*!< H2CMFREEIE (SPE to CPU message free interrupt enable) */ - -/******************** Bit definition for HSP_SPE_ISR register ********************/ -#define HSP_SPE_ISR_C2HMRDYF_Pos (0UL) -#define HSP_SPE_ISR_C2HMRDYF_Msk (0x1UL << HSP_SPE_ISR_C2HMRDYF_Pos) /*!< 0x00000001 */ -#define HSP_SPE_ISR_C2HMRDYF HSP_SPE_ISR_C2HMRDYF_Msk /*!< C2HMRDYF (CPU to SPE message box status) */ - -#define HSP_SPE_ISR_H2CMFREEF_Pos (1UL) -#define HSP_SPE_ISR_H2CMFREEF_Msk (0x1UL << HSP_SPE_ISR_H2CMFREEF_Pos) /*!< 0x00000002 */ -#define HSP_SPE_ISR_H2CMFREEF HSP_SPE_ISR_H2CMFREEF_Msk /*!< H2CMFREEF (SPE to CPU message box status) */ - -#define HSP_SPE_ISR_RSTREQF_Pos (4UL) -#define HSP_SPE_ISR_RSTREQF_Msk (0x1UL << HSP_SPE_ISR_RSTREQF_Pos) /*!< 0x00000010 */ -#define HSP_SPE_ISR_RSTREQF HSP_SPE_ISR_RSTREQF_Msk /*!< RSTREQF (HSP reset request) */ - -#define HSP_SPE_ISR_BUF0EVTF_Pos (12UL) -#define HSP_SPE_ISR_BUF0EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF0EVTF_Pos) /*!< 0x00001000 */ -#define HSP_SPE_ISR_BUF0EVTF HSP_SPE_ISR_BUF0EVTF_Msk /*!< BUF0EVTF (BUF0 status) */ - -#define HSP_SPE_ISR_BUF1EVTF_Pos (13UL) -#define HSP_SPE_ISR_BUF1EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF1EVTF_Pos) /*!< 0x00002000 */ -#define HSP_SPE_ISR_BUF1EVTF HSP_SPE_ISR_BUF1EVTF_Msk /*!< BUF1EVTF (BUF1 status) */ - -#define HSP_SPE_ISR_BUF2EVTF_Pos (14UL) -#define HSP_SPE_ISR_BUF2EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF2EVTF_Pos) /*!< 0x00004000 */ -#define HSP_SPE_ISR_BUF2EVTF HSP_SPE_ISR_BUF2EVTF_Msk /*!< BUF2EVTF (BUF2 status) */ - -#define HSP_SPE_ISR_BUF3EVTF_Pos (15UL) -#define HSP_SPE_ISR_BUF3EVTF_Msk (0x1UL << HSP_SPE_ISR_BUF3EVTF_Pos) /*!< 0x00008000 */ -#define HSP_SPE_ISR_BUF3EVTF HSP_SPE_ISR_BUF3EVTF_Msk /*!< BUF3EVTF (BUF3 status) */ - -/******************** Bit definition for HSP_TCUCFGR register ********************/ -#define HSP_TCUCFGR_TSKCMP0_Pos (0UL) -#define HSP_TCUCFGR_TSKCMP0_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x0000003F */ -#define HSP_TCUCFGR_TSKCMP0 HSP_TCUCFGR_TSKCMP0_Msk /*!< TSKCMP0[5:0] bits (Task compare 0 (1)) */ -#define HSP_TCUCFGR_TSKCMP0_0 (0x01UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000001 */ -#define HSP_TCUCFGR_TSKCMP0_1 (0x02UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000002 */ -#define HSP_TCUCFGR_TSKCMP0_2 (0x04UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000004 */ -#define HSP_TCUCFGR_TSKCMP0_3 (0x08UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000008 */ -#define HSP_TCUCFGR_TSKCMP0_4 (0x10UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000010 */ -#define HSP_TCUCFGR_TSKCMP0_5 (0x20UL << HSP_TCUCFGR_TSKCMP0_Pos) /*!< 0x00000020 */ - -#define HSP_TCUCFGR_TC0EN_Pos (7UL) -#define HSP_TCUCFGR_TC0EN_Msk (0x1UL << HSP_TCUCFGR_TC0EN_Pos) /*!< 0x00000080 */ -#define HSP_TCUCFGR_TC0EN HSP_TCUCFGR_TC0EN_Msk /*!< TC0EN (Task comparator 0 enable (1)) */ - -#define HSP_TCUCFGR_TSKCMP1_Pos (8UL) -#define HSP_TCUCFGR_TSKCMP1_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00003F00 */ -#define HSP_TCUCFGR_TSKCMP1 HSP_TCUCFGR_TSKCMP1_Msk /*!< TSKCMP1[5:0] bits (Task compare 1 (1)) */ -#define HSP_TCUCFGR_TSKCMP1_0 (0x01UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000100 */ -#define HSP_TCUCFGR_TSKCMP1_1 (0x02UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000200 */ -#define HSP_TCUCFGR_TSKCMP1_2 (0x04UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000400 */ -#define HSP_TCUCFGR_TSKCMP1_3 (0x08UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00000800 */ -#define HSP_TCUCFGR_TSKCMP1_4 (0x10UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00001000 */ -#define HSP_TCUCFGR_TSKCMP1_5 (0x20UL << HSP_TCUCFGR_TSKCMP1_Pos) /*!< 0x00002000 */ - -#define HSP_TCUCFGR_TC1EN_Pos (15UL) -#define HSP_TCUCFGR_TC1EN_Msk (0x1UL << HSP_TCUCFGR_TC1EN_Pos) /*!< 0x00008000 */ -#define HSP_TCUCFGR_TC1EN HSP_TCUCFGR_TC1EN_Msk /*!< TC1EN (Task comparator 1 enable (1)) */ - -#define HSP_TCUCFGR_TSKCMP2_Pos (16UL) -#define HSP_TCUCFGR_TSKCMP2_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x003F0000 */ -#define HSP_TCUCFGR_TSKCMP2 HSP_TCUCFGR_TSKCMP2_Msk /*!< TSKCMP2[5:0] bits (Task compare 2 (1)) */ -#define HSP_TCUCFGR_TSKCMP2_0 (0x01UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00010000 */ -#define HSP_TCUCFGR_TSKCMP2_1 (0x02UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00020000 */ -#define HSP_TCUCFGR_TSKCMP2_2 (0x04UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00040000 */ -#define HSP_TCUCFGR_TSKCMP2_3 (0x08UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00080000 */ -#define HSP_TCUCFGR_TSKCMP2_4 (0x10UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00100000 */ -#define HSP_TCUCFGR_TSKCMP2_5 (0x20UL << HSP_TCUCFGR_TSKCMP2_Pos) /*!< 0x00200000 */ - -#define HSP_TCUCFGR_TC2EN_Pos (23UL) -#define HSP_TCUCFGR_TC2EN_Msk (0x1UL << HSP_TCUCFGR_TC2EN_Pos) /*!< 0x00800000 */ -#define HSP_TCUCFGR_TC2EN HSP_TCUCFGR_TC2EN_Msk /*!< TC2EN (Task comparator 2 enable (1)) */ - -#define HSP_TCUCFGR_TSKCMP3_Pos (24UL) -#define HSP_TCUCFGR_TSKCMP3_Msk (0x3FUL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x3F000000 */ -#define HSP_TCUCFGR_TSKCMP3 HSP_TCUCFGR_TSKCMP3_Msk /*!< TSKCMP3[5:0] bits (Task compare 3 (1)) */ -#define HSP_TCUCFGR_TSKCMP3_0 (0x01UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x01000000 */ -#define HSP_TCUCFGR_TSKCMP3_1 (0x02UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x02000000 */ -#define HSP_TCUCFGR_TSKCMP3_2 (0x04UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x04000000 */ -#define HSP_TCUCFGR_TSKCMP3_3 (0x08UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x08000000 */ -#define HSP_TCUCFGR_TSKCMP3_4 (0x10UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x10000000 */ -#define HSP_TCUCFGR_TSKCMP3_5 (0x20UL << HSP_TCUCFGR_TSKCMP3_Pos) /*!< 0x20000000 */ - -#define HSP_TCUCFGR_TC3EN_Pos (31UL) -#define HSP_TCUCFGR_TC3EN_Msk (0x1UL << HSP_TCUCFGR_TC3EN_Pos) /*!< 0x80000000 */ -#define HSP_TCUCFGR_TC3EN HSP_TCUCFGR_TC3EN_Msk /*!< TC3EN (Task comparator 3 enable ) */ - -/******************** Bit definition for HSP_TOVLPCR register ********************/ -#define HSP_TOVLPCR_TOVLPEN_Pos (0UL) -#define HSP_TOVLPCR_TOVLPEN_Msk (0x1UL << HSP_TOVLPCR_TOVLPEN_Pos) /*!< 0x00000001 */ -#define HSP_TOVLPCR_TOVLPEN HSP_TOVLPCR_TOVLPEN_Msk /*!< TOVLPEN (Task overlap enable (1)) */ - -#define HSP_TOVLPCR_LTNB_Pos (8UL) -#define HSP_TOVLPCR_LTNB_Msk (0x3FUL << HSP_TOVLPCR_LTNB_Pos) /*!< 0x00003F00 */ -#define HSP_TOVLPCR_LTNB HSP_TOVLPCR_LTNB_Msk /*!< LTNB[5:0] bits (Lower task number value (1)) */ - -#define HSP_TOVLPCR_HTNB_Pos (16UL) -#define HSP_TOVLPCR_HTNB_Msk (0x3FUL << HSP_TOVLPCR_HTNB_Pos) /*!< 0x003F0000 */ -#define HSP_TOVLPCR_HTNB HSP_TOVLPCR_HTNB_Msk /*!< HTNB[5:0] bits (Higher task number value ) */ - -/******************** Bit definition for HSP_SNPR register ********************/ -#define HSP_SNPR_SNPSELA_Pos (0UL) -#define HSP_SNPR_SNPSELA_Msk (0x7UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000007 */ -#define HSP_SNPR_SNPSELA HSP_SNPR_SNPSELA_Msk /*!< SNPSELA[2:0] bits (Snoop group A signal selection) */ -#define HSP_SNPR_SNPSELA_0 (0x1UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000001 */ -#define HSP_SNPR_SNPSELA_1 (0x2UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000002 */ -#define HSP_SNPR_SNPSELA_2 (0x4UL << HSP_SNPR_SNPSELA_Pos) /*!< 0x00000004 */ - -#define HSP_SNPR_SNPSELB_Pos (4UL) -#define HSP_SNPR_SNPSELB_Msk (0x7UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000070 */ -#define HSP_SNPR_SNPSELB HSP_SNPR_SNPSELB_Msk /*!< SNPSELB[2:0] bits (Snoop group B signal selection) */ -#define HSP_SNPR_SNPSELB_0 (0x1UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000010 */ -#define HSP_SNPR_SNPSELB_1 (0x2UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000020 */ -#define HSP_SNPR_SNPSELB_2 (0x4UL << HSP_SNPR_SNPSELB_Pos) /*!< 0x00000040 */ - -/******************** Bit definition for HSP_CCNTR register ********************/ -#define HSP_CCNTR_CCNTR_Pos (0UL) -#define HSP_CCNTR_CCNTR_Msk (0xFFFFFFFFUL << HSP_CCNTR_CCNTR_Pos) /*!< 0xFFFFFFFF */ -#define HSP_CCNTR_CCNTR HSP_CCNTR_CCNTR_Msk /*!< CCNTR[31:0] bits (Conflict counter) */ - -/****************** Bit definition for HSP_CAPDR register *******************/ -#define HSP_CAPDR_TSTAMP_Pos (0UL) -#define HSP_CAPDR_TSTAMP_Msk (0x3FFFUL << HSP_CAPDR_TSTAMP_Pos) /*!< 0x00003FFF */ -#define HSP_CAPDR_TSTAMP HSP_CAPDR_TSTAMP_Msk /*!< Time-stamp value */ -#define HSP_CAPDR_IFHIST_Pos (14UL) -#define HSP_CAPDR_IFHIST_Msk (0xFFUL << HSP_CAPDR_IFHIST_Pos) /*!< 0x003FC000 */ -#define HSP_CAPDR_IFHIST HSP_CAPDR_IFHIST_Msk /*!< IF condition history */ -#define HSP_CAPDR_IFCNT_Pos (22UL) -#define HSP_CAPDR_IFCNT_Msk (0xFUL << HSP_CAPDR_IFCNT_Pos) /*!< 0x03C00000 */ -#define HSP_CAPDR_IFCNT HSP_CAPDR_IFCNT_Msk /*!< IF instruction counter */ -#define HSP_CAPDR_TSKNB_Pos (26UL) -#define HSP_CAPDR_TSKNB_Msk (0x3FUL << HSP_CAPDR_TSKNB_Pos) /*!< 0xFC000000 */ -#define HSP_CAPDR_TSKNB HSP_CAPDR_TSKNB_Msk /*!< Last captured task number */ - -#define HSP_CAPDR_ALT_IFHIST_Pos (0UL) -#define HSP_CAPDR_ALT_IFHIST_Msk (0x7FFFUL << HSP_CAPDR_ALT_IFHIST_Pos) /*!< 0x00007FFF */ -#define HSP_CAPDR_ALT_IFHIST HSP_CAPDR_IFHIST_Msk /*!< IF condition history */ -#define HSP_CAPDR_ALT_PFCTNB_Pos (16UL) -#define HSP_CAPDR_ALT_PFCTNB_Msk (0x3FUL << HSP_CAPDR_ALT_PFCTNB_Pos) /*!< 0x0003F0000 */ -#define HSP_CAPDR_ALT_PFCTNB HSP_CAPDR_TSTAMP_Msk /*!< Processing Function Number */ -#define HSP_CAPDR_ALT_IFCNT_Pos (22UL) -#define HSP_CAPDR_ALT_IFCNT_Msk (0xFUL << HSP_CAPDR_ALT_IFCNT_Pos) /*!< 0x03C00000 */ -#define HSP_CAPDR_ALT_IFCNT HSP_CAPDR_IFCNT_Msk /*!< IF instruction counter */ -#define HSP_CAPDR_ALT_TSKNB_Pos (26UL) -#define HSP_CAPDR_ALT_TSKNB_Msk (0x3FUL << HSP_CAPDR_ALT_TSKNB_Pos) /*!< 0xFC000000 */ -#define HSP_CAPDR_ALT_TSKNB HSP_CAPDR_TSKNB_Msk /*!< Last captured task number */ - -/******************** Bit definition for HSP_CAPCR register ********************/ -#define HSP_CAPCR_CAPMOD_Pos (0UL) -#define HSP_CAPCR_CAPMOD_Msk (0x3UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000003 */ -#define HSP_CAPCR_CAPMOD HSP_CAPCR_CAPMOD_Msk /*!< CAPMOD[1:0] bits (Capture mode ) */ -#define HSP_CAPCR_CAPMOD_0 (0x1UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000001 */ -#define HSP_CAPCR_CAPMOD_1 (0x2UL << HSP_CAPCR_CAPMOD_Pos) /*!< 0x00000002 */ - -#define HSP_CAPCR_FRCNTEN_Pos (2UL) -#define HSP_CAPCR_FRCNTEN_Msk (0x1UL << HSP_CAPCR_FRCNTEN_Pos) /*!< 0x00000004 */ -#define HSP_CAPCR_FRCNTEN HSP_CAPCR_FRCNTEN_Msk /*!< FRCNTEN (Free-running counter enable ) */ - -#define HSP_CAPCR_PRESC_Pos (4UL) -#define HSP_CAPCR_PRESC_Msk (0x1FUL << HSP_CAPCR_PRESC_Pos) /*!< 0x000001F0 */ -#define HSP_CAPCR_PRESC HSP_CAPCR_PRESC_Msk /*!< PRESC[4:0] bits (Time-stamp prescaler value ) */ -#define HSP_CAPCR_PRESC_0 (0x01UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000010 */ -#define HSP_CAPCR_PRESC_1 (0x02UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000020 */ -#define HSP_CAPCR_PRESC_2 (0x04UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000040 */ -#define HSP_CAPCR_PRESC_3 (0x08UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000080 */ -#define HSP_CAPCR_PRESC_4 (0x10UL << HSP_CAPCR_PRESC_Pos) /*!< 0x00000100 */ - -#define HSP_CAPCR_TSKFLT_Pos (12UL) -#define HSP_CAPCR_TSKFLT_Msk (0x1UL << HSP_CAPCR_TSKFLT_Pos) /*!< 0x00001000 */ -#define HSP_CAPCR_TSKFLT HSP_CAPCR_TSKFLT_Msk /*!< TSKFLT (Task filter enable (1)) */ - -#define HSP_CAPCR_CCNTREN_Pos (16UL) -#define HSP_CAPCR_CCNTREN_Msk (0x1UL << HSP_CAPCR_CCNTREN_Pos) /*!< 0x00010000 */ -#define HSP_CAPCR_CCNTREN HSP_CAPCR_CCNTREN_Msk /*!< CCNTREN (Conflict counter enable ) */ - -/******************** Bit definition for HSP_ERR_IER register ********************/ -#define HSP_ERR_IER_TRGIOVRIE_Pos (8UL) -#define HSP_ERR_IER_TRGIOVRIE_Msk (0x1UL << HSP_ERR_IER_TRGIOVRIE_Pos) /*!< 0x00000100 */ -#define HSP_ERR_IER_TRGIOVRIE HSP_ERR_IER_TRGIOVRIE_Msk /*!< TRGIOVRIE (TRGITF overrun interrupt enable) */ - -#define HSP_ERR_IER_B0ERRIE_Pos (12UL) -#define HSP_ERR_IER_B0ERRIE_Msk (0x1UL << HSP_ERR_IER_B0ERRIE_Pos) /*!< 0x00001000 */ -#define HSP_ERR_IER_B0ERRIE HSP_ERR_IER_B0ERRIE_Msk /*!< B0ERRIE (H2CBUFF0 underrun or C2HBUFF0 overrun interrupt enable) */ - -#define HSP_ERR_IER_B1ERRIE_Pos (13UL) -#define HSP_ERR_IER_B1ERRIE_Msk (0x1UL << HSP_ERR_IER_B1ERRIE_Pos) /*!< 0x00002000 */ -#define HSP_ERR_IER_B1ERRIE HSP_ERR_IER_B1ERRIE_Msk /*!< B1ERRIE (H2CBUFF1 underrun or C2HBUFF1 overrun interrupt enable) */ - -#define HSP_ERR_IER_B2ERRIE_Pos (14UL) -#define HSP_ERR_IER_B2ERRIE_Msk (0x1UL << HSP_ERR_IER_B2ERRIE_Pos) /*!< 0x00004000 */ -#define HSP_ERR_IER_B2ERRIE HSP_ERR_IER_B2ERRIE_Msk /*!< B2ERRIE (H2CBUFF2 underrun or C2HBUFF2 overrun interrupt enable) */ - -#define HSP_ERR_IER_B3ERRIE_Pos (15UL) -#define HSP_ERR_IER_B3ERRIE_Msk (0x1UL << HSP_ERR_IER_B3ERRIE_Pos) /*!< 0x00008000 */ -#define HSP_ERR_IER_B3ERRIE HSP_ERR_IER_B3ERRIE_Msk /*!< B3ERRIE (H2CBUFF3 underrun or C2HBUFF3 overrun interrupt enable) */ - -#define HSP_ERR_IER_CAPOVRIE_Pos (16UL) -#define HSP_ERR_IER_CAPOVRIE_Msk (0x1UL << HSP_ERR_IER_CAPOVRIE_Pos) /*!< 0x00010000 */ -#define HSP_ERR_IER_CAPOVRIE HSP_ERR_IER_CAPOVRIE_Msk /*!< CAPOVRIE (Capture register overrun interrupt enable) */ - -#define HSP_ERR_IER_FWERRIE_Pos (17UL) -#define HSP_ERR_IER_FWERRIE_Msk (0x1UL << HSP_ERR_IER_FWERRIE_Pos) /*!< 0x00020000 */ -#define HSP_ERR_IER_FWERRIE HSP_ERR_IER_FWERRIE_Msk /*!< FWERRIE (Firmware error interrupt enable) */ - -#define HSP_ERR_IER_SCHERRIE_Pos (18UL) -#define HSP_ERR_IER_SCHERRIE_Msk (0x1UL << HSP_ERR_IER_SCHERRIE_Pos) /*!< 0x00040000 */ -#define HSP_ERR_IER_SCHERRIE HSP_ERR_IER_SCHERRIE_Msk /*!< SCHERRIE (Scheduler error interrupt enable) */ - -#define HSP_ERR_IER_BKINIE_Pos (19UL) -#define HSP_ERR_IER_BKINIE_Msk (0x1UL << HSP_ERR_IER_BKINIE_Pos) /*!< 0x00080000 */ -#define HSP_ERR_IER_BKINIE HSP_ERR_IER_BKINIE_Msk /*!< BKINIE (Break input interrupt enable) */ - -#define HSP_ERR_IER_HDEGOVRIE_Pos (20UL) -#define HSP_ERR_IER_HDEGOVRIE_Msk (0x1UL << HSP_ERR_IER_HDEGOVRIE_Pos) /*!< 0x00100000 */ -#define HSP_ERR_IER_HDEGOVRIE HSP_ERR_IER_HDEGOVRIE_Msk /*!< HDEGOVRIE (SPE event overrun interrupt enable) */ - -#define HSP_ERR_IER_OPCOERRIE_Pos (22UL) -#define HSP_ERR_IER_OPCOERRIE_Msk (0x1UL << HSP_ERR_IER_OPCOERRIE_Pos) /*!< 0x00400000 */ -#define HSP_ERR_IER_OPCOERRIE HSP_ERR_IER_OPCOERRIE_Msk /*!< OPCOERRIE (Invalid Op. code error interrupt enable) */ - -#define HSP_ERR_IER_ACCERRIE_Pos (23UL) -#define HSP_ERR_IER_ACCERRIE_Msk (0x1UL << HSP_ERR_IER_ACCERRIE_Pos) /*!< 0x00800000 */ -#define HSP_ERR_IER_ACCERRIE HSP_ERR_IER_ACCERRIE_Msk /*!< ACCERRIE (SPE access error interrupt enable) */ - -#define HSP_ERR_IER_UDFIE_Pos (24UL) -#define HSP_ERR_IER_UDFIE_Msk (0x1UL << HSP_ERR_IER_UDFIE_Pos) /*!< 0x01000000 */ -#define HSP_ERR_IER_UDFIE HSP_ERR_IER_UDFIE_Msk /*!< UDFIE (FPU Underflow exception interrupt enable) */ - -#define HSP_ERR_IER_OVFIE_Pos (25UL) -#define HSP_ERR_IER_OVFIE_Msk (0x1UL << HSP_ERR_IER_OVFIE_Pos) /*!< 0x02000000 */ -#define HSP_ERR_IER_OVFIE HSP_ERR_IER_OVFIE_Msk /*!< OVFIE (FPU Overflow exception interrupt enable) */ - -#define HSP_ERR_IER_DBZIE_Pos (26UL) -#define HSP_ERR_IER_DBZIE_Msk (0x1UL << HSP_ERR_IER_DBZIE_Pos) /*!< 0x04000000 */ -#define HSP_ERR_IER_DBZIE HSP_ERR_IER_DBZIE_Msk /*!< DBZIE (FPU division-by-zero exception interrupt enable) */ - -#define HSP_ERR_IER_INVIE_Pos (27UL) -#define HSP_ERR_IER_INVIE_Msk (0x1UL << HSP_ERR_IER_INVIE_Pos) /*!< 0x08000000 */ -#define HSP_ERR_IER_INVIE HSP_ERR_IER_INVIE_Msk /*!< INVIE (FPU Invalid exception interrupt enable) */ - -#define HSP_ERR_IER_DENORMIE_Pos (28UL) -#define HSP_ERR_IER_DENORMIE_Msk (0x1UL << HSP_ERR_IER_DENORMIE_Pos) /*!< 0x10000000 */ -#define HSP_ERR_IER_DENORMIE HSP_ERR_IER_DENORMIE_Msk /*!< DENORMIE (FPU denormal interrupt enable) */ - -/******************** Bit definition for HSP_EVT_IER register ********************/ -#define HSP_EVT_IER_H2CMRDYIE_Pos (0UL) -#define HSP_EVT_IER_H2CMRDYIE_Msk (0x1UL << HSP_EVT_IER_H2CMRDYIE_Pos) /*!< 0x00000001 */ -#define HSP_EVT_IER_H2CMRDYIE HSP_EVT_IER_H2CMRDYIE_Msk /*!< H2CMRDYIE (HSP to CPU message ready interrupt enable) */ - -#define HSP_EVT_IER_C2HMFREEIE_Pos (1UL) -#define HSP_EVT_IER_C2HMFREEIE_Msk (0x1UL << HSP_EVT_IER_C2HMFREEIE_Pos) /*!< 0x00000002 */ -#define HSP_EVT_IER_C2HMFREEIE HSP_EVT_IER_C2HMFREEIE_Msk /*!< C2HMFREEIE (CPU to HSP message box free interrupt enable) */ - -#define HSP_EVT_IER_DCDONEIE_Pos (2UL) -#define HSP_EVT_IER_DCDONEIE_Msk (0x1UL << HSP_EVT_IER_DCDONEIE_Pos) /*!< 0x00000004 */ -#define HSP_EVT_IER_DCDONEIE HSP_EVT_IER_DCDONEIE_Msk /*!< DCDONEIE (Direct command done interrupt enable) */ - -#define HSP_EVT_IER_CAPRDYIE_Pos (4UL) -#define HSP_EVT_IER_CAPRDYIE_Msk (0x1UL << HSP_EVT_IER_CAPRDYIE_Pos) /*!< 0x00000010 */ -#define HSP_EVT_IER_CAPRDYIE HSP_EVT_IER_CAPRDYIE_Msk /*!< CAPRDYIE (Capture buffer data ready interrupt enable) */ - -#define HSP_EVT_IER_CDEGRDYIE_Pos (7UL) -#define HSP_EVT_IER_CDEGRDYIE_Msk (0x1UL << HSP_EVT_IER_CDEGRDYIE_Pos) /*!< 0x00000080 */ -#define HSP_EVT_IER_CDEGRDYIE HSP_EVT_IER_CDEGRDYIE_Msk /*!< CDEGRDYIE (CPU Dedicated event generator ready interrupt enable) */ - -#define HSP_EVT_IER_SOFWFEIE_Pos (8UL) -#define HSP_EVT_IER_SOFWFEIE_Msk (0x1UL << HSP_EVT_IER_SOFWFEIE_Pos) /*!< 0x00000100 */ -#define HSP_EVT_IER_SOFWFEIE HSP_EVT_IER_SOFWFEIE_Msk /*!< SOFWFEIE (Start of WFE interrupt enable) */ - -#define HSP_EVT_IER_EOFWFEIE_Pos (9UL) -#define HSP_EVT_IER_EOFWFEIE_Msk (0x1UL << HSP_EVT_IER_EOFWFEIE_Pos) /*!< 0x00000200 */ -#define HSP_EVT_IER_EOFWFEIE HSP_EVT_IER_EOFWFEIE_Msk /*!< EOFWFEIE (End of WFE interrupt enable) */ - -#define HSP_EVT_IER_B0EVTIE_Pos (12UL) -#define HSP_EVT_IER_B0EVTIE_Msk (0x1UL << HSP_EVT_IER_B0EVTIE_Pos) /*!< 0x00001000 */ -#define HSP_EVT_IER_B0EVTIE HSP_EVT_IER_B0EVTIE_Msk /*!< B0EVTIE (BUFF0 event interrupt enable) */ - -#define HSP_EVT_IER_B1EVTIE_Pos (13UL) -#define HSP_EVT_IER_B1EVTIE_Msk (0x1UL << HSP_EVT_IER_B1EVTIE_Pos) /*!< 0x00002000 */ -#define HSP_EVT_IER_B1EVTIE HSP_EVT_IER_B1EVTIE_Msk /*!< B1EVTIE (BUFF1 event interrupt enable) */ - -#define HSP_EVT_IER_B2EVTIE_Pos (14UL) -#define HSP_EVT_IER_B2EVTIE_Msk (0x1UL << HSP_EVT_IER_B2EVTIE_Pos) /*!< 0x00004000 */ -#define HSP_EVT_IER_B2EVTIE HSP_EVT_IER_B2EVTIE_Msk /*!< B2EVTIE (BUFF2 event interrupt enable) */ - -#define HSP_EVT_IER_B3EVTIE_Pos (15UL) -#define HSP_EVT_IER_B3EVTIE_Msk (0x1UL << HSP_EVT_IER_B3EVTIE_Pos) /*!< 0x00008000 */ -#define HSP_EVT_IER_B3EVTIE HSP_EVT_IER_B3EVTIE_Msk /*!< B3EVTIE (BUFF3 event interrupt enable) */ - -#define HSP_EVT_IER_SOTECP0IE_Pos (16UL) -#define HSP_EVT_IER_SOTECP0IE_Msk (0x1UL << HSP_EVT_IER_SOTECP0IE_Pos) /*!< 0x00010000 */ -#define HSP_EVT_IER_SOTECP0IE HSP_EVT_IER_SOTECP0IE_Msk /*!< SOTECP0IE (Start of task generated by event comparator 0 interrupt enable) */ - -#define HSP_EVT_IER_SOTECP1IE_Pos (17UL) -#define HSP_EVT_IER_SOTECP1IE_Msk (0x1UL << HSP_EVT_IER_SOTECP1IE_Pos) /*!< 0x00020000 */ -#define HSP_EVT_IER_SOTECP1IE HSP_EVT_IER_SOTECP1IE_Msk /*!< SOTECP1IE (Start of task generated by event comparator 1 interrupt enable) */ - -#define HSP_EVT_IER_SOTECP2IE_Pos (18UL) -#define HSP_EVT_IER_SOTECP2IE_Msk (0x1UL << HSP_EVT_IER_SOTECP2IE_Pos) /*!< 0x00040000 */ -#define HSP_EVT_IER_SOTECP2IE HSP_EVT_IER_SOTECP2IE_Msk /*!< SOTECP2IE (Start of task generated by event comparator 2 interrupt enable) */ - -#define HSP_EVT_IER_SOTECP3IE_Pos (19UL) -#define HSP_EVT_IER_SOTECP3IE_Msk (0x1UL << HSP_EVT_IER_SOTECP3IE_Pos) /*!< 0x00080000 */ -#define HSP_EVT_IER_SOTECP3IE HSP_EVT_IER_SOTECP3IE_Msk /*!< SOTECP3IE (Start of task generated by event comparator 3 interrupt enable) */ - -#define HSP_EVT_IER_EOTECP0IE_Pos (20UL) -#define HSP_EVT_IER_EOTECP0IE_Msk (0x1UL << HSP_EVT_IER_EOTECP0IE_Pos) /*!< 0x00100000 */ -#define HSP_EVT_IER_EOTECP0IE HSP_EVT_IER_EOTECP0IE_Msk /*!< EOTECP0IE (End of task generated by event comparator 0 interrupt enable) */ - -#define HSP_EVT_IER_EOTECP1IE_Pos (21UL) -#define HSP_EVT_IER_EOTECP1IE_Msk (0x1UL << HSP_EVT_IER_EOTECP1IE_Pos) /*!< 0x00200000 */ -#define HSP_EVT_IER_EOTECP1IE HSP_EVT_IER_EOTECP1IE_Msk /*!< EOTECP1IE (End of task generated by event comparator 1 interrupt enable) */ - -#define HSP_EVT_IER_EOTECP2IE_Pos (22UL) -#define HSP_EVT_IER_EOTECP2IE_Msk (0x1UL << HSP_EVT_IER_EOTECP2IE_Pos) /*!< 0x00400000 */ -#define HSP_EVT_IER_EOTECP2IE HSP_EVT_IER_EOTECP2IE_Msk /*!< EOTECP2IE (End of task generated by event comparator 2 interrupt enable) */ - -#define HSP_EVT_IER_EOTECP3IE_Pos (23UL) -#define HSP_EVT_IER_EOTECP3IE_Msk (0x1UL << HSP_EVT_IER_EOTECP3IE_Pos) /*!< 0x00800000 */ -#define HSP_EVT_IER_EOTECP3IE HSP_EVT_IER_EOTECP3IE_Msk /*!< EOTECP3IE (End of task generated by event comparator 3 interrupt enable) */ - -#define HSP_EVT_IER_TOVLPIE_Pos (28UL) -#define HSP_EVT_IER_TOVLPIE_Msk (0x1UL << HSP_EVT_IER_TOVLPIE_Pos) /*!< 0x10000000 */ -#define HSP_EVT_IER_TOVLPIE HSP_EVT_IER_TOVLPIE_Msk /*!< TOVLPIE (Task overlap flag interrupt enable) */ - -#define HSP_EVT_IER_FPUSATIE_Pos (31UL) -#define HSP_EVT_IER_FPUSATIE_Msk (0x1UL << HSP_EVT_IER_FPUSATIE_Pos) /*!< 0x80000000 */ -#define HSP_EVT_IER_FPUSATIE HSP_EVT_IER_FPUSATIE_Msk /*!< FPUSATIE (Saturation flag interrupt enable) */ - -/******************** Bit definition for HSP_PFCTEVT_IER register ********************/ -#define HSP_PFCTEVT_IER_PFCTIE_Pos (0UL) -#define HSP_PFCTEVT_IER_PFCTIE_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PFCTEVT_IER_PFCTIE HSP_PFCTEVT_IER_PFCTIE_Msk /*!< PFCTIE[31:0] bits (Processing function flags interrupt enable) */ -#define HSP_PFCTEVT_IER_PFCTIE_0 (0x00001UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000001 */ -#define HSP_PFCTEVT_IER_PFCTIE_1 (0x00002UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000002 */ -#define HSP_PFCTEVT_IER_PFCTIE_2 (0x00004UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000004 */ -#define HSP_PFCTEVT_IER_PFCTIE_3 (0x00008UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000008 */ -#define HSP_PFCTEVT_IER_PFCTIE_4 (0x00010UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000010 */ -#define HSP_PFCTEVT_IER_PFCTIE_5 (0x00020UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000020 */ -#define HSP_PFCTEVT_IER_PFCTIE_6 (0x00040UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000040 */ -#define HSP_PFCTEVT_IER_PFCTIE_7 (0x00080UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000080 */ -#define HSP_PFCTEVT_IER_PFCTIE_8 (0x00100UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000100 */ -#define HSP_PFCTEVT_IER_PFCTIE_9 (0x00200UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000200 */ -#define HSP_PFCTEVT_IER_PFCTIE_10 (0x00400UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000400 */ -#define HSP_PFCTEVT_IER_PFCTIE_11 (0x00800UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00000800 */ -#define HSP_PFCTEVT_IER_PFCTIE_12 (0x01000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00001000 */ -#define HSP_PFCTEVT_IER_PFCTIE_13 (0x02000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00002000 */ -#define HSP_PFCTEVT_IER_PFCTIE_14 (0x04000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00004000 */ -#define HSP_PFCTEVT_IER_PFCTIE_15 (0x08000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00008000 */ -#define HSP_PFCTEVT_IER_PFCTIE_16 (0x10000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00010000 */ -#define HSP_PFCTEVT_IER_PFCTIE_17 (0x20000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00020000 */ -#define HSP_PFCTEVT_IER_PFCTIE_18 (0x40000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00040000 */ -#define HSP_PFCTEVT_IER_PFCTIE_19 (0x80000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00080000 */ -#define HSP_PFCTEVT_IER_PFCTIE_20 (0x100000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00100000 */ -#define HSP_PFCTEVT_IER_PFCTIE_21 (0x200000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00200000 */ -#define HSP_PFCTEVT_IER_PFCTIE_22 (0x400000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00400000 */ -#define HSP_PFCTEVT_IER_PFCTIE_23 (0x800000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x00800000 */ -#define HSP_PFCTEVT_IER_PFCTIE_24 (0x1000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x01000000 */ -#define HSP_PFCTEVT_IER_PFCTIE_25 (0x2000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x02000000 */ -#define HSP_PFCTEVT_IER_PFCTIE_26 (0x4000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x04000000 */ -#define HSP_PFCTEVT_IER_PFCTIE_27 (0x8000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x08000000 */ -#define HSP_PFCTEVT_IER_PFCTIE_28 (0x10000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x10000000 */ -#define HSP_PFCTEVT_IER_PFCTIE_29 (0x20000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x20000000 */ -#define HSP_PFCTEVT_IER_PFCTIE_30 (0x40000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x40000000 */ -#define HSP_PFCTEVT_IER_PFCTIE_31 (0x80000000UL << HSP_PFCTEVT_IER_PFCTIE_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_ERR_ISR register ********************/ -#define HSP_ERR_ISR_TRGIOVRF_Pos (8UL) -#define HSP_ERR_ISR_TRGIOVRF_Msk (0x1UL << HSP_ERR_ISR_TRGIOVRF_Pos) /*!< 0x00000100 */ -#define HSP_ERR_ISR_TRGIOVRF HSP_ERR_ISR_TRGIOVRF_Msk /*!< TRGIOVRF (TRGITF overrun flag) */ - -#define HSP_ERR_ISR_B0ERRF_Pos (12UL) -#define HSP_ERR_ISR_B0ERRF_Msk (0x1UL << HSP_ERR_ISR_B0ERRF_Pos) /*!< 0x00001000 */ -#define HSP_ERR_ISR_B0ERRF HSP_ERR_ISR_B0ERRF_Msk /*!< B0ERRF (H2CBUFF0 underrun or C2HBUFF0 overrun flag) */ - -#define HSP_ERR_ISR_B1ERRF_Pos (13UL) -#define HSP_ERR_ISR_B1ERRF_Msk (0x1UL << HSP_ERR_ISR_B1ERRF_Pos) /*!< 0x00002000 */ -#define HSP_ERR_ISR_B1ERRF HSP_ERR_ISR_B1ERRF_Msk /*!< B1ERRF (H2CBUFF1 underrun or C2HBUFF1 overrun flag) */ - -#define HSP_ERR_ISR_B2ERRF_Pos (14UL) -#define HSP_ERR_ISR_B2ERRF_Msk (0x1UL << HSP_ERR_ISR_B2ERRF_Pos) /*!< 0x00004000 */ -#define HSP_ERR_ISR_B2ERRF HSP_ERR_ISR_B2ERRF_Msk /*!< B2ERRF (H2CBUFF2 underrun or C2HBUFF2 overrun flag) */ - -#define HSP_ERR_ISR_B3ERRF_Pos (15UL) -#define HSP_ERR_ISR_B3ERRF_Msk (0x1UL << HSP_ERR_ISR_B3ERRF_Pos) /*!< 0x00008000 */ -#define HSP_ERR_ISR_B3ERRF HSP_ERR_ISR_B3ERRF_Msk /*!< B3ERRF (H2CBUFF3 underrun or C2HBUFF3 overrun flag) */ - -#define HSP_ERR_ISR_CAPOVRF_Pos (16UL) -#define HSP_ERR_ISR_CAPOVRF_Msk (0x1UL << HSP_ERR_ISR_CAPOVRF_Pos) /*!< 0x00010000 */ -#define HSP_ERR_ISR_CAPOVRF HSP_ERR_ISR_CAPOVRF_Msk /*!< CAPOVRF (Capture register overrun flag) */ - -#define HSP_ERR_ISR_FWERRF_Pos (17UL) -#define HSP_ERR_ISR_FWERRF_Msk (0x1UL << HSP_ERR_ISR_FWERRF_Pos) /*!< 0x00020000 */ -#define HSP_ERR_ISR_FWERRF HSP_ERR_ISR_FWERRF_Msk /*!< FWERRF (Firmware error flag) */ - -#define HSP_ERR_ISR_SCHERRF_Pos (18UL) -#define HSP_ERR_ISR_SCHERRF_Msk (0x1UL << HSP_ERR_ISR_SCHERRF_Pos) /*!< 0x00040000 */ -#define HSP_ERR_ISR_SCHERRF HSP_ERR_ISR_SCHERRF_Msk /*!< SCHERRF (Scheduler error flag) */ - -#define HSP_ERR_ISR_BKINF_Pos (19UL) -#define HSP_ERR_ISR_BKINF_Msk (0x1UL << HSP_ERR_ISR_BKINF_Pos) /*!< 0x00080000 */ -#define HSP_ERR_ISR_BKINF HSP_ERR_ISR_BKINF_Msk /*!< BKINF (Break input flag) */ - -#define HSP_ERR_ISR_HDEGOVRF_Pos (20UL) -#define HSP_ERR_ISR_HDEGOVRF_Msk (0x1UL << HSP_ERR_ISR_HDEGOVRF_Pos) /*!< 0x00100000 */ -#define HSP_ERR_ISR_HDEGOVRF HSP_ERR_ISR_HDEGOVRF_Msk /*!< HDEGOVRF (SPE event overrun flag) */ - -#define HSP_ERR_ISR_OPCOERRF_Pos (22UL) -#define HSP_ERR_ISR_OPCOERRF_Msk (0x1UL << HSP_ERR_ISR_OPCOERRF_Pos) /*!< 0x00400000 */ -#define HSP_ERR_ISR_OPCOERRF HSP_ERR_ISR_OPCOERRF_Msk /*!< OPCOERRF (Invalid OpCode error flag) */ - -#define HSP_ERR_ISR_ACCERRF_Pos (23UL) -#define HSP_ERR_ISR_ACCERRF_Msk (0x1UL << HSP_ERR_ISR_ACCERRF_Pos) /*!< 0x00800000 */ -#define HSP_ERR_ISR_ACCERRF HSP_ERR_ISR_ACCERRF_Msk /*!< ACCERRF (SPE Access error flag) */ - -#define HSP_ERR_ISR_FPUERRF_Pos (24UL) -#define HSP_ERR_ISR_FPUERRF_Msk (0x1UL << HSP_ERR_ISR_FPUERRF_Pos) /*!< 0x01000000 */ -#define HSP_ERR_ISR_FPUERRF HSP_ERR_ISR_FPUERRF_Msk /*!< FPUERRF (Computation error flag) */ - -/******************** Bit definition for HSP_EVT_ISR register ********************/ -#define HSP_EVT_ISR_H2CMRDYF_Pos (0UL) -#define HSP_EVT_ISR_H2CMRDYF_Msk (0x1UL << HSP_EVT_ISR_H2CMRDYF_Pos) /*!< 0x00000001 */ -#define HSP_EVT_ISR_H2CMRDYF HSP_EVT_ISR_H2CMRDYF_Msk /*!< H2CMRDYF (HSP to CPU message ready flag) */ - -#define HSP_EVT_ISR_C2HMFREEF_Pos (1UL) -#define HSP_EVT_ISR_C2HMFREEF_Msk (0x1UL << HSP_EVT_ISR_C2HMFREEF_Pos) /*!< 0x00000002 */ -#define HSP_EVT_ISR_C2HMFREEF HSP_EVT_ISR_C2HMFREEF_Msk /*!< C2HMFREEF (CPU to HSP message box free flag) */ - -#define HSP_EVT_ISR_DCDONEF_Pos (2UL) -#define HSP_EVT_ISR_DCDONEF_Msk (0x1UL << HSP_EVT_ISR_DCDONEF_Pos) /*!< 0x00000004 */ -#define HSP_EVT_ISR_DCDONEF HSP_EVT_ISR_DCDONEF_Msk /*!< DCDONEF (Direct command done flag) */ - -#define HSP_EVT_ISR_CAPRDYF_Pos (4UL) -#define HSP_EVT_ISR_CAPRDYF_Msk (0x1UL << HSP_EVT_ISR_CAPRDYF_Pos) /*!< 0x00000010 */ -#define HSP_EVT_ISR_CAPRDYF HSP_EVT_ISR_CAPRDYF_Msk /*!< CAPRDYF (Capture buffer data ready flag) */ - -#define HSP_EVT_ISR_CDEGRDYF_Pos (7UL) -#define HSP_EVT_ISR_CDEGRDYF_Msk (0x1UL << HSP_EVT_ISR_CDEGRDYF_Pos) /*!< 0x00000080 */ -#define HSP_EVT_ISR_CDEGRDYF HSP_EVT_ISR_CDEGRDYF_Msk /*!< CDEGRDYF (CPU Dedicated event generator ready flag) */ - -#define HSP_EVT_ISR_SOFWFEF_Pos (8UL) -#define HSP_EVT_ISR_SOFWFEF_Msk (0x1UL << HSP_EVT_ISR_SOFWFEF_Pos) /*!< 0x00000100 */ -#define HSP_EVT_ISR_SOFWFEF HSP_EVT_ISR_SOFWFEF_Msk /*!< SOFWFEF (Start of WFE flag) */ - -#define HSP_EVT_ISR_EOFWFEF_Pos (9UL) -#define HSP_EVT_ISR_EOFWFEF_Msk (0x1UL << HSP_EVT_ISR_EOFWFEF_Pos) /*!< 0x00000200 */ -#define HSP_EVT_ISR_EOFWFEF HSP_EVT_ISR_EOFWFEF_Msk /*!< EOFWFEF (End of WFE flag) */ - -#define HSP_EVT_ISR_B0EVTF_Pos (12UL) -#define HSP_EVT_ISR_B0EVTF_Msk (0x1UL << HSP_EVT_ISR_B0EVTF_Pos) /*!< 0x00001000 */ -#define HSP_EVT_ISR_B0EVTF HSP_EVT_ISR_B0EVTF_Msk /*!< B0EVTF (BUFF0 event flag) */ - -#define HSP_EVT_ISR_B1EVTF_Pos (13UL) -#define HSP_EVT_ISR_B1EVTF_Msk (0x1UL << HSP_EVT_ISR_B1EVTF_Pos) /*!< 0x00002000 */ -#define HSP_EVT_ISR_B1EVTF HSP_EVT_ISR_B1EVTF_Msk /*!< B1EVTF (BUFF1 event flag) */ - -#define HSP_EVT_ISR_B2EVTF_Pos (14UL) -#define HSP_EVT_ISR_B2EVTF_Msk (0x1UL << HSP_EVT_ISR_B2EVTF_Pos) /*!< 0x00004000 */ -#define HSP_EVT_ISR_B2EVTF HSP_EVT_ISR_B2EVTF_Msk /*!< B2EVTF (BUFF2 event flag) */ - -#define HSP_EVT_ISR_B3EVTF_Pos (15UL) -#define HSP_EVT_ISR_B3EVTF_Msk (0x1UL << HSP_EVT_ISR_B3EVTF_Pos) /*!< 0x00008000 */ -#define HSP_EVT_ISR_B3EVTF HSP_EVT_ISR_B3EVTF_Msk /*!< B3EVTF (BUFF3 event flag) */ - -#define HSP_EVT_ISR_SOTECP0F_Pos (16UL) -#define HSP_EVT_ISR_SOTECP0F_Msk (0x1UL << HSP_EVT_ISR_SOTECP0F_Pos) /*!< 0x00010000 */ -#define HSP_EVT_ISR_SOTECP0F HSP_EVT_ISR_SOTECP0F_Msk /*!< SOTECP0F (Start of task flag, for event comparator 0) */ - -#define HSP_EVT_ISR_SOTECP1F_Pos (17UL) -#define HSP_EVT_ISR_SOTECP1F_Msk (0x1UL << HSP_EVT_ISR_SOTECP1F_Pos) /*!< 0x00020000 */ -#define HSP_EVT_ISR_SOTECP1F HSP_EVT_ISR_SOTECP1F_Msk /*!< SOTECP1F (Start of task flag, for event comparator 1) */ - -#define HSP_EVT_ISR_SOTECP2F_Pos (18UL) -#define HSP_EVT_ISR_SOTECP2F_Msk (0x1UL << HSP_EVT_ISR_SOTECP2F_Pos) /*!< 0x00040000 */ -#define HSP_EVT_ISR_SOTECP2F HSP_EVT_ISR_SOTECP2F_Msk /*!< SOTECP2F (Start of task flag, for event comparator 2) */ - -#define HSP_EVT_ISR_SOTECP3F_Pos (19UL) -#define HSP_EVT_ISR_SOTECP3F_Msk (0x1UL << HSP_EVT_ISR_SOTECP3F_Pos) /*!< 0x00080000 */ -#define HSP_EVT_ISR_SOTECP3F HSP_EVT_ISR_SOTECP3F_Msk /*!< SOTECP3F (Start of task flag, for event comparator 3) */ - -#define HSP_EVT_ISR_EOTECP0F_Pos (20UL) -#define HSP_EVT_ISR_EOTECP0F_Msk (0x1UL << HSP_EVT_ISR_EOTECP0F_Pos) /*!< 0x00100000 */ -#define HSP_EVT_ISR_EOTECP0F HSP_EVT_ISR_EOTECP0F_Msk /*!< EOTECP0F (End of task flag, for event comparator 0) */ - -#define HSP_EVT_ISR_EOTECP1F_Pos (21UL) -#define HSP_EVT_ISR_EOTECP1F_Msk (0x1UL << HSP_EVT_ISR_EOTECP1F_Pos) /*!< 0x00200000 */ -#define HSP_EVT_ISR_EOTECP1F HSP_EVT_ISR_EOTECP1F_Msk /*!< EOTECP1F (End of task flag, for event comparator 1) */ - -#define HSP_EVT_ISR_EOTECP2F_Pos (22UL) -#define HSP_EVT_ISR_EOTECP2F_Msk (0x1UL << HSP_EVT_ISR_EOTECP2F_Pos) /*!< 0x00400000 */ -#define HSP_EVT_ISR_EOTECP2F HSP_EVT_ISR_EOTECP2F_Msk /*!< EOTECP2F (End of task flag, for event comparator 2) */ - -#define HSP_EVT_ISR_EOTECP3F_Pos (23UL) -#define HSP_EVT_ISR_EOTECP3F_Msk (0x1UL << HSP_EVT_ISR_EOTECP3F_Pos) /*!< 0x00800000 */ -#define HSP_EVT_ISR_EOTECP3F HSP_EVT_ISR_EOTECP3F_Msk /*!< EOTECP3F (End of task flag, for event comparator 3) */ - -#define HSP_EVT_ISR_TOVLPF_Pos (28UL) -#define HSP_EVT_ISR_TOVLPF_Msk (0x1UL << HSP_EVT_ISR_TOVLPF_Pos) /*!< 0x10000000 */ -#define HSP_EVT_ISR_TOVLPF HSP_EVT_ISR_TOVLPF_Msk /*!< TOVLPF (Task overlap flag) */ - -#define HSP_EVT_ISR_FPUSATF_Pos (31UL) -#define HSP_EVT_ISR_FPUSATF_Msk (0x1UL << HSP_EVT_ISR_FPUSATF_Pos) /*!< 0x80000000 */ -#define HSP_EVT_ISR_FPUSATF HSP_EVT_ISR_FPUSATF_Msk /*!< FPUSATF (FPU saturation flag) */ - -/******************** Bit definition for HSP_PFCTEVT_ISR register ********************/ -#define HSP_PFCTEVT_ISR_PFCTF_Pos (0UL) -#define HSP_PFCTEVT_ISR_PFCTF_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PFCTEVT_ISR_PFCTF HSP_PFCTEVT_ISR_PFCTF_Msk /*!< PFCTF[31:0] bits (Flags generated by SPE processing functions ) */ -#define HSP_PFCTEVT_ISR_PFCTF_0 (0x00001UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000001 */ -#define HSP_PFCTEVT_ISR_PFCTF_1 (0x00002UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000002 */ -#define HSP_PFCTEVT_ISR_PFCTF_2 (0x00004UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000004 */ -#define HSP_PFCTEVT_ISR_PFCTF_3 (0x00008UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000008 */ -#define HSP_PFCTEVT_ISR_PFCTF_4 (0x00010UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000010 */ -#define HSP_PFCTEVT_ISR_PFCTF_5 (0x00020UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000020 */ -#define HSP_PFCTEVT_ISR_PFCTF_6 (0x00040UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000040 */ -#define HSP_PFCTEVT_ISR_PFCTF_7 (0x00080UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000080 */ -#define HSP_PFCTEVT_ISR_PFCTF_8 (0x00100UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000100 */ -#define HSP_PFCTEVT_ISR_PFCTF_9 (0x00200UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000200 */ -#define HSP_PFCTEVT_ISR_PFCTF_10 (0x00400UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000400 */ -#define HSP_PFCTEVT_ISR_PFCTF_11 (0x00800UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00000800 */ -#define HSP_PFCTEVT_ISR_PFCTF_12 (0x01000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00001000 */ -#define HSP_PFCTEVT_ISR_PFCTF_13 (0x02000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00002000 */ -#define HSP_PFCTEVT_ISR_PFCTF_14 (0x04000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00004000 */ -#define HSP_PFCTEVT_ISR_PFCTF_15 (0x08000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00008000 */ -#define HSP_PFCTEVT_ISR_PFCTF_16 (0x10000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00010000 */ -#define HSP_PFCTEVT_ISR_PFCTF_17 (0x20000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00020000 */ -#define HSP_PFCTEVT_ISR_PFCTF_18 (0x40000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00040000 */ -#define HSP_PFCTEVT_ISR_PFCTF_19 (0x80000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00080000 */ -#define HSP_PFCTEVT_ISR_PFCTF_20 (0x100000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00100000 */ -#define HSP_PFCTEVT_ISR_PFCTF_21 (0x200000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00200000 */ -#define HSP_PFCTEVT_ISR_PFCTF_22 (0x400000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00400000 */ -#define HSP_PFCTEVT_ISR_PFCTF_23 (0x800000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x00800000 */ -#define HSP_PFCTEVT_ISR_PFCTF_24 (0x1000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x01000000 */ -#define HSP_PFCTEVT_ISR_PFCTF_25 (0x2000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x02000000 */ -#define HSP_PFCTEVT_ISR_PFCTF_26 (0x4000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x04000000 */ -#define HSP_PFCTEVT_ISR_PFCTF_27 (0x8000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x08000000 */ -#define HSP_PFCTEVT_ISR_PFCTF_28 (0x10000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x10000000 */ -#define HSP_PFCTEVT_ISR_PFCTF_29 (0x20000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x20000000 */ -#define HSP_PFCTEVT_ISR_PFCTF_30 (0x40000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x40000000 */ -#define HSP_PFCTEVT_ISR_PFCTF_31 (0x80000000UL << HSP_PFCTEVT_ISR_PFCTF_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_ERRINFR register ********************/ -#define HSP_ERRINFR_INEXACT_Pos (0UL) -#define HSP_ERRINFR_INEXACT_Msk (0x1UL << HSP_ERRINFR_INEXACT_Pos) /*!< 0x00000001 */ -#define HSP_ERRINFR_INEXACT HSP_ERRINFR_INEXACT_Msk /*!< INEXACT (INEXACT exception flag) */ - -#define HSP_ERRINFR_UDFLOW_Pos (1UL) -#define HSP_ERRINFR_UDFLOW_Msk (0x1UL << HSP_ERRINFR_UDFLOW_Pos) /*!< 0x00000002 */ -#define HSP_ERRINFR_UDFLOW HSP_ERRINFR_UDFLOW_Msk /*!< UDFLOW (UNDERFLOW exception flag) */ - -#define HSP_ERRINFR_OVFLOW_Pos (2UL) -#define HSP_ERRINFR_OVFLOW_Msk (0x1UL << HSP_ERRINFR_OVFLOW_Pos) /*!< 0x00000004 */ -#define HSP_ERRINFR_OVFLOW HSP_ERRINFR_OVFLOW_Msk /*!< OVFLOW (OVERFLOW exception flag) */ - -#define HSP_ERRINFR_DIVZERO_Pos (3UL) -#define HSP_ERRINFR_DIVZERO_Msk (0x1UL << HSP_ERRINFR_DIVZERO_Pos) /*!< 0x00000008 */ -#define HSP_ERRINFR_DIVZERO HSP_ERRINFR_DIVZERO_Msk /*!< DIVZERO (Division by zero exception flag) */ - -#define HSP_ERRINFR_INVALID_Pos (4UL) -#define HSP_ERRINFR_INVALID_Msk (0x1UL << HSP_ERRINFR_INVALID_Pos) /*!< 0x00000010 */ -#define HSP_ERRINFR_INVALID HSP_ERRINFR_INVALID_Msk /*!< INVALID (INVALID exception flag) */ - -#define HSP_ERRINFR_DENORM_Pos (5UL) -#define HSP_ERRINFR_DENORM_Msk (0x1UL << HSP_ERRINFR_DENORM_Pos) /*!< 0x00000020 */ -#define HSP_ERRINFR_DENORM HSP_ERRINFR_DENORM_Msk /*!< DENORM (DENORMAL exception flag) */ - -#define HSP_ERRINFR_CMERR_Pos (8UL) -#define HSP_ERRINFR_CMERR_Msk (0x1UL << HSP_ERRINFR_CMERR_Pos) /*!< 0x00000100 */ -#define HSP_ERRINFR_CMERR HSP_ERRINFR_CMERR_Msk /*!< CMERR (Code memory access error flag) */ - -#define HSP_ERRINFR_DMERR_Pos (9UL) -#define HSP_ERRINFR_DMERR_Msk (0x1UL << HSP_ERRINFR_DMERR_Pos) /*!< 0x00000200 */ -#define HSP_ERRINFR_DMERR HSP_ERRINFR_DMERR_Msk /*!< DMERR (Data memory access error flag) */ - -#define HSP_ERRINFR_MAHBERR_Pos (11UL) -#define HSP_ERRINFR_MAHBERR_Msk (0x1UL << HSP_ERRINFR_MAHBERR_Pos) /*!< 0x00000800 */ -#define HSP_ERRINFR_MAHBERR HSP_ERRINFR_MAHBERR_Msk /*!< MAHBERR (Internal AHB access error flag) */ - -#define HSP_ERRINFR_SAHBERR_Pos (12UL) -#define HSP_ERRINFR_SAHBERR_Msk (0x1UL << HSP_ERRINFR_SAHBERR_Pos) /*!< 0x00001000 */ -#define HSP_ERRINFR_SAHBERR HSP_ERRINFR_SAHBERR_Msk /*!< SAHBERR (Slave AHB access error flag) */ - -#define HSP_ERRINFR_TRGIERR_Pos (16UL) -#define HSP_ERRINFR_TRGIERR_Msk (0x3FFUL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x03FF0000 */ -#define HSP_ERRINFR_TRGIERR HSP_ERRINFR_TRGIERR_Msk /*!< TRGIERR[9:0] bits (TRGIN error information) */ -#define HSP_ERRINFR_TRGIERR_0 (0x001UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00010000 */ -#define HSP_ERRINFR_TRGIERR_1 (0x002UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00020000 */ -#define HSP_ERRINFR_TRGIERR_2 (0x004UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00040000 */ -#define HSP_ERRINFR_TRGIERR_3 (0x008UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00080000 */ -#define HSP_ERRINFR_TRGIERR_4 (0x010UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00100000 */ -#define HSP_ERRINFR_TRGIERR_5 (0x020UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00200000 */ -#define HSP_ERRINFR_TRGIERR_6 (0x040UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00400000 */ -#define HSP_ERRINFR_TRGIERR_7 (0x080UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x00800000 */ -#define HSP_ERRINFR_TRGIERR_8 (0x100UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x01000000 */ -#define HSP_ERRINFR_TRGIERR_9 (0x200UL << HSP_ERRINFR_TRGIERR_Pos) /*!< 0x02000000 */ - -/******************** Bit definition for HSP_ERR_ICR register ********************/ -#define HSP_ERR_ICR_TRGIOVRC_Pos (8UL) -#define HSP_ERR_ICR_TRGIOVRC_Msk (0x1UL << HSP_ERR_ICR_TRGIOVRC_Pos) /*!< 0x00000100 */ -#define HSP_ERR_ICR_TRGIOVRC HSP_ERR_ICR_TRGIOVRC_Msk /*!< TRGIOVRC (Clear TRGIOVRF flag) */ - -#define HSP_ERR_ICR_B0ERRC_Pos (12UL) -#define HSP_ERR_ICR_B0ERRC_Msk (0x1UL << HSP_ERR_ICR_B0ERRC_Pos) /*!< 0x00001000 */ -#define HSP_ERR_ICR_B0ERRC HSP_ERR_ICR_B0ERRC_Msk /*!< B0ERRC (Clear B0ERRF flag) */ - -#define HSP_ERR_ICR_B1ERRC_Pos (13UL) -#define HSP_ERR_ICR_B1ERRC_Msk (0x1UL << HSP_ERR_ICR_B1ERRC_Pos) /*!< 0x00002000 */ -#define HSP_ERR_ICR_B1ERRC HSP_ERR_ICR_B1ERRC_Msk /*!< B1ERRC (Clear B1ERRF flag) */ - -#define HSP_ERR_ICR_B2ERRC_Pos (14UL) -#define HSP_ERR_ICR_B2ERRC_Msk (0x1UL << HSP_ERR_ICR_B2ERRC_Pos) /*!< 0x00004000 */ -#define HSP_ERR_ICR_B2ERRC HSP_ERR_ICR_B2ERRC_Msk /*!< B2ERRC (Clear B2ERRF flag) */ - -#define HSP_ERR_ICR_B3ERRC_Pos (15UL) -#define HSP_ERR_ICR_B3ERRC_Msk (0x1UL << HSP_ERR_ICR_B3ERRC_Pos) /*!< 0x00008000 */ -#define HSP_ERR_ICR_B3ERRC HSP_ERR_ICR_B3ERRC_Msk /*!< B3ERRC (Clear B3ERRF flag) */ - -#define HSP_ERR_ICR_CAPOVRC_Pos (16UL) -#define HSP_ERR_ICR_CAPOVRC_Msk (0x1UL << HSP_ERR_ICR_CAPOVRC_Pos) /*!< 0x00010000 */ -#define HSP_ERR_ICR_CAPOVRC HSP_ERR_ICR_CAPOVRC_Msk /*!< CAPOVRC (Clear CAPOVRF flag) */ - -#define HSP_ERR_ICR_FWERRC_Pos (17UL) -#define HSP_ERR_ICR_FWERRC_Msk (0x1UL << HSP_ERR_ICR_FWERRC_Pos) /*!< 0x00020000 */ -#define HSP_ERR_ICR_FWERRC HSP_ERR_ICR_FWERRC_Msk /*!< FWERRC (Clear FWERRF flag) */ - -#define HSP_ERR_ICR_SCHERRC_Pos (18UL) -#define HSP_ERR_ICR_SCHERRC_Msk (0x1UL << HSP_ERR_ICR_SCHERRC_Pos) /*!< 0x00040000 */ -#define HSP_ERR_ICR_SCHERRC HSP_ERR_ICR_SCHERRC_Msk /*!< SCHERRC (Clear SCHERRF flag) */ - -#define HSP_ERR_ICR_BKINC_Pos (19UL) -#define HSP_ERR_ICR_BKINC_Msk (0x1UL << HSP_ERR_ICR_BKINC_Pos) /*!< 0x00080000 */ -#define HSP_ERR_ICR_BKINC HSP_ERR_ICR_BKINC_Msk /*!< BKINC (Clear BKINF flag) */ - -#define HSP_ERR_ICR_HDEGOVRC_Pos (20UL) -#define HSP_ERR_ICR_HDEGOVRC_Msk (0x1UL << HSP_ERR_ICR_HDEGOVRC_Pos) /*!< 0x00100000 */ -#define HSP_ERR_ICR_HDEGOVRC HSP_ERR_ICR_HDEGOVRC_Msk /*!< HDEGOVRC (Clear HDEGOVRF flag) */ - -#define HSP_ERR_ICR_OPCOERRC_Pos (22UL) -#define HSP_ERR_ICR_OPCOERRC_Msk (0x1UL << HSP_ERR_ICR_OPCOERRC_Pos) /*!< 0x00400000 */ -#define HSP_ERR_ICR_OPCOERRC HSP_ERR_ICR_OPCOERRC_Msk /*!< OPCOERRC (Clear OPCOERRF flag) */ - -#define HSP_ERR_ICR_ACCERRC_Pos (23UL) -#define HSP_ERR_ICR_ACCERRC_Msk (0x1UL << HSP_ERR_ICR_ACCERRC_Pos) /*!< 0x00800000 */ -#define HSP_ERR_ICR_ACCERRC HSP_ERR_ICR_ACCERRC_Msk /*!< ACCERRC (Clear ACCERRF flag) */ - -#define HSP_ERR_ICR_FPUERRC_Pos (24UL) -#define HSP_ERR_ICR_FPUERRC_Msk (0x1UL << HSP_ERR_ICR_FPUERRC_Pos) /*!< 0x01000000 */ -#define HSP_ERR_ICR_FPUERRC HSP_ERR_ICR_FPUERRC_Msk /*!< FPUERRC (Clear FPUERRF flag) */ - -/******************** Bit definition for HSP_EVT_ICR register ********************/ -#define HSP_EVT_ICR_H2CMRDYC_Pos (0UL) -#define HSP_EVT_ICR_H2CMRDYC_Msk (0x1UL << HSP_EVT_ICR_H2CMRDYC_Pos) /*!< 0x00000001 */ -#define HSP_EVT_ICR_H2CMRDYC HSP_EVT_ICR_H2CMRDYC_Msk /*!< H2CMRDYC (Clear H2CMRDYF flag) */ - -#define HSP_EVT_ICR_C2HMFREEC_Pos (1UL) -#define HSP_EVT_ICR_C2HMFREEC_Msk (0x1UL << HSP_EVT_ICR_C2HMFREEC_Pos) /*!< 0x00000002 */ -#define HSP_EVT_ICR_C2HMFREEC HSP_EVT_ICR_C2HMFREEC_Msk /*!< C2HMFREEC (Clear C2HMFREEF flag) */ - -#define HSP_EVT_ICR_DCDONEC_Pos (2UL) -#define HSP_EVT_ICR_DCDONEC_Msk (0x1UL << HSP_EVT_ICR_DCDONEC_Pos) /*!< 0x00000004 */ -#define HSP_EVT_ICR_DCDONEC HSP_EVT_ICR_DCDONEC_Msk /*!< DCDONEC (Clear DCDONEF flag) */ - -#define HSP_EVT_ICR_CDEGRDYC_Pos (7UL) -#define HSP_EVT_ICR_CDEGRDYC_Msk (0x1UL << HSP_EVT_ICR_CDEGRDYC_Pos) /*!< 0x00000080 */ -#define HSP_EVT_ICR_CDEGRDYC HSP_EVT_ICR_CDEGRDYC_Msk /*!< CDEGRDYC (Clear of CDEGRDYF flag) */ - -#define HSP_EVT_ICR_SOFWFEC_Pos (8UL) -#define HSP_EVT_ICR_SOFWFEC_Msk (0x1UL << HSP_EVT_ICR_SOFWFEC_Pos) /*!< 0x00000100 */ -#define HSP_EVT_ICR_SOFWFEC HSP_EVT_ICR_SOFWFEC_Msk /*!< SOFWFEC (Clear of SOFWFEF flag) */ - -#define HSP_EVT_ICR_EOFWFEC_Pos (9UL) -#define HSP_EVT_ICR_EOFWFEC_Msk (0x1UL << HSP_EVT_ICR_EOFWFEC_Pos) /*!< 0x00000200 */ -#define HSP_EVT_ICR_EOFWFEC HSP_EVT_ICR_EOFWFEC_Msk /*!< EOFWFEC (Clear of EOFWFEF flag) */ - -#define HSP_EVT_ICR_SOTECP0C_Pos (16UL) -#define HSP_EVT_ICR_SOTECP0C_Msk (0x1UL << HSP_EVT_ICR_SOTECP0C_Pos) /*!< 0x00010000 */ -#define HSP_EVT_ICR_SOTECP0C HSP_EVT_ICR_SOTECP0C_Msk /*!< SOTECP0C (Clear SOTECP0F flag) */ - -#define HSP_EVT_ICR_SOTECP1C_Pos (17UL) -#define HSP_EVT_ICR_SOTECP1C_Msk (0x1UL << HSP_EVT_ICR_SOTECP1C_Pos) /*!< 0x00020000 */ -#define HSP_EVT_ICR_SOTECP1C HSP_EVT_ICR_SOTECP1C_Msk /*!< SOTECP1C (Clear SOTECP1F flag) */ - -#define HSP_EVT_ICR_SOTECP2C_Pos (18UL) -#define HSP_EVT_ICR_SOTECP2C_Msk (0x1UL << HSP_EVT_ICR_SOTECP2C_Pos) /*!< 0x00040000 */ -#define HSP_EVT_ICR_SOTECP2C HSP_EVT_ICR_SOTECP2C_Msk /*!< SOTECP2C (Clear SOTECP2F flag) */ - -#define HSP_EVT_ICR_SOTECP3C_Pos (19UL) -#define HSP_EVT_ICR_SOTECP3C_Msk (0x1UL << HSP_EVT_ICR_SOTECP3C_Pos) /*!< 0x00080000 */ -#define HSP_EVT_ICR_SOTECP3C HSP_EVT_ICR_SOTECP3C_Msk /*!< SOTECP3C (Clear SOTECP3F flag) */ - -#define HSP_EVT_ICR_EOTECP0C_Pos (20UL) -#define HSP_EVT_ICR_EOTECP0C_Msk (0x1UL << HSP_EVT_ICR_EOTECP0C_Pos) /*!< 0x00100000 */ -#define HSP_EVT_ICR_EOTECP0C HSP_EVT_ICR_EOTECP0C_Msk /*!< EOTECP0C (Clear EOTECP0F flag) */ - -#define HSP_EVT_ICR_EOTECP1C_Pos (21UL) -#define HSP_EVT_ICR_EOTECP1C_Msk (0x1UL << HSP_EVT_ICR_EOTECP1C_Pos) /*!< 0x00200000 */ -#define HSP_EVT_ICR_EOTECP1C HSP_EVT_ICR_EOTECP1C_Msk /*!< EOTECP1C (Clear EOTECP1F flag) */ - -#define HSP_EVT_ICR_EOTECP2C_Pos (22UL) -#define HSP_EVT_ICR_EOTECP2C_Msk (0x1UL << HSP_EVT_ICR_EOTECP2C_Pos) /*!< 0x00400000 */ -#define HSP_EVT_ICR_EOTECP2C HSP_EVT_ICR_EOTECP2C_Msk /*!< EOTECP2C (Clear EOTECP2F flag) */ - -#define HSP_EVT_ICR_EOTECP3C_Pos (23UL) -#define HSP_EVT_ICR_EOTECP3C_Msk (0x1UL << HSP_EVT_ICR_EOTECP3C_Pos) /*!< 0x00800000 */ -#define HSP_EVT_ICR_EOTECP3C HSP_EVT_ICR_EOTECP3C_Msk /*!< EOTECP3C (Clear EOTECP3F flag) */ - -#define HSP_EVT_ICR_TOVLPC_Pos (28UL) -#define HSP_EVT_ICR_TOVLPC_Msk (0x1UL << HSP_EVT_ICR_TOVLPC_Pos) /*!< 0x10000000 */ -#define HSP_EVT_ICR_TOVLPC HSP_EVT_ICR_TOVLPC_Msk /*!< TOVLPC (Clear TOVLPF flag) */ - -#define HSP_EVT_ICR_FPUSATC_Pos (31UL) -#define HSP_EVT_ICR_FPUSATC_Msk (0x1UL << HSP_EVT_ICR_FPUSATC_Pos) /*!< 0x80000000 */ -#define HSP_EVT_ICR_FPUSATC HSP_EVT_ICR_FPUSATC_Msk /*!< FPUSATC (Clear FPUSATF flag) */ - -/******************** Bit definition for HSP_PFCTEVT_ICR register ********************/ -#define HSP_PFCTEVT_ICR_PFCTC_Pos (0UL) -#define HSP_PFCTEVT_ICR_PFCTC_Msk (0xFFFFFFFFUL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0xFFFFFFFF */ -#define HSP_PFCTEVT_ICR_PFCTC HSP_PFCTEVT_ICR_PFCTC_Msk /*!< PFCTC[31:0] bits (Clear PFCTF[31:0] flag) */ -#define HSP_PFCTEVT_ICR_PFCTC_0 (0x00001UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000001 */ -#define HSP_PFCTEVT_ICR_PFCTC_1 (0x00002UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000002 */ -#define HSP_PFCTEVT_ICR_PFCTC_2 (0x00004UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000004 */ -#define HSP_PFCTEVT_ICR_PFCTC_3 (0x00008UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000008 */ -#define HSP_PFCTEVT_ICR_PFCTC_4 (0x00010UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000010 */ -#define HSP_PFCTEVT_ICR_PFCTC_5 (0x00020UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000020 */ -#define HSP_PFCTEVT_ICR_PFCTC_6 (0x00040UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000040 */ -#define HSP_PFCTEVT_ICR_PFCTC_7 (0x00080UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000080 */ -#define HSP_PFCTEVT_ICR_PFCTC_8 (0x00100UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000100 */ -#define HSP_PFCTEVT_ICR_PFCTC_9 (0x00200UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000200 */ -#define HSP_PFCTEVT_ICR_PFCTC_10 (0x00400UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000400 */ -#define HSP_PFCTEVT_ICR_PFCTC_11 (0x00800UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00000800 */ -#define HSP_PFCTEVT_ICR_PFCTC_12 (0x01000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00001000 */ -#define HSP_PFCTEVT_ICR_PFCTC_13 (0x02000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00002000 */ -#define HSP_PFCTEVT_ICR_PFCTC_14 (0x04000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00004000 */ -#define HSP_PFCTEVT_ICR_PFCTC_15 (0x08000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00008000 */ -#define HSP_PFCTEVT_ICR_PFCTC_16 (0x10000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00010000 */ -#define HSP_PFCTEVT_ICR_PFCTC_17 (0x20000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00020000 */ -#define HSP_PFCTEVT_ICR_PFCTC_18 (0x40000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00040000 */ -#define HSP_PFCTEVT_ICR_PFCTC_19 (0x80000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00080000 */ -#define HSP_PFCTEVT_ICR_PFCTC_20 (0x100000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00100000 */ -#define HSP_PFCTEVT_ICR_PFCTC_21 (0x200000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00200000 */ -#define HSP_PFCTEVT_ICR_PFCTC_22 (0x400000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00400000 */ -#define HSP_PFCTEVT_ICR_PFCTC_23 (0x800000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x00800000 */ -#define HSP_PFCTEVT_ICR_PFCTC_24 (0x1000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x01000000 */ -#define HSP_PFCTEVT_ICR_PFCTC_25 (0x2000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x02000000 */ -#define HSP_PFCTEVT_ICR_PFCTC_26 (0x4000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x04000000 */ -#define HSP_PFCTEVT_ICR_PFCTC_27 (0x8000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x08000000 */ -#define HSP_PFCTEVT_ICR_PFCTC_28 (0x10000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x10000000 */ -#define HSP_PFCTEVT_ICR_PFCTC_29 (0x20000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x20000000 */ -#define HSP_PFCTEVT_ICR_PFCTC_30 (0x40000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x40000000 */ -#define HSP_PFCTEVT_ICR_PFCTC_31 (0x80000000UL << HSP_PFCTEVT_ICR_PFCTC_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for HSP_FWVERR register ********************/ -#define HSP_FWVERR_CRAMINREV_Pos (0UL) -#define HSP_FWVERR_CRAMINREV_Msk (0xFFUL << HSP_FWVERR_CRAMINREV_Pos) /*!< 0x000000FF */ -#define HSP_FWVERR_CRAMINREV HSP_FWVERR_CRAMINREV_Msk /*!< CRAMINREV[7:0] bits (Code RAM Minor revision) */ - -#define HSP_FWVERR_CRAMAJREV_Pos (8UL) -#define HSP_FWVERR_CRAMAJREV_Msk (0xFUL << HSP_FWVERR_CRAMAJREV_Pos) /*!< 0x00000F00 */ -#define HSP_FWVERR_CRAMAJREV HSP_FWVERR_CRAMAJREV_Msk /*!< CRAMAJREV[3:0] bits (Code RAM Major revision) */ - -#define HSP_FWVERR_CROMINREV_Pos (12UL) -#define HSP_FWVERR_CROMINREV_Msk (0xFFUL << HSP_FWVERR_CROMINREV_Pos) /*!< 0x000FF000 */ -#define HSP_FWVERR_CROMINREV HSP_FWVERR_CROMINREV_Msk /*!< CROMINREV[7:0] bits (Code ROM Minor revision) */ - -#define HSP_FWVERR_CROMAJREV_Pos (20UL) -#define HSP_FWVERR_CROMAJREV_Msk (0xFUL << HSP_FWVERR_CROMAJREV_Pos) /*!< 0x000F0000 */ -#define HSP_FWVERR_CROMAJREV HSP_FWVERR_CROMAJREV_Msk /*!< CROMAJREV[3:0] bits (Code ROM Major revision) */ - -#define HSP_FWVERR_DROMINREV_Pos (24UL) -#define HSP_FWVERR_DROMINREV_Msk (0xFUL << HSP_FWVERR_DROMINREV_Pos) /*!< 0x00F00000 */ -#define HSP_FWVERR_DROMINREV HSP_FWVERR_DROMINREV_Msk /*!< DROMINREV[3:0] bits (Data ROM Minor revision) */ - -#define HSP_FWVERR_DROMAJREV_Pos (28UL) -#define HSP_FWVERR_DROMAJREV_Msk (0xFUL << HSP_FWVERR_DROMAJREV_Pos) /*!< 0x0F000000 */ -#define HSP_FWVERR_DROMAJREV HSP_FWVERR_DROMAJREV_Msk /*!< DROMAJREV[3:0] bits (Data ROM Major revision) */ - -/******************************************************************************/ -/* */ -/* Inter-integrated Circuit Interface (I2C) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for I2C_CR1 register *******************/ -#define I2C_CR1_PE_Pos (0UL) -#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ -#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ -#define I2C_CR1_TXIE_Pos (1UL) -#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ -#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ -#define I2C_CR1_RXIE_Pos (2UL) -#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ -#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ -#define I2C_CR1_ADDRIE_Pos (3UL) -#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ -#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ -#define I2C_CR1_NACKIE_Pos (4UL) -#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ -#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ -#define I2C_CR1_STOPIE_Pos (5UL) -#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ -#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ -#define I2C_CR1_TCIE_Pos (6UL) -#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ -#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ -#define I2C_CR1_ERRIE_Pos (7UL) -#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ -#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ -#define I2C_CR1_DNF_Pos (8UL) -#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ -#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ -#define I2C_CR1_ANFOFF_Pos (12UL) -#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ -#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST_Pos (13UL) -#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ -#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ -#define I2C_CR1_TXDMAEN_Pos (14UL) -#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ -#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ -#define I2C_CR1_RXDMAEN_Pos (15UL) -#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ -#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ -#define I2C_CR1_SBC_Pos (16UL) -#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ -#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ -#define I2C_CR1_NOSTRETCH_Pos (17UL) -#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ -#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ -#define I2C_CR1_WUPEN_Pos (18UL) -#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ -#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ -#define I2C_CR1_GCEN_Pos (19UL) -#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ -#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ -#define I2C_CR1_SMBHEN_Pos (20UL) -#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ -#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ -#define I2C_CR1_SMBDEN_Pos (21UL) -#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ -#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ -#define I2C_CR1_ALERTEN_Pos (22UL) -#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ -#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ -#define I2C_CR1_PECEN_Pos (23UL) -#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ -#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ -#define I2C_CR1_FMP_Pos (24UL) -#define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ -#define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< FMP enable */ -#define I2C_CR1_ADDRACLR_Pos (30UL) -#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ -#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ -#define I2C_CR1_STOPFACLR_Pos (31UL) -#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ -#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ - -/****************** Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_SADD_Pos (0UL) -#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ -#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ -#define I2C_CR2_RD_WRN_Pos (10UL) -#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ -#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ -#define I2C_CR2_ADD10_Pos (11UL) -#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ -#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ -#define I2C_CR2_HEAD10R_Pos (12UL) -#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ -#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ -#define I2C_CR2_START_Pos (13UL) -#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ -#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ -#define I2C_CR2_STOP_Pos (14UL) -#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ -#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ -#define I2C_CR2_NACK_Pos (15UL) -#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ -#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ -#define I2C_CR2_NBYTES_Pos (16UL) -#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ -#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ -#define I2C_CR2_RELOAD_Pos (24UL) -#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ -#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ -#define I2C_CR2_AUTOEND_Pos (25UL) -#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ -#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ -#define I2C_CR2_PECBYTE_Pos (26UL) -#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ -#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ - -/******************* Bit definition for I2C_OAR1 register ******************/ -#define I2C_OAR1_OA1_Pos (0UL) -#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ -#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ -#define I2C_OAR1_OA1MODE_Pos (10UL) -#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ -#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ -#define I2C_OAR1_OA1EN_Pos (15UL) -#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ -#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ - -/******************* Bit definition for I2C_OAR2 register ******************/ -#define I2C_OAR2_OA2_Pos (1UL) -#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ -#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ -#define I2C_OAR2_OA2MSK_Pos (8UL) -#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ -#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ -#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ -#define I2C_OAR2_OA2MASK01_Pos (8UL) -#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ -#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ -#define I2C_OAR2_OA2MASK02_Pos (9UL) -#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ -#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ -#define I2C_OAR2_OA2MASK03_Pos (8UL) -#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ -#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ -#define I2C_OAR2_OA2MASK04_Pos (10UL) -#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ -#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ -#define I2C_OAR2_OA2MASK05_Pos (8UL) -#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ -#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ -#define I2C_OAR2_OA2MASK06_Pos (9UL) -#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ -#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ -#define I2C_OAR2_OA2MASK07_Pos (8UL) -#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ -#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ -#define I2C_OAR2_OA2EN_Pos (15UL) -#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ -#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ - -/******************* Bit definition for I2C_TIMINGR register *******************/ -#define I2C_TIMINGR_SCLL_Pos (0UL) -#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ -#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ -#define I2C_TIMINGR_SCLH_Pos (8UL) -#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ -#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ -#define I2C_TIMINGR_SDADEL_Pos (16UL) -#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ -#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ -#define I2C_TIMINGR_SCLDEL_Pos (20UL) -#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ -#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ -#define I2C_TIMINGR_PRESC_Pos (28UL) -#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ -#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ - -/******************* Bit definition for I2C_TIMEOUTR register *******************/ -#define I2C_TIMEOUTR_TIMEOUTA_Pos (0UL) -#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ -#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ -#define I2C_TIMEOUTR_TIDLE_Pos (12UL) -#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ -#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ -#define I2C_TIMEOUTR_TIMOUTEN_Pos (15UL) -#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ -#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ -#define I2C_TIMEOUTR_TIMEOUTB_Pos (16UL) -#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ -#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ -#define I2C_TIMEOUTR_TEXTEN_Pos (31UL) -#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ -#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ - -/****************** Bit definition for I2C_ISR register *********************/ -#define I2C_ISR_TXE_Pos (0UL) -#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ -#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ -#define I2C_ISR_TXIS_Pos (1UL) -#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ -#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ -#define I2C_ISR_RXNE_Pos (2UL) -#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ -#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ -#define I2C_ISR_ADDR_Pos (3UL) -#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ -#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ -#define I2C_ISR_NACKF_Pos (4UL) -#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ -#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ -#define I2C_ISR_STOPF_Pos (5UL) -#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ -#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ -#define I2C_ISR_TC_Pos (6UL) -#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ -#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ -#define I2C_ISR_TCR_Pos (7UL) -#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ -#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ -#define I2C_ISR_BERR_Pos (8UL) -#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ -#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ -#define I2C_ISR_ARLO_Pos (9UL) -#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ -#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ -#define I2C_ISR_OVR_Pos (10UL) -#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ -#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ -#define I2C_ISR_PECERR_Pos (11UL) -#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ -#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ -#define I2C_ISR_TIMEOUT_Pos (12UL) -#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ -#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ -#define I2C_ISR_ALERT_Pos (13UL) -#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ -#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ -#define I2C_ISR_BUSY_Pos (15UL) -#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ -#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ -#define I2C_ISR_DIR_Pos (16UL) -#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ -#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ -#define I2C_ISR_ADDCODE_Pos (17UL) -#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ -#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ - -/****************** Bit definition for I2C_ICR register *********************/ -#define I2C_ICR_ADDRCF_Pos (3UL) -#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ -#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ -#define I2C_ICR_NACKCF_Pos (4UL) -#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ -#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ -#define I2C_ICR_STOPCF_Pos (5UL) -#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ -#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ -#define I2C_ICR_BERRCF_Pos (8UL) -#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ -#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ -#define I2C_ICR_ARLOCF_Pos (9UL) -#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ -#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ -#define I2C_ICR_OVRCF_Pos (10UL) -#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ -#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ -#define I2C_ICR_PECCF_Pos (11UL) -#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ -#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ -#define I2C_ICR_TIMOUTCF_Pos (12UL) -#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ -#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ -#define I2C_ICR_ALERTCF_Pos (13UL) -#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ -#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ - -/****************** Bit definition for I2C_PECR register *********************/ -#define I2C_PECR_PEC_Pos (0UL) -#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ -#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ - -/****************** Bit definition for I2C_RXDR register *********************/ -#define I2C_RXDR_RXDATA_Pos (0UL) -#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ -#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ - -/****************** Bit definition for I2C_TXDR register *********************/ -#define I2C_TXDR_TXDATA_Pos (0UL) -#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ -#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ - -/****************** Bit definition for I2C_AUTOCR register ********************/ -#define I2C_AUTOCR_TCDMAEN_Pos (6UL) -#define I2C_AUTOCR_TCDMAEN_Msk (0x1UL << I2C_AUTOCR_TCDMAEN_Pos) /*!< 0x00000040 */ -#define I2C_AUTOCR_TCDMAEN I2C_AUTOCR_TCDMAEN_Msk /*!< DMA request enable on Transfer Complete event */ -#define I2C_AUTOCR_TCRDMAEN_Pos (7UL) -#define I2C_AUTOCR_TCRDMAEN_Msk (0x1UL << I2C_AUTOCR_TCRDMAEN_Pos) /*!< 0x00000080 */ -#define I2C_AUTOCR_TCRDMAEN I2C_AUTOCR_TCRDMAEN_Msk /*!< DMA request enable on Transfer Complete Reload event */ -#define I2C_AUTOCR_TRIGSEL_Pos (16UL) -#define I2C_AUTOCR_TRIGSEL_Msk (0xFUL << I2C_AUTOCR_TRIGSEL_Pos) /*!< 0x000F0000 */ -#define I2C_AUTOCR_TRIGSEL I2C_AUTOCR_TRIGSEL_Msk /*!< Trigger selection */ -#define I2C_AUTOCR_TRIGPOL_Pos (20UL) -#define I2C_AUTOCR_TRIGPOL_Msk (0x1UL << I2C_AUTOCR_TRIGPOL_Pos) /*!< 0x000100000 */ -#define I2C_AUTOCR_TRIGPOL I2C_AUTOCR_TRIGPOL_Msk /*!< Trigger polarity */ -#define I2C_AUTOCR_TRIGEN_Pos (21UL) -#define I2C_AUTOCR_TRIGEN_Msk (0x1UL << I2C_AUTOCR_TRIGEN_Pos) /*!< 0x000200000 */ -#define I2C_AUTOCR_TRIGEN I2C_AUTOCR_TRIGEN_Msk /*!< Trigger enable */ - -/******************************************************************************/ -/* */ -/* Improved Inter-integrated Circuit Interface (I3C) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for I3C_CR register *********************/ -#define I3C_CR_DCNT_Pos (0UL) -#define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ -#define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ -#define I3C_CR_RNW_Pos (16UL) -#define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ -#define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ -#define I3C_CR_CCC_Pos (16UL) -#define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ -#define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ -#define I3C_CR_ADD_Pos (17UL) -#define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ -#define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ -#define I3C_CR_MTYPE_Pos (27UL) -#define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ -#define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ -#define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ -#define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ -#define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ -#define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ -#define I3C_CR_MEND_Pos (31UL) -#define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ -#define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ - -/******************* Bit definition for I3C_CFGR register *******************/ -#define I3C_CFGR_EN_Pos (0UL) -#define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ -#define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ -#define I3C_CFGR_CRINIT_Pos (1UL) -#define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ -#define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ -#define I3C_CFGR_NOARBH_Pos (2UL) -#define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ -#define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ -#define I3C_CFGR_RSTPTRN_Pos (3UL) -#define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ -#define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ -#define I3C_CFGR_EXITPTRN_Pos (4UL) -#define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ -#define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ -#define I3C_CFGR_HKSDAEN_Pos (5UL) -#define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ -#define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ -#define I3C_CFGR_HJACK_Pos (7UL) -#define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ -#define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ -#define I3C_CFGR_RXDMAEN_Pos (8UL) -#define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ -#define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ -#define I3C_CFGR_RXFLUSH_Pos (9UL) -#define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ -#define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ -#define I3C_CFGR_RXTHRES_Pos (10UL) -#define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ -#define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ -#define I3C_CFGR_TXDMAEN_Pos (12UL) -#define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ -#define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ -#define I3C_CFGR_TXFLUSH_Pos (13UL) -#define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ -#define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ -#define I3C_CFGR_TXTHRES_Pos (14UL) -#define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ -#define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ -#define I3C_CFGR_SDMAEN_Pos (16UL) -#define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ -#define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ -#define I3C_CFGR_SFLUSH_Pos (17UL) -#define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ -#define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ -#define I3C_CFGR_SMODE_Pos (18UL) -#define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ -#define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ -#define I3C_CFGR_TMODE_Pos (19UL) -#define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ -#define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ -#define I3C_CFGR_CDMAEN_Pos (20UL) -#define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ -#define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ -#define I3C_CFGR_CFLUSH_Pos (21UL) -#define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ -#define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ -#define I3C_CFGR_FCFDIS_Pos (23UL) -#define I3C_CFGR_FCFDIS_Msk (0x1UL << I3C_CFGR_FCFDIS_Pos) /*!< 0x00800000 */ -#define I3C_CFGR_FCFDIS I3C_CFGR_FCFDIS_Msk /*!< FCF generation disable */ -#define I3C_CFGR_TRIGSEL_Pos (24UL) -#define I3C_CFGR_TRIGSEL_Msk (0xFUL << I3C_CFGR_TRIGSEL_Pos) /*!< 0x0F000000 */ -#define I3C_CFGR_TRIGSEL I3C_CFGR_TRIGSEL_Msk /*!< Trigger selection */ -#define I3C_CFGR_TRIGPOL_Pos (28UL) -#define I3C_CFGR_TRIGPOL_Msk (0x1UL << I3C_CFGR_TRIGPOL_Pos) /*!< 0x10000000 */ -#define I3C_CFGR_TRIGPOL I3C_CFGR_TRIGPOL_Msk /*!< Trigger polarity */ -#define I3C_CFGR_TRIGHWEN_Pos (29UL) -#define I3C_CFGR_TRIGHWEN_Msk (0x1UL << I3C_CFGR_TRIGHWEN_Pos) /*!< 0x20000000 */ -#define I3C_CFGR_TRIGHWEN I3C_CFGR_TRIGHWEN_Msk /*!< Trigger enable */ -#define I3C_CFGR_TSFSET_Pos (30UL) -#define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ -#define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ - -/******************* Bit definition for I3C_RDR register ********************/ -#define I3C_RDR_RDB0_Pos (0UL) -#define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ -#define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ - -/****************** Bit definition for I3C_RDWR register ********************/ -#define I3C_RDWR_RDBx_Pos (0UL) -#define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ -#define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ -#define I3C_RDWR_RDB0_Pos (0UL) -#define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ -#define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ -#define I3C_RDWR_RDB1_Pos (8UL) -#define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ -#define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ -#define I3C_RDWR_RDB2_Pos (16UL) -#define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ -#define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ -#define I3C_RDWR_RDB3_Pos (24UL) -#define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ -#define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ - -/******************* Bit definition for I3C_TDR register ********************/ -#define I3C_TDR_TDB0_Pos (0UL) -#define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ -#define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ - -/****************** Bit definition for I3C_TDWR register ********************/ -#define I3C_TDWR_TDBx_Pos (0UL) -#define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ -#define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ -#define I3C_TDWR_TDB0_Pos (0UL) -#define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ -#define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ -#define I3C_TDWR_TDB1_Pos (8UL) -#define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ -#define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ -#define I3C_TDWR_TDB2_Pos (16UL) -#define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ -#define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ -#define I3C_TDWR_TDB3_Pos (24UL) -#define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ -#define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ - -/******************* Bit definition for I3C_IBIDR register ******************/ -#define I3C_IBIDR_IBIDBx_Pos (0UL) -#define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ -#define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ -#define I3C_IBIDR_IBIDB0_Pos (0UL) -#define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ -#define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ -#define I3C_IBIDR_IBIDB1_Pos (8UL) -#define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ -#define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ -#define I3C_IBIDR_IBIDB2_Pos (16UL) -#define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ -#define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ -#define I3C_IBIDR_IBIDB3_Pos (24UL) -#define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ -#define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ - -/****************** Bit definition for I3C_TGTTDR register ******************/ -#define I3C_TGTTDR_TGTTDCNT_Pos (0UL) -#define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ -#define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ -#define I3C_TGTTDR_PRELOAD_Pos (16UL) -#define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ -#define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ - -/******************* Bit definition for I3C_SR register *********************/ -#define I3C_SR_XDCNT_Pos (0UL) -#define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ -#define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ -#define I3C_SR_ABT_Pos (17UL) -#define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ -#define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ -#define I3C_SR_DIR_Pos (18UL) -#define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ -#define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ -#define I3C_SR_MID_Pos (24UL) -#define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ -#define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ - -/******************* Bit definition for I3C_SER register ********************/ -#define I3C_SER_CODERR_Pos (0UL) -#define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ -#define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ -#define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ -#define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ -#define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ -#define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ -#define I3C_SER_PERR_Pos (4UL) -#define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ -#define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ -#define I3C_SER_STALL_Pos (5UL) -#define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ -#define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ -#define I3C_SER_DOVR_Pos (6UL) -#define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ -#define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ -#define I3C_SER_COVR_Pos (7UL) -#define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ -#define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ -#define I3C_SER_ANACK_Pos (8UL) -#define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ -#define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ -#define I3C_SER_DNACK_Pos (9UL) -#define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ -#define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ -#define I3C_SER_DERR_Pos (10UL) -#define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ -#define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ - -/******************* Bit definition for I3C_RMR register ********************/ -#define I3C_RMR_IBIRDCNT_Pos (0UL) -#define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ -#define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ -#define I3C_RMR_RCODE_Pos (8UL) -#define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ -#define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ -#define I3C_RMR_RADD_Pos (17UL) -#define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ -#define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ - -/******************* Bit definition for I3C_EVR register ********************/ -#define I3C_EVR_CFEF_Pos (0UL) -#define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ -#define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ -#define I3C_EVR_TXFEF_Pos (1UL) -#define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ -#define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ -#define I3C_EVR_CFNFF_Pos (2UL) -#define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ -#define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ -#define I3C_EVR_SFNEF_Pos (3UL) -#define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ -#define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ -#define I3C_EVR_TXFNFF_Pos (4UL) -#define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ -#define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ -#define I3C_EVR_RXFNEF_Pos (5UL) -#define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ -#define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ -#define I3C_EVR_TXLASTF_Pos (6UL) -#define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ -#define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ -#define I3C_EVR_RXLASTF_Pos (7UL) -#define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ -#define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ -#define I3C_EVR_FCF_Pos (9UL) -#define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ -#define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ -#define I3C_EVR_RXTGTENDF_Pos (10UL) -#define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ -#define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ -#define I3C_EVR_ERRF_Pos (11UL) -#define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ -#define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ -#define I3C_EVR_IBIF_Pos (15UL) -#define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ -#define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ -#define I3C_EVR_IBIENDF_Pos (16UL) -#define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ -#define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ -#define I3C_EVR_CRF_Pos (17UL) -#define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ -#define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ -#define I3C_EVR_CRUPDF_Pos (18UL) -#define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ -#define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ -#define I3C_EVR_HJF_Pos (19UL) -#define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ -#define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ -#define I3C_EVR_WKPF_Pos (21UL) -#define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ -#define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ -#define I3C_EVR_GETF_Pos (22UL) -#define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ -#define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ -#define I3C_EVR_STAF_Pos (23UL) -#define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ -#define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ -#define I3C_EVR_DAUPDF_Pos (24UL) -#define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ -#define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ -#define I3C_EVR_MWLUPDF_Pos (25UL) -#define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ -#define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ -#define I3C_EVR_MRLUPDF_Pos (26UL) -#define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ -#define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ -#define I3C_EVR_RSTF_Pos (27UL) -#define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ -#define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ -#define I3C_EVR_ASUPDF_Pos (28UL) -#define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ -#define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ -#define I3C_EVR_INTUPDF_Pos (29UL) -#define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ -#define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ -#define I3C_EVR_DEFF_Pos (30UL) -#define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ -#define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ -#define I3C_EVR_GRPF_Pos (31UL) -#define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ -#define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ - -/******************* Bit definition for I3C_IER register ********************/ -#define I3C_IER_CFNFIE_Pos (2UL) -#define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ -#define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ -#define I3C_IER_SFNEIE_Pos (3UL) -#define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ -#define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ -#define I3C_IER_TXFNFIE_Pos (4UL) -#define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ -#define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ -#define I3C_IER_RXFNEIE_Pos (5UL) -#define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ -#define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ -#define I3C_IER_FCIE_Pos (9UL) -#define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ -#define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ -#define I3C_IER_RXTGTENDIE_Pos (10UL) -#define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ -#define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ -#define I3C_IER_ERRIE_Pos (11UL) -#define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ -#define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ -#define I3C_IER_IBIIE_Pos (15UL) -#define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ -#define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ -#define I3C_IER_IBIENDIE_Pos (16UL) -#define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ -#define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ -#define I3C_IER_CRIE_Pos (17UL) -#define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ -#define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ -#define I3C_IER_CRUPDIE_Pos (18UL) -#define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ -#define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ -#define I3C_IER_HJIE_Pos (19UL) -#define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ -#define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ -#define I3C_IER_WKPIE_Pos (21UL) -#define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ -#define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ -#define I3C_IER_GETIE_Pos (22UL) -#define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ -#define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ -#define I3C_IER_STAIE_Pos (23UL) -#define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ -#define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ -#define I3C_IER_DAUPDIE_Pos (24UL) -#define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ -#define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ -#define I3C_IER_MWLUPDIE_Pos (25UL) -#define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ -#define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ -#define I3C_IER_MRLUPDIE_Pos (26UL) -#define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ -#define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ -#define I3C_IER_RSTIE_Pos (27UL) -#define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ -#define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ -#define I3C_IER_ASUPDIE_Pos (28UL) -#define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ -#define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ -#define I3C_IER_INTUPDIE_Pos (29UL) -#define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ -#define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ -#define I3C_IER_DEFIE_Pos (30UL) -#define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ -#define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ -#define I3C_IER_GRPIE_Pos (31UL) -#define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ -#define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ - -/******************* Bit definition for I3C_CEVR register *******************/ -#define I3C_CEVR_CFCF_Pos (9UL) -#define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ -#define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ -#define I3C_CEVR_CRXTGTENDF_Pos (10UL) -#define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ -#define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ -#define I3C_CEVR_CERRF_Pos (11UL) -#define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ -#define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ -#define I3C_CEVR_CIBIF_Pos (15UL) -#define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ -#define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ -#define I3C_CEVR_CIBIENDF_Pos (16UL) -#define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ -#define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ -#define I3C_CEVR_CCRF_Pos (17UL) -#define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ -#define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ -#define I3C_CEVR_CCRUPDF_Pos (18UL) -#define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ -#define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ -#define I3C_CEVR_CHJF_Pos (19UL) -#define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ -#define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ -#define I3C_CEVR_CWKPF_Pos (21UL) -#define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ -#define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ -#define I3C_CEVR_CGETF_Pos (22UL) -#define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ -#define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ -#define I3C_CEVR_CSTAF_Pos (23UL) -#define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ -#define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ -#define I3C_CEVR_CDAUPDF_Pos (24UL) -#define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ -#define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ -#define I3C_CEVR_CMWLUPDF_Pos (25UL) -#define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ -#define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ -#define I3C_CEVR_CMRLUPDF_Pos (26UL) -#define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ -#define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ -#define I3C_CEVR_CRSTF_Pos (27UL) -#define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ -#define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ -#define I3C_CEVR_CASUPDF_Pos (28UL) -#define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ -#define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ -#define I3C_CEVR_CINTUPDF_Pos (29UL) -#define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ -#define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ -#define I3C_CEVR_CDEFF_Pos (30UL) -#define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ -#define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ -#define I3C_CEVR_CGRPF_Pos (31UL) -#define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ -#define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ - -/******************* Bit definition for I3C_MISR register *******************/ -#define I3C_MISR_CFNFMIS_Pos (2UL) -#define I3C_MISR_CFNFMIS_Msk (0x1UL << I3C_MISR_CFNFMIS_Pos) /*!< 0x00000004 */ -#define I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS_Msk /*!< Control FIFO Not Full Mask Interrupt Status */ -#define I3C_MISR_SFNEMIS_Pos (3UL) -#define I3C_MISR_SFNEMIS_Msk (0x1UL << I3C_MISR_SFNEMIS_Pos) /*!< 0x00000008 */ -#define I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS_Msk /*!< Status FIFO Not Empty Mask Interrupt Status */ -#define I3C_MISR_TXFNFMIS_Pos (4UL) -#define I3C_MISR_TXFNFMIS_Msk (0x1UL << I3C_MISR_TXFNFMIS_Pos) /*!< 0x00000010 */ -#define I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS_Msk /*!< TX FIFO Not Full Mask Interrupt Status */ -#define I3C_MISR_RXFNEMIS_Pos (5UL) -#define I3C_MISR_RXFNEMIS_Msk (0x1UL << I3C_MISR_RXFNEMIS_Pos) /*!< 0x00000020 */ -#define I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS_Msk /*!< RX FIFO Not Empty Mask Interrupt Status */ -#define I3C_MISR_FCMIS_Pos (9UL) -#define I3C_MISR_FCMIS_Msk (0x1UL << I3C_MISR_FCMIS_Pos) /*!< 0x00000200 */ -#define I3C_MISR_FCMIS I3C_MISR_FCMIS_Msk /*!< Frame Complete Mask Interrupt Status */ -#define I3C_MISR_RXTGTENDMIS_Pos (10UL) -#define I3C_MISR_RXTGTENDMIS_Msk (0x1UL << I3C_MISR_RXTGTENDMIS_Pos) /*!< 0x00000400 */ -#define I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS_Msk /*!< Reception Target End Mask Interrupt Status */ -#define I3C_MISR_ERRMIS_Pos (11UL) -#define I3C_MISR_ERRMIS_Msk (0x1UL << I3C_MISR_ERRMIS_Pos) /*!< 0x00000800 */ -#define I3C_MISR_ERRMIS I3C_MISR_ERRMIS_Msk /*!< Error Mask Interrupt Status */ -#define I3C_MISR_IBIMIS_Pos (15UL) -#define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ -#define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Mask Interrupt Status */ -#define I3C_MISR_IBIENDMIS_Pos (16UL) -#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ -#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Mask Interrupt Status */ -#define I3C_MISR_CRMIS_Pos (17UL) -#define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ -#define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Mask Interrupt Status */ -#define I3C_MISR_CRUPDMIS_Pos (18UL) -#define I3C_MISR_CRUPDMIS_Msk (0x1UL << I3C_MISR_CRUPDMIS_Pos) /*!< 0x00040000 */ -#define I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS_Msk /*!< Controller-role Update Mask Interrupt Status */ -#define I3C_MISR_HJMIS_Pos (19UL) -#define I3C_MISR_HJMIS_Msk (0x1UL << I3C_MISR_HJMIS_Pos) /*!< 0x00080000 */ -#define I3C_MISR_HJMIS I3C_MISR_HJMIS_Msk /*!< Hot Join Mask Interrupt Status */ -#define I3C_MISR_WKPMIS_Pos (21UL) -#define I3C_MISR_WKPMIS_Msk (0x1UL << I3C_MISR_WKPMIS_Pos) /*!< 0x00200000 */ -#define I3C_MISR_WKPMIS I3C_MISR_WKPMIS_Msk /*!< Wake Up Mask Interrupt Status */ -#define I3C_MISR_GETMIS_Pos (22UL) -#define I3C_MISR_GETMIS_Msk (0x1UL << I3C_MISR_GETMIS_Pos) /*!< 0x00400000 */ -#define I3C_MISR_GETMIS I3C_MISR_GETMIS_Msk /*!< Get type CCC received Mask Interrupt Status */ -#define I3C_MISR_STAMIS_Pos (23UL) -#define I3C_MISR_STAMIS_Msk (0x1UL << I3C_MISR_STAMIS_Pos) /*!< 0x00800000 */ -#define I3C_MISR_STAMIS I3C_MISR_STAMIS_Msk /*!< Get Status Mask Interrupt Status */ -#define I3C_MISR_DAUPDMIS_Pos (24UL) -#define I3C_MISR_DAUPDMIS_Msk (0x1UL << I3C_MISR_DAUPDMIS_Pos) /*!< 0x01000000 */ -#define I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS_Msk /*!< Dynamic Address Update Mask Interrupt Status */ -#define I3C_MISR_MWLUPDMIS_Pos (25UL) -#define I3C_MISR_MWLUPDMIS_Msk (0x1UL << I3C_MISR_MWLUPDMIS_Pos) /*!< 0x02000000 */ -#define I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS_Msk /*!< Max Write Length Update Mask Interrupt Status */ -#define I3C_MISR_MRLUPDMIS_Pos (26UL) -#define I3C_MISR_MRLUPDMIS_Msk (0x1UL << I3C_MISR_MRLUPDMIS_Pos) /*!< 0x04000000 */ -#define I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS_Msk /*!< Max Read Length Update Mask Interrupt Status */ -#define I3C_MISR_RSTMIS_Pos (27UL) -#define I3C_MISR_RSTMIS_Msk (0x1UL << I3C_MISR_RSTMIS_Pos) /*!< 0x08000000 */ -#define I3C_MISR_RSTMIS I3C_MISR_RSTMIS_Msk /*!< Reset Mask Interrupt Status, due to Reset pattern received */ -#define I3C_MISR_ASUPDMIS_Pos (28UL) -#define I3C_MISR_ASUPDMIS_Msk (0x1UL << I3C_MISR_ASUPDMIS_Pos) /*!< 0x10000000 */ -#define I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS_Msk /*!< Activity State Mask Interrupt Status */ -#define I3C_MISR_INTUPDMIS_Pos (29UL) -#define I3C_MISR_INTUPDMIS_Msk (0x1UL << I3C_MISR_INTUPDMIS_Pos) /*!< 0x20000000 */ -#define I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS_Msk /*!< Interrupt Update Mask Interrupt Status */ -#define I3C_MISR_DEFMIS_Pos (30UL) -#define I3C_MISR_DEFMIS_Msk (0x1UL << I3C_MISR_DEFMIS_Pos) /*!< 0x40000000 */ -#define I3C_MISR_DEFMIS I3C_MISR_DEFMIS_Msk /*!< List of Targets Command Received Mask Interrupt Status */ -#define I3C_MISR_GRPMIS_Pos (31UL) -#define I3C_MISR_GRPMIS_Msk (0x1UL << I3C_MISR_GRPMIS_Pos) /*!< 0x80000000 */ -#define I3C_MISR_GRPMIS I3C_MISR_GRPMIS_Msk /*!< List of Group Addresses Command Received Mask Interrupt Status */ - -/****************** Bit definition for I3C_DEVR0 register *******************/ -#define I3C_DEVR0_DAVAL_Pos (0UL) -#define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ -#define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ -#define I3C_DEVR0_DA_Pos (1UL) -#define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ -#define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ -#define I3C_DEVR0_IBIEN_Pos (16UL) -#define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ -#define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ -#define I3C_DEVR0_CREN_Pos (17UL) -#define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ -#define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ -#define I3C_DEVR0_HJEN_Pos (19UL) -#define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ -#define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ -#define I3C_DEVR0_AS_Pos (20UL) -#define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ -#define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ -#define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ -#define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ -#define I3C_DEVR0_RSTACT_Pos (22UL) -#define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ -#define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ -#define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ -#define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ -#define I3C_DEVR0_RSTVAL_Pos (24UL) -#define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ -#define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ - -/****************** Bit definition for I3C_DEVRX register *******************/ -#define I3C_DEVRX_DA_Pos (1UL) -#define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ -#define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ -#define I3C_DEVRX_IBIACK_Pos (16UL) -#define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ -#define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ -#define I3C_DEVRX_CRACK_Pos (17UL) -#define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ -#define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ -#define I3C_DEVRX_IBIDEN_Pos (18UL) -#define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ -#define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ -#define I3C_DEVRX_SUSP_Pos (19UL) -#define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ -#define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ -#define I3C_DEVRX_DIS_Pos (31UL) -#define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ -#define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ - -/****************** Bit definition for I3C_MAXRLR register ******************/ -#define I3C_MAXRLR_MRL_Pos (0UL) -#define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ -#define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ -#define I3C_MAXRLR_IBIP_Pos (16UL) -#define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ -#define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ -#define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ -#define I3C_MAXRLR_IBIP_1 (0x2UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00020000 */ -#define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ - -/****************** Bit definition for I3C_MAXWLR register ******************/ -#define I3C_MAXWLR_MWL_Pos (0UL) -#define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ -#define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ - -/**************** Bit definition for I3C_TIMINGR0 register ******************/ -#define I3C_TIMINGR0_SCLL_PP_Pos (0UL) -#define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ -#define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ -#define I3C_TIMINGR0_SCLH_I3C_Pos (8UL) -#define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ -#define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ -#define I3C_TIMINGR0_SCLL_OD_Pos (16UL) -#define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ -#define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ -#define I3C_TIMINGR0_SCLH_I2C_Pos (24UL) -#define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ -#define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ - -/**************** Bit definition for I3C_TIMINGR1 register ******************/ -#define I3C_TIMINGR1_AVAL_Pos (0UL) -#define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ -#define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ -#define I3C_TIMINGR1_ASNCR_Pos (8UL) -#define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ -#define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ -#define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ -#define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ -#define I3C_TIMINGR1_FREE_Pos (16UL) -#define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ -#define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ -#define I3C_TIMINGR1_SDA_HD_Pos (28UL) -#define I3C_TIMINGR1_SDA_HD_Msk (0x3UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x30000000 */ -#define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ -#define I3C_TIMINGR1_SDA_HD_0 (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x10000000 */ -#define I3C_TIMINGR1_SDA_HD_1 (0x2UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x20000000 */ - -/**************** Bit definition for I3C_TIMINGR2 register ******************/ -#define I3C_TIMINGR2_STALLT_Pos (0UL) -#define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ -#define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ -#define I3C_TIMINGR2_STALLD_Pos (1UL) -#define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ -#define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ -#define I3C_TIMINGR2_STALLC_Pos (2UL) -#define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ -#define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ -#define I3C_TIMINGR2_STALLA_Pos (3UL) -#define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ -#define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ -#define I3C_TIMINGR2_STALLR_Pos (4UL) -#define I3C_TIMINGR2_STALLR_Msk (0x1UL << I3C_TIMINGR2_STALLR_Pos) /*!< 0x00000010 */ -#define I3C_TIMINGR2_STALLR I3C_TIMINGR2_STALLR_Msk /*!< Stall on I2C Read ACK bit */ -#define I3C_TIMINGR2_STALLS_Pos (5UL) -#define I3C_TIMINGR2_STALLS_Msk (0x1UL << I3C_TIMINGR2_STALLS_Pos) /*!< 0x00000020 */ -#define I3C_TIMINGR2_STALLS I3C_TIMINGR2_STALLS_Msk /*!< Stall on I2C Write ACK bit */ -#define I3C_TIMINGR2_STALLL_Pos (6UL) -#define I3C_TIMINGR2_STALLL_Msk (0x1UL << I3C_TIMINGR2_STALLL_Pos) /*!< 0x00000040 */ -#define I3C_TIMINGR2_STALLL I3C_TIMINGR2_STALLL_Msk /*!< Stall on I2C Address ACK bit */ -#define I3C_TIMINGR2_STALL_Pos (8UL) -#define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ -#define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ - -/******************* Bit definition for I3C_BCR register ********************/ -#define I3C_BCR_BCR_Pos (0UL) -#define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ -#define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ -#define I3C_BCR_BCR0_Pos (0UL) -#define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ -#define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ -#define I3C_BCR_BCR1_Pos (1UL) -#define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ -#define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ -#define I3C_BCR_BCR2_Pos (2UL) -#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ -#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ -#define I3C_BCR_BCR3_Pos (3UL) -#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */ -#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */ -#define I3C_BCR_BCR4_Pos (4UL) -#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */ -#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */ -#define I3C_BCR_BCR5_Pos (5UL) -#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */ -#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */ -#define I3C_BCR_BCR6_Pos (6UL) -#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ -#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ - -/******************* Bit definition for I3C_DCR register ********************/ -#define I3C_DCR_DCR_Pos (0UL) -#define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ -#define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ - -/***************** Bit definition for I3C_GETCAPR register ******************/ -#define I3C_GETCAPR_CAPPEND_Pos (14UL) -#define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ -#define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ - -/***************** Bit definition for I3C_CRCAPR register *******************/ -#define I3C_CRCAPR_CAPDHOFF_Pos (3UL) -#define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ -#define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ -#define I3C_CRCAPR_CAPGRP_Pos (9UL) -#define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ -#define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ - -/**************** Bit definition for I3C_GETMXDSR register ******************/ -#define I3C_GETMXDSR_HOFFAS_Pos (0UL) -#define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ -#define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ -#define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ -#define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ -#define I3C_GETMXDSR_FMT_Pos (8UL) -#define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ -#define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ -#define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ -#define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ -#define I3C_GETMXDSR_RDTURN_Pos (16UL) -#define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ -#define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ -#define I3C_GETMXDSR_TSCO_Pos (24UL) -#define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ -#define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ - -/****************** Bit definition for I3C_EPIDR register *******************/ -#define I3C_EPIDR_MIPIID_Pos (12UL) -#define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ -#define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ -#define I3C_EPIDR_IDTSEL_Pos (16UL) -#define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ -#define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ -#define I3C_EPIDR_MIPIMID_Pos (17UL) -#define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ -#define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ - -/******************************************************************************/ -/* */ -/* ICACHE */ -/* */ -/******************************************************************************/ -/****************** Bit definition for ICACHE_CR register *******************/ -#define ICACHE_CR_EN_Pos (0UL) -#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ -#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< Enable */ -#define ICACHE_CR_CACHEINV_Pos (1UL) -#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ -#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ -#define ICACHE_CR_WAYSEL_Pos (2UL) -#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ -#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< Ways selection */ -#define ICACHE_CR_HITMEN_Pos (16UL) -#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ -#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< Hit monitor enable */ -#define ICACHE_CR_MISSMEN_Pos (17UL) -#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ -#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< Miss monitor enable */ -#define ICACHE_CR_HITMRST_Pos (18UL) -#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ -#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< Hit monitor reset */ -#define ICACHE_CR_MISSMRST_Pos (19UL) -#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ -#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< Miss monitor reset */ - -/****************** Bit definition for ICACHE_SR register *******************/ -#define ICACHE_SR_BUSYF_Pos (0UL) -#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ -#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< Busy flag */ -#define ICACHE_SR_BSYENDF_Pos (1UL) -#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ -#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< Busy end flag */ -#define ICACHE_SR_ERRF_Pos (2UL) -#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ -#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< Cache error flag */ - -/****************** Bit definition for ICACHE_IER register ******************/ -#define ICACHE_IER_BSYENDIE_Pos (1UL) -#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ -#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ -#define ICACHE_IER_ERRIE_Pos (2UL) -#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ -#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ - -/****************** Bit definition for ICACHE_FCR register ******************/ -#define ICACHE_FCR_CBSYENDF_Pos (1UL) -#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ -#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ -#define ICACHE_FCR_CERRF_Pos (2UL) -#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ -#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ - -/****************** Bit definition for ICACHE_HMONR register ****************/ -#define ICACHE_HMONR_HITMON_Pos (0UL) -#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ -#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< Cache hit monitor register */ - -/****************** Bit definition for ICACHE_MMONR register ****************/ -#define ICACHE_MMONR_MISSMON_Pos (0UL) -#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ -#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< Cache miss monitor register */ - -/****************** Bit definition for ICACHE_CRRx register *****************/ -#define ICACHE_CRRx_BASEADDR_Pos (0UL) -#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ -#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< Base address of region X to remap */ -#define ICACHE_CRRx_RSIZE_Pos (9UL) -#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ -#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< Region X size */ -#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ -#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ -#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ -#define ICACHE_CRRx_REN_Pos (15UL) -#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ -#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< Region X enable */ -#define ICACHE_CRRx_REMAPADDR_Pos (16UL) -#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ -#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< Remap address of Region X to be remapped */ -#define ICACHE_CRRx_MSTSEL_Pos (28UL) -#define ICACHE_CRRx_MSTSEL_Msk (0x1UL << ICACHE_CRRx_MSTSEL_Pos) /*!< 0x10000000 */ -#define ICACHE_CRRx_MSTSEL ICACHE_CRRx_MSTSEL_Msk /*!< Region X AHB cache master selection */ -#define ICACHE_CRRx_HBURST_Pos (31UL) -#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ -#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< Region X output burst type */ - -/******************************************************************************/ -/* */ -/* Independent WATCHDOG */ -/* */ -/******************************************************************************/ -/******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY_Pos (0UL) -#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ -#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! */ - -/******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0UL) -#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ -#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk -#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ -#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ -#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ -#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4UL) -#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ -#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk -#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ -#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ -#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7UL) -#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ -#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8UL) -#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ -#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk -#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ -#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ -#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ -#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12UL) -#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ -#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk -#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ -#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ -#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15UL) -#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ -#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16UL) -#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ -#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk -#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ -#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ -#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ -#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20UL) -#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ -#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk -#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ -#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22UL) -#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ -#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23UL) -#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ -#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24UL) -#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ -#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk -#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ -#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ -#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ -#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28UL) -#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ -#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk -#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ -#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30UL) -#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ -#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31UL) -#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ -#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk - -/******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0UL) -#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ -#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24UL) -#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ -#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk -#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ -#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ -#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ -#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ -#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31UL) -#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ -#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk - -/******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0UL) -#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ -#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk -#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ -#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ -#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ -#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4UL) -#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ -#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk -#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ -#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ -#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7UL) -#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ -#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8UL) -#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ -#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk -#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ -#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ -#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ -#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12UL) -#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ -#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk -#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ -#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ -#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15UL) -#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ -#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16UL) -#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ -#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk -#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ -#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ -#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ -#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20UL) -#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ -#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk -#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ -#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22UL) -#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ -#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23UL) -#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ -#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24UL) -#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ -#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk -#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ -#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ -#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ -#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28UL) -#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ -#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk -#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ -#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30UL) -#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ -#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31UL) -#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ -#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk - -/******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0UL) -#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ -#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24UL) -#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ -#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk -#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ -#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ -#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ -#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ -#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31UL) -#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ -#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk - -/******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0UL) -#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ -#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1UL) -#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ -#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2UL) -#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ -#define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3UL) -#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ -#define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4UL) -#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ -#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5UL) -#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ -#define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6UL) -#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ -#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk - -/******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0UL) -#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ -#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1UL) -#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ -#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2UL) -#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ -#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3UL) -#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ -#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4UL) -#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ -#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5UL) -#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ -#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6UL) -#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ -#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk - -/******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0UL) -#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ -#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1UL) -#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ -#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2UL) -#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ -#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3UL) -#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ -#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4UL) -#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ -#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5UL) -#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ -#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6UL) -#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ -#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk - -/******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0UL) -#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ -#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1UL) -#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ -#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2UL) -#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ -#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3UL) -#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ -#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4UL) -#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ -#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5UL) -#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ -#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6UL) -#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ -#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk - -/******************** Bits definition for RTC_TAMPTSCR register ******************/ -#define RTC_TAMPTSCR_TAMP1TS_Pos (0UL) -#define RTC_TAMPTSCR_TAMP1TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP1TS_Pos) /*!< 0x00000001 */ -#define RTC_TAMPTSCR_TAMP1TS RTC_TAMPTSCR_TAMP1TS_Msk -#define RTC_TAMPTSCR_TAMP2TS_Pos (1UL) -#define RTC_TAMPTSCR_TAMP2TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP2TS_Pos) /*!< 0x00000002 */ -#define RTC_TAMPTSCR_TAMP2TS RTC_TAMPTSCR_TAMP2TS_Msk -#define RTC_TAMPTSCR_TAMP3TS_Pos (2UL) -#define RTC_TAMPTSCR_TAMP3TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP3TS_Pos) /*!< 0x00000004 */ -#define RTC_TAMPTSCR_TAMP3TS RTC_TAMPTSCR_TAMP3TS_Msk -#define RTC_TAMPTSCR_TAMP4TS_Pos (3UL) -#define RTC_TAMPTSCR_TAMP4TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP4TS_Pos) /*!< 0x00000008 */ -#define RTC_TAMPTSCR_TAMP4TS RTC_TAMPTSCR_TAMP4TS_Msk -#define RTC_TAMPTSCR_TAMP5TS_Pos (4UL) -#define RTC_TAMPTSCR_TAMP5TS_Msk (0x1UL << RTC_TAMPTSCR_TAMP5TS_Pos) /*!< 0x00000010 */ -#define RTC_TAMPTSCR_TAMP5TS RTC_TAMPTSCR_TAMP5TS_Msk -#define RTC_TAMPTSCR_ITAMPTS_Pos (16UL) -#define RTC_TAMPTSCR_ITAMPTS_Msk (0x1UL << RTC_TAMPTSCR_ITAMPTS_Pos) /*!< 0x00010000 */ -#define RTC_TAMPTSCR_ITAMPTS RTC_TAMPTSCR_ITAMPTS_Msk - -/******************** Bits definition for RTC_TSIDR register ******************/ -#define RTC_TSIDR_TSID_Pos (0UL) -#define RTC_TSIDR_TSID_Msk (0x3FUL << RTC_TSIDR_TSID_Pos) /*!< 0x0000003F */ -#define RTC_TSIDR_TSID RTC_TSIDR_TSID_Msk -#define RTC_TSIDR_TSID_0 (0x1UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000001 */ -#define RTC_TSIDR_TSID_1 (0x2UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000002 */ -#define RTC_TSIDR_TSID_2 (0x4UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000004 */ -#define RTC_TSIDR_TSID_3 (0x8UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000008 */ -#define RTC_TSIDR_TSID_4 (0x10UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000010 */ -#define RTC_TSIDR_TSID_5 (0x20UL << RTC_TSIDR_TSID_Pos) /*!< 0x00000020 */ - -/******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0UL) -#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ -#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk - -/******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0UL) -#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ -#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk - -/******************************************************************************/ -/* */ -/* Serial Audio Interface */ -/* */ -/******************************************************************************/ -/******************* Bit definition for SAI_xCR1 register *******************/ -#define SAI_xCR1_MODE_Pos (0UL) -#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ -#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!>2) /*!< Input modulus number of bits */ -#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ - -/* Compute Montgomery parameter output data */ -#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ - -/* Compute modular exponentiation input data */ -#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ -#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ -#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ -#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ -#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ -#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ -#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ -#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ -#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ - -/* Compute modular exponentiation output data */ -#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ -#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ -#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ -#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ - -/* Compute ECC scalar multiplication input data */ -#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ -#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ -#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ -#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ -#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ -#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ - -/* Compute ECC scalar multiplication output data */ -#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ -#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ -#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ - -/* Point check input data */ -#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ -#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ -#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ -#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ - -/* Point check output data */ -#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ - -/* ECDSA signature input data */ -#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ -#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ -#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ -#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ -#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ -#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ -#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ -#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ - -/* ECDSA signature output data */ -#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ -#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ -#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ -#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ -#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ - -/* ECDSA verification input data */ -#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ -#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ -#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ -#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ -#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ -#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ -#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ -#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ -#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ - -/* ECDSA verification output data */ -#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* RSA CRT exponentiation input data */ -#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ -#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ -#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ -#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ -#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ -#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ -#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ - -/* RSA CRT exponentiation output data */ -#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Modular reduction input data */ -#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ -#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ -#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ -#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ - -/* Modular reduction output data */ -#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Arithmetic addition input data */ -#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ - -/* Arithmetic addition output data */ -#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Arithmetic subtraction input data */ -#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ - -/* Arithmetic subtraction output data */ -#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Arithmetic multiplication input data */ -#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ - -/* Arithmetic multiplication output data */ -#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Comparison input data */ -#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ - -/* Comparison output data */ -#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Modular addition input data */ -#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ - -/* Modular addition output data */ -#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Modular inversion input data */ -#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ - -/* Modular inversion output data */ -#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Modular subtraction input data */ -#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ - -/* Modular subtraction output data */ -#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Montgomery multiplication input data */ -#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ - -/* Montgomery multiplication output data */ -#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Generic Arithmetic input data */ -#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ - -/* Generic Arithmetic output data */ -#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ - -/* Compute ECC complete addition input data */ -#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ -#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ -#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ - -/* Compute ECC complete addition output data */ -#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ -#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ -#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ - -/* Compute ECC double base ladder input data */ -#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ -#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ -#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ -#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ -#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ - -/* Compute ECC double base ladder output data */ -#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ -#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ -#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ - -/* Compute ECC projective to affine conversion input data */ -#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ -#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ -#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ -#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ -#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ - -/* Compute ECC projective to affine conversion output data */ -#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ -#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ -#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ - - -/******************************************************************************/ -/* */ -/* VREFBUF */ -/* */ -/******************************************************************************/ -/******************* Bit definition for VREFBUF_CSR register ****************/ -#define VREFBUF_CSR_ENVR_Pos (0UL) -#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ -#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!Purpose

Update history

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Official Release

    -
  • Official release of CMSIS for STM32U3xx firmware package supporting STM32U385xx/STM32U375xx/STM32U3B5xx/STM32U3C5xx devices
    • +
  • Official release of CMSIS for STM32U3xx firmware package supporting STM32U335xx/STM32U345xx/STM32U356xx/STM32U366xx/STM32U375xx/STM32U385xx/STM32U3B5xx/STM32U3C5xx devices
  • CMSIS Device Release version of bits and registers definition aligned with RM0487

Contents

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  • First official release of STM32U335xx/STM32U345xx/STM32U356xx/STM32U366xx
    • +
  • Update registers and bit definition for all derivatives after last update of RNG4.4.
    • +
  • Created startup and Linker files of STM32U3 256K for CubeIDE
    • +
  • Add ADC1 security bit for U3 256K variants
    • +
  • Enable CCB HW sanity check on more U3 variants
    • +
+

Known Limitations

+
    +
  • None
    • +
+
+
+
+ +
+

Official Release

+
    +
  • Official release of CMSIS for STM32U3xx firmware package supporting STM32U385xx/STM32U375xx/STM32U3B5xx/STM32U3C5xx devices
    • +
  • CMSIS Device Release version of bits and registers definition aligned with RM0487
    • +
+

Contents

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  • First official release of STM32U3B5xx/STM32U3C5xx
  • Add COMP2 output-blanking PWM assignment
  • Fix Missing OR operator in IS_TIM_CCXN_INSTANCE definition
    • @@ -76,7 +98,7 @@

    Contents

  • Add SPI4 instance for STM32U3 2M
  • Update FLASH linker files with correct flash size
-

Known Limitations

+

Known Limitations

  • None
@@ -89,13 +111,13 @@

Maintenance Release

  • Maintenance release of CMSIS for STM32U3xx firmware package supporting STM32U385xx/STM32U375xx devices
-

Contents

+

Contents

  • Add PKA on STM32U375xx
  • Add CCB sanity check feature on STM32U385xx
  • Swap bit position FLASH MEM and FLASH REG in GTZC1 TZIC registers
-

Known Limitations

+

Known Limitations

  • None
@@ -108,13 +130,13 @@

Maintenance Release

  • Maintenance release of CMSIS for STM32U3xx firmware package supporting STM32U385xx/STM32U375xx devices
-

Contents

+

Contents

  • Fix PWR_I3CPUCR2_PG14_I3CPU_Pos value
  • Suppress unused bit
  • Minor fix on comments
-

Known Limitations

+

Known Limitations

  • None
@@ -127,14 +149,14 @@

First Release

  • First official release of CMSIS for STM32U3xx firmware package supporting STM32U385xx/STM32U375xx devices
-

Contents

+

Contents

  • First official release of CMSIS devices drivers
    • Support of STM32U385xx/STM32U375xx devices
-

Known Limitations

+

Known Limitations

  • None
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Release_Notes.md b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Release_Notes.md new file mode 100644 index 0000000000..79b7f1c5ea --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Release_Notes.md @@ -0,0 +1,142 @@ + + +# Release Notes for STM32U3xx CMSIS +Copyright © 2024 - 2026 STMicroelectronics\ + +[![ST logo](_htmresc/st_logo_2020.png)](https://www.st.com) + +# Purpose + +This driver provides the CMSIS device for the STM32U3xx product. This covers + +- STM32U375xx devices +- STM32U385xx devices + +This driver is composed of the description of the registers under "Include" directory. + +Various template files are provided to easily build an application. They can be adapted to fit applications requirements. + +- Templates/system_stm32u3xx.c contains the initialization code referred as SystemInit. +- Startup files are provided as example for EWARM©, MDK-ARM©, STM32CubeIDE©. +- Linker files are provided as example for EWARM©, MDK-ARM©, STM32CubeIDE©. + + + +# Update history + + +
+ +## Official Release + +- Official release of CMSIS for **STM32U3xx** firmware package supporting **STM32U335xx/STM32U345xx/STM32U356xx/STM32U366xx/STM32U375xx/STM32U385xx/STM32U3B5xx/STM32U3C5xx** devices +- CMSIS Device Release version of bits and registers definition aligned with **RM0487** + +## Contents +- First official release of STM32U335xx/STM32U345xx/STM32U356xx/STM32U366xx +- Update registers and bit definition for all derivatives after last update of RNG4.4. +- Created startup and Linker files of STM32U3 256K for CubeIDE +- Add ADC1 security bit for U3 256K variants +- Enable CCB HW sanity check on more U3 variants + +## Known Limitations + +- None + +
+ + +
+ +## Official Release + +- Official release of CMSIS for **STM32U3xx** firmware package supporting **STM32U385xx/STM32U375xx/STM32U3B5xx/STM32U3C5xx** devices +- CMSIS Device Release version of bits and registers definition aligned with **RM0487** + +## Contents +- First official release of STM32U3B5xx/STM32U3C5xx +- Add COMP2 output-blanking PWM assignment +- Fix Missing OR operator in IS_TIM_CCXN_INSTANCE definition +- Set stack limit (MSPLIM) in CMSIS Device templates +- Remove "__section_static_hsp_data_bram_start__" & "__section_static_hsp_data_bram_end__" useless symbols +- Fix wrong memory region for HSP_DATA_BRAM +- Add missing bit fields in flash +- Update scatter file with correct flash size +- Add Begin/End symbols for HSP_DATA_BRAM memory region +- Add clock defaults to system file +- Add/Update TSC registers for U3 derivatives +- Add/Update DBGMCU registers +- Add SYSCFG_CFGR1_TSC_G2_IO3 and SYSCFG_CFGR1_TSC_G2_IO1 bit definitions in SYSCFG_CFGR1 +- Fix wrong macro value for VREFBUF_CSR_VRS_2 +- Update TIM8 IRQ Handler name and remove unused AES IRQ handler +- Add I2C4 macros for STM32U3 2M +- Rename "HSP_BKO0CFGR_xxxx" constants by "HSP_BKOCFGR_xxxx" +- Fix wrong macro HSPI1 to HSP1 in DBGMCU_AHB1FZR_DBG_HSP1 +- CMSIS update removing ADC DIFSEL register +- Fix MPCBB registers for SRAM3 +- CMSIS correction for TIM8_S Definition +- Add SPI4 instance for STM32U3 2M +- Update FLASH linker files with correct flash size + +## Known Limitations + +- None + +
+ + +
+ +## Maintenance Release + +- Maintenance release of CMSIS for **STM32U3xx** firmware package supporting **STM32U385xx/STM32U375xx** devices + +## Contents +- Add PKA on STM32U375xx +- Add CCB sanity check feature on STM32U385xx +- Swap bit position FLASH MEM and FLASH REG in GTZC1 TZIC registers + +## Known Limitations + +- None + +
+ + +
+ +## Maintenance Release + +- Maintenance release of CMSIS for **STM32U3xx** firmware package supporting **STM32U385xx/STM32U375xx** devices + +## Contents +- Fix PWR_I3CPUCR2_PG14_I3CPU_Pos value +- Suppress unused bit +- Minor fix on comments + +## Known Limitations + +- None + +
+ + +
+ +## First Release + +- First official release of CMSIS for **STM32U3xx** firmware package supporting **STM32U385xx/STM32U375xx** devices + +## Contents + +- First official release of CMSIS devices drivers + - Support of STM32U385xx/STM32U375xx devices + +## Known Limitations + +- None + +
+ + +Info \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_FLASH.ld new file mode 100644 index 0000000000..b46bb1b909 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_FLASH.ld @@ -0,0 +1,188 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32U335xx Device from STM32U3 series +** 256KBytes FLASH +** 80KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 80K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_FLASH_ns.ld new file mode 100644 index 0000000000..2e907a8003 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_FLASH_ns.ld @@ -0,0 +1,188 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32U335xx Device from STM32U3 series +** 256KBytes FLASH +** 64KBytes RAM2 +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM2) + LENGTH(RAM2); /* end of "RAM2" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM2 (xrw) : ORIGIN = 0x20004000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 128K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM2" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM2 AT> FLASH + + /* Uninitialized data section into "RAM2" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM2 + + /* User_heap_stack section, used to check that there is enough "RAM2" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM2 + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_FLASH_s.ld new file mode 100644 index 0000000000..6a63941275 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_FLASH_s.ld @@ -0,0 +1,196 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32U335xx Device from STM32U3 series +** 256KBytes FLASH +** 16KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 16K + FLASH (rx) : ORIGIN = 0x0C000000, LENGTH = 120K + FLASH_NSC (rx) : ORIGIN = 0x0C01E000, LENGTH = 8K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_RAM.ld new file mode 100644 index 0000000000..b910596535 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_RAM.ld @@ -0,0 +1,188 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32U356xx Device from STM32U3 series +** 256KBytes FLASH +** 64KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x2000C000, LENGTH = 32K + FLASH (rx) : ORIGIN = 0x0A000000, LENGTH = 48K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_RAM_ns.ld new file mode 100644 index 0000000000..e73c34f286 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_RAM_ns.ld @@ -0,0 +1,188 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32U335xx Device from STM32U3 series +** 256KBytes FLASH +** 64KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20011000, LENGTH = 12K + FLASH (rx) : ORIGIN = 0x0A006000, LENGTH = 36K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_RAM_s.ld new file mode 100644 index 0000000000..4742b3dc7c --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U335xx_RAM_s.ld @@ -0,0 +1,196 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32U335xx Device from STM32U3 series +** 256KBytes FLASH +** 64KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x3000F000, LENGTH = 8K + FLASH (rx) : ORIGIN = 0x0E000000, LENGTH = 16K + FLASH_NSC (rx) : ORIGIN = 0x0E004000, LENGTH = 8K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_FLASH.ld new file mode 100644 index 0000000000..6a206896d8 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_FLASH.ld @@ -0,0 +1,188 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32U345xx Device from STM32U3 series +** 256KBytes FLASH +** 80KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 80K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_FLASH_ns.ld new file mode 100644 index 0000000000..adfe27f4b4 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_FLASH_ns.ld @@ -0,0 +1,188 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32U345xx Device from STM32U3 series +** 256KBytes FLASH +** 64KBytes RAM2 +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM2) + LENGTH(RAM2); /* end of "RAM2" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM2 (xrw) : ORIGIN = 0x20004000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 128K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM2" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM2 AT> FLASH + + /* Uninitialized data section into "RAM2" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM2 + + /* User_heap_stack section, used to check that there is enough "RAM2" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM2 + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_FLASH_s.ld new file mode 100644 index 0000000000..c2e901c491 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_FLASH_s.ld @@ -0,0 +1,196 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32U345xx Device from STM32U3 series +** 256KBytes FLASH +** 16KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 16K + FLASH (rx) : ORIGIN = 0x0C000000, LENGTH = 120K + FLASH_NSC (rx) : ORIGIN = 0x0C01E000, LENGTH = 8K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_RAM.ld new file mode 100644 index 0000000000..27c831fb1f --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_RAM.ld @@ -0,0 +1,188 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32U345xx Device from STM32U3 series +** 256KBytes FLASH +** 64KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x2000C000, LENGTH = 32K + FLASH (rx) : ORIGIN = 0x0A000000, LENGTH = 48K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_RAM_ns.ld new file mode 100644 index 0000000000..91637f1cf3 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_RAM_ns.ld @@ -0,0 +1,188 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32U345xx Device from STM32U3 series +** 256KBytes FLASH +** 64KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20011000, LENGTH = 12K + FLASH (rx) : ORIGIN = 0x0A006000, LENGTH = 36K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_RAM_s.ld new file mode 100644 index 0000000000..5b4c9cb659 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U345xx_RAM_s.ld @@ -0,0 +1,196 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32U345xx Device from STM32U3 series +** 256KBytes FLASH +** 64KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x3000F000, LENGTH = 8K + FLASH (rx) : ORIGIN = 0x0E000000, LENGTH = 16K + FLASH_NSC (rx) : ORIGIN = 0x0E004000, LENGTH = 8K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/startup_stm32u335xx.s b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/startup_stm32u335xx.s new file mode 100644 index 0000000000..914b647f60 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/startup_stm32u335xx.s @@ -0,0 +1,570 @@ +/** + ****************************************************************************** + * @file startup_stm32u335xx.s + * @author Auto-generated by STM32CubeIDE + * @brief STM32U335xxx device vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m33 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + ldr r0, =_sstack + msr MSPLIM, r0 /* set stack pointer limit */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M33. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word SecureFault_Handler + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word RTC_IRQHandler + .word RTC_S_IRQHandler + .word TAMP_IRQHandler + .word RAMCFG_IRQHandler + .word FLASH_IRQHandler + .word FLASH_S_IRQHandler + .word GTZC_IRQHandler + .word RCC_IRQHandler + .word RCC_S_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word EXTI5_IRQHandler + .word EXTI6_IRQHandler + .word EXTI7_IRQHandler + .word EXTI8_IRQHandler + .word EXTI9_IRQHandler + .word EXTI10_IRQHandler + .word EXTI11_IRQHandler + .word EXTI12_IRQHandler + .word EXTI13_IRQHandler + .word EXTI14_IRQHandler + .word EXTI15_IRQHandler + .word IWDG_IRQHandler + .word 0 + .word GPDMA1_Channel0_IRQHandler + .word GPDMA1_Channel1_IRQHandler + .word GPDMA1_Channel2_IRQHandler + .word GPDMA1_Channel3_IRQHandler + .word GPDMA1_Channel4_IRQHandler + .word GPDMA1_Channel5_IRQHandler + .word GPDMA1_Channel6_IRQHandler + .word GPDMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word DAC1_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word TIM1_BRK_TERR_IERR_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_DIR_IDX_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word 0 + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word I3C1_EV_IRQHandler + .word I3C1_ER_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word 0 + .word USART3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word LPUART1_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word TIM15_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word COMP_IRQHandler + .word USB_FS_IRQHandler + .word CRS_IRQHandler + .word 0 + .word OCTOSPI1_IRQHandler + .word 0 + .word 0 + .word 0 + .word GPDMA1_Channel8_IRQHandler + .word GPDMA1_Channel9_IRQHandler + .word GPDMA1_Channel10_IRQHandler + .word GPDMA1_Channel11_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word 0 + .word 0 + .word TSC_IRQHandler + .word 0 + .word RNG_IRQHandler + .word FPU_IRQHandler + .word HASH_IRQHandler + .word 0 + .word LPTIM3_IRQHandler + .word SPI3_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word ICACHE_IRQHandler + .word 0 + .word 0 + .word LPTIM4_IRQHandler + .word 0 + .word ADF1_IRQHandler + .word ADC2_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word PWR_IRQHandler + .word PWR_S_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SecureFault_Handler + .thumb_set SecureFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak RTC_S_IRQHandler + .thumb_set RTC_S_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak RAMCFG_IRQHandler + .thumb_set RAMCFG_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak FLASH_S_IRQHandler + .thumb_set FLASH_S_IRQHandler,Default_Handler + + .weak GTZC_IRQHandler + .thumb_set GTZC_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak RCC_S_IRQHandler + .thumb_set RCC_S_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak DAC1_IRQHandler + .thumb_set DAC1_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak TIM1_BRK_TERR_IERR_IRQHandler + .thumb_set TIM1_BRK_TERR_IERR_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_DIR_IDX_IRQHandler + .thumb_set TIM1_TRG_COM_DIR_IDX_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak I3C1_EV_IRQHandler + .thumb_set I3C1_EV_IRQHandler,Default_Handler + + .weak I3C1_ER_IRQHandler + .thumb_set I3C1_ER_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak USB_FS_IRQHandler + .thumb_set USB_FS_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel8_IRQHandler + .thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler + + .weak GPDMA1_Channel9_IRQHandler + .thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler + + .weak GPDMA1_Channel10_IRQHandler + .thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler + + .weak GPDMA1_Channel11_IRQHandler + .thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak ADF1_IRQHandler + .thumb_set ADF1_IRQHandler,Default_Handler + + .weak ADC2_IRQHandler + .thumb_set ADC2_IRQHandler,Default_Handler + + .weak PWR_IRQHandler + .thumb_set PWR_IRQHandler,Default_Handler + + .weak PWR_S_IRQHandler + .thumb_set PWR_S_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/startup_stm32u345xx.s b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/startup_stm32u345xx.s new file mode 100644 index 0000000000..8b9ff45bef --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/startup_stm32u345xx.s @@ -0,0 +1,573 @@ +/** + ****************************************************************************** + * @file startup_stm32u345xx.s + * @author Auto-generated by STM32CubeIDE + * @brief STM32U345xxx device vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m33 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + ldr r0, =_sstack + msr MSPLIM, r0 /* set stack pointer limit */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M33. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word SecureFault_Handler + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word RTC_IRQHandler + .word RTC_S_IRQHandler + .word TAMP_IRQHandler + .word RAMCFG_IRQHandler + .word FLASH_IRQHandler + .word FLASH_S_IRQHandler + .word GTZC_IRQHandler + .word RCC_IRQHandler + .word RCC_S_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word EXTI5_IRQHandler + .word EXTI6_IRQHandler + .word EXTI7_IRQHandler + .word EXTI8_IRQHandler + .word EXTI9_IRQHandler + .word EXTI10_IRQHandler + .word EXTI11_IRQHandler + .word EXTI12_IRQHandler + .word EXTI13_IRQHandler + .word EXTI14_IRQHandler + .word EXTI15_IRQHandler + .word IWDG_IRQHandler + .word 0 + .word GPDMA1_Channel0_IRQHandler + .word GPDMA1_Channel1_IRQHandler + .word GPDMA1_Channel2_IRQHandler + .word GPDMA1_Channel3_IRQHandler + .word GPDMA1_Channel4_IRQHandler + .word GPDMA1_Channel5_IRQHandler + .word GPDMA1_Channel6_IRQHandler + .word GPDMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word DAC1_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word TIM1_BRK_TERR_IERR_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_DIR_IDX_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word 0 + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word I3C1_EV_IRQHandler + .word I3C1_ER_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word 0 + .word USART3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word LPUART1_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word TIM15_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word COMP_IRQHandler + .word USB_FS_IRQHandler + .word CRS_IRQHandler + .word 0 + .word OCTOSPI1_IRQHandler + .word 0 + .word 0 + .word 0 + .word GPDMA1_Channel8_IRQHandler + .word GPDMA1_Channel9_IRQHandler + .word GPDMA1_Channel10_IRQHandler + .word GPDMA1_Channel11_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word 0 + .word 0 + .word TSC_IRQHandler + .word AES_IRQHandler + .word RNG_IRQHandler + .word FPU_IRQHandler + .word HASH_IRQHandler + .word 0 + .word LPTIM3_IRQHandler + .word SPI3_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word ICACHE_IRQHandler + .word 0 + .word 0 + .word LPTIM4_IRQHandler + .word 0 + .word ADF1_IRQHandler + .word ADC2_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word PWR_IRQHandler + .word PWR_S_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SecureFault_Handler + .thumb_set SecureFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak RTC_S_IRQHandler + .thumb_set RTC_S_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak RAMCFG_IRQHandler + .thumb_set RAMCFG_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak FLASH_S_IRQHandler + .thumb_set FLASH_S_IRQHandler,Default_Handler + + .weak GTZC_IRQHandler + .thumb_set GTZC_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak RCC_S_IRQHandler + .thumb_set RCC_S_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak DAC1_IRQHandler + .thumb_set DAC1_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak TIM1_BRK_TERR_IERR_IRQHandler + .thumb_set TIM1_BRK_TERR_IERR_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_DIR_IDX_IRQHandler + .thumb_set TIM1_TRG_COM_DIR_IDX_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak I3C1_EV_IRQHandler + .thumb_set I3C1_EV_IRQHandler,Default_Handler + + .weak I3C1_ER_IRQHandler + .thumb_set I3C1_ER_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak USB_FS_IRQHandler + .thumb_set USB_FS_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel8_IRQHandler + .thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler + + .weak GPDMA1_Channel9_IRQHandler + .thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler + + .weak GPDMA1_Channel10_IRQHandler + .thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler + + .weak GPDMA1_Channel11_IRQHandler + .thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak ADF1_IRQHandler + .thumb_set ADF1_IRQHandler,Default_Handler + + .weak ADC2_IRQHandler + .thumb_set ADC2_IRQHandler,Default_Handler + + .weak PWR_IRQHandler + .thumb_set PWR_IRQHandler,Default_Handler + + .weak PWR_S_IRQHandler + .thumb_set PWR_S_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 0e7714891e..e46d6f656b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -17,7 +17,7 @@ * STM32L5: 1.0.7 * STM32MP1: 1.7.0 * STM32U0: 1.3.0 - * STM32U3: 1.3.0 + * STM32U3: 1.4.0 * STM32U5: 1.4.2 * STM32WB: 1.12.3 * STM32WB0: 1.4.0 diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal.h index 0a70c18ab9..7e540194dc 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal.h @@ -75,7 +75,7 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @brief STM32U3xx HAL Driver version number */ #define __STM32U3xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ -#define __STM32U3xx_HAL_VERSION_SUB1 (0x02UL) /*!< [23:16] sub1 version */ +#define __STM32U3xx_HAL_VERSION_SUB1 (0x04UL) /*!< [23:16] sub1 version */ #define __STM32U3xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */ #define __STM32U3xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32U3xx_HAL_VERSION ((__STM32U3xx_HAL_VERSION_MAIN << 24U)\ diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_adc_ex.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_adc_ex.h index cd4045c17e..cae57ec1f6 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_adc_ex.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_adc_ex.h @@ -862,32 +862,47 @@ typedef struct * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ +#if defined(ADC1) && defined(ADC2) #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || \ (((__HANDLE__)->Instance) == ADC2) ) +#else +#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) +#endif /* ADC1 && ADC2 */ /** * @brief Verify the ADC instance connected to the battery voltage VBAT. * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ +#if defined(ADC1) && defined(ADC2) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\ (((__HANDLE__)->Instance) == ADC2) ) - +#else +#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) +#endif /* ADC1 && ADC2 */ /** * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ +#if defined (ADC1) && defined (ADC2) #define ADC_VREFINT_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\ (((__HANDLE__)->Instance) == ADC2) ) +#else +#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) +#endif /* ADC1 && ADC2 */ /** * @brief Verify the ADC instance connected to the internal VDDCore. * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ +#if defined(ADC1) && defined(ADC2) #define ADC_VDDCORE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\ (((__HANDLE__)->Instance) == ADC2) ) +#else +#define ADC_VDDCORE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) +#endif /* ADC1 && ADC2 */ /** * @brief Verify the length of scheduled injected conversions group. @@ -911,6 +926,7 @@ typedef struct * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ +#if defined(ADC1) && defined(ADC2) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \ ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ @@ -937,6 +953,31 @@ typedef struct ((((__HANDLE__)->Instance) == ADC2) && \ (((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2) || \ ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)))) +#else +#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \ + ((__CHANNEL__) == ADC_CHANNEL_1) || \ + ((__CHANNEL__) == ADC_CHANNEL_2) || \ + ((__CHANNEL__) == ADC_CHANNEL_3) || \ + ((__CHANNEL__) == ADC_CHANNEL_4) || \ + ((__CHANNEL__) == ADC_CHANNEL_5) || \ + ((__CHANNEL__) == ADC_CHANNEL_6) || \ + ((__CHANNEL__) == ADC_CHANNEL_7) || \ + ((__CHANNEL__) == ADC_CHANNEL_8) || \ + ((__CHANNEL__) == ADC_CHANNEL_9) || \ + ((__CHANNEL__) == ADC_CHANNEL_10) || \ + ((__CHANNEL__) == ADC_CHANNEL_11) || \ + ((__CHANNEL__) == ADC_CHANNEL_12) || \ + ((__CHANNEL__) == ADC_CHANNEL_13) || \ + ((__CHANNEL__) == ADC_CHANNEL_14) || \ + ((__CHANNEL__) == ADC_CHANNEL_15) || \ + ((__CHANNEL__) == ADC_CHANNEL_16) || \ + ((__CHANNEL__) == ADC_CHANNEL_17) || \ + ((__CHANNEL__) == ADC_CHANNEL_18) || \ + ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ + ((__CHANNEL__) == ADC_CHANNEL_VDDCORE) || \ + ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT)) +#endif /* ADC1 && ADC2 */ /** diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_ccb.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_ccb.h index dd3d417aa3..604f813ab7 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_ccb.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_ccb.h @@ -22,6 +22,9 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32u3xx_hal_def.h" +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +#include "stm32u3xx_ll_rng.h" +#endif /* RNG_HTSR0_RPERRX) || RNG_HTSR1_ADERRX */ /** @addtogroup STM32U3xx_HAL_Driver * @{ diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_cryp.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_cryp.h index 7a491c00f9..dfd6461e97 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_cryp.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_cryp.h @@ -26,6 +26,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32u3xx_hal_def.h" +#include "stm32u3xx_ll_rng.h" /** @addtogroup STM32U3xx_HAL_Driver * @{ diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_dma.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_dma.h index b4ffd67a39..eaab7cbc71 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_dma.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_dma.h @@ -312,8 +312,10 @@ typedef struct __DMA_HandleTypeDef #define GPDMA1_REQUEST_I3C1_TX 50U /*!< GPDMA1 HW request is I3C1_TX */ #define GPDMA1_REQUEST_I3C1_TC 51U /*!< GPDMA1 HW request is I3C1_TC */ #define GPDMA1_REQUEST_I3C1_RS 52U /*!< GPDMA1 HW request is I3C1_RS */ -/* Reserved 53U */ -/* Reserved 54U */ +#if defined (GFXPAND1) +#define GPDMA1_REQUEST_GFXPAND_IN 53U /*!< GPDMA1 HW request is GFXPAND_IN */ +#define GPDMA1_REQUEST_GFXPAND_OUT 54U /*!< GPDMA1 HW request is GFXPAND_OUT */ +#endif /* GFXPAND1 */ /* Reserved 55U */ #define GPDMA1_REQUEST_TIM2_CH1 56U /*!< GPDMA1 HW request is TIM2_CH1 */ #define GPDMA1_REQUEST_TIM2_CH2 57U /*!< GPDMA1 HW request is TIM2_CH2 */ diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_gpio_ex.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_gpio_ex.h index 42882b8a37..ac766c9983 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_gpio_ex.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_gpio_ex.h @@ -67,9 +67,9 @@ extern "C" { /** * @brief AF 1 selection */ -#if defined(STM32U356xx) || defined(STM32U366xx) || defined(STM32U396xx) || defined(STM32U3A6xx) +#if defined(STM32U396xx) || defined(STM32U3A6xx) #define GPIO_AF1_USART3 ((uint8_t)0x01) /*!< USART3 Alternate Function mapping */ -#endif /* defined(STM32U356xx) || defined(STM32U366xx) || defined(STM32U396xx) || defined(STM32U3A6xx) */ +#endif /* defined(STM32U396xx) || defined(STM32U3A6xx) */ #define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ #define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */ #define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ @@ -168,9 +168,9 @@ extern "C" { #if !(defined(STM32U356xx) || defined(STM32U366xx) || defined(STM32U335xx) || defined(STM32U345xx)) #define GPIO_AF6_I3C2 ((uint8_t)0x06) /*!< I3C2 Alternate Function mapping */ #endif /* !(defined(STM32U356xx) || defined(STM32U366xx) || defined(STM32U335xx) || defined(STM32U345xx)) */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /*!< SPI2 Alternate Function mapping */ #if !(defined(STM32U335xx) || defined(STM32U345xx)) #define GPIO_AF6_SPI3 ((uint8_t)0x06) /*!< SPI3 Alternate Function mapping */ -#define GPIO_AF6_SPI2 ((uint8_t)0x06) /*!< SPI2 Alternate Function mapping */ #endif /* !(defined(STM32U335xx) || defined(STM32U345xx)) */ #if defined(STM32U3B5xx) || defined(STM32U3C5xx) #define GPIO_AF6_SPI4 ((uint8_t)0x06) /*!< SPI4 Alternate Function mapping */ @@ -319,16 +319,23 @@ extern "C" { /** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index * @{ */ -#if defined(GPIOF) +#if defined(GPIOA) && defined(GPIOB) && defined(GPIOC) && defined(GPIOD) && \ + !defined(GPIOE) && !defined(GPIOF) && !defined(GPIOG) && defined(GPIOH) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ + ((__GPIOx__) == (GPIOB))? 1UL :\ + ((__GPIOx__) == (GPIOC))? 2UL :\ + ((__GPIOx__) == (GPIOD))? 3UL :\ + ((__GPIOx__) == (GPIOH))? 7UL : 16UL) +#elif defined(GPIOA) && defined(GPIOB) && defined(GPIOC) && defined(GPIOD) && \ + defined(GPIOE) && !defined(GPIOF) && !defined(GPIOG) && defined(GPIOH) #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ ((__GPIOx__) == (GPIOB))? 1UL :\ ((__GPIOx__) == (GPIOC))? 2UL :\ ((__GPIOx__) == (GPIOD))? 3UL :\ ((__GPIOx__) == (GPIOE))? 4UL :\ - ((__GPIOx__) == (GPIOF))? 5UL :\ - ((__GPIOx__) == (GPIOG))? 6UL :\ ((__GPIOx__) == (GPIOH))? 7UL : 16UL) -#elif defined(GPIOG) +#elif defined(GPIOA) && defined(GPIOB) && defined(GPIOC) && defined(GPIOD) && \ + defined(GPIOE) && !defined(GPIOF) && defined(GPIOG) && defined(GPIOH) #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ ((__GPIOx__) == (GPIOB))? 1UL :\ ((__GPIOx__) == (GPIOC))? 2UL :\ @@ -342,8 +349,11 @@ extern "C" { ((__GPIOx__) == (GPIOC))? 2UL :\ ((__GPIOx__) == (GPIOD))? 3UL :\ ((__GPIOx__) == (GPIOE))? 4UL :\ + ((__GPIOx__) == (GPIOF))? 5UL :\ + ((__GPIOx__) == (GPIOG))? 6UL :\ ((__GPIOx__) == (GPIOH))? 7UL : 16UL) -#endif /* GPIOF */ +#endif /* defined(GPIOA) && defined(GPIOB) && defined(GPIOC) && defined(GPIOD) && + !defined(GPIOE) && !defined(GPIOF) && !defined(GPIOG) && defined(GPIOH) */ /** * @} diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_gtzc.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_gtzc.h index afdb67f5a5..f7ea2b7527 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_gtzc.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_gtzc.h @@ -224,7 +224,13 @@ typedef struct #define GTZC_PERIPH_CRC (GTZC_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos) #define GTZC_PERIPH_TSC (GTZC_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos) #define GTZC_PERIPH_ICACHE_REG (GTZC_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos) -#define GTZC_PERIPH_ADC12 (GTZC_PERIPH_REG3 | GTZC_CFGR3_ADC12_Pos) +#if defined(ADC1) && defined(ADC2) +#define GTZC_PERIPH_ADC (GTZC_PERIPH_REG3 | GTZC_CFGR3_ADC12_Pos) +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#elif defined(ADC1) +#define GTZC_PERIPH_ADC (GTZC_PERIPH_REG3 | GTZC_CFGR3_ADC1_Pos) +#define GTZC_PERIPH_ADC1 GTZC_PERIPH_ADC +#endif /* ADC1 and ADC2 */ #if defined(AES) #define GTZC_PERIPH_AES (GTZC_PERIPH_REG3 | GTZC_CFGR3_AES_Pos) #endif /* AES */ @@ -243,7 +249,9 @@ typedef struct #define GTZC_PERIPH_OCTOSPI1_REG (GTZC_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI1_REG_Pos) #define GTZC_PERIPH_RAMCFG (GTZC_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos) #define GTZC_PERIPH_DAC1 (GTZC_PERIPH_REG3 | GTZC_CFGR3_DAC1_Pos) +#if defined(ADF1) #define GTZC_PERIPH_ADF1 (GTZC_PERIPH_REG3 | GTZC_CFGR3_ADF1_Pos) +#endif /* ADF1 */ #if defined(HSP1) #define GTZC_PERIPH_HSP1 (GTZC_PERIPH_REG3 | GTZC_CFGR3_HSP1_Pos) #endif /* HSP1 */ diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_hsp.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_hsp.h index ba2700081a..8bbc61fcb8 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_hsp.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_hsp.h @@ -1323,10 +1323,17 @@ typedef enum /** Enumerate to define the Trigger Interconnect Matrix */ typedef enum { +#if defined(STM32U3C5xx) || defined(STM32U3B5xx) HAL_HSP_TRGIN_DMA1_CH1_TC, HAL_HSP_TRGIN_DMA1_CH2_TC, HAL_HSP_TRGIN_DMA1_CH3_TC, HAL_HSP_TRGIN_DMA1_CH4_TC, +#else + HAL_HSP_TRGIN_DMA1_CH8_TC, + HAL_HSP_TRGIN_DMA1_CH9_TC, + HAL_HSP_TRGIN_DMA1_CH10_TC, + HAL_HSP_TRGIN_DMA1_CH11_TC, +#endif /* STM32U3C5xx || STM32U3B5xx */ HAL_HSP_TRGIN_EXTI0, HAL_HSP_TRGIN_EXTI1, HAL_HSP_TRGIN_TIM1_TRGO, diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_irda_ex.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_irda_ex.h index 9c9c04f52b..2b3f89d88e 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_irda_ex.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_irda_ex.h @@ -69,6 +69,27 @@ extern "C" { * @param __CLOCKSOURCE__ output variable. * @retval IRDA clocking source, written in __CLOCKSOURCE__. */ +#if !defined(USART2) && !defined (UART5) +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#elif !defined(USART2) #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -92,7 +113,35 @@ extern "C" { (__CLOCKSOURCE__) = 0U; \ } \ } while(0U) - +#else +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#endif /* USART2, USART5 */ /** @brief Compute the mask to apply to retrieve the received data * according to the word length and to the parity bits activation. diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_pcd.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_pcd.h index 8b01df2a0d..05db953449 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_pcd.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_pcd.h @@ -104,7 +104,7 @@ typedef struct uint32_t Setup[12]; /*!< Setup packet buffer */ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; - + uint32_t FrameNumber; /*!< Store Current Frame number */ uint32_t lpm_active; /*!< Enable or disable the Link Power Management . This parameter can be set to ENABLE or DISABLE */ @@ -199,7 +199,6 @@ typedef struct #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR2 |= USB_WAKEUP_EXTI_LINE #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR2 &= ~(USB_WAKEUP_EXTI_LINE) - /** * @} */ diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_pwr_ex.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_pwr_ex.h index 03b098745a..b48a043c18 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_pwr_ex.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_pwr_ex.h @@ -68,20 +68,24 @@ extern "C" { */ /* SRAM1 pages retention defines */ #define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 page 1 retention in Stop modes (Stop 0, 1, 2, 3) */ +#if defined(PWR_CR2_SRAM1PDS2) #define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_CR2_SRAM1PDS2 /*!< SRAM1 page 2 retention in Stop modes (Stop 0, 1, 2, 3) */ #define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_CR2_SRAM1PDS3 /*!< SRAM1 page 3 retention in Stop modes (Stop 0, 1, 2, 3) */ #define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_CR2_SRAM1PDS4 /*!< SRAM1 page 4 retention in Stop modes (Stop 0, 1, 2, 3) */ #define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_CR2_SRAM1PDS5 /*!< SRAM1 page 5 retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif/*PWR_CR2_SRAM1PDS2*/ #if defined(PWR_CR2_SRAM1PDS6) #define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_CR2_SRAM1PDS6 /*!< SRAM1 page 6 retention in Stop modes (Stop 0, 1, 2, 3) */ #define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_CR2_SRAM1PDS7 /*!< SRAM1 page 7 retention in Stop modes (Stop 0, 1, 2, 3) */ #define PWR_SRAM1_FULL_STOP_RETENTION (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 | PWR_CR2_SRAM1PDS3 | PWR_CR2_SRAM1PDS4 |\ PWR_CR2_SRAM1PDS5 | PWR_CR2_SRAM1PDS6 | PWR_CR2_SRAM1PDS7) /*!< SRAM1 full retention in Stop modes (Stop 0, 1, 2, 3) */ -#else +#elif defined(PWR_CR2_SRAM1PDS2) #define PWR_SRAM1_FULL_STOP_RETENTION (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 | PWR_CR2_SRAM1PDS3 | PWR_CR2_SRAM1PDS4 |\ PWR_CR2_SRAM1PDS5) /*!< SRAM1 full retention in Stop modes (Stop 0, 1, 2, 3) */ +#else +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_CR2_SRAM1PDS1 #endif /* PWR_CR2_SRAM1PDS6 */ /* SRAM2 pages retention defines */ @@ -167,7 +171,9 @@ extern "C" { #define PWR_GPIO_B (1U) /*!< GPIO port B */ #define PWR_GPIO_C (2U) /*!< GPIO port C */ #define PWR_GPIO_D (3U) /*!< GPIO port D */ +#if defined(PWR_PDCRE_PD15) #define PWR_GPIO_E (4U) /*!< GPIO port E */ +#endif/*PWR_PDCRE_PD15*/ #if defined(RAMCFG_SRAM3) #define PWR_GPIO_F (5U) /*!< GPIO port F */ #endif /* RAMCFG_SRAM3 */ @@ -211,9 +217,9 @@ extern "C" { #define PWR_I3CPU_PA7 PWR_I3CPUCR1_PA7_I3CPU /*!< I3C pull-up on PA7 */ #define PWR_I3CPU_PB2 PWR_I3CPUCR1_PB2_I3CPU /*!< I3C pull-up on PB2 */ #define PWR_I3CPU_PB6 PWR_I3CPUCR1_PB6_I3CPU /*!< I3C pull-up on PB6 */ -#if defined(RAMCFG_SRAM3) +#if defined(PWR_I3CPUCR1_PB7_I3CPU) #define PWR_I3CPU_PB7 PWR_I3CPUCR1_PB7_I3CPU /*!< I3C pull-up on PB7 */ -#endif /* RAMCFG_SRAM3 */ +#endif /* PWR_I3CPUCR1_PB7_I3CPU */ #if defined(PWR_I3CPUCR1_PB8_I3CPU) #define PWR_I3CPU_PB8 PWR_I3CPUCR1_PB8_I3CPU /*!< I3C pull-up on PB8 */ #define PWR_I3CPU_PB9 PWR_I3CPUCR1_PB9_I3CPU /*!< I3C pull-up on PB9 */ @@ -221,19 +227,23 @@ extern "C" { #define PWR_I3CPU_PB10 PWR_I3CPUCR1_PB10_I3CPU /*!< I3C pull-up on PB10 */ #define PWR_I3CPU_PB12 PWR_I3CPUCR1_PB12_I3CPU /*!< I3C pull-up on PB12 */ #define PWR_I3CPU_PB13 PWR_I3CPUCR1_PB13_I3CPU /*!< I3C pull-up on PB13 */ -#if defined(PWR_I3CPUCR1_PB8_I3CPU) +#if defined(PWR_I3CPUCR1_PB14_I3CPU) #define PWR_I3CPU_PB14 PWR_I3CPUCR1_PB14_I3CPU /*!< I3C pull-up on PB14 */ +#endif /* PWR_I3CPUCR1_PB14_I3CPU */ +#if defined(PWR_I3CPUCR2_PC0_I3CPU) #define PWR_I3CPU_PC0 (PWR_I3CPUCR2_PC0_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PC0 */ -#endif /* PWR_I3CPUCR1_PB8_I3CPU */ +#endif /* PWR_I3CPUCR2_PC0_I3CPU */ +#if defined(PWR_I3CPUCR2_PC1_I3CPU) #define PWR_I3CPU_PC1 (PWR_I3CPUCR2_PC1_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PC1 */ #define PWR_I3CPU_PD12 (PWR_I3CPUCR2_PD12_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PD12 */ #define PWR_I3CPU_PD13 (PWR_I3CPUCR2_PD13_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PD13 */ -#if defined(PWR_I3CPUCR1_PB8_I3CPU) +#endif/* PWR_I3CPUCR2_PC1_I3CPU */ +#if defined(PWR_I3CPUCR2_PG7_I3CPU) #define PWR_I3CPU_PG7 (PWR_I3CPUCR2_PG7_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PG7 */ #define PWR_I3CPU_PG8 (PWR_I3CPUCR2_PG8_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PG8 */ #define PWR_I3CPU_PG13 (PWR_I3CPUCR2_PG13_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PG13 */ #define PWR_I3CPU_PG14 (PWR_I3CPUCR2_PG14_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PG14 */ -#endif /* PWR_I3CPUCR1_PB8_I3CPU */ +#endif /* PWR_I3CPUCR2_PG7_I3CPU */ #define PWR_I3CPU_PH3 (PWR_I3CPUCR2_PH3_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PH3 */ #if defined(RAMCFG_SRAM3) @@ -243,16 +253,20 @@ extern "C" { PWR_I3CPU_PC0 | PWR_I3CPU_PC1 | PWR_I3CPU_PD12 | PWR_I3CPU_PD13 |\ PWR_I3CPU_PG7 | PWR_I3CPU_PG8 | PWR_I3CPU_PG13 | PWR_I3CPU_PG14 |\ PWR_I3CPU_PH3) -#elif defined(PWR_I3CPUCR1_PB8_I3CPU) +#elif defined(PWR_I3CPUCR2_PC0_I3CPU) #define PWR_I3CPUCR_ALL (PWR_I3CPU_PA1 | PWR_I3CPU_PA6 | PWR_I3CPU_PA7 | PWR_I3CPU_PB2 |\ PWR_I3CPU_PB6 | PWR_I3CPU_PB8 | PWR_I3CPU_PB9 | PWR_I3CPU_PB10 |\ PWR_I3CPU_PB12 | PWR_I3CPU_PB13 | PWR_I3CPU_PB14 | PWR_I3CPU_PC0 |\ PWR_I3CPU_PC1 | PWR_I3CPU_PD12 | PWR_I3CPU_PD13 | PWR_I3CPU_PG7 |\ PWR_I3CPU_PG8 | PWR_I3CPU_PG13 | PWR_I3CPU_PG14 | PWR_I3CPU_PH3) -#else +#elif defined(PWR_I3CPUCR2_PC1_I3CPU) #define PWR_I3CPUCR_ALL (PWR_I3CPU_PA1 | PWR_I3CPU_PA6 | PWR_I3CPU_PA7 | PWR_I3CPU_PB2 |\ PWR_I3CPU_PB6 | PWR_I3CPU_PB10 | PWR_I3CPU_PB12 | PWR_I3CPU_PB13 |\ PWR_I3CPU_PC1 | PWR_I3CPU_PD12 | PWR_I3CPU_PD13 | PWR_I3CPU_PH3) +#else +#define PWR_I3CPUCR_ALL (PWR_I3CPU_PA1 | PWR_I3CPU_PA6 | PWR_I3CPU_PA7 | PWR_I3CPU_PB2 |\ + PWR_I3CPU_PB6 | PWR_I3CPU_PB7 | PWR_I3CPU_PB8 | PWR_I3CPU_PB9 |\ + PWR_I3CPU_PB10 | PWR_I3CPU_PB12 | PWR_I3CPU_PB13 | PWR_I3CPU_PH3) #endif /* defined(RAMCFG_SRAM3)*/ /*!< I3C pull-up all */ /** @@ -322,13 +336,19 @@ extern "C" { ((__GPIO_PORT__) == PWR_GPIO_E) ||\ ((__GPIO_PORT__) == PWR_GPIO_G) ||\ ((__GPIO_PORT__) == PWR_GPIO_H)) -#else +#elif defined(PWR_GPIO_E) #define IS_PWR_GPIO_PORT(__GPIO_PORT__) (((__GPIO_PORT__) == PWR_GPIO_A) ||\ ((__GPIO_PORT__) == PWR_GPIO_B) ||\ ((__GPIO_PORT__) == PWR_GPIO_C) ||\ ((__GPIO_PORT__) == PWR_GPIO_D) ||\ ((__GPIO_PORT__) == PWR_GPIO_E) ||\ ((__GPIO_PORT__) == PWR_GPIO_H)) +#else +#define IS_PWR_GPIO_PORT(__GPIO_PORT__) (((__GPIO_PORT__) == PWR_GPIO_A) ||\ + ((__GPIO_PORT__) == PWR_GPIO_B) ||\ + ((__GPIO_PORT__) == PWR_GPIO_C) ||\ + ((__GPIO_PORT__) == PWR_GPIO_D) ||\ + ((__GPIO_PORT__) == PWR_GPIO_H)) #endif /* PWR_GPIO_G */ #endif /* defined(RAMCFG_SRAM3) */ @@ -348,7 +368,7 @@ extern "C" { #endif /* RAMCFG_SRAM3 */ /* RAMs retention in Stop mode check macro */ -#if defined(RAMCFG_SRAM3) && defined(PWR_PKA_STOP_RETENTION) +#if defined(RAMCFG_SRAM3) #define IS_PWR_RAM_STOP_RETENTION(__RAM__) (((__RAM__) == PWR_SRAM1_PAGE1_STOP_RETENTION) ||\ ((__RAM__) == PWR_SRAM1_PAGE2_STOP_RETENTION) ||\ ((__RAM__) == PWR_SRAM1_PAGE3_STOP_RETENTION) ||\ @@ -371,30 +391,7 @@ extern "C" { ((__RAM__) == PWR_ICACHE_STOP_RETENTION) ||\ ((__RAM__) == PWR_FDCAN_USB_STOP_RETENTION) ||\ ((__RAM__) == PWR_PKA_STOP_RETENTION)) -#elif defined(RAMCFG_SRAM3) && !defined(PWR_PKA_STOP_RETENTION) -#define IS_PWR_RAM_STOP_RETENTION(__RAM__) (((__RAM__) == PWR_SRAM1_PAGE1_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_PAGE2_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_PAGE3_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_PAGE4_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_PAGE5_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_PAGE6_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_PAGE7_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_FULL_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM2_PAGE1_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM2_PAGE2_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM2_PAGE3_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM2_FULL_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM3_PAGE1_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM3_PAGE2_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM3_PAGE3_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM3_PAGE4_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM3_PAGE5_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM3_FULL_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM4_FULL_STOP_RETENTION) ||\ - ((__RAM__) == PWR_ICACHE_STOP_RETENTION) ||\ - ((__RAM__) == PWR_FDCAN_USB_STOP_RETENTION)) - -#elif defined(PWR_SRAM1_PAGE6_STOP_RETENTION) && defined(PWR_PKA_STOP_RETENTION) +#elif defined(PWR_SRAM1_PAGE6_STOP_RETENTION) #define IS_PWR_RAM_STOP_RETENTION(__RAM__) (((__RAM__) == PWR_SRAM1_PAGE1_STOP_RETENTION) ||\ ((__RAM__) == PWR_SRAM1_PAGE2_STOP_RETENTION) ||\ ((__RAM__) == PWR_SRAM1_PAGE3_STOP_RETENTION) ||\ @@ -410,24 +407,7 @@ extern "C" { ((__RAM__) == PWR_ICACHE_STOP_RETENTION) ||\ ((__RAM__) == PWR_FDCAN_USB_STOP_RETENTION) ||\ ((__RAM__) == PWR_PKA_STOP_RETENTION)) - -#elif defined(PWR_SRAM1_PAGE6_STOP_RETENTION) && !defined(PWR_PKA_STOP_RETENTION) -#define IS_PWR_RAM_STOP_RETENTION(__RAM__) (((__RAM__) == PWR_SRAM1_PAGE1_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_PAGE2_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_PAGE3_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_PAGE4_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_PAGE5_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_PAGE6_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_PAGE7_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_FULL_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM2_PAGE1_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM2_PAGE2_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM2_PAGE3_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM2_FULL_STOP_RETENTION) ||\ - ((__RAM__) == PWR_ICACHE_STOP_RETENTION) ||\ - ((__RAM__) == PWR_FDCAN_USB_STOP_RETENTION)) - -#elif defined(PWR_PKA_STOP_RETENTION) && !defined(PWR_SRAM1_PAGE6_STOP_RETENTION) && !defined(RAMCFG_SRAM3) +#elif defined(PWR_SRAM1_PAGE2_STOP_RETENTION) #define IS_PWR_RAM_STOP_RETENTION(__RAM__) (((__RAM__) == PWR_SRAM1_PAGE1_STOP_RETENTION) ||\ ((__RAM__) == PWR_SRAM1_PAGE2_STOP_RETENTION) ||\ ((__RAM__) == PWR_SRAM1_PAGE3_STOP_RETENTION) ||\ @@ -442,12 +422,7 @@ extern "C" { ((__RAM__) == PWR_FDCAN_USB_STOP_RETENTION) ||\ ((__RAM__) == PWR_PKA_STOP_RETENTION)) #else -#define IS_PWR_RAM_STOP_RETENTION(__RAM__) (((__RAM__) == PWR_SRAM1_PAGE1_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_PAGE2_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_PAGE3_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_PAGE4_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_PAGE5_STOP_RETENTION) ||\ - ((__RAM__) == PWR_SRAM1_FULL_STOP_RETENTION) ||\ +#define IS_PWR_RAM_STOP_RETENTION(__RAM__) (((__RAM__) == PWR_SRAM1_FULL_STOP_RETENTION) ||\ ((__RAM__) == PWR_SRAM2_PAGE1_STOP_RETENTION) ||\ ((__RAM__) == PWR_SRAM2_PAGE2_STOP_RETENTION) ||\ ((__RAM__) == PWR_SRAM2_PAGE3_STOP_RETENTION) ||\ @@ -463,7 +438,7 @@ extern "C" { ((__PAGE__) == PWR_SRAM2_FULL_STANDBY_RETENTION)) /* I3C Pull-up configuration check macro */ -#if defined(PWR_I3CPU_PB7) +#if defined(RAMCFG_SRAM3) #define IS_PWR_I3C_PULLUP_GPIO(__GPIO__) (((__GPIO__) == PWR_I3CPU_PA1) ||\ ((__GPIO__) == PWR_I3CPU_PA6) ||\ ((__GPIO__) == PWR_I3CPU_PA7) ||\ @@ -486,7 +461,7 @@ extern "C" { ((__GPIO__) == PWR_I3CPU_PG14) ||\ ((__GPIO__) == PWR_I3CPU_PH3) ||\ ((__GPIO__) == PWR_I3CPUCR_ALL)) -#elif defined(PWR_I3CPU_PB8) +#elif defined(PWR_I3CPU_PC0) #define IS_PWR_I3C_PULLUP_GPIO(__GPIO__) (((__GPIO__) == PWR_I3CPU_PA1) ||\ ((__GPIO__) == PWR_I3CPU_PA6) ||\ ((__GPIO__) == PWR_I3CPU_PA7) ||\ @@ -508,12 +483,13 @@ extern "C" { ((__GPIO__) == PWR_I3CPU_PG14) ||\ ((__GPIO__) == PWR_I3CPU_PH3) ||\ ((__GPIO__) == PWR_I3CPUCR_ALL)) -#else +#elif defined(PWR_I3CPU_PC1) #define IS_PWR_I3C_PULLUP_GPIO(__GPIO__) (((__GPIO__) == PWR_I3CPU_PA1) ||\ ((__GPIO__) == PWR_I3CPU_PA6) ||\ ((__GPIO__) == PWR_I3CPU_PA7) ||\ ((__GPIO__) == PWR_I3CPU_PB2) ||\ ((__GPIO__) == PWR_I3CPU_PB6) ||\ + ((__GPIO__) == PWR_I3CPU_PB7) ||\ ((__GPIO__) == PWR_I3CPU_PB10) ||\ ((__GPIO__) == PWR_I3CPU_PB12) ||\ ((__GPIO__) == PWR_I3CPU_PB13) ||\ @@ -522,7 +498,21 @@ extern "C" { ((__GPIO__) == PWR_I3CPU_PD13) ||\ ((__GPIO__) == PWR_I3CPU_PH3) ||\ ((__GPIO__) == PWR_I3CPUCR_ALL)) -#endif /* defined(PWR_I3CPU_PB7) */ +#else +#define IS_PWR_I3C_PULLUP_GPIO(__GPIO__) (((__GPIO__) == PWR_I3CPU_PA1) ||\ + ((__GPIO__) == PWR_I3CPU_PA6) ||\ + ((__GPIO__) == PWR_I3CPU_PA7) ||\ + ((__GPIO__) == PWR_I3CPU_PB2) ||\ + ((__GPIO__) == PWR_I3CPU_PB6) ||\ + ((__GPIO__) == PWR_I3CPU_PB7) ||\ + ((__GPIO__) == PWR_I3CPU_PB8) ||\ + ((__GPIO__) == PWR_I3CPU_PB9) ||\ + ((__GPIO__) == PWR_I3CPU_PB10) ||\ + ((__GPIO__) == PWR_I3CPU_PB12) ||\ + ((__GPIO__) == PWR_I3CPU_PB13) ||\ + ((__GPIO__) == PWR_I3CPU_PH3) ||\ + ((__GPIO__) == PWR_I3CPUCR_ALL)) +#endif /* defined(RAMCFG_SRAM3) */ /** * @} */ diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_rcc.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_rcc.h index f2fb7d23a1..b7a193c4fc 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_rcc.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_rcc.h @@ -337,6 +337,8 @@ typedef struct #define RCC_MCO_GPIOPIN_MASK (0xFFFFuL << RCC_MCO_GPIOPIN_POS) #define RCC_MCO_GPIOPORT_POS 16U #define RCC_MCO_GPIOPORT_MASK (0xFuL << RCC_MCO_GPIOPORT_POS) +#define RCC_MCO_GPIOPORTA 0x0uL +#define RCC_MCO_GPIOPORTB 0x1uL #define RCC_MCO_GPIOAF_POS 20U #define RCC_MCO_GPIOAF_MASK (0xFuL << RCC_MCO_GPIOAF_POS) #define RCC_MCO_INDEX_POS 28U @@ -347,13 +349,22 @@ typedef struct * @{ */ #define RCC_MCO1_PA8 ((0x00U << RCC_MCO_INDEX_POS) |\ + (RCC_MCO_GPIOPORTA << RCC_MCO_GPIOPORT_POS) |\ (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | GPIO_PIN_8) +#if defined(STM32U366xx) || defined(STM32U356xx) +#define RCC_MCO1_PB8 ((0x00U << RCC_MCO_INDEX_POS) |\ + (RCC_MCO_GPIOPORTB << RCC_MCO_GPIOPORT_POS) |\ + (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | GPIO_PIN_8) +#endif /* defined(STM32U366xx) || defined(STM32U356xx) */ #define RCC_MCO1_PA9 ((0x00U << RCC_MCO_INDEX_POS) |\ + (RCC_MCO_GPIOPORTA << RCC_MCO_GPIOPORT_POS) |\ (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | GPIO_PIN_9) #define RCC_MCO1 RCC_MCO1_PA8 #define RCC_MCO2_PA8 ((0x01U << RCC_MCO_INDEX_POS) |\ + (RCC_MCO_GPIOPORTA << RCC_MCO_GPIOPORT_POS) |\ (GPIO_AF11_MCO2 << RCC_MCO_GPIOAF_POS) | GPIO_PIN_8) #define RCC_MCO2_PA10 ((0x01U << RCC_MCO_INDEX_POS) |\ + (RCC_MCO_GPIOPORTA << RCC_MCO_GPIOPORT_POS) |\ (GPIO_AF11_MCO2 << RCC_MCO_GPIOAF_POS) | GPIO_PIN_10) #define RCC_MCO2 RCC_MCO2_PA8 #define RCC_MCO RCC_MCO1 @@ -645,7 +656,22 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR2, RCC_AHB1ENR2_PWREN); \ UNUSED(tmpreg); \ } while(0) - +#if defined(GFXPAND1) +#define __HAL_RCC_GFXPAND_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_GFXPAND1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_GFXPAND1EN); \ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GFXPAND_CLK_DISABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_GFXPAND1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_GFXPAND1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GFXPAND1 */ #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR1, RCC_AHB1ENR1_GPDMA1EN) #if defined(ADF1) #define __HAL_RCC_ADF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR1, RCC_AHB1ENR1_ADF1EN) @@ -1429,6 +1455,9 @@ typedef struct #if defined(OCTOSPI1) #define __HAL_RCC_OCTOSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) != 0U) #endif /* OCTOSPI1 */ +#if defined(GFXPAND1) +#define __HAL_RCC_GFXPAND_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_GFXPAND1EN) != 0U) +#endif /* GFXPAND1 */ /** * @} */ @@ -1596,6 +1625,9 @@ typedef struct #if defined(OCTOSPI1) #define __HAL_RCC_OCTOSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) #endif /* OCTOSPI1 */ +#if defined(GFXPAND1) +#define __HAL_RCC_GFXPAND_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_GFXPAND1RST) +#endif /* GFXPAND1 */ #define __HAL_RCC_AHB2_RELEASE_RESET() do { \ WRITE_REG(RCC->AHB2RSTR1, 0x00000000U); \ @@ -1635,6 +1667,9 @@ typedef struct #if defined(OCTOSPI1) #define __HAL_RCC_OCTOSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) #endif /* OCTOSPI1 */ +#if defined(GFXPAND1) +#define __HAL_RCC_GFXPAND_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_GFXPAND1RST) +#endif /* GFXPAND1 */ /** * @} */ @@ -1898,6 +1933,9 @@ typedef struct #if defined(OCTOSPI1) #define __HAL_RCC_OCTOSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SLPENR2, RCC_AHB2SLPENR2_OCTOSPI1SLPEN) #endif /* OCTOSPI1 */ +#if defined(GFXPAND1) +#define __HAL_RCC_GFXPAND_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SLPENR2, RCC_AHB2SLPENR2_GFXPAND1SLPEN) +#endif /* GFXPAND1 */ #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SLPENR1, RCC_AHB2SLPENR1_GPIOASLPEN) #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SLPENR1, RCC_AHB2SLPENR1_GPIOBSLPEN) @@ -1921,6 +1959,9 @@ typedef struct #if defined(PKA) #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SLPENR1, RCC_AHB2SLPENR1_PKASLPEN) #endif /* PKA */ +#if defined(GFXPAND1) +#define __HAL_RCC_GFXPAND_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SLPENR2, RCC_AHB2SLPENR2_GFXPAND1SLPEN) +#endif /* GFXPAND1 */ #if defined(SAES) #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SLPENR1, RCC_AHB2SLPENR1_SAESSLPEN) #endif /* SAES */ @@ -2176,6 +2217,9 @@ typedef struct #if defined(OCTOSPI1) #define __HAL_RCC_OCTOSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SLPENR2, RCC_AHB2SLPENR2_OCTOSPI1SLPEN) != 0U) #endif /* OCTOSPI1 */ +#if defined(GFXPAND1) +#define __HAL_RCC_GFXPAND_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SLPENR2, RCC_AHB2SLPENR2_GFXPAND1SLPEN) != 0U) +#endif /* GFXPAND1 */ /** * @} */ @@ -3093,10 +3137,10 @@ typedef struct * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ - ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ - ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ - (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \ - ? 1U : 0U) + ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ + ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \ + ? 1U : 0U) /** * @} */ @@ -3189,8 +3233,14 @@ typedef struct ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) +#if defined(STM32U356xx) || defined(STM32U366xx) +#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1_PA8) || ((__MCOX__) == RCC_MCO1_PA9) || \ + ((__MCOX__) == RCC_MCO1_PB8) || \ + ((__MCOX__) == RCC_MCO2_PA8) || ((__MCOX__) == RCC_MCO2_PA10)) +#else #define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1_PA8) || ((__MCOX__) == RCC_MCO1_PA9) || \ ((__MCOX__) == RCC_MCO2_PA8) || ((__MCOX__) == RCC_MCO2_PA10)) +#endif /* defined(STM32U356xx) || defined(STM32U366xx) */ #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_rng_ex.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_rng_ex.h index 98fd85b0a4..46168e5aa9 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_rng_ex.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_rng_ex.h @@ -26,6 +26,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32u3xx_hal_def.h" +#include "stm32u3xx_ll_rng.h" /** @addtogroup STM32U3xx_HAL_Driver * @{ @@ -56,7 +57,7 @@ typedef struct uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can be a value of @ref RNGEx_Clock_Divider_Factor */ - uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a + uint32_t NistCompliance; /*!< NIST compliance configuration.This parameter can be a value of @ref RNGEx_NIST_Compliance */ uint32_t AutoReset; /*!< automatic reset When a noise source error occurs value of @ref RNGEx_Auto_Reset */ @@ -115,8 +116,8 @@ typedef struct /** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ -#define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ -#define RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */ +#define RNG_NIST_COMPLIANT (0x00000000UL) /*!< Default NIST compliant configuration*/ +#define RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST compliant configuration */ /** * @} @@ -195,6 +196,10 @@ typedef struct #define IS_RNG_CONFIG3(__CONFIG3__) ((__CONFIG3__) <= 0xFUL) #define IS_RNG_ARDIS(__ARDIS__) (((__ARDIS__) == RNG_ARDIS_ENABLE) || \ ((__ARDIS__) == RNG_ARDIS_DISABLE)) +#define IS_RNG_HTCR_INDEX(__INDEX__) (((__INDEX__) == 0x01U) || \ + ((__INDEX__) == 0x02U) || \ + ((__INDEX__) == 0x03U)) +#define IS_RNG_HTCR_VALUE(__VALUE__) ((__VALUE__) <= 0x3FFFF) /** @@ -230,6 +235,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); +HAL_StatusTypeDef HAL_RNGEx_SetHealthFactorConfig(RNG_HandleTypeDef *hrng, uint32_t htcr_idx, uint32_t htcr_value); /** * @} diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_smartcard.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_smartcard.h index 6e3e9edfe7..b7acea48fe 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_smartcard.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_smartcard.h @@ -850,6 +850,27 @@ typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard) * @param __CLOCKSOURCE__ output variable. * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. */ +#if defined(USART2) +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#else #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -865,6 +886,7 @@ typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard) (__CLOCKSOURCE__) = 0U; \ } \ } while(0U) +#endif /* USART2 */ /** @brief Check the Baud rate range. diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_uart_ex.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_uart_ex.h index e0c3cecef7..74315da7f7 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_uart_ex.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_uart_ex.h @@ -297,12 +297,17 @@ HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart * @param __CLOCKSOURCE__ output variable. * @retval UART clocking source, written in __CLOCKSOURCE__. */ +#if defined(UART5) && defined(USART2) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ else if((__HANDLE__)->Instance == USART3) \ { \ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ @@ -324,7 +329,59 @@ HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart (__CLOCKSOURCE__) = 0U; \ } \ } while(0U) - +#elif defined(UART5) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#else +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#endif /*UART5*/ /** @brief Report the UART mask to apply to retrieve the received data * according to the word length and to the parity bits activation. diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_usart.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_usart.h index c874c974f9..1e5b83bb77 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_usart.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_usart.h @@ -712,12 +712,17 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @param __CLOCKSOURCE__ output variable. * @retval the USART clocking source, written in __CLOCKSOURCE__. */ +#if defined(USART2) #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ else if((__HANDLE__)->Instance == USART3) \ { \ (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ @@ -727,7 +732,23 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin (__CLOCKSOURCE__) = 0U; \ } \ } while(0U) - +#else +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#endif /*UART2*/ /** @brief Check USART Baud rate. * @param __BAUDRATE__ Baudrate specified by the user. diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_adc.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_adc.h index 3a7a5caa0a..aaef01a6b1 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_adc.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_adc.h @@ -479,6 +479,9 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */ #endif /* ADC_MULTIMODE_SUPPORT */ +#if !defined(ADC_MULTIMODE_SUPPORT) + uint32_t Dummy; /*!< Reserved to avoid an empty struct when multimode is not supported. */ +#endif /* ADC_MULTIMODE_SUPPORT */ } LL_ADC_CommonInitTypeDef; @@ -942,16 +945,26 @@ to which the offset programmed will be applied (independently of channel mapped #define LL_ADC_CHANNEL_16 (16UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN16 */ #define LL_ADC_CHANNEL_17 (17UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN17 */ #define LL_ADC_CHANNEL_18 (18UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN18 */ +#if defined(ADC1) && defined(ADC2) #define LL_ADC_CHANNEL_VREFINT (0UL \ | ADC_CHANNEL_INTERNAL_ADC1 | ADC_CHANNEL_INTERNAL_ADC2 \ | LL_ADC_PATH_INTERNAL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ +#else +#define LL_ADC_CHANNEL_VREFINT (0UL \ + | ADC_CHANNEL_INTERNAL_ADC1 \ + | LL_ADC_PATH_INTERNAL_VREFINT) /*!< ADC internal channel + connected to VrefInt: Internal voltage reference. */ +#endif /* ADC1 && ADC2 */ +#if defined(ADC2) #define LL_ADC_CHANNEL_DAC1CH1_ADC2 (14UL \ | ADC_CHANNEL_INTERNAL_ADC2) /*!< ADC internal channel DAC1 channel 1, channel specific to ADC2 */ #define LL_ADC_CHANNEL_DAC1CH2_ADC2 (15UL \ | ADC_CHANNEL_INTERNAL_ADC2) /*!< ADC internal channel DAC1 channel 2, channel specific to ADC2 */ +#endif /* ADC2 */ +#if defined(ADC1) && defined(ADC2) #define LL_ADC_CHANNEL_VBAT (16UL \ | ADC_CHANNEL_INTERNAL_ADC1 | ADC_CHANNEL_INTERNAL_ADC2 \ | LL_ADC_PATH_INTERNAL_VBAT) /*!< ADC internal channel @@ -965,6 +978,21 @@ to which the offset programmed will be applied (independently of channel mapped | ADC_CHANNEL_INTERNAL_ADC1 | ADC_CHANNEL_INTERNAL_ADC2 \ | LL_ADC_PATH_INTERNAL_VDDCORE) /*!< ADC internal channel Vddcore */ +#else +#define LL_ADC_CHANNEL_VBAT (16UL \ + | ADC_CHANNEL_INTERNAL_ADC1 \ + | LL_ADC_PATH_INTERNAL_VBAT) /*!< ADC internal channel + connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have + Vbat always below Vdda. */ +#define LL_ADC_CHANNEL_TEMPSENSOR (17UL \ + | ADC_CHANNEL_INTERNAL_ADC1 \ + | LL_ADC_PATH_INTERNAL_TEMPSENSOR) /*!< ADC internal channel + Temperature sensor */ +#define LL_ADC_CHANNEL_VDDCORE (18UL \ + | ADC_CHANNEL_INTERNAL_ADC1 \ + | LL_ADC_PATH_INTERNAL_VDDCORE) /*!< ADC internal channel + Vddcore */ +#endif /* ADC1 && ADC2 */ /** * @} */ @@ -1697,6 +1725,7 @@ to which the offset programmed will be applied (independently of channel mapped #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ LL_ADC_AWD_CHANNEL_17_REG_INJ /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */ +#if defined(ADC2) #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG LL_ADC_AWD_CHANNEL_14_REG /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 Channel 1, converted by group regular only */ @@ -1715,6 +1744,7 @@ to which the offset programmed will be applied (independently of channel mapped #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ LL_ADC_AWD_CHANNEL_15_REG_INJ /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 Channel 2, converted by either group regular or injected */ +#endif /* ADC2 */ /** * @} */ @@ -2273,6 +2303,7 @@ to which the offset programmed will be applied (independently of channel mapped * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. * Value "1" if the internal channel selected is available on the ADC instance selected. */ +#if defined(ADC1) && defined(ADC2) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ ((((__ADC_INSTANCE__) == ADC1) \ &&(((__CHANNEL__ & ADC_CHANNEL_INTERNAL_ADC1) == ADC_CHANNEL_INTERNAL_ADC1)) \ @@ -2282,6 +2313,12 @@ to which the offset programmed will be applied (independently of channel mapped &&(((__CHANNEL__ & ADC_CHANNEL_INTERNAL_ADC2) == ADC_CHANNEL_INTERNAL_ADC2)) \ ) \ ) +#else +#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + ((((__ADC_INSTANCE__) == ADC1) \ + &&(((__CHANNEL__ & ADC_CHANNEL_INTERNAL_ADC1) == ADC_CHANNEL_INTERNAL_ADC1)) \ + )) +#endif /* ADC1 && ADC2 */ /** * @brief Helper macro to define ADC analog watchdog parameter: @@ -2522,6 +2559,7 @@ to which the offset programmed will be applied (independently of channel mapped * @param __ADCx__ ADC instance * @retval __ADCx__ ADC instance master of the corresponding ADC common instance */ +#if defined(ADC1) && defined(ADC2) #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \ ( ( ((__ADCx__) == ADC2) \ )? \ @@ -2529,6 +2567,9 @@ to which the offset programmed will be applied (independently of channel mapped : \ (__ADCx__) \ ) +#else +#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) (ADC1) +#endif /* ADC1 && ADC2 */ #endif /* ADC_MULTIMODE_SUPPORT */ /** @@ -2541,7 +2582,11 @@ to which the offset programmed will be applied (independently of channel mapped * @param __ADCx__ ADC instance * @retval ADC common register instance */ +#if defined(ADC1) && defined(ADC2) #define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON) +#else +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC1_COMMON) +#endif /* ADC1 && ADC2 */ /** * @brief Helper macro to check if all ADC instances sharing the same @@ -2560,8 +2605,13 @@ to which the offset programmed will be applied (independently of channel mapped * Value "1" if at least one ADC instance sharing the same ADC common instance * is enabled. */ +#if defined(ADC1) && defined(ADC2) #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2)) +#else +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + LL_ADC_IsEnabled(ADC1) +#endif /* ADC1 && ADC2 */ /** * @brief Helper macro to define the ADC conversion data full-scale digital * value corresponding to the selected ADC resolution. diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_bus.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_bus.h index a8b8a54e3b..5835c2e16a 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_bus.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_bus.h @@ -122,7 +122,11 @@ extern "C" { #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR1_GPIOBEN #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR1_GPIOCEN #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR1_GPIODEN +#if defined(GPIOE) #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR1_GPIOEEN +#else +#define LL_AHB2_GRP1_PERIPH_GPIOE 0U +#endif /* #if defined(GPIOE) */ #if defined(GPIOF) #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR1_GPIOFEN #else @@ -205,7 +209,12 @@ extern "C" { * @{ */ #define LL_AHB2_GRP2_PERIPH_OCTOSPI1 RCC_AHB2ENR2_OCTOSPI1EN -#define LL_AHB2_GRP2_PERIPH_ALL RCC_AHB2ENR2_OCTOSPI1EN +#if defined(GFXPAND1) +#define LL_AHB2_GRP2_PERIPH_GFXPAND1 RCC_AHB2ENR2_GFXPAND1EN +#else +#define LL_AHB2_GRP2_PERIPH_GFXPAND1 0U +#endif /* GFXPAND1 */ +#define LL_AHB2_GRP2_PERIPH_ALL (LL_AHB2_GRP2_PERIPH_OCTOSPI1 | LL_AHB2_GRP2_PERIPH_GFXPAND1) /** * @} */ diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_dma.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_dma.h index 196cb8fc45..9b39c879fd 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_dma.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_dma.h @@ -1014,8 +1014,10 @@ typedef struct #define LL_GPDMA1_REQUEST_I3C1_TX 50U /*!< GPDMA1 HW request is I3C1_TX */ #define LL_GPDMA1_REQUEST_I3C1_TC 51U /*!< GPDMA1 HW request is I3C1_TC */ #define LL_GPDMA1_REQUEST_I3C1_RS 52U /*!< GPDMA1 HW request is I3C1_RS */ -/* Reserved 53U */ -/* Reserved 54U */ +#if defined (GFXPAND1) +#define LL_GPDMA1_REQUEST_GFXPAND_IN 53U /*!< GPDMA1 HW request is GFXPAND_IN */ +#define LL_GPDMA1_REQUEST_GFXPAND_OUT 54U /*!< GPDMA1 HW request is GFXPAND_OUT */ +#endif /* GFXPAND1 */ /* Reserved 55U */ #define LL_GPDMA1_REQUEST_TIM2_CH1 56U /*!< GPDMA1 HW request is TIM2_CH1 */ #define LL_GPDMA1_REQUEST_TIM2_CH2 57U /*!< GPDMA1 HW request is TIM2_CH2 */ diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_pwr.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_pwr.h index f29bde7172..ec98a4e028 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_pwr.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_pwr.h @@ -175,10 +175,12 @@ extern "C" { */ #define LL_PWR_SRAM1_STOP_NO_RETENTION (0U) /*!< SRAM1 no retention in Stop modes (Stop 0, 1, 2, 3) */ #define LL_PWR_SRAM1_STOP_PAGE1_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 page 1 retention Stop modes (Stop 0, 1, 2, 3) */ +#if defined(PWR_CR2_SRAM1PDS2) #define LL_PWR_SRAM1_STOP_PAGE2_RETENTION PWR_CR2_SRAM1PDS2 /*!< SRAM1 page 2 retention Stop modes (Stop 0, 1, 2, 3) */ #define LL_PWR_SRAM1_STOP_PAGE3_RETENTION PWR_CR2_SRAM1PDS3 /*!< SRAM1 page 3 retention Stop modes (Stop 0, 1, 2, 3) */ #define LL_PWR_SRAM1_STOP_PAGE4_RETENTION PWR_CR2_SRAM1PDS4 /*!< SRAM1 page 4 retention Stop modes (Stop 0, 1, 2, 3) */ #define LL_PWR_SRAM1_STOP_PAGE5_RETENTION PWR_CR2_SRAM1PDS5 /*!< SRAM1 page 5 retention Stop modes (Stop 0, 1, 2, 3) */ +#endif/*PWR_CR2_SRAM1PDS2*/ #if defined(PWR_CR2_SRAM1PDS6) #define LL_PWR_SRAM1_STOP_PAGE6_RETENTION PWR_CR2_SRAM1PDS6 /*!< SRAM1 page 6 retention Stop modes (Stop 0, 1, 2, 3) */ #define LL_PWR_SRAM1_STOP_PAGE7_RETENTION PWR_CR2_SRAM1PDS7 /*!< SRAM1 page 7 retention Stop modes (Stop 0, 1, 2, 3) */ @@ -186,9 +188,11 @@ extern "C" { PWR_CR2_SRAM1PDS4 | PWR_CR2_SRAM1PDS5 | PWR_CR2_SRAM1PDS6 |\ PWR_CR2_SRAM1PDS7) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ -#else +#elif defined(PWR_CR2_SRAM1PDS2) #define LL_PWR_SRAM1_STOP_FULL_RETENTION (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 | PWR_CR2_SRAM1PDS3 |\ PWR_CR2_SRAM1PDS4 | PWR_CR2_SRAM1PDS5) +#else +#define LL_PWR_SRAM1_STOP_FULL_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ #endif /* PWR_CR2_SRAM1PDS6 */ /** @@ -360,9 +364,9 @@ extern "C" { #define LL_PWR_I3CPUCR1_PA7 PWR_I3CPUCR1_PA7_I3CPU /*!< I3C pull-up on PA7 */ #define LL_PWR_I3CPUCR1_PB2 PWR_I3CPUCR1_PB2_I3CPU /*!< I3C pull-up on PB2 */ #define LL_PWR_I3CPUCR1_PB6 PWR_I3CPUCR1_PB6_I3CPU /*!< I3C pull-up on PB6 */ -#if defined(RAMCFG_SRAM3) +#if defined(PWR_I3CPUCR1_PB7_I3CPU) #define LL_PWR_I3CPUCR1_PB7 PWR_I3CPUCR1_PB7_I3CPU /*!< I3C pull-up on PB7 */ -#endif /* defined(RAMCFG_SRAM3) */ +#endif /* defined(PWR_I3CPUCR1_PB7_I3CPU) */ #if defined(PWR_I3CPUCR1_PB8_I3CPU) #define LL_PWR_I3CPUCR1_PB8 PWR_I3CPUCR1_PB8_I3CPU /*!< I3C pull-up on PB8 */ #define LL_PWR_I3CPUCR1_PB9 PWR_I3CPUCR1_PB9_I3CPU /*!< I3C pull-up on PB9 */ @@ -370,19 +374,24 @@ extern "C" { #define LL_PWR_I3CPUCR1_PB10 PWR_I3CPUCR1_PB10_I3CPU /*!< I3C pull-up on PB10 */ #define LL_PWR_I3CPUCR1_PB12 PWR_I3CPUCR1_PB12_I3CPU /*!< I3C pull-up on PB12 */ #define LL_PWR_I3CPUCR1_PB13 PWR_I3CPUCR1_PB13_I3CPU /*!< I3C pull-up on PB13 */ -#if defined(PWR_I3CPUCR1_PB8_I3CPU) +#if defined(PWR_I3CPUCR1_PB14_I3CPU) #define LL_PWR_I3CPUCR1_PB14 PWR_I3CPUCR1_PB14_I3CPU /*!< I3C pull-up on PB14 */ -#endif /* PWR_I3CPUCR1_PB8_I3CPU */ -#if defined(LL_PWR_I3CPUCR1_PB7) +#endif /* PWR_I3CPUCR1_PB14_I3CPU */ +#if defined(RAMCFG_SRAM3) #define LL_PWR_I3CPUCR1_ALL (LL_PWR_I3CPUCR1_PA1 | LL_PWR_I3CPUCR1_PA6 | LL_PWR_I3CPUCR1_PA7 |\ LL_PWR_I3CPUCR1_PB2 | LL_PWR_I3CPUCR1_PB6 | LL_PWR_I3CPUCR1_PB7 |\ LL_PWR_I3CPUCR1_PB8 | LL_PWR_I3CPUCR1_PB9 | LL_PWR_I3CPUCR1_PB10 |\ LL_PWR_I3CPUCR1_PB12 | LL_PWR_I3CPUCR1_PB13 | LL_PWR_I3CPUCR1_PB14) -#elif defined(PWR_I3CPUCR1_PB8_I3CPU) +#elif defined(PWR_I3CPUCR1_PB14_I3CPU) #define LL_PWR_I3CPUCR1_ALL (LL_PWR_I3CPUCR1_PA1 | LL_PWR_I3CPUCR1_PA6 | LL_PWR_I3CPUCR1_PA7 |\ LL_PWR_I3CPUCR1_PB2 | LL_PWR_I3CPUCR1_PB6 | LL_PWR_I3CPUCR1_PB8 |\ LL_PWR_I3CPUCR1_PB9 | LL_PWR_I3CPUCR1_PB10 | LL_PWR_I3CPUCR1_PB12 |\ LL_PWR_I3CPUCR1_PB13 | LL_PWR_I3CPUCR1_PB14) +#elif defined(PWR_I3CPUCR1_PB8_I3CPU) +#define LL_PWR_I3CPUCR1_ALL (LL_PWR_I3CPUCR1_PA1 | LL_PWR_I3CPUCR1_PA6 | LL_PWR_I3CPUCR1_PA7 |\ + LL_PWR_I3CPUCR1_PB2 | LL_PWR_I3CPUCR1_PB6 | LL_PWR_I3CPUCR1_PB7 |\ + LL_PWR_I3CPUCR1_PB8 | LL_PWR_I3CPUCR1_PB9 | LL_PWR_I3CPUCR1_PB10 |\ + LL_PWR_I3CPUCR1_PB12 | LL_PWR_I3CPUCR1_PB13) #else #define LL_PWR_I3CPUCR1_ALL (LL_PWR_I3CPUCR1_PA1 | LL_PWR_I3CPUCR1_PA6 | LL_PWR_I3CPUCR1_PA7 |\ LL_PWR_I3CPUCR1_PB2 | LL_PWR_I3CPUCR1_PB6 | LL_PWR_I3CPUCR1_PB10 |\ @@ -399,9 +408,11 @@ extern "C" { #if defined(PWR_I3CPUCR2_PC0_I3CPU) #define LL_PWR_I3CPUCR2_PC0 PWR_I3CPUCR2_PC0_I3CPU /*!< I3C pull-up on PC0 */ #endif /* defined(PWR_I3CPUCR2_PC0_I3CPU) */ +#if defined(PWR_I3CPUCR2_PC1_I3CPU) #define LL_PWR_I3CPUCR2_PC1 PWR_I3CPUCR2_PC1_I3CPU /*!< I3C pull-up on PC1 */ #define LL_PWR_I3CPUCR2_PD12 PWR_I3CPUCR2_PD12_I3CPU /*!< I3C pull-up on PD12 */ #define LL_PWR_I3CPUCR2_PD13 PWR_I3CPUCR2_PD13_I3CPU /*!< I3C pull-up on PD13 */ +#endif /* defined(PWR_I3CPUCR2_PC1_I3CPU) */ #if defined(PWR_I3CPUCR2_PC0_I3CPU) #define LL_PWR_I3CPUCR2_PG7 PWR_I3CPUCR2_PG7_I3CPU /*!< I3C pull-up on PG7 */ #define LL_PWR_I3CPUCR2_PG8 PWR_I3CPUCR2_PG8_I3CPU /*!< I3C pull-up on PG8 */ @@ -413,8 +424,11 @@ extern "C" { #define LL_PWR_I3CPUCR2_ALL (LL_PWR_I3CPUCR2_PC0 | LL_PWR_I3CPUCR2_PC1 | LL_PWR_I3CPUCR2_PD12 |\ LL_PWR_I3CPUCR2_PD13 | LL_PWR_I3CPUCR2_PG7 | LL_PWR_I3CPUCR2_PG8 |\ LL_PWR_I3CPUCR2_PG13 | LL_PWR_I3CPUCR2_PG14 | LL_PWR_I3CPUCR2_PH3) +#elif defined(PWR_I3CPUCR2_PC1_I3CPU) +#define LL_PWR_I3CPUCR2_ALL (LL_PWR_I3CPUCR2_PC1 | LL_PWR_I3CPUCR2_PD12 | LL_PWR_I3CPUCR2_PD13 |\ + LL_PWR_I3CPUCR2_PH3) #else -#define LL_PWR_I3CPUCR2_ALL (LL_PWR_I3CPUCR2_PC1 | LL_PWR_I3CPUCR2_PD12 | LL_PWR_I3CPUCR2_PH3) +#define LL_PWR_I3CPUCR2_ALL LL_PWR_I3CPUCR2_PH3 #endif /* defined(PWR_I3CPUCR2_PC0_I3CPU) */ /*!< I3C pull-up all for port C-D-G-H */ /** diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_rcc.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_rcc.h index f122c1766e..2bf7221a17 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_rcc.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_rcc.h @@ -2469,30 +2469,30 @@ __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(uint32_t RTCx_clksource) /** * @brief Enable RTC and TAMP clock - * @rmtoll BDCR RTCEN LL_RCC_RTC_ClockEnable + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC * @retval None */ -__STATIC_INLINE void LL_RCC_RTC_ClockEnable(void) +__STATIC_INLINE void LL_RCC_EnableRTC(void) { SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); } /** * @brief Disable RTC and TAMP clock - * @rmtoll BDCR RTCEN LL_RCC_RTC_ClockDisable + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC * @retval None */ -__STATIC_INLINE void LL_RCC_RTC_ClockDisable(void) +__STATIC_INLINE void LL_RCC_DisableRTC(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); } /** * @brief Check if RTC and TAMP clock is enabled or not - * @rmtoll BDCR RTCEN LL_RCC_RTC_IsEnabled + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC * @retval 1 or 0 */ -__STATIC_INLINE uint32_t LL_RCC_RTC_IsEnabled(void) +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) { return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_rng.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_rng.h index 44658bfa7f..3dbf070692 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_rng.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_rng.h @@ -134,6 +134,26 @@ typedef struct * @} */ +/** @defgroup RNG_LL_NSCR_Oscillator_Sources Oscillator Sources Defines + * @{ + */ +#define LL_RNG_OSC_1 RNG_NSCR_EN_OSC1 +#define LL_RNG_OSC_2 RNG_NSCR_EN_OSC2 +#define LL_RNG_OSC_3 RNG_NSCR_EN_OSC3 +/** + * @} + */ + +/** @defgroup RNG_LL_NSCR_Noise_Sources_Ports Noise Sources Ports Defines + * @{ + */ +#define LL_RNG_NOISE_SRC_1 (0x01UL) +#define LL_RNG_NOISE_SRC_2 (0x02UL) +#define LL_RNG_NOISE_SRC_3 (0x04UL) +/** + * @} + */ + /** @defgroup RNG_LL_EC_IT IT Defines * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros * @{ @@ -674,7 +694,10 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) { - WRITE_REG(RNGx->HTCR, HTCFG); +#if defined(RNG_HTCR_NIST_VALUE) + /* For NIST compliance we can fin the recommended value in the application note AN4230 */ +#endif /* defined(RNG_HTCR_NIST_VALUE) */ + WRITE_REG(RNGx->HTCR[0], HTCFG); } /** @@ -685,12 +708,170 @@ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) */ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx) { - return (uint32_t)READ_REG(RNGx->HTCR); + return (uint32_t)READ_REG(RNGx->HTCR[0]); +} + +/** + * @} + */ + +/** @defgroup RNG Additional Health Test Control + * @{ + */ + +/** + * @brief Set RNG Additional Health Test Control + * @rmtoll HTCR HTCFG LL_RNG_SetAdditionalHealthTest + * @param RNGx RNG Instance + * @param htcr_idx Additional health tests registers index can be one f the following values + * @param HTCFG can be values of 32 bits + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetAdditionalHealthTest(RNG_TypeDef *RNGx, uint32_t htcr_idx, uint32_t HTCFG) +{ + WRITE_REG(RNGx->HTCR[htcr_idx], HTCFG); } +/** + * @brief Get RNG Additional Health Test Control + * @rmtoll HTCR HTCFG LL_RNG_GetAdditionalHealthTest + * @param RNGx RNG Instance + * @param htcr_idx Additional health tests registers index + * @retval Return 32-bit RNG Health Test configuration + */ +__STATIC_INLINE uint32_t LL_RNG_GetAdditionalHealthTest(const RNG_TypeDef *RNGx, uint32_t htcr_idx) +{ + return (uint32_t)READ_REG(RNGx->HTCR[htcr_idx]); +} /** * @} */ + + +/** @defgroup RNG_LL_EF_Noise_Test_Control Noise Test Control + * @{ + */ + +/** + * @brief Set RNG Noise Test Control + * @rmtoll NSCR NOISECFG LL_RNG_SetNoiseConfig + * @param RNGx RNG Instance + * @param NOISECFG can be values of 32 bits + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetNoiseConfig(RNG_TypeDef *RNGx, uint32_t NOISECFG) +{ + /* For NIST compliance we can fin the recommended value in the application note AN4230 */ + WRITE_REG(RNGx->NSCR, NOISECFG); +} + +/** + * @brief Get RNG Noise Test Control + * @rmtoll NSCR NOISECFG LL_RNG_GetNoiseConfig + * @param RNGx RNG Instance + * @retval Return 32-bit RNG Noise Test configuration + */ +__STATIC_INLINE uint32_t LL_RNG_GetNoiseConfig(const RNG_TypeDef *RNGx) +{ + return (uint32_t)READ_REG(RNGx->NSCR); +} + +/** + * @} + */ + +/** @defgroup RNG Health Tests Status control + * @{ + */ + +/** + * @brief Get RNG Health Tests Status. + * @rmtoll HTSR htsr_idx LL_RNG_GetHealthTestStatus + * @param RNGx RNG Instance + * @param htsr_idx Health tests registers status index + * @retval Return 32-bit RNG Health Test Status + */ +__STATIC_INLINE uint32_t LL_RNG_GetHealthTestStatus(const RNG_TypeDef *RNGx, uint32_t htsr_idx) +{ + return (uint32_t)READ_REG(RNGx->HTSR[htsr_idx]); +} + +/** + * @} + */ + +/** @defgroup RNG noise source mask Control + * @{ + */ + +/** + * @brief Set RNG noise source mask. + * @rmtoll NSMR htsr_idx LL_RNG_GetNoiseSourceMask + * @param RNGx RNG Instance + * @param nsmr can be values of 32 bits + */ +__STATIC_INLINE void LL_RNG_SetNoiseSourceMask(RNG_TypeDef *RNGx, uint32_t nsmr) +{ + WRITE_REG(RNGx->NSMR, nsmr); +} + +/** + * @brief Get RNG noise source mask. + * @rmtoll NSMR htsr_idx LL_RNG_GetNoiseSourceMask + * @param RNGx RNG Instance + * @retval Return 32-bit RNG Noise Source Mask + */ +__STATIC_INLINE uint32_t LL_RNG_GetNoiseSourceMask(const RNG_TypeDef *RNGx) +{ + return READ_REG(RNGx->NSMR); +} + +/** + * @} + */ + +/** @defgroup RNG noise source Control + * @{ + */ + +/** + * @brief Set RNG Noise Source Configuration. + * @rmtoll + * NSCR NSCR LL_RNG_GetOscNoiseSrc + * @param RNGx RNG Instance + * @param osc be one of the following values: + * @arg @ref LL_RNG_OSC_1 + * @arg @ref LL_RNG_OSC_2 + * @arg @ref LL_RNG_OSC_3 + * @retval can be one of the following values: + * @arg @ref LL_RNG_NOISE_SRC_1 + * @arg @ref LL_RNG_NOISE_SRC_2 + * @arg @ref LL_RNG_NOISE_SRC_3 + */ +__STATIC_INLINE void LL_RNG_SetOscNoiseSrc(RNG_TypeDef *RNGx, uint32_t osc) +{ + WRITE_REG(RNGx->NSCR, osc); +} + +/** + * @brief Get RNG Noise Source Configuration. + * @rmtoll + * NSCR NSCR LL_RNG_GetOscNoiseSrc + * @param RNGx RNG Instance + * @param osc be one of the following values: + * @arg @ref LL_RNG_OSC_1 + * @arg @ref LL_RNG_OSC_2 + * @arg @ref LL_RNG_OSC_3 + * @retval can be one of the following values: + * @arg @ref LL_RNG_NOISE_SRC_1 + * @arg @ref LL_RNG_NOISE_SRC_2 + * @arg @ref LL_RNG_NOISE_SRC_3 + */ +__STATIC_INLINE uint32_t LL_RNG_GetOscNoiseSrc(const RNG_TypeDef *RNGx, uint32_t osc) +{ + return (READ_BIT(RNGx->NSCR, osc) >> POSITION_VAL(osc)); +} + #if defined(USE_FULL_LL_DRIVER) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_tim.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_tim.h index a2fec17f15..a05c67e083 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_tim.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_tim.h @@ -1063,6 +1063,7 @@ typedef struct #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM_AF1_ETRSEL_3 /*!< TIM2_ETR is connected to TIM3 ETR */ #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM4 ETR */ #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LSE */ +#define LL_TIM_TIM2_ETRSOURCE_USBFS_SOF (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to USB_SOF */ /** * @} */ @@ -1092,6 +1093,7 @@ typedef struct #define LL_TIM_TIM4_ETRSOURCE_COMP2 TIM_AF1_ETRSEL_1 /*!< TIM4_ETR is connected to COMP2 OUT */ #define LL_TIM_TIM4_ETRSOURCE_MSIK (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to MSIK */ #define LL_TIM_TIM4_ETRSOURCE_HSI TIM_AF1_ETRSEL_2 /*!< TIM4_ETR is connected to HSI */ +#define LL_TIM_TIM4_ETRSOURCE_MSIS (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to MSIS */ #define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR TIM_AF1_ETRSEL_3 /*!< TIM4_ETR is connected to TIM3 ETR */ /** * @} @@ -3956,6 +3958,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE + * @arg @ref LL_TIM_TIM2_ETRSOURCE_USBFS_SOF * * TIM3: any combination of ETR_RMP where * @@ -3977,6 +3980,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2 * @arg @ref LL_TIM_TIM4_ETRSOURCE_MSIK * @arg @ref LL_TIM_TIM4_ETRSOURCE_HSI + * @arg @ref LL_TIM_TIM4_ETRSOURCE_MSIS * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR * * TIM8: any combination of ETR_RMP where (**) diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_usb.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_usb.h index e92b9e4a1b..c36622e2ee 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_usb.h +++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_ll_usb.h @@ -696,21 +696,21 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; #define USB_DRD_SET_CHEP_CNT_RX_REG(pdwReg, wCount) \ do { \ uint32_t wNBlocks; \ - \ - (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ + uint32_t wRegVal = (uint32_t)(pdwReg) & ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ \ if ((wCount) == 0U) \ { \ - (pdwReg) |= USB_CNTRX_BLSIZE; \ + wRegVal |= USB_CNTRX_BLSIZE; \ } \ else if ((wCount) <= 62U) \ { \ - USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + USB_DRD_CALC_BLK2(wRegVal, (wCount), wNBlocks); \ } \ else \ { \ - USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + USB_DRD_CALC_BLK32(wRegVal, (wCount), wNBlocks); \ } \ + (pdwReg) = wRegVal; \ } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ @@ -892,9 +892,10 @@ HAL_StatusTypeDef USB_HC_Activate(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uin #endif /* defined (HAL_HCD_MODULE_ENABLED) */ uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx); -uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx); HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx); +uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx); + HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx); diff --git a/system/Drivers/STM32U3xx_HAL_Driver/LICENSE.md b/system/Drivers/STM32U3xx_HAL_Driver/LICENSE.md index eb0b33cda6..85878f41ac 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/LICENSE.md +++ b/system/Drivers/STM32U3xx_HAL_Driver/LICENSE.md @@ -24,4 +24,4 @@ ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/system/Drivers/STM32U3xx_HAL_Driver/README.md b/system/Drivers/STM32U3xx_HAL_Driver/README.md index 75940878e2..81c88c29de 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/README.md +++ b/system/Drivers/STM32U3xx_HAL_Driver/README.md @@ -1,6 +1,6 @@ # STM32CubeU3 HAL Driver MCU Component -![tag](https://img.shields.io/badge/tag-v1.3.0-brightgreen.svg) +![tag](https://img.shields.io/badge/tag-v1.4.0-brightgreen.svg) ## Overview @@ -36,4 +36,4 @@ The full **STM32CubeU3** MCU package is available [here](https://github.com/STMi ## Troubleshooting -Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. \ No newline at end of file diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32U3xx_HAL_Driver/Release_Notes.html index 72d61b5026..994b73d405 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32U3xx_HAL_Driver/Release_Notes.html @@ -40,17 +40,135 @@

Purpose

Update History

- +

Official release

    +
  • Official Release of STM32CubeU3 HAL/LL Drivers supporting STM32U335xx/STM32U345xx/STM32U356xx/STM32U366xx/STM32U375xx/STM32U385xx/STM32U3B5xx/STM32U3C5xx devices
    • +
+

Contents

+

HAL Drivers updates

+
    +
  • HAL ADC driver +
      +
    • Fix ADC Peripheral Definitions for STM32U3-256K
      • +
    • +
  • HAL CCB driver +
      +
    • Update related to recover from seed Error sequence after RNG v4_4 SW workaround
      • +
    • Update related to the last RNG specification HTCR–> HTCR[0]
      • +
    • Update related to a typo in the call register(CR->SR)
      • +
    • Add CCB handle to RNG resilience recover seed error call
      • +
    • Include ll_rng.h in ccb driver
      • +
    • +
  • HAL_CRYP driver +
      +
    • SA0076 fixed
      • +
    • Update related to tickstart variable that should be not flagged by SAES
      • +
    • Update related to recover from seed Error sequence after RNG v4_4 SW workaround
      • +
    • Fix Failed Decryption with AES GCM Cipher TAG issue
      • +
    • Update related to TK: Failed Decryption with AES GCM Cipher TAG issue
      • +
    • McuAstyle warning fixed
      • +
    • Coverity issue INTEGER_OVERFLOW fixed
      • +
    • Update related to non availability of SAES in U3-256k
      • +
    • Update related to a typo in the call register(CR->SR)
      • +
    • +
  • HAL GPIO driver +
      +
    • fix for Build errors: identifier “GPIO_AF6_SPI2” is undefined
      • +
    • Remove unavailable GPIO_AF1_USART3 alternate function
      • +
    • Fix MCUAstyle errors
      • +
    • +
  • HAL GTZC driver +
      +
    • fix GTZC_PERIPH_ADC12 macro for STM32U3-256K
      • +
    • +
  • HAL IRDA driver +
      +
    • Remove UART5 support
      • +
    • +
  • HAL LCD driver +
      +
    • Fix some McuStyle errors
      • +
    • +
  • HAL PWR driver +
      +
    • Update SRAM1 pages for STM32U3-256K
      • +
    • +
  • HAL RCC driver +
      +
    • Add extra MCO on PB8 for STM32U3 512K
      • +
    • Fix incorrect macros and logic for MCO in RCC for STM32U3 512K
      • +
    • Fix MCUAstyle errors
      • +
    • +
  • HAL RNG driver +
      +
    • Update HAL_RNGEx_GetConfig to get NoiseSource (NSCR)
      • +
    • Update recover from seed Error sequence after the requested RNG v4_4 SW workaround
      • +
    • Add to error state check at the beginning of seed recover sequence
      • +
    • Update related to a typo in the call register(CR->SR)
      • +
    • Update the comment of NistCompliance field (RNG_ConfigTypeDef)
      • +
    • Fix MISRAC2012-Rule-13.5 warning
      • +
    • +
  • HAL SMARTCARD driver +
      +
    • Fixed for USART2 support for STM32U3-2M
      • +
    • +
  • HAL TIM driver +
      +
    • Added the external timer trigger source for TIM2 and TIM4
      • +
    • +
  • HAL UART driver +
      +
    • USART2 is undefined in the context of U3 derivatives
      • +
    • Add UART5 and USART1 AF support for STM32U3 512K
      • +
    • +
  • HAL USART driver +
      +
    • USART2 is undefined in the context of U3 derivatives
      • +
    • +
  • HAL USB driver +
      +
    • Fix to avoid out of band possible read
      • +
    • Fix to update RX count reg in single operation
      • +
    • Add get frame number support
      • +
    • +
+

LL Drivers updates

+
    +
  • LL ADC driver +
      +
    • Fixing conflicting definition of __LL_ADC_COMMON_INSTANCE
      • +
    • +
  • LL RCC driver +
      +
    • Update RCC LL functions for RTC similar to other STM32 products
      • +
    • +
+

Backward compatibility

+
    +
  • Not applicable
    • +
+

Known Limitations

+
    +
  • Not applicable
    • +
+


+

+
+
+
+ +
+

Official release

+
  • Official Release of STM32CubeU3 HAL/LL Drivers supporting STM32U375xx/STM32U385xx/STM32U3B5xx/STM32U3C5xx devices
    • First delivery of HAL HSP driver
-

Contents

-

HAL Drivers updates

+

Contents

+

HAL Drivers updates

  • HAL CCB driver
      @@ -193,7 +311,7 @@

      HAL Drivers updates

    • Add IsMemoryMapped() API
-

LL Drivers updates

+

LL Drivers updates

  • LL COMP driver
      @@ -247,11 +365,11 @@

      LL Drivers updates

    • Fix Misra-C:2012 warnings Rule-12.2
-

Backward compatibility

+

Backward compatibility

  • Not applicable
-

Known Limitations

+

Known Limitations

  • Not applicable
@@ -266,8 +384,8 @@

Maintenance release

  • Maintenance Release of STM32CubeU3 HAL/LL Drivers supporting STM32U375xx/STM32U385xx devices
-

Contents

-

HAL Drivers updates

+

Contents

+

HAL Drivers updates

  • HAL FLASH driver
      @@ -293,7 +411,7 @@

      HAL Drivers updates

    • Comments enhancement
-

LL Drivers updates

+

LL Drivers updates

  • LL PWR driver
      @@ -304,11 +422,11 @@

      LL Drivers updates

    • Comments enhancement
-

Backward compatibility

+

Backward compatibility

  • Not applicable
-

Known Limitations

+

Known Limitations

  • Not applicable
@@ -323,8 +441,8 @@

Maintenance release

  • Maintenance Release of STM32CubeU3 HAL/LL Drivers supporting STM32U375xx/STM32U385xx devices
-

Contents

-

HAL Drivers updates

+

Contents

+

HAL Drivers updates

  • HAL CCB driver
      @@ -380,7 +498,7 @@

      HAL Drivers updates

    • Check BUSY flag instead of TC flag in indirect mode to be sure that command is well completed (FIFO flush)
-

LL Drivers updates

+

LL Drivers updates

  • LL LPUART driver
      @@ -391,11 +509,11 @@

      LL Drivers updates

    • Solve Coverity out-of-bound memory access warning in use of USART_PRESCALER_TAB array
-

Backward compatibility

+

Backward compatibility

  • Not applicable
-

Known Limitations

+

Known Limitations

  • Not applicable
@@ -410,7 +528,7 @@

First Release

  • First Official Release of STM32CubeU3 HAL/LL Drivers supporting STM32U375xx/STM32U385xx devices
-

Contents

+

Contents

  • STM32CubeU3 HAL/LL Drivers supporting STM32U375xx/STM32U385xx devices :
      @@ -423,11 +541,11 @@

      Supported Devices and boards

    • STM32U375xx/STM32U385xx devices
    • NUCLEO-U385RG-Q (Rev.E) board
    -

    Backward compatibility

    +

    Backward compatibility

    • Not applicable
    -

    Known Limitations

    +

    Known Limitations

    • None
    diff --git a/system/Drivers/STM32U3xx_HAL_Driver/SW_Security_Level.md b/system/Drivers/STM32U3xx_HAL_Driver/SW_Security_Level.md new file mode 100644 index 0000000000..de7ed807d2 --- /dev/null +++ b/system/Drivers/STM32U3xx_HAL_Driver/SW_Security_Level.md @@ -0,0 +1,47 @@ + + +## Copyright (c) 2026 STMicroelectronics. +## All rights reserved +
    +
    + +## SW Security Classification + +[STM32Trust software security policies](https://wiki.st.com/stm32mcu/wiki/Security:STM32Trust_software_security_policies) define four levels of SW Security classification, each level defines a set of security policies for the applicable SW. + +| SW | SW Security Level +|:--------- |:-------| +| **STM32U3xx HAL Driver** | Medium| + + +
    + +## IMPORTANT SECURITY NOTICE + +The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that: + +- ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified. + +- Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product. + +- Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies. + +- While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application. + +- All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. + +AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise. + +
    + +## IMPORTANT NOTICE - READ CAREFULLY + +STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgment. + +Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers' products. +No license, express or implied, to any intellectual property right is granted by ST herein. +Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. +ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. +Information in this document supersedes and replaces information previously supplied in any prior versions of this document. + +Copyright (c) 2026 STMicroelectronics - All rights reserved \ No newline at end of file diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_adc.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_adc.c index 28319fe8b8..e1627fc706 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_adc.c +++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_adc.c @@ -1457,8 +1457,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti } } #else - /* Check ADC DMA mode */ - if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE) + if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0) != 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_ccb.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_ccb.c index 2e2ce891ac..3dfd877c8a 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_ccb.c +++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_ccb.c @@ -93,7 +93,9 @@ #ifndef HAL_CCB_TIMEOUT_DEFAULT_VALUE #define HAL_CCB_TIMEOUT_DEFAULT_VALUE 0xFFFFU /* CCB Timeout.*/ #endif /*HAL_CCB_TIMEOUT_DEFAULT_VALUE */ - +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +#define CCB_RNG_TIMEOUT_VALUE 0x00000002U +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ /** * @} */ @@ -291,6 +293,10 @@ static HAL_StatusTypeDef PKA_ECDSAVerif(CCB_HandleTypeDef *hccb, CCB_ECDSACurveP CCB_ECDSASignTypeDef *pSignature); static uint32_t PKA_ECDSAVerif_Result(CCB_HandleTypeDef *hccb); static void CCB_PKA_RAMReset(CCB_HandleTypeDef *hccb); +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +HAL_StatusTypeDef CCB_RNG_ResilientRecoverSeedError(CCB_HandleTypeDef *hccb); +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ + /** @defgroup CCB_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @@ -847,14 +853,14 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_GenerateWrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_WrappingKeyTypeDef *pWrappingKey, CCB_ECDSAKeyBlobTypeDef *pWrappedPrivateKeyBlob) { - uint8_t count; + uint32_t count; uint32_t key_size; uint32_t iv_temp[4] = {0}; uint32_t tag_temp[4] = {0}; uint32_t wrapped_key_temp[80U] = {0}; #if defined (HW_SANITY_CHECK_SUPPORT) - uint32_t tickstart = HAL_GetTick(); + uint32_t tickstart; __IO uint16_t f_count; uint16_t random1 = 0; uint16_t random2 = 0; @@ -1117,12 +1123,22 @@ HAL_StatusTypeDef HAL_CCB_ECDSA_Sign(CCB_HandleTypeDef *hccb, CCB_ECDSACurvePara /* Initialize SAES */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* Disable the SAES peripheral */ - HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + /* Disable the SAES peripheral */ + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; - /* Set state and return error */ - hccb->State = HAL_CCB_STATE_ERROR; - return HAL_ERROR; + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Update the state */ @@ -1644,8 +1660,8 @@ HAL_StatusTypeDef HAL_CCB_RSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_RSAPar { uint8_t exp_base[520U] = {0}; uint32_t count; - __IO uint16_t f_count; #if defined(SW_SANITY_CHECK_SUPPORT) + __IO uint16_t f_count; uint16_t random0 = 0; #endif /* GENERATOR_SW_SANITY_CHECK_AVAILABLE_ALL_DEVICES */ uint32_t modular_exp_ref[520U] = {0}; @@ -2298,7 +2314,17 @@ static HAL_StatusTypeDef Protect_PKA_Init(CCB_HandleTypeDef *hccb, uint32_t Oper /* Wait the INITOK flag Setting */ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_INITOK, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - return HAL_ERROR; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Reset any pending flag */ @@ -2361,7 +2387,17 @@ static HAL_StatusTypeDef Unprotected_PKA_Init(CCB_HandleTypeDef *hccb) /* Wait the INITOK flag Setting */ if (Unprotect_PKA_WaitFLAG(hccb, PKA_SR_INITOK, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - return HAL_ERROR; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Reset any pending flag */ @@ -2391,7 +2427,7 @@ static HAL_StatusTypeDef CCB_RNG_Init(CCB_HandleTypeDef *hccb) #endif /* defined(RNG_CR_NIST_VALUE) */ #if defined(RNG_HTCR_NIST_VALUE) /* Recommended value for NIST compliance, refer to application note AN4230 */ - WRITE_REG(HAL_CCB_GET_RNG_INSTANCE(hccb)->HTCR, RNG_HTCR_NIST_VALUE); + WRITE_REG(HAL_CCB_GET_RNG_INSTANCE(hccb)->HTCR[0], RNG_HTCR_NIST_VALUE); #endif /* defined(RNG_HTCR_NIST_VALUE) */ #if defined(RNG_NSCR_NIST_VALUE) WRITE_REG(HAL_CCB_GET_RNG_INSTANCE(hccb)->NSCR, RNG_NSCR_NIST_VALUE); @@ -2420,17 +2456,30 @@ static HAL_StatusTypeDef CCB_RNG_Init(CCB_HandleTypeDef *hccb) /* Enable the RNG Peripheral */ HAL_CCB_GET_RNG_INSTANCE(hccb)->CR |= RNG_CR_RNGEN; - /* verify that no seed error */ - if ((HAL_CCB_GET_RNG_INSTANCE(hccb)->SR & (RNG_SR_SEIS)) != (uint32_t)RESET) - { - /* Set state and return error */ - return HAL_ERROR; - } + tickstart = HAL_GetTick(); /* Check if data register contains valid random data */ - if (CCB_RNG_Wait_SET_FLAG(hccb, RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + while (HAL_IS_BIT_CLR(HAL_CCB_GET_RNG_INSTANCE(hccb)->SR, RNG_SR_DRDY)) { - return HAL_ERROR; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ + + if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE) + { + HAL_CCB_GET_RNG_INSTANCE(hccb)->CR &= ~RNG_CR_RNGEN; + + /* Set state and return error */ + return HAL_ERROR; + } } /* Return function status */ @@ -2947,12 +2996,22 @@ static HAL_StatusTypeDef CCB_WrapSymmetricKey(CCB_HandleTypeDef *hccb, const uin /* Initialize SAES */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* Disable the SAES peripheral clock */ - HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + /* Disable the SAES peripheral */ + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; - /* Set state and return error */ - hccb->State = HAL_CCB_STATE_ERROR; - return HAL_ERROR; + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Update the state */ @@ -3390,12 +3449,22 @@ static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB /* Initialize SAES */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* Disable the SAES peripheral clock */ - HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + /* Disable the SAES peripheral */ + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; - /* Set state and return error */ - hccb->State = HAL_CCB_STATE_ERROR; - return HAL_ERROR; + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Update the state */ @@ -3581,8 +3650,17 @@ static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB /* Wait for Galois Filter End of Computation */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* return error */ - return HAL_ERROR; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } if ((operand_size % 4UL) != 0UL) { @@ -3771,12 +3849,22 @@ static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb, /* Initialize SAES */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* Disable the SAES peripheral clock */ - HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + /* Disable the SAES peripheral */ + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; - /* Set state and return error */ - hccb->State = HAL_CCB_STATE_ERROR; - return HAL_ERROR; + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Update the state */ @@ -3950,8 +4038,17 @@ static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb, /* Wait for Galois Filter End of Computation */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* return error */ - return HAL_ERROR; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } if ((operand_size % 4UL) != 0UL) @@ -4196,12 +4293,22 @@ static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E /* Initialize SAES */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* Disable the SAES peripheral */ - HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + /* Disable the SAES peripheral */ + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; - /* Set state and return error */ - hccb->State = HAL_CCB_STATE_ERROR; - return HAL_ERROR; + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Update the state */ @@ -4583,12 +4690,22 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS /* Initialize SAES */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* Disable the SAES peripheral clock */ - HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + /* Disable the SAES peripheral */ + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; - /* Set state, error code and return error */ - hccb->State = HAL_CCB_STATE_ERROR; - return HAL_ERROR; + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Update the state */ @@ -4770,8 +4887,17 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS /* Wait for Galois Filter End of Computation */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* return error */ - return HAL_ERROR; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } if ((operand_size % 4UL) != 0UL) @@ -4827,8 +4953,17 @@ static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RS /* Wait for Galois Filter End of Computation */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* return error */ - return HAL_ERROR; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } if ((operand_size % 4UL) != 0UL) @@ -5033,12 +5168,22 @@ static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_ /* Initialize SAES */ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - /* Disable the SAES peripheral */ - HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CCB_RNG_ResilientRecoverSeedError(hccb) != HAL_OK) + { + /* Disable the SAES peripheral */ + HAL_CCB_GET_SAES_INSTANCE(hccb)->CR &= ~AES_CR_EN; - /* Set state and return error */ - hccb->State = HAL_CCB_STATE_ERROR; - return HAL_ERROR; + /* Set state and return error */ + hccb->State = HAL_CCB_STATE_ERROR; + return HAL_ERROR; + } + } +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ } /* Update the state */ @@ -5544,7 +5689,7 @@ static HAL_StatusTypeDef PKA_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E uint32_t tickstart; uint32_t timeout = HAL_CCB_TIMEOUT_DEFAULT_VALUE; - /*********************************************************************************** Set input parameter in PKA RAM */ + /********************************************************************************** Set input parameter in PKA RAM */ /* Get the prime order n length */ HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS]\ = GetOptBitSize_u8(pCurveParam->primeOrderSizeByte, *(pCurveParam->pPrimeOrder)); @@ -5599,7 +5744,7 @@ static HAL_StatusTypeDef PKA_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_E RAM_PARAM_END(HAL_CCB_GET_PKA_INSTANCE(hccb)->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((pCurveParam->modulusSizeByte + 3UL) / 4UL)); - /********************************************************************************************** Start the operation */ + /******************************************************************************************** Start the operation */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -5876,6 +6021,188 @@ static void CCB_PKA_RAMReset(CCB_HandleTypeDef *hccb) } } +#if (defined(RNG_HTSR0_RPERRX) || defined(RNG_HTSR1_ADERRX)) +/** + * @brief RNG sequence to resilient recover from a seed error + * @retval HAL status + */ +HAL_StatusTypeDef CCB_RNG_ResilientRecoverSeedError(CCB_HandleTypeDef *hccb) +{ + uint32_t timeout; + uint32_t htsr_temp = 0U; + uint32_t htsr_previous_temp = 0U; + uint32_t htsr_count = 0U; + uint32_t nsmr_temp = 0U; + uint32_t tickstart1 = 0U; + uint32_t tickstart2 = 0U; + uint32_t tickstart3 = 0U; + uint32_t oscillators_count = 0U; + uint32_t config_b_fewer_than_6_osc_count = 0U; + uint8_t count = 0U; + + /* timeout here is an emperic value */ + timeout = (1UL + ((1UL << (READ_BIT(HAL_CCB_GET_RNG_INSTANCE(hccb)->CR, RNG_CR_CLKDIV) >> 16UL)) + * CCB_RNG_TIMEOUT_VALUE / 8UL)); + LL_RNG_Enable(HAL_CCB_GET_RNG_INSTANCE(hccb)); + + tickstart1 = HAL_GetTick(); + + /* Check if seed error current status indicates no error and auto-reset succeeded */ + if (LL_RNG_IsActiveFlag_SECS(HAL_CCB_GET_RNG_INSTANCE(hccb)) == 0U) + { + /* Clear SEIS flag when automatic reset is activated */ + LL_RNG_ClearFlag_SEIS(HAL_CCB_GET_RNG_INSTANCE(hccb)); + } + + else /* Sequence to fully recover from a seed error*/ + { + if (LL_RNG_IsConfigLocked(HAL_CCB_GET_RNG_INSTANCE(hccb)) == 0U) + { + do + { + if (LL_RNG_IsActiveFlag_SECS(HAL_CCB_GET_RNG_INSTANCE(hccb)) == 0U) + { + break; + } + /* Read oscillator status registers combined */ + htsr_temp = LL_RNG_GetHealthTestStatus(HAL_CCB_GET_RNG_INSTANCE(hccb), 0U); + htsr_temp |= LL_RNG_GetHealthTestStatus(HAL_CCB_GET_RNG_INSTANCE(hccb), 1U); + if (htsr_temp > 0U) + { + /* If any oscillator status bits overlap with previous status, increment counter */ + if ((htsr_temp & htsr_previous_temp) != 0U) + { + htsr_count++; + } + + if (htsr_count > 3U) + { + /* if the same repetitive or adaptative error is detected 3 times */ + nsmr_temp = LL_RNG_GetNoiseSourceMask(HAL_CCB_GET_RNG_INSTANCE(hccb)); + + /* deactivate the same osc in each triple oscillator (Mask oscillators with the seed error by + clearing bits shifted right by 1) */ + nsmr_temp = nsmr_temp & ~(htsr_temp >> 1U); + + /* Count the number of active oscillators in nsmr */ + oscillators_count = 0U; + for (count = 0U; count < 9U; count++) + { + if (((nsmr_temp >> count) & 0x1U) != 0U) + { + /* increment count1 for each 1 in nsmr */ + oscillators_count++; + } + } + + if (oscillators_count < 6U) + { + /* If fewer than 6 oscillators remain active, unmask all oscillators --> Reset masking */ + nsmr_temp = LL_RNG_GetOscNoiseSrc(HAL_CCB_GET_RNG_INSTANCE(hccb), + LL_RNG_NOISE_SRC_1 | LL_RNG_NOISE_SRC_2 | LL_RNG_NOISE_SRC_3); + htsr_previous_temp = 0; + htsr_count = 0U; + if ((HAL_CCB_GET_RNG_INSTANCE(hccb)->CR & RNG_CR_CLKDIV_Msk) < + ((uint32_t)RNG_CAND_NIST_CR_VALUE & RNG_CR_CLKDIV_Msk)) + { + config_b_fewer_than_6_osc_count++; + } + } + + if (config_b_fewer_than_6_osc_count > 2U) + { + /* Reset RNG condition */ + WRITE_REG(HAL_CCB_GET_RNG_INSTANCE(hccb)->CR, (RNG_CR_CONDRST_Msk | (uint32_t)RNG_CAND_NIST_CR_VALUE)); + + /* Update mask register with new oscillator mask */ + LL_RNG_SetNoiseSourceMask(HAL_CCB_GET_RNG_INSTANCE(hccb), nsmr_temp); + + /* Clear condition reset bit to resume operation */ + LL_RNG_DisableCondReset(HAL_CCB_GET_RNG_INSTANCE(hccb)); + } + + else + { + /* Reset RNG condition */ + WRITE_REG(HAL_CCB_GET_RNG_INSTANCE(hccb)->CR, + (HAL_CCB_GET_RNG_INSTANCE(hccb)->CR & ~RNG_CR_RNGEN_Msk) | RNG_CR_CONDRST_Msk); + + /* Update mask register with new oscillator mask */ + LL_RNG_SetNoiseSourceMask(HAL_CCB_GET_RNG_INSTANCE(hccb), nsmr_temp); + + /* Clear condition reset bit to resume operation */ + LL_RNG_DisableCondReset(HAL_CCB_GET_RNG_INSTANCE(hccb)); + } + } + + else + { + /* Briefly toggle conditional reset to recover RNG */ + WRITE_REG(HAL_CCB_GET_RNG_INSTANCE(hccb)->CR, + (HAL_CCB_GET_RNG_INSTANCE(hccb)->CR & ~RNG_CR_RNGEN_Msk) | RNG_CR_CONDRST_Msk); + + /* unmask all oscillators to find another working condition */ + LL_RNG_SetNoiseSourceMask(HAL_CCB_GET_RNG_INSTANCE(hccb), + LL_RNG_GetOscNoiseSrc(RNG, LL_RNG_OSC_1 | LL_RNG_OSC_2 | LL_RNG_OSC_3)); + LL_RNG_DisableCondReset(HAL_CCB_GET_RNG_INSTANCE(hccb)); + } + + /* Wait until RNG is not busy */ + tickstart2 = HAL_GetTick(); + do + { + if ((HAL_GetTick() - tickstart2) > CCB_RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + LL_RNG_Disable(HAL_CCB_GET_RNG_INSTANCE(hccb)); + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(HAL_CCB_GET_RNG_INSTANCE(hccb)->SR, RNG_SR_BUSY)); + + /* No timeout --> Enable RNG */ + LL_RNG_Enable(HAL_CCB_GET_RNG_INSTANCE(hccb)); + tickstart3 = HAL_GetTick(); + do + { + if (LL_RNG_IsActiveFlag_DRDY(HAL_CCB_GET_RNG_INSTANCE(hccb)) != 0UL) + { + break; + } + if ((HAL_GetTick() - tickstart3) > timeout) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_RNG_IsActiveFlag_DRDY(HAL_CCB_GET_RNG_INSTANCE(hccb)) == 0UL) + { + if (LL_RNG_IsActiveFlag_SECS(HAL_CCB_GET_RNG_INSTANCE(hccb)) == 0UL) + { + LL_RNG_Disable(HAL_CCB_GET_RNG_INSTANCE(hccb)); + return HAL_ERROR; + } + } + } + } while (LL_RNG_IsActiveFlag_SECS(HAL_CCB_GET_RNG_INSTANCE(hccb)) == 0UL); + + /* Accumulate seed error status bits */ + htsr_previous_temp = htsr_previous_temp | htsr_temp; + } + } while ((HAL_GetTick() - tickstart1) <= timeout); + } + } + + /*Check if seed error current status (SECS)is set */ + if (LL_RNG_IsActiveFlag_SECS(HAL_CCB_GET_RNG_INSTANCE(hccb)) != 0U) + { + return HAL_ERROR; + } + + return HAL_OK; +} +#endif /* RNG_HTSR0_RPERRX || RNG_HTSR1_ADERRX */ + +/** + * @} + */ + /** * @} */ diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_cryp.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_cryp.c index 7726b5dd96..f23d47cf60 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_cryp.c +++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_cryp.c @@ -306,6 +306,7 @@ * @{ */ #define CRYP_GENERAL_TIMEOUT 82U +#define CRYP_RNG_TIMEOUT_VALUE 2U #define CRYP_TIMEOUT_KEYPREPARATION 82U /*!< The latency of key preparation operation is 82 clock cycles.*/ #define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /*!< The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/ @@ -383,6 +384,7 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static void CRYP_CopyPartialOutputWord(uint32_t *pOutputWord, uint32_t word, uint32_t dataType, uint32_t validBytes); #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output); static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input); @@ -392,6 +394,50 @@ static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Ou static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input, uint32_t KeySize); static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ +HAL_StatusTypeDef CRYP_RNG_ResilientRecoverSeedError(void); + +static void CRYP_CopyPartialOutputWord(uint32_t *pOutputWord, uint32_t word, uint32_t dataType, uint32_t validBytes) +{ + uint8_t *pDst = (uint8_t *)pOutputWord; + uint8_t *pSrc = (uint8_t *)&word; + uint32_t dstIndex = 0U; + uint32_t index; + uint32_t maskValue; + /* DataType-dependent byte maps used to keep only valid bytes from the last partial CCM word. */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; + + if (validBytes >= 4U) + { + *pOutputWord = word; + return; + } + + /* Select bytes that are valid for the active DataType, then compact them at output start. */ + maskValue = mask[(dataType * 2U) + validBytes]; + + for (index = 0U; index < 4U; index++) + { + if ((maskValue & ((uint32_t)0xFFU << (index * 8U))) != 0U) + { + pDst[dstIndex] = pSrc[index]; + dstIndex++; + if (dstIndex == validBytes) + { + break; + } + } + } + + for (index = dstIndex; index < 4U; index++) + { + /* Zero-fill trailing bytes to keep deterministic output for non-aligned payload sizes. */ + pDst[index] = 0U; + } +} /** @@ -485,6 +531,12 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ +#if !defined(SAES) + /* Set the key size, data type and Algorithm */ + cr_value = (uint32_t)(hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + /* Set the key size, data type, algorithm and mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, cr_value); +#else if (hcryp->Instance == AES) { /* Set the key size, data type and Algorithm */ @@ -494,6 +546,18 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } else { + /*Check if there is an RNG seed error */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + /* Attempt to recover from the seed error */ + if (CRYP_RNG_ResilientRecoverSeedError() != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear Rng error interrupt flag */ + SET_BIT(hcryp->Instance->ICR, AES_ICR_RNGEIF); + } /* SAES is initializing, fetching random number from the RNG */ tickstart = HAL_GetTick(); while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)) @@ -528,6 +592,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | AES_CR_KEYSEL | AES_CR_KEYPROT, cr_value); } +#endif /* !SAES */ /* Reset Error Code field */ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE; @@ -634,6 +699,18 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit; hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; +#if !defined(SAES) + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Set the key size, data type, AlgoMode and operating mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); +#else if (hcryp->Instance == AES) { /* Check the busy flag before writing CR register */ @@ -681,6 +758,7 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD /* Set to 0 the number of non-valid bytes using NPBLB field of CR register*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); } +#endif /* ! SAES*/ /* Clear error flags */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); __HAL_UNLOCK(hcryp); @@ -1402,6 +1480,17 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, hcryp->Size = Size; } +#if !defined(SAES) + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Set the operating mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); +#else if (hcryp->Instance == AES) { /* Check the busy flag before writing CR register */ @@ -1426,6 +1515,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, /* Set the operating mode and normal key selection */ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_ENCRYPT | CRYP_KEYMODE_NORMAL); } +#endif /* !SAES */ /* Algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; @@ -1806,7 +1896,9 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput) { HAL_StatusTypeDef status; +#if defined(SAES) uint32_t count; +#endif /* SAES */ uint32_t algo; uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ #ifdef USE_FULL_ASSERT @@ -1874,6 +1966,9 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp if ((dokeyivconfig == 1U) && (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)) { +#if !defined(SAES) + CRYP_SetKey(hcryp, hcryp->Init.KeySize); +#else if (hcryp->Instance == AES) { /* Set the Key */ @@ -1912,6 +2007,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp } } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID)); } +#endif /* SAES */ /* Set the Initialization Vector */ if (hcryp->Init.Algorithm != CRYP_AES_ECB) { @@ -2236,7 +2332,9 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti uint16_t incount; /* Temporary CrypInCount Value */ uint16_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ +#if defined(SAES) uint32_t tickstart; +#endif /* SEAS */ if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE)) { @@ -2260,6 +2358,9 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || \ (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ALWAYS)) { +#if !defined(SAES) + CRYP_SetKey(hcryp, hcryp->Init.KeySize); +#else if (hcryp->Instance == AES) { /* Set the Key */ @@ -2302,6 +2403,7 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti } } } +#endif /* SAES */ if (hcryp->Init.Algorithm != CRYP_AES_ECB) { /* Set the Initialization Vector */ @@ -2372,7 +2474,9 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti */ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) { +#if defined(SAES) uint32_t count; +#endif /* SAES */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) @@ -2394,6 +2498,9 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) if ((dokeyivconfig == 1U) && (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)) { +#if !defined(SAES) + CRYP_SetKey(hcryp, hcryp->Init.KeySize); +#else if (hcryp->Instance == AES) { /* Set the Key */ @@ -2432,6 +2539,7 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) } } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID)); } +#endif /* SAES */ if (hcryp->Init.Algorithm != CRYP_AES_ECB) { /* Set the Initialization Vector*/ @@ -2510,6 +2618,42 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti if (dokeyivconfig == 1U) { +#if !defined(SAES) + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ + { + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Algorithm CTR */ + { + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } +#else if (hcryp->Instance == AES) { /* Key preparation for ECB/CBC */ @@ -2606,6 +2750,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); } } +#endif /* !defined(SAES) */ /* Set IV */ if (hcryp->Init.Algorithm != CRYP_AES_ECB) { @@ -2708,6 +2853,54 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) if (dokeyivconfig == 1U) { +#if !defined(SAES) + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) + { + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count--; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_ISR_CCF)); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Algorithm CTR */ + { + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } +#else if (hcryp->Instance == AES) { /* Key preparation for ECB/CBC */ @@ -2818,6 +3011,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); } } +#endif /* SAES */ /* Set IV */ if (hcryp->Init.Algorithm != CRYP_AES_ECB) { @@ -2886,6 +3080,55 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) if (dokeyivconfig == 1U) { +#if !defined(SAES) + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) + { + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count--; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_ISR_CCF)); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Algorithm CTR */ + { + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } +#else if (hcryp->Instance == AES) { /* Key preparation for ECB/CBC */ @@ -2996,6 +3239,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); } } +#endif /* SAES */ if (hcryp->Init.Algorithm != CRYP_AES_ECB) { @@ -3148,6 +3392,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) uint32_t lastwordsize; uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t mode; + uint32_t crypoutcount; CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; @@ -3222,7 +3467,17 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) count = 0U; while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (count < 4U)) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count]; + crypoutcount = hcryp->CrypOutCount; + if ((((hcryp->Size % 4U) != 0U) && (crypoutcount == ((((uint32_t)hcryp->Size + 3U) / 4U) - 1U))) + && (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[count], + hcryp->Init.DataType, (((uint32_t)hcryp->Size) % 4U)); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count]; + } hcryp->CrypOutCount++; count++; } @@ -3470,6 +3725,7 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t i; + uint32_t crypoutcount; /* Write the input block in the IN FIFO */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); @@ -3505,7 +3761,17 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) i = 0U; while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + crypoutcount = hcryp->CrypOutCount; + if ((((hcryp->Size % 4U) != 0U) && (crypoutcount == ((((uint32_t)hcryp->Size + 3U) / 4U) - 1U))) + && (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[i], + hcryp->Init.DataType, (((uint32_t)hcryp->Size) % 4U)); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + } hcryp->CrypOutCount++; i++; } @@ -3714,10 +3980,18 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t npblb; uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t index; - uint32_t lastwordsize; + uint32_t tmp; + uint32_t lastwordsize ; + uint32_t lastoutputwordsize; + uint32_t nolastpaddingbytes; uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32- bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 1- bit data type */ + }; if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { if (hcryp->KeyIVConfig == 1U) @@ -3841,14 +4115,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); } /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } + lastwordsize = (16U - npblb) / 4U; + /* last block optionally pad the data with zeros*/ for (index = 0U; index < lastwordsize; index ++) { @@ -3856,6 +4124,16 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } + + if ((npblb % 4U) != 0U) + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + tmp &= mask[((hcryp->Init.DataType) * 2U) + ((16U - npblb) % 4U)]; + hcryp->Instance->DINR = tmp; + index++; + } + while (index < 4U) { /* pad the data with zeros to have a complete block */ @@ -3877,6 +4155,17 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + /* Number of words in last block to read from DOUT*/ + if ((npblb % 4U) == 0U) + { + lastoutputwordsize = (16U - npblb) / 4U; + } + else + { + lastoutputwordsize = ((16U - npblb) / 4U) + 1U; + } + + /*Read the output block from the output FIFO */ for (index = 0U; index < 4U; index++) { @@ -3884,9 +4173,20 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t get CrypOutBuff from temporary buffer */ temp[index] = hcryp->Instance->DOUTR; } - for (index = 0U; index < lastwordsize; index++) + for (index = 0U; index < lastoutputwordsize; index++) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index]; + if ((index == (lastoutputwordsize - 1U)) && ((npblb % 4U) != 0U) + && (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + nolastpaddingbytes = npblb % 4U; + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[index], + hcryp->Init.DataType, 4U - nolastpaddingbytes); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index]; + } + hcryp->CrypOutCount++; } } @@ -4376,10 +4676,17 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t loopcounter; uint32_t npblb; uint32_t lastwordsize; + uint32_t lastoutputwordsize; uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ + uint32_t tmp; uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32- bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 1- bit data type */ + }; if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { @@ -4506,14 +4813,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t } /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } + lastwordsize = (16U - npblb) / 4U; /* Write the last input block in the IN FIFO */ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++) @@ -4521,6 +4821,15 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } + if ((npblb % 4U) != 0U) + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + /* Keep only valid bytes of the last partial input word, according to DataType byte ordering. */ + tmp &= mask[(hcryp->Init.DataType * 2U) + ((16U - npblb) % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + } /* Pad the data with zeros to have a complete block */ while (loopcounter < 4U) @@ -4528,6 +4837,15 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t hcryp->Instance->DINR = 0U; loopcounter++; } + /* Number of words in last block to read from DOUT*/ + if ((npblb % 4U) == 0U) + { + lastoutputwordsize = (16U - npblb) / 4U; + } + else + { + lastoutputwordsize = ((16U - npblb) / 4U) + 1U; + } /* just wait for hash computation */ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { @@ -4542,9 +4860,17 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t get CrypOutBuff from temporary buffer */ temp[loopcounter] = hcryp->Instance->DOUTR; } - for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + for (loopcounter = 0U; loopcounter < lastoutputwordsize; loopcounter++) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter]; + if ((loopcounter == (lastoutputwordsize - 1U)) && ((npblb % 4U) != 0U)) + { + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[loopcounter], + hcryp->Init.DataType, 4U - (npblb % 4U)); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter]; + } hcryp->CrypOutCount++; } } @@ -5033,6 +5359,7 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) uint16_t incount; /* Temporary CrypInCount Value */ uint16_t outcount; /* Temporary CrypOutCount Value */ uint32_t i; + uint32_t crypoutcount; /***************************** Payload phase *******************************/ @@ -5045,7 +5372,17 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) i = 0U; while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + crypoutcount = hcryp->CrypOutCount; + if ((((hcryp->Size % 4U) != 0U) && (crypoutcount == ((((uint32_t)hcryp->Size + 3U) / 4U) - 1U))) + && (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[i], + hcryp->Init.DataType, (((uint32_t)hcryp->Size) % 4U)); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + } hcryp->CrypOutCount++; i++; } @@ -5266,7 +5603,16 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr } for (index = 0U; index < lastwordsize; index++) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; + if ((index == (lastwordsize - 1U)) && ((npblb % 4U) != 0U) + && (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[index], + hcryp->Init.DataType, 4U - (npblb % 4U)); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; + } hcryp->CrypOutCount++; } @@ -5785,9 +6131,10 @@ static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout { uint32_t count = Timeout; - do + /* Wait until CCF is set or timeout occurs */ + while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) { - count-- ; + if (count == 0U) { /* Disable the CRYP peripheral clock */ @@ -5807,8 +6154,11 @@ static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout /*Call legacy weak error callback*/ HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + return; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); + + count-- ; + } /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -6164,6 +6514,177 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) } } #endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */ +/** + * @brief RNG sequence to resilient recover from a seed error + * @retval HAL status + */ +HAL_StatusTypeDef CRYP_RNG_ResilientRecoverSeedError(void) +{ + uint32_t timeout; + uint32_t htsr_temp = 0U; + uint32_t htsr_previous_temp = 0U; + uint32_t htsr_count = 0U; + uint32_t nsmr_temp = 0U; + uint32_t tickstart1 = 0U; + uint32_t tickstart2 = 0U; + uint32_t tickstart3 = 0U; + uint32_t oscillators_count = 0U; + uint32_t config_b_fewer_than_6_osc_count = 0U; + uint8_t count = 0U; + + /* timeout here is an emperic value */ + timeout = (1UL + ((1UL << (READ_BIT(RNG->CR, RNG_CR_CLKDIV) >> 16UL)) * CRYP_RNG_TIMEOUT_VALUE / 8UL)); + LL_RNG_Enable(RNG); + + tickstart1 = HAL_GetTick(); + + /* Check if seed error current status indicates no error and auto-reset succeeded */ + if (LL_RNG_IsActiveFlag_SECS(RNG) == 0U) + { + /* Clear SEIS flag when automatic reset is activated */ + LL_RNG_ClearFlag_SEIS(RNG); + } + + else /* Sequence to fully recover from a seed error*/ + { + if (LL_RNG_IsConfigLocked(RNG) == 0U) + { + do + { + if (LL_RNG_IsActiveFlag_SECS(RNG) == 0U) + { + break; + } + /* Read oscillator status registers combined */ + htsr_temp = LL_RNG_GetHealthTestStatus(RNG, 0U); + htsr_temp |= LL_RNG_GetHealthTestStatus(RNG, 1U); + if (htsr_temp > 0U) + { + /* If any oscillator status bits overlap with previous status, increment counter */ + if ((htsr_temp & htsr_previous_temp) != 0U) + { + htsr_count++; + } + + if (htsr_count > 3U) + { + /* if the same repetitive or adaptative error is detected 3 times */ + nsmr_temp = LL_RNG_GetNoiseSourceMask(RNG); + + /* deactivate the same osc in each triple oscillator (Mask oscillators with the seed error by + clearing bits shifted right by 1) */ + nsmr_temp = nsmr_temp & ~(htsr_temp >> 1U); + + /* Count the number of active oscillators in nsmr */ + oscillators_count = 0U; + for (count = 0U; count < 9U; count++) + { + if (((nsmr_temp >> count) & 0x1U) != 0U) + { + /* increment count1 for each 1 in nsmr */ + oscillators_count++; + } + } + + if (oscillators_count < 6U) + { + /* If fewer than 6 oscillators remain active, unmask all oscillators --> Reset masking */ + nsmr_temp = LL_RNG_GetOscNoiseSrc(RNG, LL_RNG_NOISE_SRC_1 | LL_RNG_NOISE_SRC_2 \ + | LL_RNG_NOISE_SRC_3); + htsr_previous_temp = 0; + htsr_count = 0U; + if ((RNG->CR & RNG_CR_CLKDIV_Msk) < ((uint32_t)RNG_CAND_NIST_CR_VALUE & RNG_CR_CLKDIV_Msk)) + { + config_b_fewer_than_6_osc_count++; + } + } + + if (config_b_fewer_than_6_osc_count > 2U) + { + /* Reset RNG condition */ + WRITE_REG(RNG->CR, (RNG_CR_CONDRST_Msk | (uint32_t)RNG_CAND_NIST_CR_VALUE)); + + /* Update mask register with new oscillator mask */ + LL_RNG_SetNoiseSourceMask(RNG, nsmr_temp); + + /* Clear condition reset bit to resume operation */ + LL_RNG_DisableCondReset(RNG); + } + + else + { + /* Reset RNG condition */ + WRITE_REG(RNG->CR, (RNG->CR & ~RNG_CR_RNGEN_Msk) | RNG_CR_CONDRST_Msk); + + /* Update mask register with new oscillator mask */ + LL_RNG_SetNoiseSourceMask(RNG, nsmr_temp); + + /* Clear condition reset bit to resume operation */ + LL_RNG_DisableCondReset(RNG); + } + } + + else + { + /* Briefly toggle conditional reset to recover RNG */ + WRITE_REG(RNG->CR, (RNG->CR & ~RNG_CR_RNGEN_Msk) | RNG_CR_CONDRST_Msk); + + /* unmask all oscillators to find another working condition */ + LL_RNG_SetNoiseSourceMask(RNG, LL_RNG_GetOscNoiseSrc(RNG, LL_RNG_OSC_1\ + | LL_RNG_OSC_2 | LL_RNG_OSC_3)); + LL_RNG_DisableCondReset(RNG); + } + + /* Wait until RNG is not busy */ + tickstart2 = HAL_GetTick(); + do + { + if ((HAL_GetTick() - tickstart2) > CRYP_RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + LL_RNG_Disable(RNG); + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(RNG->SR, RNG_SR_BUSY)); + + /* No timeout --> Enable RNG */ + LL_RNG_Enable(RNG); + tickstart3 = HAL_GetTick(); + do + { + if (LL_RNG_IsActiveFlag_DRDY(RNG) != 0UL) + { + break; + } + if ((HAL_GetTick() - tickstart3) > timeout) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_RNG_IsActiveFlag_DRDY(RNG) == 0UL) + { + if (LL_RNG_IsActiveFlag_SECS(RNG) == 0UL) + { + LL_RNG_Disable(RNG); + return HAL_ERROR; + } + } + } + } while (LL_RNG_IsActiveFlag_SECS(RNG) == 0UL); + + /* Accumulate seed error status bits */ + htsr_previous_temp = htsr_previous_temp | htsr_temp; + } + } while ((HAL_GetTick() - tickstart1) <= timeout); + } + } + + /*Check if seed error current status (SECS)is set */ + if (LL_RNG_IsActiveFlag_SECS(RNG) != 0U) + { + return HAL_ERROR; + } + + return HAL_OK; +} /** * @} */ diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_cryp_ex.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_cryp_ex.c index 31e8bd5088..cac6b68059 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_cryp_ex.c +++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_cryp_ex.c @@ -64,8 +64,10 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +#if defined(SAES) static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +#endif /* defined(SAES) */ static HAL_StatusTypeDef CRYPEx_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout); /* Exported functions---------------------------------------------------------*/ /** @addtogroup CRYPEx_Exported_Functions @@ -308,6 +310,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, c * @} */ +#if defined(SAES) /** @defgroup CRYPEx_Exported_Functions_Group2 Wrap and Unwrap key functions * @brief Wrap and Unwrap key functions. @@ -741,6 +744,7 @@ static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t T __HAL_UNLOCK(hcryp); return HAL_OK; } +#endif /* defined(SAES)*/ /** * @brief Wait Instance Flag * @param hcryp cryp handle diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_gtzc.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_gtzc.c index 4de873c996..8da07897f5 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_gtzc.c +++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_gtzc.c @@ -113,6 +113,26 @@ /* Definitions for GTZC TZSC & TZIC ALL register values */ /* TZSC1 / TZIC1 instances */ +#if defined(STM32U335xx) || defined(STM32U345xx) +#define TZSC1_SECCFGR1_ALL (0x00C6ADF7UL) +#define TZSC1_SECCFGR2_ALL (0x0001FA7BUL) +#define TZSC1_SECCFGR3_ALL (0x01D03958UL) + +#define TZSC1_PRIVCFGR1_ALL (0x00C6ADF7UL) +#define TZSC1_PRIVCFGR2_ALL (0x0001FA7BUL) +#define TZSC1_PRIVCFGR3_ALL (0x01D03958UL) + +#define TZIC1_IER1_ALL (0x00C6ADF7UL) +#define TZIC1_IER2_ALL (0x0001FA7BUL) +#define TZIC1_IER3_ALL (0x01D03958UL) +#define TZIC1_IER4_ALL (0x0F00C1FFUL) + +#define TZIC1_FCR1_ALL (0x00C6ADF7UL) +#define TZIC1_FCR2_ALL (0x0001FA7BUL) +#define TZIC1_FCR3_ALL (0x01D03958UL) +#define TZIC1_FCR4_ALL (0x0F00C1FFUL) +#endif /* defined(STM32U335xx) || defined(STM32U345xx) */ + #if defined(STM32U356xx) || defined(STM32U366xx) #define TZSC1_SECCFGR1_ALL (0x01E2BDF7UL) #define TZSC1_SECCFGR2_ALL (0x0003FA7BUL) @@ -173,6 +193,26 @@ #define TZIC1_FCR4_ALL (0xFF00C1FFUL) #endif /* defined(STM32U3B5xx) || defined(STM32U3C5xx) */ +#if defined(STM32U396xx) || defined(STM32U3A6xx) +#define TZSC1_SECCFGR1_ALL (0x01E6FDF7UL) +#define TZSC1_SECCFGR2_ALL (0x0003FFFFUL) +#define TZSC1_SECCFGR3_ALL (0x23FFF978UL) + +#define TZSC1_PRIVCFGR1_ALL (0x01E6FDF7UL) +#define TZSC1_PRIVCFGR2_ALL (0x0003FFFFUL) +#define TZSC1_PRIVCFGR3_ALL (0x23FFF978UL) + +#define TZIC1_IER1_ALL (0x01E6FDF7UL) +#define TZIC1_IER2_ALL (0x0003FFFFUL) +#define TZIC1_IER3_ALL (0x23FFF978UL) +#define TZIC1_IER4_ALL (0xFF00C1FFUL) + +#define TZIC1_FCR1_ALL (0x01E6FDF7UL) +#define TZIC1_FCR2_ALL (0x0003FFFFUL) +#define TZIC1_FCR3_ALL (0x23FFF978UL) +#define TZIC1_FCR4_ALL (0xFF00C1FFUL) +#endif /* defined(STM32U396xx) || defined(STM32U3A6xx) */ + /** * @} */ diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_hsp.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_hsp.c index 268c80a022..8bb2f065d8 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_hsp.c +++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_hsp.c @@ -567,6 +567,7 @@ * @param source id of the trigger signal (@ref HAL_HSP_TRGIN_SourceTypeDef). * @retval SET (id is valid) or RESET (id is invalid) */ +#if defined(STM32U3C5xx) || defined(STM32U3B5xx) #define IS_HSP_TRGIN_SOURCE(source) \ (((source) == HAL_HSP_TRGIN_DMA1_CH1_TC) \ || ((source) == HAL_HSP_TRGIN_DMA1_CH2_TC) \ @@ -588,6 +589,29 @@ || ((source) == HAL_HSP_TRGIN_LPTIM2_CH1) \ || ((source) == HAL_HSP_TRGIN_LPTIM2_CH2) \ || ((source) == HAL_HSP_TRGIN_ADF1_SAD_DET)) +#else +#define IS_HSP_TRGIN_SOURCE(source) \ + (((source) == HAL_HSP_TRGIN_DMA1_CH8_TC) \ + || ((source) == HAL_HSP_TRGIN_DMA1_CH9_TC) \ + || ((source) == HAL_HSP_TRGIN_DMA1_CH10_TC) \ + || ((source) == HAL_HSP_TRGIN_DMA1_CH11_TC) \ + || ((source) == HAL_HSP_TRGIN_EXTI0) \ + || ((source) == HAL_HSP_TRGIN_EXTI1) \ + || ((source) == HAL_HSP_TRGIN_TIM1_TRGO) \ + || ((source) == HAL_HSP_TRGIN_TIM1_TRGO2) \ + || ((source) == HAL_HSP_TRGIN_TIM2_TRGO) \ + || ((source) == HAL_HSP_TRGIN_TIM3_TRGO) \ + || ((source) == HAL_HSP_TRGIN_TIM6_TRGO) \ + || ((source) == HAL_HSP_TRGIN_TIM7_TRGO) \ + || ((source) == HAL_HSP_TRGIN_TIM8_TRGO) \ + || ((source) == HAL_HSP_TRGIN_TIM8_TRGO2) \ + || ((source) == HAL_HSP_TRGIN_TIM15_TRGO) \ + || ((source) == HAL_HSP_TRGIN_LPTIM1_CH1) \ + || ((source) == HAL_HSP_TRGIN_LPTIM1_CH2) \ + || ((source) == HAL_HSP_TRGIN_LPTIM2_CH1) \ + || ((source) == HAL_HSP_TRGIN_LPTIM2_CH2) \ + || ((source) == HAL_HSP_TRGIN_ADF1_SAD_DET)) +#endif /* STM32U3C5xx || STM32U3B5xx */ /** diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_pcd.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_pcd.c index 983af85000..06662a11d3 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_pcd.c +++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_pcd.c @@ -745,7 +745,7 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) status = HAL_ERROR; } - return status; + return status; } /** @@ -1047,6 +1047,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + /* store current frame number */ + hpcd->FrameNumber = USB_GetCurrentFrame(hpcd->Instance); + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else @@ -1640,6 +1643,9 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) count = 0U; #endif /* USE_USB_DOUBLE_BUFFER */ + /* store current frame number */ + hpcd->FrameNumber = USB_GetCurrentFrame(hpcd->Instance); + /* stay in loop while pending interrupts */ while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) { @@ -1648,6 +1654,11 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_IDN); + if (epindex >= 8U) + { + return HAL_ERROR; + } + if (epindex == 0U) { /* Decode and service control endpoint interrupt */ diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_pwr_ex.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_pwr_ex.c index d08b5b3c90..2fbe657b09 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_pwr_ex.c +++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_pwr_ex.c @@ -907,10 +907,12 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_P CLEAR_BIT(PWR->PDCRD, GPIO_Pin); break; +#if defined(PWR_GPIO_E) case PWR_GPIO_E: /* Apply Pull Up to GPIO port E */ SET_BIT(PWR->PUCRE, GPIO_Pin); CLEAR_BIT(PWR->PDCRE, GPIO_Pin); break; +#endif/*PWR_GPIO_E*/ #if defined(PWR_GPIO_F) case PWR_GPIO_F: /* Apply Pull Up to GPIO port F */ @@ -980,9 +982,11 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_ CLEAR_BIT(PWR->PUCRD, GPIO_Pin); break; +#if defined(PWR_GPIO_E) case PWR_GPIO_E: /* Disable Pull Up for GPIO port E */ CLEAR_BIT(PWR->PUCRE, GPIO_Pin); break; +#endif/*PWR_GPIO_E*/ #if defined(PWR_GPIO_F) case PWR_GPIO_F: /* Disable Pull Up for GPIO port F */ @@ -1060,10 +1064,12 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO CLEAR_BIT(PWR->PUCRD, GPIO_Pin); break; +#if defined(PWR_GPIO_E) case PWR_GPIO_E: /* Apply Pull Down to GPIO port E */ SET_BIT(PWR->PDCRE, GPIO_Pin); CLEAR_BIT(PWR->PUCRE, GPIO_Pin); break; +#endif/*PWR_GPIO_E*/ #if defined(PWR_GPIO_F) case PWR_GPIO_F: /* Apply Pull Down to GPIO port F */ @@ -1133,9 +1139,11 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPI CLEAR_BIT(PWR->PDCRD, GPIO_Pin); break; +#if defined(PWR_GPIO_E) case PWR_GPIO_E: /* Disable Pull Down for GPIO port E */ CLEAR_BIT(PWR->PDCRE, GPIO_Pin); break; +#endif/*PWR_GPIO_E*/ #if defined(PWR_GPIO_F) case PWR_GPIO_F: /* Disable Pull Down for GPIO port F */ diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_rcc.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_rcc.c index fb0819b6ed..f280342b97 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_rcc.c +++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_rcc.c @@ -83,8 +83,13 @@ /** @defgroup RCC_Private_Macros RCC Private Macros * @{ */ +#if defined(STM32U366xx) || defined(STM32U356xx) +#define __MCO_PORTB_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define MCO_GPIO_PORTB GPIOB +#endif /* defined(STM32U366xx) || defined(STM32U356xx) */ #define __MCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() #define MCO_GPIO_PORT GPIOA + /** * @} */ @@ -1013,6 +1018,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStru * @param RCC_MCOx specifies the instance of clock output and its associated pin. * @arg @ref RCC_MCO1_PA8 Clock source to output on MCO1 pin(PA8) * @arg @ref RCC_MCO1_PA9 Clock source to output on MCO1 pin(PA9) + * @arg @ref RCC_MCO1_PB8 Clock source to output on MCO1 pin(PB8) **Only + * for STM32U356xx and STM32U366xx** * @arg @ref RCC_MCO2_PA8 Clock source to output on MCO2 pin(PA8) * @arg @ref RCC_MCO2_PA10 Clock source to output on MCO2 pin(PA10) * @param RCC_MCOSource specifies the clock source to output. @@ -1059,12 +1066,25 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M { GPIO_InitTypeDef GPIO_InitStruct; uint32_t clearmask; + GPIO_TypeDef *gpio_port = MCO_GPIO_PORT; /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); - /* MCO Clock Enable. On U3, MCO1 and MCO2 are always on GPIOA */ + /* MCO Clock Enable and select correct GPIO port */ +#if defined(STM32U366xx) || defined(STM32U356xx) + if (((RCC_MCOx & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS) == RCC_MCO_GPIOPORTB) + { + __MCO_PORTB_CLK_ENABLE(); + gpio_port = MCO_GPIO_PORTB; + } + else + { + __MCO_CLK_ENABLE(); + } +#else __MCO_CLK_ENABLE(); +#endif /* defined(STM32U366xx) || defined(STM32U356xx) */ /* Configure the MCO1 pin in alternate function mode */ GPIO_InitStruct.Pin = (RCC_MCOx & RCC_MCO_GPIOPIN_MASK); @@ -1072,7 +1092,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Alternate = ((RCC_MCOx & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS); - HAL_GPIO_Init(MCO_GPIO_PORT, &GPIO_InitStruct); + HAL_GPIO_Init(gpio_port, &GPIO_InitStruct); if ((RCC_MCOx & RCC_MCO_INDEX_MASK) != 0x00u) { diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_rng.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_rng.c index 5665aa0077..590d467cc6 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_rng.c +++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_rng.c @@ -197,8 +197,20 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Disable RNG */ __HAL_RNG_DISABLE(hrng); +#if defined(RNG_CR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->CR, RNG_CR_NIST_VALUE | RNG_CR_CONDRST | hrng->Init.ClockErrorDetection); +#else /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST); +#endif /* RNG_CR_NIST_VALUE */ +#if defined(RNG_HTCR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->HTCR[0], RNG_HTCR_NIST_VALUE); +#endif /* RNG_HTCR_NIST_VALUE */ +#if defined(RNG_NSCR_NIST_VALUE) + WRITE_REG(hrng->Instance->NSCR, RNG_NSCR_NIST_VALUE); +#endif /* RNG_NSCR_NIST_VALUE */ /* Writing bit CONDRST=0 */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); @@ -633,7 +645,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; /* Check if there is a seed error */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; @@ -653,6 +665,14 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t /* Check if data register contains valid random data */ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) { + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; + hrng->State = HAL_RNG_STATE_READY; + return HAL_ERROR; + } + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { /* New check to avoid false timeout detection in case of preemption */ @@ -799,7 +819,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Clear the clock error flag */ - __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI); + __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI); return; } diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_rng_ex.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_rng_ex.c index c898f28013..5ee86affd4 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_rng_ex.c +++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_rng_ex.c @@ -51,6 +51,7 @@ /* Private macros ------------------------------------------------------------*/ /* Private functions prototypes ----------------------------------------------*/ /* Private functions --------------------------------------------------------*/ +HAL_StatusTypeDef RNG_ResilientRecoverSeedError(RNG_HandleTypeDef *hrng); /* Exported functions --------------------------------------------------------*/ /** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions @@ -127,7 +128,7 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigT (uint32_t)(RNG_CR_CONDRST | cr_value)); /* RNG health test control in accordance with NIST */ - WRITE_REG(hrng->Instance->HTCR, pConf->HealthTest); + WRITE_REG(hrng->Instance->HTCR[0], pConf->HealthTest); /* Writing bit CONDRST=0*/ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); @@ -155,6 +156,14 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigT /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; + /*Check if seed error current status (SECS)is set */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_SR_SECS) != RESET) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; + return HAL_ERROR; + } + /* function status */ status = HAL_OK; } @@ -202,7 +211,7 @@ HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef pConf->ClockDivider = (hrng->Instance->CR & RNG_CR_CLKDIV); pConf->NistCompliance = (hrng->Instance->CR & RNG_CR_NISTC); pConf->AutoReset = (hrng->Instance->CR & RNG_CR_ARDIS); - pConf->HealthTest = (hrng->Instance->HTCR); + pConf->HealthTest = (hrng->Instance->HTCR[0]); /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; @@ -286,11 +295,13 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) /** * @brief RNG sequence to recover from a seed error * @param hrng: pointer to a RNG_HandleTypeDef structure. + * @warning Recover from seed error will adapt the parameters config1,2,3 to overcome seed error. * @retval HAL status */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) { HAL_StatusTypeDef status; + HAL_RNG_StateTypeDef state; /* Check the RNG handle allocation */ if (hrng == NULL) @@ -298,14 +309,16 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) return HAL_ERROR; } + state = hrng->State; + /* Check RNG peripheral state */ - if (hrng->State == HAL_RNG_STATE_READY) + if ((state == HAL_RNG_STATE_READY) || (state == HAL_RNG_STATE_ERROR)) { /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; /* sequence to fully recover from a seed error */ - status = RNG_RecoverSeedError(hrng); + status = RNG_ResilientRecoverSeedError(hrng); if (status == HAL_ERROR) { /* Update the error code */ @@ -322,6 +335,75 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) return status; } +/** + * @brief Configure the RNG additional health tests. + * @param hrng hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @param htcr_idx is a value of the htcr. + * @param htcr_value Health test value. + * @retval HAL_OK configuration succeeded. + * @retval HAL_ERROR configuration fail. + * @retval HAL_INVALID_PARAM invalid parameter. + */ +HAL_StatusTypeDef HAL_RNGEx_SetHealthFactorConfig(RNG_HandleTypeDef *hrng, uint32_t htcr_idx, uint32_t htcr_value) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t tickstart; + + assert_param(IS_RNG_HTCR_INDEX(htcr_idx)); + assert_param(IS_RNG_HTCR_VALUE(htcr_value)); + + /* Check the RNG handle allocation */ + if (hrng == NULL) + { + return HAL_ERROR; + } + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + if (LL_RNG_IsConfigLocked(hrng->Instance) == 0U) + { + LL_RNG_EnableCondReset(hrng->Instance); + LL_RNG_SetAdditionalHealthTest(hrng->Instance, htcr_idx, htcr_value); + LL_RNG_DisableCondReset(hrng->Instance); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for conditioning reset process to be completed */ + while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of prememption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } + } + } + } + + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_READY; + + /* function status */ + status = HAL_OK; + } + else + { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + return status; +} /** * @} */ @@ -330,6 +412,200 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) * @} */ +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup RNG_Private_Functions RNG Private Functions + * @brief RNG Private Functions + * @{ + */ + +/** + * @brief RNG sequence to resilient recover from a seed error + * @param hrng pointer to a RNG_HandleTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef RNG_ResilientRecoverSeedError(RNG_HandleTypeDef *hrng) +{ + uint32_t timeout; + uint32_t htsr_temp = 0U; + uint32_t htsr_previous_temp = 0U; + uint32_t htsr_count = 0U; + uint32_t nsmr_temp = 0U; + uint32_t tickstart1 = 0U; + uint32_t tickstart2 = 0U; + uint32_t tickstart3 = 0U; + uint32_t oscillators_count = 0U; + uint32_t config_b_fewer_than_6_osc_count = 0U; + uint8_t count = 0U; + + /* timeout here is an emperic value */ + timeout = (1UL + ((1UL << (READ_BIT(hrng->Instance->CR, RNG_CR_CLKDIV) >> 16UL)) * RNG_TIMEOUT_VALUE / 8UL)); + LL_RNG_Enable(hrng->Instance); + + tickstart1 = HAL_GetTick(); + + /* Check if seed error current status indicates no error and auto-reset succeeded */ + if (LL_RNG_IsActiveFlag_SECS(hrng->Instance) == 0U) + { + /* Clear SEIS flag when automatic reset is activated */ + LL_RNG_ClearFlag_SEIS(hrng->Instance); + } + + else /* Sequence to fully recover from a seed error*/ + { + if (LL_RNG_IsConfigLocked(hrng->Instance) == 0U) + { + do + { + if (LL_RNG_IsActiveFlag_SECS(hrng->Instance) == 0U) + { + break; + } + /* Read oscillator status registers combined */ + htsr_temp = LL_RNG_GetHealthTestStatus(hrng->Instance, 0U); + htsr_temp |= LL_RNG_GetHealthTestStatus(hrng->Instance, 1U); + if (htsr_temp > 0U) + { + /* If any oscillator status bits overlap with previous status, increment counter */ + if ((htsr_temp & htsr_previous_temp) != 0U) + { + htsr_count++; + } + + if (htsr_count > 3U) + { + /* if the same repetitive or adaptative error is detected 3 times */ + nsmr_temp = LL_RNG_GetNoiseSourceMask(hrng->Instance); + + /* deactivate the same osc in each triple oscillator (Mask oscillators with the seed error by + clearing bits shifted right by 1) */ + nsmr_temp = nsmr_temp & ~(htsr_temp >> 1U); + + /* Count the number of active oscillators in nsmr */ + oscillators_count = 0U; + for (count = 0U; count < 9U; count++) + { + if (((nsmr_temp >> count) & 0x1U) != 0U) + { + /* increment count1 for each 1 in nsmr */ + oscillators_count++; + } + } + + if (oscillators_count < 6U) + { + /* If fewer than 6 oscillators remain active, unmask all oscillators --> Reset masking */ + nsmr_temp = LL_RNG_GetOscNoiseSrc(hrng->Instance, LL_RNG_NOISE_SRC_1 | LL_RNG_NOISE_SRC_2 \ + | LL_RNG_NOISE_SRC_3); + htsr_previous_temp = 0; + htsr_count = 0U; + if ((hrng->Instance->CR & RNG_CR_CLKDIV_Msk) < ((uint32_t)RNG_CAND_NIST_CR_VALUE & RNG_CR_CLKDIV_Msk)) + { + config_b_fewer_than_6_osc_count++; + } + } + + if (config_b_fewer_than_6_osc_count > 2U) + { + /* Reset RNG condition */ + WRITE_REG(hrng->Instance->CR, (RNG_CR_CONDRST_Msk | (uint32_t)RNG_CAND_NIST_CR_VALUE)); + + /* Update mask register with new oscillator mask */ + LL_RNG_SetNoiseSourceMask(hrng->Instance, nsmr_temp); + + /* Clear condition reset bit to resume operation */ + LL_RNG_DisableCondReset(hrng->Instance); + } + + else + { + /* Reset RNG condition */ + WRITE_REG(hrng->Instance->CR, (hrng->Instance->CR & ~RNG_CR_RNGEN_Msk) | RNG_CR_CONDRST_Msk); + + /* Update mask register with new oscillator mask */ + LL_RNG_SetNoiseSourceMask(hrng->Instance, nsmr_temp); + + /* Clear condition reset bit to resume operation */ + LL_RNG_DisableCondReset(hrng->Instance); + } + } + + else + { + /* Briefly toggle conditional reset to recover RNG */ + WRITE_REG(hrng->Instance->CR, (hrng->Instance->CR & ~RNG_CR_RNGEN_Msk) | RNG_CR_CONDRST_Msk); + + /* unmask all oscillators to find another working condition */ + LL_RNG_SetNoiseSourceMask(hrng->Instance, LL_RNG_GetOscNoiseSrc(hrng->Instance, LL_RNG_OSC_1\ + | LL_RNG_OSC_2 | LL_RNG_OSC_3)); + LL_RNG_DisableCondReset(hrng->Instance); + } + + /* Wait until RNG is not busy */ + tickstart2 = HAL_GetTick(); + do + { + if ((HAL_GetTick() - tickstart2) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + LL_RNG_Disable(hrng->Instance); + hrng->State = HAL_RNG_STATE_ERROR; + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_SR_BUSY)); + + /* No timeout --> Enable RNG */ + LL_RNG_Enable(hrng->Instance); + tickstart3 = HAL_GetTick(); + do + { + if (LL_RNG_IsActiveFlag_DRDY(hrng->Instance) != 0UL) + { + break; + } + if ((HAL_GetTick() - tickstart3) > timeout) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_RNG_IsActiveFlag_DRDY(hrng->Instance) == 0UL) + { + if (LL_RNG_IsActiveFlag_SECS(hrng->Instance) == 0UL) + { + LL_RNG_Disable(hrng->Instance); + hrng->State = HAL_RNG_STATE_ERROR; + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } + } + } + } while (LL_RNG_IsActiveFlag_SECS(hrng->Instance) == 0UL); + + /* Accumulate seed error status bits */ + htsr_previous_temp = htsr_previous_temp | htsr_temp; + } + } while ((HAL_GetTick() - tickstart1) <= timeout); + } + } + + /*Check if seed error current status (SECS)is set */ + if (LL_RNG_IsActiveFlag_SECS(hrng->Instance) != 0U) + { + hrng->ErrorCode &= HAL_RNG_ERROR_SEED; + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } + + /* Update the error code */ + hrng->ErrorCode &= ~ HAL_RNG_ERROR_SEED; + + /* Return the function status */ + hrng->State = HAL_RNG_STATE_READY; + __HAL_UNLOCK(hrng); + return HAL_OK; +} + +/** + * @} + */ #endif /* RNG_CR_CONDRST */ #endif /* HAL_RNG_MODULE_ENABLED */ /** diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_uart.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_uart.c index 9789f747bd..df27c3a32e 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_uart.c +++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_uart.c @@ -1161,7 +1161,15 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); pdata8bits++; } - huart->TxXferCount--; + if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX) + { + huart->TxXferCount--; + } + else + { + /* Process was aborted during the transmission */ + return HAL_ERROR; + } } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) @@ -1257,7 +1265,15 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); pdata8bits++; } - huart->RxXferCount--; + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + huart->RxXferCount--; + } + else + { + /* Process was aborted during the reception */ + return HAL_ERROR; + } } /* At end of Rx process, restore huart->RxState to Ready */ @@ -1790,10 +1806,6 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) } #endif /* HAL_DMA_MODULE_ENABLED */ - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -1862,9 +1874,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) } #endif /* HAL_DMA_MODULE_ENABLED */ - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { @@ -1929,9 +1938,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) } #endif /* HAL_DMA_MODULE_ENABLED */ - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -2059,10 +2065,6 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (abortcplt == 1U) { - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Clear ISR function pointers */ huart->RxISR = NULL; huart->TxISR = NULL; @@ -2143,8 +2145,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) } else { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -2165,9 +2165,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) else #endif /* HAL_DMA_MODULE_ENABLED */ { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -2242,9 +2239,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) } else { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; @@ -2271,9 +2265,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) else #endif /* HAL_DMA_MODULE_ENABLED */ { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; @@ -3696,8 +3687,6 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* Check if DMA in circular mode */ if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) { - huart->TxXferCount = 0U; - /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -3748,8 +3737,6 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* Check if DMA in circular mode */ if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) { - huart->RxXferCount = 0U; - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -3776,8 +3763,6 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - huart->RxXferCount = 0; - /* Check current nb of data still to be received on DMA side. DMA Normal mode, remaining nb of data will be 0 DMA Circular mode, remaining nb of data is reset to RxXferSize */ @@ -3873,7 +3858,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { - huart->TxXferCount = 0U; UART_EndTxTransfer(huart); } @@ -3881,7 +3865,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { - huart->RxXferCount = 0U; UART_EndRxTransfer(huart); } @@ -3905,7 +3888,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->RxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ @@ -3939,10 +3921,6 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) } } - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -3994,10 +3972,6 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } } - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -4035,8 +4009,6 @@ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->TxXferCount = 0U; - /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { @@ -4068,8 +4040,6 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_ll_gpio.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_ll_gpio.c index ade32cd73a..b4b51427ca 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_ll_gpio.c +++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_ll_gpio.c @@ -134,11 +134,13 @@ ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx) LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD); LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD); } +#if defined(GPIOE) else if (GPIOx == GPIOE) { LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE); LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE); } +#endif /* defined(GPIOE) */ #if defined(GPIOG) else if (GPIOx == GPIOG) { diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_ll_usb.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_ll_usb.c index 404573a0bf..800dc1abe9 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_ll_usb.c +++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_ll_usb.c @@ -975,6 +975,16 @@ void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABu } } +/** + * @brief Return Current Frame number + * @param USBx Selected device + * @retval current frame number + */ +uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx) +{ + return (uint32_t)(USBx->FNR & 0x7FFU); +} + /*------------------------------------------------------------------------*/ /* HOST API */ @@ -1054,16 +1064,6 @@ uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx) } } -/** - * @brief Return Host Current Frame number - * @param USBx Selected device - * @retval current frame number - */ -uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx) -{ - return USBx->FNR & 0x7FFU; -} - #if defined (HAL_HCD_MODULE_ENABLED) /** * @brief Initialize a host channel diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_ll_utils.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_ll_utils.c index 1f865b8943..028ecc89b0 100644 --- a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_ll_utils.c +++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_ll_utils.c @@ -191,7 +191,7 @@ void LL_mDelay(uint32_t Delay) /* Add this code to indicate that local variable is not used */ ((void)tmp); - /* Add a period to guaranty minimum wait */ + /* Add a period to guarantee minimum wait */ if (tmpDelay < LL_MAX_DELAY) { tmpDelay++; diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 1a099a3214..b1b2a195c6 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -17,7 +17,7 @@ * STM32L5: 1.0.7 * STM32MP1: 1.7.0 * STM32U0: 1.3.0 - * STM32U3: 1.2.0 + * STM32U3: 1.4.0 * STM32U5: 1.6.2 * STM32WB: 1.14.7 * STM32WB0: 1.4.0