diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h index 8d1355495a..d46c83a0e2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h @@ -3100,11 +3100,11 @@ typedef struct /* Specific ADC4 */ #define ADC4_CFGR1_EXTSEL_Pos (6UL) -#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ -#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ -#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC4_CFGR1_CHSELRMOD_Pos (21UL) #define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ @@ -4792,8 +4792,9 @@ typedef struct #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /******************** RNG Nist Compliance Values *******************/ -#define RNG_CR_NIST_VALUE (0x00F00D00U) -#define RNG_HTCR_NIST_VALUE (0xAAC7U) +#define RNG_CR_NIST_VALUE (0x00F11F00U) +#define RNG_HTCR_NIST_VALUE (0x76B3U) +#define RNG_NSCR_NIST_VALUE (0x24C2U) /******************************************************************************/ /* */ @@ -15165,33 +15166,33 @@ typedef struct #define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR3_SPI3SEL_Pos (3UL) -#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ #define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */ #define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ #define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR3_I2C3SEL_Pos (6UL) -#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ #define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000100 */ -#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ #define RCC_CCIPR3_LPTIM34SEL_Pos (8UL) -#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000300 */ #define RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR3_LPTIM1SEL_Pos (10UL) -#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ #define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ #define RCC_CCIPR3_ADCDACSEL_Pos (12UL) -#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00007000 */ #define RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00010000 */ -#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00020000 */ -#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR3_DAC1SEL_Pos (15UL) -#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00008000 */ #define RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk /*!< DAC1 Sample & Hold Clock Source Selection */ #define RCC_CCIPR3_ADF1SEL_Pos (16UL) #define RCC_CCIPR3_ADF1SEL_Msk (0x7UL << RCC_CCIPR3_ADF1SEL_Pos) /*!< 0x00070000 */ @@ -19646,9 +19647,6 @@ typedef struct #define I2C_CR1_ANFOFF_Pos (12UL) #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST_Pos (13UL) -#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ -#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ #define I2C_CR1_TXDMAEN_Pos (14UL) #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u545xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u545xx.h index 087c473551..d0ac4e003e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u545xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u545xx.h @@ -3264,11 +3264,11 @@ typedef struct /* Specific ADC4 */ #define ADC4_CFGR1_EXTSEL_Pos (6UL) -#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ -#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ -#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC4_CFGR1_CHSELRMOD_Pos (21UL) #define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ @@ -4956,8 +4956,9 @@ typedef struct #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /******************** RNG Nist Compliance Values *******************/ -#define RNG_CR_NIST_VALUE (0x00F00D00U) -#define RNG_HTCR_NIST_VALUE (0xAAC7U) +#define RNG_CR_NIST_VALUE (0x00F11F00U) +#define RNG_HTCR_NIST_VALUE (0x76B3U) +#define RNG_NSCR_NIST_VALUE (0x24C2U) /******************************************************************************/ /* */ @@ -15717,33 +15718,33 @@ typedef struct #define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR3_SPI3SEL_Pos (3UL) -#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ #define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */ #define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ #define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR3_I2C3SEL_Pos (6UL) -#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ #define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000100 */ -#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ #define RCC_CCIPR3_LPTIM34SEL_Pos (8UL) -#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000300 */ #define RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR3_LPTIM1SEL_Pos (10UL) -#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ #define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ #define RCC_CCIPR3_ADCDACSEL_Pos (12UL) -#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00007000 */ #define RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00010000 */ -#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00020000 */ -#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR3_DAC1SEL_Pos (15UL) -#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00008000 */ #define RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk /*!< DAC1 Sample & Hold Clock Source Selection */ #define RCC_CCIPR3_ADF1SEL_Pos (16UL) #define RCC_CCIPR3_ADF1SEL_Msk (0x7UL << RCC_CCIPR3_ADF1SEL_Pos) /*!< 0x00070000 */ @@ -20242,9 +20243,6 @@ typedef struct #define I2C_CR1_ANFOFF_Pos (12UL) #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST_Pos (13UL) -#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ -#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ #define I2C_CR1_TXDMAEN_Pos (14UL) #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u575xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u575xx.h index 9113956f9d..6da4966413 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u575xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u575xx.h @@ -3502,11 +3502,11 @@ typedef struct /* Specific ADC4 */ #define ADC4_CFGR1_EXTSEL_Pos (6UL) -#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ -#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ -#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC4_CFGR1_CHSELRMOD_Pos (21UL) #define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ @@ -16680,33 +16680,33 @@ typedef struct #define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR3_SPI3SEL_Pos (3UL) -#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ #define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */ #define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ #define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR3_I2C3SEL_Pos (6UL) -#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ #define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000100 */ -#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ #define RCC_CCIPR3_LPTIM34SEL_Pos (8UL) -#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000300 */ #define RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR3_LPTIM1SEL_Pos (10UL) -#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ #define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ #define RCC_CCIPR3_ADCDACSEL_Pos (12UL) -#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00007000 */ #define RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00010000 */ -#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00020000 */ -#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR3_DAC1SEL_Pos (15UL) -#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00008000 */ #define RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk /*!< DAC1 Sample & Hold Clock Source Selection */ #define RCC_CCIPR3_ADF1SEL_Pos (16UL) #define RCC_CCIPR3_ADF1SEL_Msk (0x7UL << RCC_CCIPR3_ADF1SEL_Pos) /*!< 0x00070000 */ @@ -21461,7 +21461,7 @@ typedef struct #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17UL) -#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ #define USB_OTG_GRXSTSP_FRMNUM_Pos (21UL) #define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ @@ -21682,10 +21682,10 @@ typedef struct /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0UL) -#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ +#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ #define USB_OTG_GLPMCFG_LPMACK_Pos (1UL) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_BESL_Pos (2UL) #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ @@ -21724,7 +21724,7 @@ typedef struct #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ #define USB_OTG_GLPMCFG_ENBESL_Pos (28UL) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ @@ -22781,9 +22781,6 @@ typedef struct #define I2C_CR1_ANFOFF_Pos (12UL) #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST_Pos (13UL) -#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ -#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ #define I2C_CR1_TXDMAEN_Pos (14UL) #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u585xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u585xx.h index c4b9a897e2..59faf6fb37 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u585xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u585xx.h @@ -3715,11 +3715,11 @@ typedef struct /* Specific ADC4 */ #define ADC4_CFGR1_EXTSEL_Pos (6UL) -#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ -#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ -#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC4_CFGR1_CHSELRMOD_Pos (21UL) #define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ @@ -17290,33 +17290,33 @@ typedef struct #define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR3_SPI3SEL_Pos (3UL) -#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ #define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */ #define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ #define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR3_I2C3SEL_Pos (6UL) -#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ #define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000100 */ -#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ #define RCC_CCIPR3_LPTIM34SEL_Pos (8UL) -#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000300 */ #define RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR3_LPTIM1SEL_Pos (10UL) -#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ #define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ #define RCC_CCIPR3_ADCDACSEL_Pos (12UL) -#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00007000 */ #define RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00010000 */ -#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00020000 */ -#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR3_DAC1SEL_Pos (15UL) -#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00008000 */ #define RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk /*!< DAC1 Sample & Hold Clock Source Selection */ #define RCC_CCIPR3_ADF1SEL_Pos (16UL) #define RCC_CCIPR3_ADF1SEL_Msk (0x7UL << RCC_CCIPR3_ADF1SEL_Pos) /*!< 0x00070000 */ @@ -22123,7 +22123,7 @@ typedef struct #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17UL) -#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ #define USB_OTG_GRXSTSP_FRMNUM_Pos (21UL) #define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ @@ -22344,10 +22344,10 @@ typedef struct /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0UL) -#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ +#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ #define USB_OTG_GLPMCFG_LPMACK_Pos (1UL) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_BESL_Pos (2UL) #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ @@ -22386,7 +22386,7 @@ typedef struct #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ #define USB_OTG_GLPMCFG_ENBESL_Pos (28UL) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ @@ -23443,9 +23443,6 @@ typedef struct #define I2C_CR1_ANFOFF_Pos (12UL) #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST_Pos (13UL) -#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ -#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ #define I2C_CR1_TXDMAEN_Pos (14UL) #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u595xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u595xx.h index c58430dbe2..9b0f67225b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u595xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u595xx.h @@ -3637,11 +3637,11 @@ typedef struct /* Specific ADC4 */ #define ADC4_CFGR1_EXTSEL_Pos (6UL) -#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ -#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ -#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC4_CFGR1_CHSELRMOD_Pos (21UL) #define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ @@ -5439,7 +5439,7 @@ typedef struct #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /******************** RNG Nist Compliance Values *******************/ -#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_CR_NIST_VALUE (0x00F11F00U) #define RNG_HTCR_NIST_VALUE (0x92F3U) #define RNG_NSCR_NIST_VALUE (0x1609U) @@ -17790,33 +17790,33 @@ typedef struct #define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR3_SPI3SEL_Pos (3UL) -#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ #define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */ #define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ #define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR3_I2C3SEL_Pos (6UL) -#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ #define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000100 */ -#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ #define RCC_CCIPR3_LPTIM34SEL_Pos (8UL) -#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000300 */ #define RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR3_LPTIM1SEL_Pos (10UL) -#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ #define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ #define RCC_CCIPR3_ADCDACSEL_Pos (12UL) -#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00007000 */ #define RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00010000 */ -#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00020000 */ -#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR3_DAC1SEL_Pos (15UL) -#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00008000 */ #define RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk /*!< DAC1 Sample & Hold Clock Source Selection */ #define RCC_CCIPR3_ADF1SEL_Pos (16UL) #define RCC_CCIPR3_ADF1SEL_Msk (0x7UL << RCC_CCIPR3_ADF1SEL_Pos) /*!< 0x00070000 */ @@ -22759,7 +22759,7 @@ typedef struct #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17UL) -#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ #define USB_OTG_GRXSTSP_FRMNUM_Pos (21UL) #define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ @@ -22992,10 +22992,10 @@ typedef struct /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0UL) -#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ +#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ #define USB_OTG_GLPMCFG_LPMACK_Pos (1UL) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_BESL_Pos (2UL) #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ @@ -23034,7 +23034,7 @@ typedef struct #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ #define USB_OTG_GLPMCFG_ENBESL_Pos (28UL) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ @@ -24090,9 +24090,6 @@ typedef struct #define I2C_CR1_ANFOFF_Pos (12UL) #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST_Pos (13UL) -#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ -#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ #define I2C_CR1_TXDMAEN_Pos (14UL) #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u599xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u599xx.h index df50903cf7..3e91400195 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u599xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u599xx.h @@ -3925,11 +3925,11 @@ typedef struct /* Specific ADC4 */ #define ADC4_CFGR1_EXTSEL_Pos (6UL) -#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ -#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ -#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC4_CFGR1_CHSELRMOD_Pos (21UL) #define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ @@ -5727,7 +5727,7 @@ typedef struct #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /******************** RNG Nist Compliance Values *******************/ -#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_CR_NIST_VALUE (0x00F11F00U) #define RNG_HTCR_NIST_VALUE (0x92F3U) #define RNG_NSCR_NIST_VALUE (0x1609U) @@ -21564,33 +21564,33 @@ typedef struct #define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR3_SPI3SEL_Pos (3UL) -#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ #define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */ #define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ #define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR3_I2C3SEL_Pos (6UL) -#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ #define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000100 */ -#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ #define RCC_CCIPR3_LPTIM34SEL_Pos (8UL) -#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000300 */ #define RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR3_LPTIM1SEL_Pos (10UL) -#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ #define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ #define RCC_CCIPR3_ADCDACSEL_Pos (12UL) -#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00007000 */ #define RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00010000 */ -#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00020000 */ -#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR3_DAC1SEL_Pos (15UL) -#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00008000 */ #define RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk /*!< DAC1 Sample & Hold Clock Source Selection */ #define RCC_CCIPR3_ADF1SEL_Pos (16UL) #define RCC_CCIPR3_ADF1SEL_Msk (0x7UL << RCC_CCIPR3_ADF1SEL_Pos) /*!< 0x00070000 */ @@ -26593,7 +26593,7 @@ typedef struct #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17UL) -#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ #define USB_OTG_GRXSTSP_FRMNUM_Pos (21UL) #define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ @@ -26826,10 +26826,10 @@ typedef struct /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0UL) -#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ +#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ #define USB_OTG_GLPMCFG_LPMACK_Pos (1UL) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_BESL_Pos (2UL) #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ @@ -26868,7 +26868,7 @@ typedef struct #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ #define USB_OTG_GLPMCFG_ENBESL_Pos (28UL) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ @@ -27924,9 +27924,6 @@ typedef struct #define I2C_CR1_ANFOFF_Pos (12UL) #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST_Pos (13UL) -#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ -#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ #define I2C_CR1_TXDMAEN_Pos (14UL) #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5a5xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5a5xx.h index 2149ab0346..aabd7028fc 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5a5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5a5xx.h @@ -3850,11 +3850,11 @@ typedef struct /* Specific ADC4 */ #define ADC4_CFGR1_EXTSEL_Pos (6UL) -#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ -#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ -#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC4_CFGR1_CHSELRMOD_Pos (21UL) #define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ @@ -5652,7 +5652,7 @@ typedef struct #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /******************** RNG Nist Compliance Values *******************/ -#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_CR_NIST_VALUE (0x00F11F00U) #define RNG_HTCR_NIST_VALUE (0x92F3U) #define RNG_NSCR_NIST_VALUE (0x1609U) @@ -18400,33 +18400,33 @@ typedef struct #define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR3_SPI3SEL_Pos (3UL) -#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ #define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */ #define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ #define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR3_I2C3SEL_Pos (6UL) -#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ #define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000100 */ -#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ #define RCC_CCIPR3_LPTIM34SEL_Pos (8UL) -#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000300 */ #define RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR3_LPTIM1SEL_Pos (10UL) -#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ #define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ #define RCC_CCIPR3_ADCDACSEL_Pos (12UL) -#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00007000 */ #define RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00010000 */ -#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00020000 */ -#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR3_DAC1SEL_Pos (15UL) -#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00008000 */ #define RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk /*!< DAC1 Sample & Hold Clock Source Selection */ #define RCC_CCIPR3_ADF1SEL_Pos (16UL) #define RCC_CCIPR3_ADF1SEL_Msk (0x7UL << RCC_CCIPR3_ADF1SEL_Pos) /*!< 0x00070000 */ @@ -23421,7 +23421,7 @@ typedef struct #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17UL) -#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ #define USB_OTG_GRXSTSP_FRMNUM_Pos (21UL) #define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ @@ -23654,10 +23654,10 @@ typedef struct /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0UL) -#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ +#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ #define USB_OTG_GLPMCFG_LPMACK_Pos (1UL) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_BESL_Pos (2UL) #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ @@ -23696,7 +23696,7 @@ typedef struct #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ #define USB_OTG_GLPMCFG_ENBESL_Pos (28UL) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ @@ -24752,9 +24752,6 @@ typedef struct #define I2C_CR1_ANFOFF_Pos (12UL) #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST_Pos (13UL) -#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ -#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ #define I2C_CR1_TXDMAEN_Pos (14UL) #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5a9xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5a9xx.h index 56ee04942d..af1725b796 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5a9xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5a9xx.h @@ -4138,11 +4138,11 @@ typedef struct /* Specific ADC4 */ #define ADC4_CFGR1_EXTSEL_Pos (6UL) -#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ -#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ -#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC4_CFGR1_CHSELRMOD_Pos (21UL) #define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ @@ -5940,7 +5940,7 @@ typedef struct #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /******************** RNG Nist Compliance Values *******************/ -#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_CR_NIST_VALUE (0x00F11F00U) #define RNG_HTCR_NIST_VALUE (0x92F3U) #define RNG_NSCR_NIST_VALUE (0x1609U) @@ -22174,33 +22174,33 @@ typedef struct #define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR3_SPI3SEL_Pos (3UL) -#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ #define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */ #define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ #define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR3_I2C3SEL_Pos (6UL) -#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ #define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000100 */ -#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ #define RCC_CCIPR3_LPTIM34SEL_Pos (8UL) -#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000300 */ #define RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR3_LPTIM1SEL_Pos (10UL) -#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ #define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ #define RCC_CCIPR3_ADCDACSEL_Pos (12UL) -#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00007000 */ #define RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00010000 */ -#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00020000 */ -#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR3_DAC1SEL_Pos (15UL) -#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00008000 */ #define RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk /*!< DAC1 Sample & Hold Clock Source Selection */ #define RCC_CCIPR3_ADF1SEL_Pos (16UL) #define RCC_CCIPR3_ADF1SEL_Msk (0x7UL << RCC_CCIPR3_ADF1SEL_Pos) /*!< 0x00070000 */ @@ -27255,7 +27255,7 @@ typedef struct #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17UL) -#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ #define USB_OTG_GRXSTSP_FRMNUM_Pos (21UL) #define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ @@ -27488,10 +27488,10 @@ typedef struct /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0UL) -#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ +#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ #define USB_OTG_GLPMCFG_LPMACK_Pos (1UL) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_BESL_Pos (2UL) #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ @@ -27530,7 +27530,7 @@ typedef struct #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ #define USB_OTG_GLPMCFG_ENBESL_Pos (28UL) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ @@ -28586,9 +28586,6 @@ typedef struct #define I2C_CR1_ANFOFF_Pos (12UL) #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST_Pos (13UL) -#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ -#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ #define I2C_CR1_TXDMAEN_Pos (14UL) #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h index f1b0de1285..d7c2fb2be5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h @@ -3933,11 +3933,11 @@ typedef struct /* Specific ADC4 */ #define ADC4_CFGR1_EXTSEL_Pos (6UL) -#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ -#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ -#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC4_CFGR1_CHSELRMOD_Pos (21UL) #define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ @@ -5735,7 +5735,7 @@ typedef struct #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /******************** RNG Nist Compliance Values *******************/ -#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_CR_NIST_VALUE (0x00F11F00U) #define RNG_HTCR_NIST_VALUE (0xA715U) #define RNG_NSCR_NIST_VALUE (0x9049U) @@ -19383,33 +19383,33 @@ typedef struct #define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR3_SPI3SEL_Pos (3UL) -#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ #define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */ #define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ #define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR3_I2C3SEL_Pos (6UL) -#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ #define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000100 */ -#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ #define RCC_CCIPR3_LPTIM34SEL_Pos (8UL) -#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000300 */ #define RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR3_LPTIM1SEL_Pos (10UL) -#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ #define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ #define RCC_CCIPR3_ADCDACSEL_Pos (12UL) -#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00007000 */ #define RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00010000 */ -#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00020000 */ -#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR3_DAC1SEL_Pos (15UL) -#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00008000 */ #define RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk /*!< DAC1 Sample & Hold Clock Source Selection */ #define RCC_CCIPR3_ADF1SEL_Pos (16UL) #define RCC_CCIPR3_ADF1SEL_Msk (0x7UL << RCC_CCIPR3_ADF1SEL_Pos) /*!< 0x00070000 */ @@ -24440,7 +24440,7 @@ typedef struct #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17UL) -#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ #define USB_OTG_GRXSTSP_FRMNUM_Pos (21UL) #define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ @@ -24673,10 +24673,10 @@ typedef struct /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0UL) -#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ +#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ #define USB_OTG_GLPMCFG_LPMACK_Pos (1UL) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_BESL_Pos (2UL) #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ @@ -24715,7 +24715,7 @@ typedef struct #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ #define USB_OTG_GLPMCFG_ENBESL_Pos (28UL) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ @@ -25771,9 +25771,6 @@ typedef struct #define I2C_CR1_ANFOFF_Pos (12UL) #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST_Pos (13UL) -#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ -#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ #define I2C_CR1_TXDMAEN_Pos (14UL) #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f9xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f9xx.h index e8b2f21dbf..7ac3f55f15 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f9xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f9xx.h @@ -4053,11 +4053,11 @@ typedef struct /* Specific ADC4 */ #define ADC4_CFGR1_EXTSEL_Pos (6UL) -#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ -#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ -#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC4_CFGR1_CHSELRMOD_Pos (21UL) #define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ @@ -5855,7 +5855,7 @@ typedef struct #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /******************** RNG Nist Compliance Values *******************/ -#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_CR_NIST_VALUE (0x00F11F00U) #define RNG_HTCR_NIST_VALUE (0xA715U) #define RNG_NSCR_NIST_VALUE (0x9049U) @@ -22524,33 +22524,33 @@ typedef struct #define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR3_SPI3SEL_Pos (3UL) -#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ #define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */ #define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ #define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR3_I2C3SEL_Pos (6UL) -#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ #define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000100 */ -#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ #define RCC_CCIPR3_LPTIM34SEL_Pos (8UL) -#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000300 */ #define RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR3_LPTIM1SEL_Pos (10UL) -#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ #define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ #define RCC_CCIPR3_ADCDACSEL_Pos (12UL) -#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00007000 */ #define RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00010000 */ -#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00020000 */ -#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR3_DAC1SEL_Pos (15UL) -#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00008000 */ #define RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk /*!< DAC1 Sample & Hold Clock Source Selection */ #define RCC_CCIPR3_ADF1SEL_Pos (16UL) #define RCC_CCIPR3_ADF1SEL_Msk (0x7UL << RCC_CCIPR3_ADF1SEL_Pos) /*!< 0x00070000 */ @@ -27593,7 +27593,7 @@ typedef struct #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17UL) -#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ #define USB_OTG_GRXSTSP_FRMNUM_Pos (21UL) #define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ @@ -27826,10 +27826,10 @@ typedef struct /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0UL) -#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ +#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ #define USB_OTG_GLPMCFG_LPMACK_Pos (1UL) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_BESL_Pos (2UL) #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ @@ -27868,7 +27868,7 @@ typedef struct #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ #define USB_OTG_GLPMCFG_ENBESL_Pos (28UL) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ @@ -28924,9 +28924,6 @@ typedef struct #define I2C_CR1_ANFOFF_Pos (12UL) #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST_Pos (13UL) -#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ -#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ #define I2C_CR1_TXDMAEN_Pos (14UL) #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g7xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g7xx.h index 09d5069e36..f3fc5488e6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g7xx.h @@ -4146,11 +4146,11 @@ typedef struct /* Specific ADC4 */ #define ADC4_CFGR1_EXTSEL_Pos (6UL) -#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ -#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ -#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC4_CFGR1_CHSELRMOD_Pos (21UL) #define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ @@ -5948,7 +5948,7 @@ typedef struct #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /******************** RNG Nist Compliance Values *******************/ -#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_CR_NIST_VALUE (0x00F11F00U) #define RNG_HTCR_NIST_VALUE (0xA715U) #define RNG_NSCR_NIST_VALUE (0x9049U) @@ -19993,33 +19993,33 @@ typedef struct #define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR3_SPI3SEL_Pos (3UL) -#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ #define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */ #define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ #define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR3_I2C3SEL_Pos (6UL) -#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ #define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000100 */ -#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ #define RCC_CCIPR3_LPTIM34SEL_Pos (8UL) -#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000300 */ #define RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR3_LPTIM1SEL_Pos (10UL) -#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ #define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ #define RCC_CCIPR3_ADCDACSEL_Pos (12UL) -#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00007000 */ #define RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00010000 */ -#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00020000 */ -#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR3_DAC1SEL_Pos (15UL) -#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00008000 */ #define RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk /*!< DAC1 Sample & Hold Clock Source Selection */ #define RCC_CCIPR3_ADF1SEL_Pos (16UL) #define RCC_CCIPR3_ADF1SEL_Msk (0x7UL << RCC_CCIPR3_ADF1SEL_Pos) /*!< 0x00070000 */ @@ -25102,7 +25102,7 @@ typedef struct #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17UL) -#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ #define USB_OTG_GRXSTSP_FRMNUM_Pos (21UL) #define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ @@ -25335,10 +25335,10 @@ typedef struct /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0UL) -#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ +#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ #define USB_OTG_GLPMCFG_LPMACK_Pos (1UL) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_BESL_Pos (2UL) #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ @@ -25377,7 +25377,7 @@ typedef struct #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ #define USB_OTG_GLPMCFG_ENBESL_Pos (28UL) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ @@ -26433,9 +26433,6 @@ typedef struct #define I2C_CR1_ANFOFF_Pos (12UL) #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST_Pos (13UL) -#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ -#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ #define I2C_CR1_TXDMAEN_Pos (14UL) #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g9xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g9xx.h index 727e7e1747..666ddaeb27 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g9xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g9xx.h @@ -4266,11 +4266,11 @@ typedef struct /* Specific ADC4 */ #define ADC4_CFGR1_EXTSEL_Pos (6UL) -#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ -#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ -#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC4_CFGR1_CHSELRMOD_Pos (21UL) #define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ @@ -6068,7 +6068,7 @@ typedef struct #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /******************** RNG Nist Compliance Values *******************/ -#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_CR_NIST_VALUE (0x00F11F00U) #define RNG_HTCR_NIST_VALUE (0xA715U) #define RNG_NSCR_NIST_VALUE (0x9049U) @@ -23134,33 +23134,33 @@ typedef struct #define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR3_SPI3SEL_Pos (3UL) -#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ #define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */ #define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ #define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR3_I2C3SEL_Pos (6UL) -#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ #define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000100 */ -#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ #define RCC_CCIPR3_LPTIM34SEL_Pos (8UL) -#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000300 */ #define RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR3_LPTIM1SEL_Pos (10UL) -#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x0000E000 */ +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ #define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00002000 */ -#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ #define RCC_CCIPR3_ADCDACSEL_Pos (12UL) -#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00007000 */ #define RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */ -#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00010000 */ -#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00020000 */ -#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR3_DAC1SEL_Pos (15UL) -#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00008000 */ #define RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk /*!< DAC1 Sample & Hold Clock Source Selection */ #define RCC_CCIPR3_ADF1SEL_Pos (16UL) #define RCC_CCIPR3_ADF1SEL_Msk (0x7UL << RCC_CCIPR3_ADF1SEL_Pos) /*!< 0x00070000 */ @@ -28255,7 +28255,7 @@ typedef struct #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17UL) -#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ #define USB_OTG_GRXSTSP_FRMNUM_Pos (21UL) #define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ @@ -28488,10 +28488,10 @@ typedef struct /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0UL) -#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ +#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ #define USB_OTG_GLPMCFG_LPMACK_Pos (1UL) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_BESL_Pos (2UL) #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ @@ -28530,7 +28530,7 @@ typedef struct #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ #define USB_OTG_GLPMCFG_ENBESL_Pos (28UL) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ @@ -29586,9 +29586,6 @@ typedef struct #define I2C_CR1_ANFOFF_Pos (12UL) #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST_Pos (13UL) -#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ -#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ #define I2C_CR1_TXDMAEN_Pos (14UL) #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h index 33e4ee8e3c..fd98b8d198 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h @@ -89,11 +89,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number 1.4.2 + * @brief CMSIS Device version number 1.4.3 */ #define __STM32U5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32U5_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ -#define __STM32U5_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ +#define __STM32U5_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ #define __STM32U5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U5_CMSIS_VERSION ((__STM32U5_CMSIS_VERSION_MAIN << 24U)\ |(__STM32U5_CMSIS_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/README.md b/system/Drivers/CMSIS/Device/ST/STM32U5xx/README.md index 07eb2a7f66..0d5de49860 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/README.md +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/README.md @@ -1,6 +1,6 @@ # STM32CubeU5 CMSIS Device MCU Component -![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/cmsis_device_u5.svg?color=brightgreen) +![tag](https://img.shields.io/badge/tag-v1.4.3-brightgreen.svg) ## Overview @@ -35,4 +35,4 @@ The full **STM32CubeU5** MCU package is available [here](https://github.com/STMi ## Troubleshooting -Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.html index efe80f81e1..149180cc63 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.html @@ -30,10 +30,27 @@

Release Notes for  STM32U5xx C

Update History

- +

Main Changes

    +
  • Align RNG NIST compliance values with the RNG register values defined in the application note.
    • +
  • Remove the I2C_CR1_SWRST bit macros.
    • +
  • Set stack limit (MSPLIM) in CMSIS Device templates.
    • +
  • Fix wrong comments related to RCC_CCIPR3 masks in stm32u5x5xx.h files.
    • +
  • Fix wrong comments at the head of startup_stm32u535/45xx.s files.
    • +
+

Backward Compatibility

+
    +
  • N/A
    • +
+
+
+
+ +
+

Main Changes

+
  • General updates to fix known defects and implementation enhancements.
  • Remove the internal CRC registers from defined CMSIS CRC structure (CRC_TypeDef).
  • Allow redefinition of the macro ‘VECT_TAB_OFFSET’ externally from the IDE, makefile, or command line.
    • @@ -41,7 +58,7 @@

    Main Changes

  • Add specific gcc linker files for STM32U5A5xx devices.
  • Increase the total SRAM size in STM32U5G9 linker file template to include SRAM6 size.
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -50,14 +67,14 @@

Backward Compatibility

-

Main Changes

+

Main Changes

  • General updates to fix known defects and implementation enhancements.
  • Fix TAMP_CR3_ITAMP7NOER bit definition to be aligned with reference manual.
  • Add missing USB_OTG_GINTSTS_RSTDET bit definition.
  • Align USB OTG bit definition with reference manual.
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -66,7 +83,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Add Bits definition for RNG_NSCR register for RNG noise source control
    • @@ -79,7 +96,7 @@

    Main Changes

  • Fix wrong declaration of g_pfnVectors size in GCC startup_stm32u5XXxx.s files
  • Update linker files to properly mark sections readonly for GCC12
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -88,12 +105,12 @@

Backward Compatibility

-

Main Changes

+

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Update STM32U5A5xx devices list with STM32U5A5QII3Q under “stm32u5xx.h” file
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -102,7 +119,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Support of new STM32U5F9xx, STM32U5G9xx, STM32U5F7xx and STM32U5G7xx devices: @@ -112,7 +129,7 @@

    Main Changes

  • Add linker files for EWARM and STM32CubeIDE toolchains of STM32U5F9xx/STM32U5G9xx/STM32U5F7xx/STM32U5G7xx devices
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -121,7 +138,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Support of stm32u535xx and stm32u545xx devices: @@ -174,7 +191,7 @@

    Main Changes

  • Rename ADC4_PW_VREFSECSMP to ADC4_PWRR_VREFSECSMP
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -183,7 +200,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

  • CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
      @@ -213,7 +230,7 @@

      Main Changes

      -

      Main Changes

      +

      Main Changes

      • Rename OTG_FS_BASE_NS to USB_OTG_FS_BASE_NS define
      • Rename OTG_FS_BASE_S to USB_OTG_FS_BASE_S define
        • @@ -225,7 +242,7 @@

        Main Changes

        -

        Main Changes

        +

        Main Changes

        • First official release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
        diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.md b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.md new file mode 100644 index 0000000000..5cc45c1083 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.md @@ -0,0 +1,228 @@ + + +# Release Notes for \ STM32U5xx CMSIS +Copyright © 2021\ STMicroelectronics\ + +[![ST logo](_htmresc/st_logo_2020.png)](https://www.st.com) + + + +# __Update History__ + + +
        + +## Main Changes + - Align RNG NIST compliance values with the RNG register values defined in the application note. + - Remove the I2C_CR1_SWRST bit macros. + - Set stack limit (MSPLIM) in CMSIS Device templates. + - Fix wrong comments related to RCC_CCIPR3 masks in stm32u5x5xx.h files. + - Fix wrong comments at the head of startup_stm32u535/45xx.s files. + +## Backward Compatibility +- N/A + +
        + + +
        + +## Main Changes + - General updates to fix known defects and implementation enhancements. + - Remove the internal CRC registers from defined CMSIS CRC structure (CRC_TypeDef). + - Allow redefinition of the macro 'VECT_TAB_OFFSET' externally from the IDE, makefile, or command line. + - Align the JPEG base address in Secure mode with the one defined for Non-Secure mode. + - Add specific gcc linker files for STM32U5A5xx devices. + - Increase the total SRAM size in STM32U5G9 linker file template to include SRAM6 size. + +## Backward Compatibility +- N/A + +
        + + +
        + +## Main Changes + - General updates to fix known defects and implementation enhancements. + - Fix TAMP_CR3_ITAMP7NOER bit definition to be aligned with reference manual. + - Add missing USB_OTG_GINTSTS_RSTDET bit definition. + - Align USB OTG bit definition with reference manual. + + +## Backward Compatibility +- N/A + +
        + + +
        + +## Main Changes + +**CMSIS Device** Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual) + + - Add Bits definition for RNG_NSCR register for RNG noise source control + - Rename RTC_CR_ALRAOCLR to RTC_CR_ALRAFCLR definition + - Rename RTC_CR_ALRBOCLR to RTC_CR_ALRBFCLR definition + - Remove SYSCFG_UCPD_CC1ENRXFILTER and SYSCFG_UCPD_CC2ENRXFILTER defines + - Remove COMP2 dependency in "stm32u545xx.h" and "stm32u545xx.h" files by removing TIM1_AF1_BKCMP2E, TIM1_AF1_BKCMP2P, TIM1_AF2_BK2CMP2E and TIM1_AF2_BK2CMP2P defines + - Remove PWR_PDCRI register in "stm32u545xx.h" and "stm32u545xx.h" files by removing PWR_PDCRI_PD0, PWR_PDCRI_PD1, PWR_PDCRI_PD2, PWR_PDCRI_PD3, PWR_PDCRI_PD4, PWR_PDCRI_PD5, PWR_PDCRI_PD6 and PWR_PDCRI_PD0 defines + - Update **partition_stm32u5XXxx.h** files headers + - Fix wrong declaration of g_pfnVectors size in GCC **startup_stm32u5XXxx.s** files + - Update linker files to properly mark sections readonly for GCC12 + + +## Backward Compatibility +- N/A + +
        + + +
        + +## Main Changes + +**CMSIS Device** Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual) + + - Update STM32U5A5xx devices list with STM32U5A5QII3Q under "stm32u5xx.h” file + + + +## Backward Compatibility +- N/A + +
        + + + +
        + +## Main Changes + +**CMSIS Device** Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual) + +- **Support of new STM32U5F9xx, STM32U5G9xx, STM32U5F7xx and STM32U5G7xx devices**: + - Add “stm32u5f9xx.h”, “stm32u5g9xx.h”, “stm32u5f7xx.h” and “stm32u5g7xx.h” files + - Add startup files “startup_stm32u5f9xx.s”, “startup_stm32u5g9xx.s”, “startup_stm32u5f7xx.s” and “startup_stm32u5g7xx.s” for EWARM, STM32CubeIDE and MDK-ARM toolchains + - Add linker files for EWARM and STM32CubeIDE toolchains of STM32U5F9xx/STM32U5G9xx/STM32U5F7xx/STM32U5G7xx devices + + +## Backward Compatibility +- N/A + +
        + + + +
        + +## Main Changes + +**CMSIS Device** Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual) + +- **Support of stm32u535xx and stm32u545xx devices**: + - Add "stm32u535xx.h" and "stm32u545xx.h" files + - Add startup files "startup_stm32u535xx.s" and "startup_stm32u545xx.s" for EWARM and STM32CUBEIDE toolchains + - Add EWARM and STM32CUBEIDE linker files for all devices for legacy and for TrustZone based application + +- **Registers and bit field definitions updates**: + + - Add USB Dual Role Device FS Endpoint registers: + - Add Bits definition for USB_DRD_CNTR register + - Add Bits definition for USB_DRD_ISTR register + - Add Bits definition for USB_DRD_FNR register + - Add Bits definition for USB_DRD_DADDR register + - Add Bit definition for USB_DRD_BTABLE register + - Add Bit definition for LPMCSR register + - Add Bits definition for USB_DRD_BCDR register + - Add Bits definition for USB_DRD_CHEP register + - Add USB_IRQn interrupt + - Add USB_OTG_GCCFG_PULLDOWNEN define + - Add LSECSSD and MSI_PLL_UNLOCK global interrupts + - Add USART_DMAREQUESTS_SW_WA define + - Add DBGMCU_APB1FZR2_DBG_I2C5_STOP and DBGMCU_APB1FZR2_DBG_I2C6_STOP defines + - Remove DBGMCU_APB1FZR2_DBG_FDCAN_STOP define + - Add AES_IER_RNGEIE AES_ICR_RNGEIF and AES_ISR_RNGEIF defines + - Add DMA2D_TRIGGER_SUPPORT define + - Rename Bit definition for EXTI_SECENR1 register to EXTI_SECCFGR1 register + - Rename Bit definition for EXTI_PRIVENR1 register to EXTI_PRIVCFGR1 register + - Add Bit definition for EXTI_LOCKR register + - Add EXTI_RTSR1_RT25, EXTI_FTSR1_FT25, EXTI_SWIER1_SWI25, EXTI_RPR1_RPIF25, EXTI_FPR1_FPIF25, EXTI_IMR1_IM25 and EXTI_EMR1_EM25 defines + - Add COMP_WINDOW_MODE_SUPPORT define + - Add Bit definition for SYSCFG_OTGHSPHYTUNER2 register + - Add SYSCFG_CFGR1_SRAMCACHED define + - Add UCPD configuration register 3 + - Add RCC_APB2RSTR_USBRST define + - Add RCC_APB2ENR_USBEN define + - Add RCC_APB2SMENR_USBSMEN define + - Add IS_SPI_GRP1_INSTANCE and IS_SPI_GRP2_INSTANCE macros + - Add IS_COMP_ALL_INSTANCE macro + - Add IS_HCD_ALL_INSTANCE and IS_PCD_ALL_INSTANCE macro + - Add PWR_CR1_FORCE_USBPWR and PWR_VOSR_VDD11USBDIS defines + - Rename OCTOSPI_CR_DQM to XSPI_CR_DMM + - Rename OCTOSPI_CR_FSEL to XSPI_OCTOSPI_CR_MSEL + - Rename ADC4_PW_AUTOFF to ADC4_PWRR_AUTOFF + - Rename ADC4_PW_DPD to ADC4_PWRR_DPD + - Rename ADC4_PW_VREFPROT to ADC4_PWRR_VREFPROT + - Rename ADC4_PW_VREFSECSMP to ADC4_PWRR_VREFSECSMP + +## Backward Compatibility +- N/A + +
        + + + +
        + +## Main Changes + +- **CMSIS Device** Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual) + - Add the support of STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices + - Define XSPI_TypeDef as alias to OCTOSPI_TypeDef and HSPI_TypeDef + - Define XSPIM_TypeDef as alias to OCTOSPIM_TypeDef + - Update XSPI bit definition to alias OCTOSPI and HSPI bits + - Add OPAMP12_COMMON_NS, OPAMP12_COMMON_S, OPAMP12_COMMON, OPAMP12_COMMON_BASE defines + - Update OPAMP_Common_TypeDef to align with reference manual + - Add the SRAM4 memory definition in all STM32CubeIDE flashloader files + - Update the flash size define to support: + - STM32U575/STM32U585: 2Mbytes flash devices + - STM32U595/STM32U5A5/STM32U599/STM32U5A9: 4Mbytes flash devices + - Rename PVD_AVD_IRQHandler to PVD_PVM_IRQHandler in all start-up files + - Rename RCC_AHB2RSTR1_ADC1RST to RCC_AHB2RSTR1_ADC12RST + - Rename RCC_AHB2ENR1_ADC1EN to RCC_AHB2ENR1_ADC12EN + - Rename RCC_AHB2SMENR1_ADC1SMEN to RCC_AHB2SMENR1_ADC12SMEN + - Rename RCC_CCIPR1_CLK48MSEL to RCC_CCIPR1_ICLKSEL + - Rename RCC_SECCFGR_CLK48MSEC to RCC_SECCFGR_ICLKSEC + - Add TIM3 and TIM4 are missing in IS_TIM_32B_COUNTER_INSTANCE macro definition + +
        + + +
        + +## Main Changes + +- Rename OTG_FS_BASE_NS to USB_OTG_FS_BASE_NS define +- Rename OTG_FS_BASE_S to USB_OTG_FS_BASE_S define +- Add LSI_STARTUP_TIME define +- Fix wrong IRQn name in partition_stm32u5xx.h + + +
        + + + +
        + +## Main Changes + +- First official release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual) + + +
        + + +For complete documentation on STM32 Microcontrollers , +visit: http://www.st.com/stm32 \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH.ld index c72c0b7e86..fe7b860e0d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH_ns.ld index 6e456b6753..10d86b08b4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH_ns.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH_s.ld index 801e17b555..edce13c425 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH_s.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM.ld index f21cecf0be..3a2c1f53ec 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM.ld @@ -36,6 +36,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM_ns.ld index 5f94a00bf3..064ce669a9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM_ns.ld @@ -36,6 +36,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM_s.ld index 7d1b0f7bc7..ca1aea1ecd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM_s.ld @@ -36,6 +36,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH.ld index e71a045604..f092988487 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH_ns.ld index 72cfba3ca1..9b5effc2a0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH_ns.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH_s.ld index 08e106564b..7736e0c571 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH_s.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM.ld index 5380959ba3..6c6fd1c9d3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM.ld @@ -36,6 +36,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM_ns.ld index f08d2e677c..dc0060cf88 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM_ns.ld @@ -36,6 +36,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM_s.ld index 49f0d35367..06afd0e016 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM_s.ld @@ -36,6 +36,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH.ld index 3393c8bf9f..f6df91b8ff 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_ns.ld index e45a87c5d1..a633dd86a1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_ns.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_s.ld index 40a828a252..68c458037e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_s.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM.ld index c4a2af226d..83cbb9f60a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM_ns.ld index 2b006d447e..3ae91219b9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM_ns.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM_s.ld index d54ffd24bc..16d582a528 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM_s.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH.ld index 7bfff4f4b8..148ad2d6d8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH_ns.ld index 8c6c94b55a..2aaf06b6b4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH_ns.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH_s.ld index 70782a7271..d6267c0b32 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH_s.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM.ld index 5d802538fc..f3370cd653 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM_ns.ld index 047c640eb2..37daa545c4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM_ns.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM_s.ld index 1302e9fbe8..fa3b8a89e9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM_s.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH.ld index 643befe6a1..8a561c91a5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH_ns.ld index 8c191d6e74..24afc0bab1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH_ns.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH_s.ld index aa02d21efb..1d14673287 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH_s.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM.ld index cad9a002fe..0c1cd692d7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM_ns.ld index 48cd502e37..a79adac940 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM_ns.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM_s.ld index db39f0db47..87d5a82f6c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM_s.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH.ld index 38155f460c..0ee352f0f6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH_ns.ld index aeff9959fd..1775f4b12e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH_ns.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH_s.ld index 407171a909..27f0701054 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH_s.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM.ld index ca59355c44..1d0b279c5d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM_ns.ld index 881f517c51..7eb672fb8a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM_ns.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM_s.ld index 2face12bec..b0a2876922 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM_s.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH.ld index f0bb40cd54..3d85faa4f5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH_ns.ld index e8e2b5c79d..a27b02752a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH_ns.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH_s.ld index 469ad194bb..e5e5b89707 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH_s.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM.ld index f87e1d7ff9..63900e8474 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM.ld @@ -36,6 +36,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM_ns.ld index 641948f7bf..4d1fced73e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM_ns.ld @@ -36,6 +36,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM_s.ld index 4f4f7a007c..de40caa65a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM_s.ld @@ -36,6 +36,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH.ld index eb60f5cde5..f0ea0f5b2a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH_ns.ld index d1701b100c..331b7a104a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH_ns.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH_s.ld index a23797ccf3..3323b60adb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH_s.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM.ld index eb64b0fab4..c1802b854a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM_ns.ld index dbe26e1415..c1963ffde6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM_ns.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM_s.ld index ca8c9ab27a..3ab73b98a7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM_s.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH.ld index c7286bd5f9..f6bcdc0489 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH_ns.ld index cce9afa7ff..80dd2c507a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH_ns.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH_s.ld index ed059605a2..6139fea575 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH_s.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM.ld index 95c5c2616a..8ac7aa04b6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM_ns.ld index 68ff41c003..d26e52ff21 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM_ns.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM_s.ld index 360af3c8dd..9231c2958c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM_s.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH.ld index 019958c1bb..b28beaf0b4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH_ns.ld index 39268b20e8..0dfc53b96f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH_ns.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH_s.ld index 6efd7ecfaf..eb4e4f4266 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH_s.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM.ld index 4b29003ad5..42c816f795 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM_ns.ld index fe10e21230..0f022556d6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM_ns.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM_s.ld index 23bfbb24c0..b02ba44bb2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM_s.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH.ld index 7763098984..a9ba8fb64e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH_ns.ld index 968b831346..9b44bf4f48 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH_ns.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH_s.ld index 6e0517c440..e1b402b4dd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH_s.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM.ld index 30507f4eca..73e22b4d8d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM_ns.ld index 66e8148ab7..bf871ccfda 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM_ns.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM_s.ld index 1961207118..8dd3d6de07 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM_s.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH.ld index e567b8cde2..069193af6a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_ns.ld index a61a1d5e19..d0d840123f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_ns.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_s.ld index d93c2da0a4..6e44ac5d1d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_s.ld @@ -38,6 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM.ld index 9c4d76d7e8..9f43637588 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_ns.ld index 0b950afe0c..31f65ef665 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_ns.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_s.ld index c4e5f228a3..8cda3e37de 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_s.ld @@ -37,6 +37,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u535xx.s b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u535xx.s index 80aa951a9a..babd20953c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u535xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u535xx.s @@ -1,26 +1,29 @@ /** - ****************************************************************************** - * @file startup_stm32u535retx.s - * @author Auto-generated by STM32CubeIDE - * @brief STM32U545RETx device vector table for GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file startup_stm32u535xx.s + * @author MCD Application Team + * @brief STM32U535xx device vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M33 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ .syntax unified .cpu cortex-m33 diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u545xx.s b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u545xx.s index ff2e215f24..9caee99c47 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u545xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u545xx.s @@ -1,26 +1,29 @@ /** - ****************************************************************************** - * @file startup_stm32u545retx.s - * @author Auto-generated by STM32CubeIDE - * @brief STM32U545RETx device vector table for GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file startup_stm32u545xx.s + * @author MCD Application Team + * @brief STM32U545xx device vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M33 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ .syntax unified .cpu cortex-m33 diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index a436597777..ab1cad5be4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -18,7 +18,7 @@ * STM32MP1: 1.7.0 * STM32U0: 1.3.0 * STM32U3: 1.4.0 - * STM32U5: 1.4.2 + * STM32U5: 1.4.3 * STM32WB: 1.12.3 * STM32WB0: 1.4.0 * STM32WBA: 1.9.0 diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index cc77833a0f..35650fcc17 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -361,7 +361,9 @@ extern "C" { #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI -#endif +#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) +#define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI +#endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4 */ @@ -1915,7 +1917,11 @@ extern "C" { #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +#define PWR_PVM_USB PWR_PVM_ENABLE +#define PWR_FLAG_PVMOUSB PWR_FLAG_PVMOVDDIO2 +#define PWR_FLAG_PVMO_USB PWR_FLAG_PVMO_VDDIO2 +#endif /* STM32G0C1xx || STM32G0B1xx */ #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING @@ -2028,6 +2034,9 @@ extern "C" { #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK #endif +#if defined (STM32H7RS) +#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO PWR_SMPS_1V8_SUPPLIES_EXT_VDD_SUPPLIES_LDO +#endif /** * @} @@ -2149,6 +2158,20 @@ extern "C" { #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER +#if defined(STM32H7RS) || defined(STM32N6) +#define FMC_SWAPBMAP_DISABLE FMC_SWAPBANK_MODE0 +#define FMC_SWAPBMAP_SDRAM_SRAM FMC_SWAPBANK_MODE1 +#define HAL_SetFMCMemorySwappingConfig HAL_FMC_SetBankSwapConfig +#define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig +#endif /* STM32H7RS || STM32N6 */ + +#if defined(STM32N6) +/* alias CMSIS */ +#define CSI_PCR_PWRDOWN_Pos CSI_PCR_NPWRDOWN_Pos +#define CSI_PCR_PWRDOWN_Msk CSI_PCR_NPWRDOWN_Msk +#define CSI_PCR_PWRDOWN CSI_PCR_NPWRDOWN +#endif /* STM32N6 */ + /** * @} */ @@ -3701,9 +3724,7 @@ extern "C" { #define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK #endif -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \ - defined(STM32U0) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3952,10 +3973,7 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ - defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || \ - defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc.h index d52c9a44c4..0e2ca2b1b3 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc.h @@ -2055,6 +2055,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @note ADC conversion data full-scale corresponds to voltage range * determined by analog voltage references Vref+ and Vref- * (refer to reference manual). + * @param __ADC_INSTANCE__ ADC instance * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_14B * @arg @ref ADC_RESOLUTION_12B @@ -2066,8 +2067,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n * @retval ADC conversion data full-scale digital value */ -#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) +#define __HAL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__) \ + __LL_ADC_DIGITAL_SCALE((__ADC_INSTANCE__), (__ADC_RESOLUTION__)) /** * @brief Helper macro to convert the ADC conversion data from diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_crc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_crc.h index 1ab7df8f21..a454b7f111 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_crc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_crc.h @@ -308,8 +308,8 @@ void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions * @{ */ -uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); -uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength); +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength); /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp.h index 015418e3a3..6817e1d64f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp.h @@ -502,7 +502,8 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF))?SET:RESET) : \ ((__FLAG__) == CRYP_FLAG_RWEIF )?((((__HANDLE__)->Instance->ISR \ & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF))?SET:RESET) : \ - ((((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF)))?SET:RESET) + ((((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == \ + (CRYP_FLAG_CCF)))?SET:RESET) /** @brief Clear the CRYP pending status flag. * @param __HANDLE__ specifies the CRYP handle. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma2d.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma2d.h index 48eba8a5ab..eb9c13df62 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma2d.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma2d.h @@ -658,7 +658,7 @@ uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d); #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) -#if defined(DMA2D_FGPFCCR_CSS) +#if defined(DMA2D_FGPFCCR_CSS) #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash.h index d54402d2da..bfdc0e183b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash.h @@ -903,6 +903,12 @@ void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); */ HAL_StatusTypeDef HAL_FLASH_Unlock(void); HAL_StatusTypeDef HAL_FLASH_Lock(void); +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +HAL_StatusTypeDef HAL_FLASH_Unlock_NS(void); +HAL_StatusTypeDef HAL_FLASH_Lock_NS(void); +HAL_StatusTypeDef HAL_FLASH_Unlock_S(void); +HAL_StatusTypeDef HAL_FLASH_Lock_S(void); +#endif /* __ARM_FEATURE_CMSE */ /* Option bytes control */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hcd.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hcd.h index dc09856235..0489e175a6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hcd.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hcd.h @@ -163,6 +163,8 @@ typedef struct */ #define HCD_PHY_ULPI 1U #define HCD_PHY_EMBEDDED 2U +#define HCD_HS_PHY_EMBEDDED 3U +#define HCD_PHY_UTMI 3U /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h index 06358af1a6..975a378734 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h @@ -573,18 +573,14 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin /** * @brief Disable the LPTIM peripheral. * @param __HANDLE__ LPTIM handle + * @note The following sequence is required to solve LPTIM disable HW limitation. + * Please check Errata Sheet ES0335 for more details under "MCU may remain + * stuck in LPTIM interrupt when entering Stop mode" section. + * @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to + * check for TIMEOUT. * @retval None */ -#define __HAL_LPTIM_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCMR1 & LPTIM_CCMR1_CC1E) == 0UL) \ - { \ - if(((__HANDLE__)->Instance->CCMR1 & LPTIM_CCMR1_CC2E) == 0UL) \ - { \ - (__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE); \ - } \ - } \ - } while(0) +#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__) /** * @brief Start the LPTIM peripheral in Continuous mode. @@ -977,9 +973,9 @@ void HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef *hlptim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** * @} @@ -1195,6 +1191,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); /** @defgroup LPTIM_Private_Functions LPTIM Private Functions * @{ */ +void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim); /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ltdc_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ltdc_ex.h index 811a030744..64cfc19b88 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ltdc_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ltdc_ex.h @@ -27,6 +27,8 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32u5xx_hal_def.h" +#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED) + #if defined (LTDC) && defined (DSI) #include "stm32u5xx_hal_dsi.h" @@ -76,6 +78,8 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD #endif /* LTDC && DSI */ +#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */ + #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h index 8ad417eb6d..728fcb9e48 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h @@ -832,6 +832,7 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_Au /* OSPI memory-mapped mode functions */ HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg); +uint32_t HAL_OSPI_IsMemoryMapped(const OSPI_HandleTypeDef *hospi); /* Callback functions in non-blocking modes ***********************************/ void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h index a7958a58fc..65f30890b8 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h @@ -119,7 +119,6 @@ typedef struct uint32_t BESL; uint32_t FrameNumber; /*!< Store Current Frame number */ - uint32_t lpm_active; /*!< Enable or disable the Link Power Management . This parameter can be set to ENABLE or DISABLE */ @@ -175,6 +174,7 @@ typedef struct */ #define PCD_PHY_ULPI 1U #define PCD_PHY_EMBEDDED 2U +#define PCD_HS_PHY_EMBEDDED 3U #define PCD_PHY_UTMI 3U /** * @} @@ -225,7 +225,6 @@ typedef struct #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\ &= (uint16_t)(~(__INTERRUPT__))) #endif /* defined (USB_DRD_FS) */ - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h index 64a2ee38bc..4d1e3bb3e7 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h @@ -772,6 +772,10 @@ typedef struct #endif /* GPU2D */ #if defined(DCACHE2) +/** + * @note This clock should be enabled only when GPU2D is in use, + * because DCACHE2 operates in conjunction with GPU2D. + */ #define __HAL_RCC_DCACHE2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN); \ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h index 807d02f26b..014b0398a3 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h @@ -56,7 +56,7 @@ typedef struct uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can be a value of @ref RNGEx_Clock_Divider_Factor */ - uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a + uint32_t NistCompliance; /*!< NIST compliance configuration.This parameter can be a value of @ref RNGEx_NIST_Compliance */ uint32_t AutoReset; /*!< automatic reset When a noise source error occurs value of @ref RNGEx_Auto_Reset */ @@ -117,8 +117,8 @@ typedef struct /** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ -#define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ -#define RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */ +#define RNG_NIST_COMPLIANT (0x00000000UL) /*!< Default NIST compliant configuration*/ +#define RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST compliant configuration */ /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc_ex.h index 0514e64f8b..705a560da7 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc_ex.h @@ -545,10 +545,10 @@ typedef struct #define RTC_FLAG_INT_TAMP_11 TAMP_SR_ITAMP11F #define RTC_FLAG_INT_TAMP_12 TAMP_SR_ITAMP12F #define RTC_FLAG_INT_TAMP_13 TAMP_SR_ITAMP13F -#define RTC_FLAG_INT_TAMP_ALL (RTC_FLAG_INT_TAMP_1 | RTC_FLAG_INT_TAMP2 |\ - RTC_FLAG_INT_TAMP_3 | RTC_FLAG_INT_TAMP5 |\ - RTC_FLAG_INT_TAMP_6 | RTC_FLAG_INT_TAMP7 |\ - RTC_FLAG_INT_TAMP_8 | RTC_FLAG_INT_TAMP9 |\ +#define RTC_FLAG_INT_TAMP_ALL (RTC_FLAG_INT_TAMP_1 | RTC_FLAG_INT_TAMP_2 |\ + RTC_FLAG_INT_TAMP_3 | RTC_FLAG_INT_TAMP_5 |\ + RTC_FLAG_INT_TAMP_6 | RTC_FLAG_INT_TAMP_7 |\ + RTC_FLAG_INT_TAMP_8 | RTC_FLAG_INT_TAMP_9 |\ RTC_FLAG_INT_TAMP_11|RTC_FLAG_INT_TAMP_12|\ RTC_FLAG_INT_TAMP_13) /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h index 7325f180af..a4b7ca81d9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h @@ -1272,7 +1272,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) * divided by the smallest oversampling used on the USART (i.e. 8) * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 20000000U) +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 20000000U) /** @brief Check UART assertion time. * @param __TIME__ 5-bit value assertion time. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_wwdg.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_wwdg.h index 4aac1b5258..b5bb6068c9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_wwdg.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_wwdg.h @@ -191,7 +191,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle + * @param __HANDLE__ WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h index cd2b362b5f..ebae7687e2 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h @@ -80,8 +80,6 @@ extern "C" { #define DMA_CHANNEL14_OFFSET (0x00000750UL) #define DMA_CHANNEL15_OFFSET (0x000007D0UL) -#define LL_DMA_CHANNEL_MAX LL_DMA_CHANNEL_15 - /* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */ static const uint32_t LL_DMA_CH_OFFSET_TAB[] = { @@ -1644,8 +1642,7 @@ __STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint3 uint32_t LinkedListBaseAddr) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLBAR, - DMA_CLBAR_LBA, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA, (LinkedListBaseAddr & DMA_CLBAR_LBA)); } @@ -1714,7 +1711,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef *DMAx, u __STATIC_INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration); } @@ -1968,7 +1965,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR1, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | DMA_CTR1_SINC | \ DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); } @@ -2004,7 +2001,7 @@ __STATIC_INLINE void LL_DMA_ConfigBurstLength(const DMA_TypeDef *DMAx, uint32_t uint32_t DestBurstLength) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR1, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \ (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1)); } @@ -3068,7 +3065,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ), Configuration); } @@ -3105,8 +3102,7 @@ __STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint3 __STATIC_INLINE void LL_DMA_SetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, - DMA_CTR2_TCEM, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM, TransferEventMode); } @@ -3209,8 +3205,7 @@ __STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, - DMA_CTR2_TRIGPOL)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL)); } /** @@ -3245,8 +3240,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint __STATIC_INLINE void LL_DMA_SetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, - DMA_CTR2_TRIGM, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM, TriggerMode); } @@ -3597,8 +3591,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, - DMA_CTR2_REQSEL, Request); + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request); } /** @@ -3775,8 +3768,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, - DMA_CTR2_REQSEL)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL)); } /** @@ -3905,8 +3897,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint3 __STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, - DMA_CTR2_TRIGSEL, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL, (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL); } @@ -4035,7 +4026,7 @@ __STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos); } @@ -4062,7 +4053,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC | DMA_CBR1_BRSDEC | DMA_CBR1_DDEC | DMA_CBR1_SDEC, Configuration); } @@ -4087,7 +4078,7 @@ __STATIC_INLINE void LL_DMA_ConfigBlkCounters(const DMA_TypeDef *DMAx, uint32_t uint32_t BlkRptCount) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, (DMA_CBR1_BNDT | DMA_CBR1_BRC), (BlkDataLength | (BlkRptCount << DMA_CBR1_BRC_Pos))); } @@ -4110,8 +4101,7 @@ __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uin uint32_t BlkRptDestAddrUpdate) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, - DMA_CBR1_BRDDEC, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC, BlkRptDestAddrUpdate); } @@ -4132,8 +4122,7 @@ __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uin __STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, - DMA_CBR1_BRDDEC)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC)); } /** @@ -4155,8 +4144,7 @@ __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint uint32_t BlkRptSrcAddrUpdate) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, - DMA_CBR1_BRSDEC, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC, BlkRptSrcAddrUpdate); } @@ -4177,8 +4165,7 @@ __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, - DMA_CBR1_BRSDEC)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC)); } /** @@ -4199,8 +4186,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, __STATIC_INLINE void LL_DMA_SetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrUpdate) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, - DMA_CBR1_DDEC, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC, DestAddrUpdate); } @@ -4221,8 +4207,7 @@ __STATIC_INLINE void LL_DMA_SetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, - DMA_CBR1_DDEC)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC)); } /** @@ -4243,8 +4228,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(const DMA_TypeDef *DMAx, uint3 __STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrUpdate) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, - DMA_CBR1_SDEC, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC, SrcAddrUpdate); } @@ -4265,8 +4249,7 @@ __STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, - DMA_CBR1_SDEC)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC)); } /** @@ -4286,8 +4269,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32 __STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, - DMA_CBR1_BRC, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRC, (BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC); } @@ -4306,7 +4288,7 @@ __STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Cha __STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos); } @@ -4338,8 +4320,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, - DMA_CBR1_BNDT, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT, BlkDataLength); } @@ -4370,8 +4351,7 @@ __STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, - DMA_CBR1_BNDT)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT)); } /** @@ -4406,8 +4386,8 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Ch DestAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CDAR, DestAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress); } /** @@ -4438,7 +4418,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Ch __STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress); } /** @@ -4468,7 +4448,7 @@ __STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Chan __STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSAR)); + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR)); } /** @@ -4499,7 +4479,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CDAR, DestAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress); } /** @@ -4529,7 +4509,7 @@ __STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Cha __STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CDAR)); + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR)); } /** @@ -4552,7 +4532,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef *DMAx, uint3 uint32_t DestAddrOffset) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR3, + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); } @@ -4572,8 +4552,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef *DMAx, uint3 __STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrOffset) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR3, - DMA_CTR3_DAO, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_DAO, ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); } @@ -4592,7 +4571,7 @@ __STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR3, + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos); } @@ -4612,8 +4591,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef *DMAx, __STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR3, - DMA_CTR3_SAO, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO, SrcAddrOffset & DMA_CTR3_SAO); } @@ -4632,8 +4610,7 @@ __STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint3 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR3, - DMA_CTR3_SAO)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO)); } /** @@ -4656,7 +4633,7 @@ __STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t BlkRptSrcAddrOffset, uint32_t BlkRptDestAddrOffset) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR2, + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO) | (BlkRptSrcAddrOffset & DMA_CBR2_BRSAO)); } @@ -4677,8 +4654,7 @@ __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx uint32_t BlkRptDestAddrOffset) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR2, - DMA_CBR2_BRDAO, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRDAO, ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO)); } @@ -4697,7 +4673,7 @@ __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx __STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR2, + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos); } @@ -4718,8 +4694,7 @@ __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t BlkRptSrcAddrOffset) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR2, - DMA_CBR2_BRSAO, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO, BlkRptSrcAddrOffset); } @@ -4738,8 +4713,7 @@ __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR2, - DMA_CBR2_BRSAO)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO)); } /** @@ -4788,7 +4762,7 @@ __STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t C uint32_t LinkedListAddrOffset) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA))); } @@ -4820,8 +4794,7 @@ __STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UT1); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); } /** @@ -4851,8 +4824,7 @@ __STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UT1); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); } /** @@ -4882,8 +4854,7 @@ __STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UT1) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1) == (DMA_CLLR_UT1)) ? 1UL : 0UL); } @@ -4914,8 +4885,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uin __STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UT2); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2); } /** @@ -4945,8 +4915,7 @@ __STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UT2); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2); } /** @@ -4976,8 +4945,7 @@ __STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UT2) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2) == (DMA_CLLR_UT2)) ? 1UL : 0UL); } @@ -5008,8 +4976,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uin __STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UB1); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); } /** @@ -5039,8 +5006,7 @@ __STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UB1); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); } /** @@ -5070,8 +5036,7 @@ __STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UB1) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1) == (DMA_CLLR_UB1)) ? 1UL : 0UL); } @@ -5102,8 +5067,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uin __STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_USA); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); } /** @@ -5133,8 +5097,7 @@ __STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_USA); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); } /** @@ -5164,8 +5127,7 @@ __STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_USA) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA) == (DMA_CLLR_USA)) ? 1UL : 0UL); } @@ -5196,8 +5158,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uin __STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UDA); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); } /** @@ -5227,8 +5188,7 @@ __STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UDA); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); } /** @@ -5258,8 +5218,7 @@ __STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UDA) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA) == (DMA_CLLR_UDA)) ? 1UL : 0UL); } @@ -5278,8 +5237,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uin __STATIC_INLINE void LL_DMA_EnableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UT3); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); } /** @@ -5297,8 +5255,7 @@ __STATIC_INLINE void LL_DMA_EnableCTR3Update(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_DisableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UT3); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); } /** @@ -5316,8 +5273,7 @@ __STATIC_INLINE void LL_DMA_DisableCTR3Update(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UT3) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3) == (DMA_CLLR_UT3)) ? 1UL : 0UL); } @@ -5336,8 +5292,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef *DMAx, uin __STATIC_INLINE void LL_DMA_EnableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UB2); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2); } /** @@ -5355,8 +5310,7 @@ __STATIC_INLINE void LL_DMA_EnableCBR2Update(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_DisableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UB2); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2); } /** @@ -5374,8 +5328,7 @@ __STATIC_INLINE void LL_DMA_DisableCBR2Update(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_UB2) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2) == (DMA_CLLR_UB2)) ? 1UL : 0UL); } @@ -5406,8 +5359,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef *DMAx, uin __STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_ULL); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); } /** @@ -5437,8 +5389,7 @@ __STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_ULL); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); } /** @@ -5468,8 +5419,7 @@ __STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_ULL) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL) == (DMA_CLLR_ULL)) ? 1UL : 0UL); } @@ -5502,8 +5452,7 @@ __STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uin uint32_t LinkedListAddrOffset) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, - DMA_CLLR_LA, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA, (LinkedListAddrOffset & DMA_CLLR_LA)); } @@ -5534,7 +5483,7 @@ __STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uin __STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA) >> DMA_CLLR_LA_Pos); } @@ -5565,7 +5514,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, __STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos); } @@ -5843,7 +5792,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef __STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_TOF); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF); } /** @@ -5873,7 +5822,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_SUSPF); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF); } /** @@ -5903,7 +5852,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Cha __STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_USEF); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF); } /** @@ -5933,7 +5882,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Chan __STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_ULEF); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF); } /** @@ -5963,7 +5912,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Chan __STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_DTEF); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF); } /** @@ -5993,7 +5942,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Chan __STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_HTF); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF); } /** @@ -6023,7 +5972,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_TCF); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF); } /** @@ -6053,8 +6002,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, - DMA_CSR_TOF) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF) == (DMA_CSR_TOF)) ? 1UL : 0UL); } @@ -6085,8 +6033,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, - DMA_CSR_SUSPF) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF) == (DMA_CSR_SUSPF)) ? 1UL : 0UL); } @@ -6117,8 +6064,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint3 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, - DMA_CSR_USEF) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF) == (DMA_CSR_USEF)) ? 1UL : 0UL); } @@ -6149,8 +6095,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, - DMA_CSR_ULEF) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF) == (DMA_CSR_ULEF)) ? 1UL : 0UL); } @@ -6181,8 +6126,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, - DMA_CSR_DTEF) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF) == (DMA_CSR_DTEF)) ? 1UL : 0UL); } @@ -6213,8 +6157,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, - DMA_CSR_HTF) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF) == (DMA_CSR_HTF)) ? 1UL : 0UL); } @@ -6245,8 +6188,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, - DMA_CSR_TCF) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF) == (DMA_CSR_TCF)) ? 1UL : 0UL); } @@ -6277,8 +6219,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, - DMA_CSR_IDLEF) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF) == (DMA_CSR_IDLEF)) ? 1UL : 0UL); } @@ -6378,8 +6319,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef *DMAx, uint3 __STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_TOIE); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE); } /** @@ -6409,8 +6349,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channe __STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_SUSPIE); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE); } /** @@ -6440,8 +6379,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Chan __STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_USEIE); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE); } /** @@ -6471,8 +6409,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_ULEIE); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE); } /** @@ -6502,8 +6439,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_DTEIE); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE); } /** @@ -6533,8 +6469,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_HTIE); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); } /** @@ -6564,8 +6499,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channe __STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_TCIE); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); } /** @@ -6595,8 +6529,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channe __STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_TOIE); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE); } /** @@ -6626,8 +6559,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_SUSPIE); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE); } /** @@ -6657,8 +6589,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Cha __STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_USEIE); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE); } /** @@ -6688,8 +6619,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Chan __STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_ULEIE); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE); } /** @@ -6719,8 +6649,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Chan __STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_DTEIE); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE); } /** @@ -6750,8 +6679,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Chan __STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_HTIE); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); } /** @@ -6781,8 +6709,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_TCIE); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); } /** @@ -6812,8 +6739,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_TOIE) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE) == DMA_CCR_TOIE) ? 1UL : 0UL); } @@ -6844,8 +6770,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_SUSPIE) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE) == DMA_CCR_SUSPIE) ? 1UL : 0UL); } @@ -6876,8 +6801,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_USEIE) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE) == DMA_CCR_USEIE) ? 1UL : 0UL); } @@ -6908,8 +6832,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_ULEIE) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE) == DMA_CCR_ULEIE) ? 1UL : 0UL); } @@ -6940,8 +6863,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_DTEIE) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE) == DMA_CCR_DTEIE) ? 1UL : 0UL); } @@ -6972,8 +6894,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_HTIE) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE) == DMA_CCR_HTIE) ? 1UL : 0UL); } @@ -7004,8 +6925,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, - DMA_CCR_TCIE) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE) == DMA_CCR_TCIE) ? 1UL : 0UL); } /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmc.h index 99e77df745..917cec6ee1 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmc.h @@ -782,8 +782,8 @@ typedef struct /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions * @{ */ - #if defined(FMC_BANK1) + /** @defgroup FMC_LL_NORSRAM NOR SRAM * @{ */ @@ -815,8 +815,8 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic * @} */ #endif /* FMC_BANK1 */ - #if defined(FMC_BANK3) + /** @defgroup FMC_LL_NAND NAND * @{ */ @@ -848,7 +848,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECC */ #endif /* FMC_BANK3 */ - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h index f3e035d8b7..69d8a6a991 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h @@ -558,6 +558,7 @@ typedef struct ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx); void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct); +void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx); /** * @} */ @@ -580,17 +581,6 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE); } -/** - * @brief Disable the LPTIM instance - * @rmtoll CR ENABLE LL_LPTIM_Disable - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) -{ - CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE); -} - /** * @brief Indicates whether the LPTIM instance is enabled. * @rmtoll CR ENABLE LL_LPTIM_IsEnabled diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pka.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pka.h index 597d09af17..3e6949e52b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pka.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pka.h @@ -516,7 +516,18 @@ __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->SR, PKA_SR_BUSY) == (PKA_SR_BUSY)) ? 1UL : 0UL); } - +#if defined(PKA_SR_INITOK) +/** + * @brief Get PKA init ok flag. + * @rmtoll SR INITOK LL_PKA_IsActiveFlag_INITOK + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_INITOK(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->SR, PKA_SR_INITOK) == (PKA_SR_INITOK)) ? 1UL : 0UL); +} +#endif /* PKA_SR_INITOK */ /** * @brief Clear PKA address error flag. * @rmtoll CLRFR ADDRERRFC LL_PKA_ClearFlag_ADDERR diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h index 75a8fc455b..656daa6122 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h @@ -134,6 +134,28 @@ typedef struct * @} */ +#if (defined(RNG_NSCR_EN_OSC1) || defined(RNG_NSCR_EN_OSC2) ||defined(RNG_NSCR_EN_OSC3)) +/** @defgroup RNG_LL_NSCR_Oscillator_Sources Oscillator Sources Defines + * @{ + */ +#define LL_RNG_OSC_1 RNG_NSCR_EN_OSC1 +#define LL_RNG_OSC_2 RNG_NSCR_EN_OSC2 +#define LL_RNG_OSC_3 RNG_NSCR_EN_OSC3 +/** + * @} + */ + +/** @defgroup RNG_LL_NSCR_Noise_Sources_Ports Noise Sources Ports Defines + * @{ + */ +#define LL_RNG_NOISE_SRC_1 (0x01UL) +#define LL_RNG_NOISE_SRC_2 (0x02UL) +#define LL_RNG_NOISE_SRC_3 (0x04UL) +/** + * @} + */ + +#endif /* RNG_CR_CONDRST */ /** @defgroup RNG_LL_EC_IT IT Defines * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros * @{ @@ -721,7 +743,6 @@ __STATIC_INLINE void LL_RNG_SetNoiseConfig(RNG_TypeDef *RNGx, uint32_t NOISECFG) */ __STATIC_INLINE uint32_t LL_RNG_GetNoiseConfig(const RNG_TypeDef *RNGx) { - return (uint32_t)READ_REG(RNGx->NSCR); } @@ -730,6 +751,50 @@ __STATIC_INLINE uint32_t LL_RNG_GetNoiseConfig(const RNG_TypeDef *RNGx) */ #endif /* defined(RNG_NSCR_NIST_VALUE) */ +#if (defined(RNG_NSCR_EN_OSC1) || defined(RNG_NSCR_EN_OSC2) || defined(RNG_NSCR_EN_OSC3)) +/** @defgroup RNG noise source Control + * @{ + */ + +/** + * @brief Set RNG Noise Source Configuration. + * @rmtoll + * NSCR NSCR LL_RNG_GetOscNoiseSrc + * @param RNGx RNG Instance + * @param osc be one of the following values: + * @arg @ref LL_RNG_OSC_1 + * @arg @ref LL_RNG_OSC_2 + * @arg @ref LL_RNG_OSC_3 + * @retval can be one of the following values: + * @arg @ref LL_RNG_NOISE_SRC_1 + * @arg @ref LL_RNG_NOISE_SRC_2 + * @arg @ref LL_RNG_NOISE_SRC_3 + */ +__STATIC_INLINE void LL_RNG_SetOscNoiseSrc(RNG_TypeDef *RNGx, uint32_t osc) +{ + WRITE_REG(RNGx->NSCR, osc); +} + +/** + * @brief Get RNG Noise Source Configuration. + * @rmtoll + * NSCR NSCR LL_RNG_GetOscNoiseSrc + * @param RNGx RNG Instance + * @param osc be one of the following values: + * @arg @ref LL_RNG_OSC_1 + * @arg @ref LL_RNG_OSC_2 + * @arg @ref LL_RNG_OSC_3 + * @retval can be one of the following values: + * @arg @ref LL_RNG_NOISE_SRC_1 + * @arg @ref LL_RNG_NOISE_SRC_2 + * @arg @ref LL_RNG_NOISE_SRC_3 + */ +__STATIC_INLINE uint32_t LL_RNG_GetOscNoiseSrc(const RNG_TypeDef *RNGx, uint32_t osc) +{ + return (READ_BIT(RNGx->NSCR, osc) >> POSITION_VAL(osc)); +} + +#endif /* defined(defined(RNG_NSCR_EN_OSC1) || RNG_NSCR_EN_OSC2 ||RNG_NSCR_EN_OSC3) */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h index 12e79790a0..6f7815b404 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h @@ -510,9 +510,9 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; /** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines * @{ */ -#define HPRT0_PRTSPD_HIGH_SPEED 0U -#define HPRT0_PRTSPD_FULL_SPEED 1U -#define HPRT0_PRTSPD_LOW_SPEED 2U +#define HPRT0_PRTSPD_HIGH_SPEED 0UL +#define HPRT0_PRTSPD_FULL_SPEED 1UL +#define HPRT0_PRTSPD_LOW_SPEED 2UL /** * @} */ @@ -955,21 +955,21 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; #define USB_DRD_SET_CHEP_CNT_RX_REG(pdwReg, wCount) \ do { \ uint32_t wNBlocks; \ - \ - (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ + uint32_t wRegVal = (uint32_t)(pdwReg) & ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ \ if ((wCount) == 0U) \ { \ - (pdwReg) |= USB_CNTRX_BLSIZE; \ + wRegVal |= USB_CNTRX_BLSIZE; \ } \ else if ((wCount) <= 62U) \ { \ - USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + USB_DRD_CALC_BLK2(wRegVal, (wCount), wNBlocks); \ } \ else \ { \ - USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + USB_DRD_CALC_BLK32(wRegVal, (wCount), wNBlocks); \ } \ + (pdwReg) = wRegVal; \ } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ @@ -1181,7 +1181,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); -HAL_StatusTypeDef USB_HC_Activate(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t ch_dir); +HAL_StatusTypeDef USB_HC_Activate(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t ch_dir); #endif /* defined (HAL_HCD_MODULE_ENABLED) */ HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); @@ -1228,9 +1228,10 @@ HAL_StatusTypeDef USB_HC_Activate(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uin #endif /* defined (HAL_HCD_MODULE_ENABLED) */ uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx); -uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx); HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx); +uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx); + HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/LICENSE.md b/system/Drivers/STM32U5xx_HAL_Driver/LICENSE.md index 9226612aea..5d67eddecd 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/LICENSE.md +++ b/system/Drivers/STM32U5xx_HAL_Driver/LICENSE.md @@ -24,4 +24,4 @@ ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/system/Drivers/STM32U5xx_HAL_Driver/README.md b/system/Drivers/STM32U5xx_HAL_Driver/README.md index 9d77735a7a..a0ff1494dc 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/README.md +++ b/system/Drivers/STM32U5xx_HAL_Driver/README.md @@ -1,6 +1,6 @@ # STM32CubeU5 HAL Driver MCU Component -![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32u5xx_hal_driver.svg?color=brightgreen) +![tag](https://img.shields.io/badge/tag-v1.6.3-brightgreen.svg) ## Overview @@ -24,7 +24,7 @@ This **stm32u5xx_hal_driver** MCU component repo is one element of the STM32Cube ## Release note -Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32u5xx_hal_driver/blob/master/Release_Notes.html). +Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32u5xx_hal_driver/blob/main/Release_Notes.html). ## Compatibility information @@ -35,4 +35,4 @@ The full **STM32CubeU5** MCU package is available [here](https://github.com/STMi ## Troubleshooting -Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. \ No newline at end of file diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html index 3d71ba22a5..1b96dcb811 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html @@ -40,7 +40,7 @@

        Purpose

        Update History

        - +

        Main Changes

          @@ -48,9 +48,163 @@

          Main Changes

        HAL/LL Drivers updates

          +
        • Fix Misra-C 2012 Rule 8.13 violations.
          • +
        • Fix Misra-C 2012 Rule 12.2 violations.
          • +
        • HAL DCACHE driver +
            +
          • Ensure DCACHE2 invalidation within the initialization phase.
            • +
          • +
        • HAL RTC driver +
            +
          • Replace WRITE_REG() with SET_BIT() in HAL_RTCEx_SetBootHardwareKey() API to avoid overwriting other bit fields.
            • +
          • Invoke SET_BIT() instead of WRITE_REG() in HAL_RTCEx_BKUPErase() and HAL_RTCEx_BKUPBlock_Enable() to avoid overwriting other bit fields.
            • +
          • Fix typos in RTC_FLAG_INT_TAMP_x names in the definition of RTC_FLAG_INT_TAMP_ALL macro.
            • +
          • +
        • HAL ADC driver +
            +
          • Remove incorrect double call of LL_ADC_REG_StartConversion() API.
            • +
          • Align arguments of macro __HAL_ADC_DIGITAL_SCALE with __LL_ADC_DIGITAL_SCALE.
            • +
          • +
        • HAL CRYP driver +
            +
          • Fix compilation error in hal_cryp_ex.c.
            • +
          • Prevent reading outside the boundaries of the local array for all data types.
            • +
          • Add padding processing when the data size is not a multiple of a word (32-bit), taking into account the data swapping type.
            • +
          • Fix Coverity issue INTEGER_OVERFLOW.
            • +
          • Remove compilation condition on tickstart local variable declaration in HAL_CRYP_Init() API.
            • +
          • Fix Misra-C 2012 Rules 9.1, 10.1, 10.4 and 12.1 violations.
            • +
          • Fix CCM partial output handling for non 32-bit aligned payloads.
            • +
          • SA0076 fixed.
            • +
          • +
        • HAL DMA driver +
            +
          • Fix compilation warning detected with STM32CubeIDE in HAL_DMAEx_List_ConvertQToDynamic() API.
            • +
          • +
        • HAL LPTIM driver +
            +
          • Implement a software workaround for the LPTIM interrupt limitation.
            • +
          • +
        • HAL FLASH driver +
            +
          • Separate secure and non-secure flash locking with new dedicated HAL APIs to avoid TrustZone access conflicts.
            • +
          • +
        • HAL PKA driver +
            +
          • Add LL_PKA_IsActiveFlag_INITOK() API to check the PKA initialization status.
            • +
          • Handle the use case of data not multiple of 4 bytes for PKA Modular Exponentiation Fast Mode.
            • +
          • +
        • HAL FDCAN driver +
            +
          • Fix GetIndex computation overflow in overwrite mode.
            • +
          • Fix MISRA-C 2012 Rule 2.2 violation.
            • +
          • Fix confusion between two timeout definitions in HAL FDCAN driver.
            • +
          • +
        • HAL/LL FMC driver +
            +
          • Remove unused local variables.
            • +
          • Handle case when HAL_NAND_Read_Status returns NAND_ERROR on other NAND APIs.
            • +
          • Remove 8-bit support from FMC NOR driver.
            • +
          • +
        • HAL I2C driver +
            +
          • Improve and simplify IsDeviceReady function.
            • +
          • +
        • HAL/LL LPUART driver +
            +
          • Update LL LPUART baud rate range.
            • +
          • Fix transfer count underflow when using polling mode.
            • +
          • +
        • HAL LTDC driver +
            +
          • Fix Coverity warnings.
            • +
          • Update to avoid compilation errors when the DSI module is not enabled.
            • +
          • +
        • HAL OCTOSPI driver +
            +
          • Add HAL_OSPI_IsMemoryMapped() API.
            • +
          • Update HAL_OSPIM_Config() API: do not enable mux when Port Low or High is not activated (Quad mode).
            • +
          • +
        • HAL RCC driver +
            +
          • Remove resetting CSR flags in HAL_RCC_DeInit() API to keep the reset cause after RCC deinitialization.
            • +
          • Add a note to clarify that DCACHE2 clock should be enabled only when GPU2D is used.
            • +
          • +
        • HAL/LL RNG driver +
            +
          • Update HAL_RNGEx_GetConfig() API to get NoiseSource.
            • +
          • Update the seed error check flag in HAL_RNG_GenerateRandomNumber() API.
            • +
          • Add error state check at the beginning of seed recover sequence in HAL_RNGEx_RecoverSeedError() API.
            • +
          • Add LL_RNG_SetOscNoiseSrc() and LL_RNG_GetOscNoiseSrc() APIs.
            • +
          • +
        • HAL SDMMC driver +
            +
          • Fix the cmd input parameter in the cmd argument structure to support the input size byte as block and byte mode according to the block mode argument in HAL_SDIO_ReadExtended() and HAL_SDIO_WriteExtended() APIs.
            • +
          • Support SD card V1 within HAL_SD.
            • +
          • Handle frequencies below 3 MHZ correctly in HAL_SD_InitCard() API.
            • +
          • Fix Misra-C Rule 10.4 violation in SD and MMC drivers.
            • +
          • Fix Misra-C 10.3 violation in SDIO driver.
            • +
          • Fix Coverity violations in SDIO and MMC drivers.
            • +
          • +
        • HAL smartcard driver +
            +
          • Update configuration sequence to better fit smartcard specifications.
            • +
          • +
        • HAL SPI driver +
            +
          • Update sConfig parameter description of HAL_SPIEx_SetConfigAutonomousMode() API.
            • +
          • +
        • HAL/LL TIM driver +
            +
          • Remove channel 2 activation in LL_TIM_HALLSENSOR_Init() API.
            • +
          • Fix UIF flag set after TIM_Base_SetConfig().
            • +
          • +
        • HAL/LL UART driver +
            +
          • Fix transfer count underflow when using polling mode.
            • +
          • Align UART baud rate macros definition between LL and HAL.
            • +
          • Remove __HAL_UART_DISABLE() call from the HAL_UART_DeInit() API.
            • +
          • Update LL LPUART baud rate range"
            • +
          • +
        • LL UCPD driver +
            +
          • Add LL UCPD LL_UCPD_IsActiveFlag_RxErr() API.
            • +
          • Correct wording in some LL API LL_UCPD_IsActiveFlag_xxx function descriptions.
            • +
          • +
        • HAL/LL USB driver +
            +
          • Ensure NYET/NAK Interrupts are enabled.
            • +
          • Remove __HAL_LOCK() from HAL_Callbacks APIs in hal_pcd and hal_hcd.
            • +
          • Activate the scatter gather mode constraint.
            • +
          • Rework port device connect/disconnect in HCD_Port_IRQHandler() function.
            • +
          • Add HCD_HS_PHY_EMBEDDED and HCD_PHY_UTMI macros.
            • +
          • Update PCD_EP_ISR_Handler() function to avoid out-of-bound possible read.
            • +
          • Fix USB_DRD_SET_CHEP_CNT_RX_REG macro to update COUNTn_RX register in single operation.
            • +
          • Add get frame number support.
            • +
          • +
        +

        Known Limitations

        +
          +
        • N/A
          • +
        +

        Backward compatibility

        +
          +
        • N/A
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • General updates to fix known defects and implementation enhancements.
          • +
        • Code quality enhancement MISRA-C:2012 Rule-12.2.
          • +
        +

        HAL/LL Drivers updates

        +
        • HAL Generic driver
            -
          • Update HAL_SetTickFreq() API to restore current tick frequency when call to HAL_InitTick() fails.
            • +
          • Update HAL_SetTickFreq() API to restore current tick frequency when call to HAL_InitTick() API fails.
        • HAL/LL GPIO driver
            @@ -58,10 +212,11 @@

            HAL/LL Drivers updates

        • HAL/LL DMA driver
            -
          • Remove extra unused parentheses in HAL_DMA_IRQHandler.
            • +
          • Remove extra unused parentheses in HAL_DMA_IRQHandler() API.
          • Add attribute ((no_inline)) to DMA_List_CheckNodesBaseAddresse() API to avoid warning with GCC compiler.
          • Add DMA XferSuspendCallback initialization before starting DMA transfers in HAL UART.
          • Add initialization of callbacks in HAL_DMA_Init() API.
            • +
          • Remove the reset of Channel Linked List Address Register (CLLR) in DMA_List_BuildNode() API.
        • HAL FLASH driver
            @@ -75,10 +230,11 @@

            HAL/LL Drivers updates

          • HAL/LL TIM driver
            • Update TIM_CCER_CCxE_MASK to support internal TIM Channel5 and TIM Channel6.
              • +
            • Fix complementary channel systematically disabled by TIM_OCx_SetConfig() API.
          • HAL/LL LPTIM driver
              -
            • Fix LL_LPTIM_CC_SetChannelMode() static function to manage properly on the fly channel mode changes.
              • +
            • Fix LL_LPTIM_CC_SetChannelMode() static API to manage properly on the fly channel mode changes.
          • HAL/LL UART driver
              @@ -101,6 +257,7 @@

              HAL/LL Drivers updates

              • Add asserts to inform user when data size or address requested is not compatible with current XSPI configuration.
              • Check BUSY flag instead of TC flag in indirect mode to be sure that command is well completed (FIFO flush).
                • +
              • Add HAL_XSPI_IsMemoryMapped() API.
            • LL LPUART driver
                @@ -114,7 +271,7 @@

                HAL/LL Drivers updates

            • HAL CRC driver
                -
              • Replace successive ‘if’ statements by ‘else if’ to improve checksum calculation performance in CRC_Handle_8() function.
                • +
              • Replace successive ‘if’ statements by ‘else if’ to improve checksum calculation performance in CRC_Handle_8() API.
            • HAL FMAC driver
                @@ -122,7 +279,7 @@

                HAL/LL Drivers updates

            • HAL/LL PKA driver
                -
              • Update PKA_ModExpFastMode_Set() function to solve the issue when data is not multiple of 4 bytes for PKA Modular Exponentiation Fast Mode.
                • +
              • Update PKA_ModExpFastMode_Set() API to solve the issue when data is not multiple of 4 bytes for PKA Modular Exponentiation Fast Mode.
              • Add specific LL PKA API to check the PKA initialization OK status: LL_PKA_IsActiveFlag_INITOK() API.
            • HAL/LL NAND driver @@ -131,7 +288,7 @@

              HAL/LL Drivers updates

          • HAL JPEG driver
              -
            • Update JPEG_DMA_ContinueProcess() function to use blocking DMA abort.
              • +
            • Update JPEG_DMA_ContinueProcess() API to use blocking DMA abort.
            • Remove multiple volatile reads in interrupt handler in JPEG_Process() and JPEG_DMA_ContinueProcess() functions.
          • HAL USB-FS driver @@ -139,11 +296,11 @@

            HAL/LL Drivers updates

          • Fix USB PCD setup and data buffers overflow (SA0035).
        -

        Known Limitations

        +

        Known Limitations

        • N/A
        -

        Backward compatibility

        +

        Backward compatibility

        • N/A
        @@ -152,11 +309,11 @@

        Backward compatibility

        -

        Main Changes

        +

        Main Changes

        • General updates to fix known defects and implementation enhancements.
        -

        HAL/LL Drivers updates

        +

        HAL/LL Drivers updates

        • HAL/LL ADC driver
            @@ -288,11 +445,11 @@

            HAL/LL Drivers updates

          • Fix the condition on EONUM flag of DOEPCTLx register in HAL_PCD_IRQHandler() to correctly check on the frame number parity.
        -

        Known Limitations

        +

        Known Limitations

        • N/A
        -

        Backward compatibility

        +

        Backward compatibility

        • N/A
        @@ -301,12 +458,12 @@

        Backward compatibility

        -

        Main Changes

        +

        Main Changes

        • Maintenance Release V1.6.0 of STM32CubeU5 Firmware Package to deploy the new HAL SDIO driver.
        • General updates to fix known defects and implementation enhancements.
        -

        HAL/LL Drivers updates

        +

        HAL/LL Drivers updates

        • HAL GENERIC driver
            @@ -330,11 +487,11 @@

            HAL/LL Drivers updates

          • Support new HAL SDIO driver.
        -

        Known Limitations

        +

        Known Limitations

        • N/A
        -

        Backward compatibility

        +

        Backward compatibility

        • N/A
        @@ -343,7 +500,7 @@

        Backward compatibility

        -

        Main Changes

        +

        Main Changes

        • HAL and LL drivers Maintenance Release for STM32U535xx/STM32U545xx, STM32U575xx/STM32U585xx, STM32U599xx/STM32U5A9xx, STM32U595xx/STM32U5A5xx, STM32U5F9xx/STM32U5G9xx and STM32U5F7xx/STM32U5G7xx devices
        • Add the HAL MMC replay protected memory block management feature
          • @@ -524,11 +681,11 @@

          LL Drivers updates

        • Rename LL_UTILS_PACKAGETYPE_WLCSP144_SMPS to LL_UTILS_PACKAGETYPE_LQFP100_DSI_SMPS define
      -

      Known Limitations

      +

      Known Limitations

      • N/A
      -

      Backward compatibility

      +

      Backward compatibility

      • N/A
      @@ -537,7 +694,7 @@

      Backward compatibility

      -

      Main Changes

      +

      Main Changes

      • HAL and LL drivers Maintenance Release for STM32U5XX devices
      • Update ADC HAL and LL drivers to fix known defects and add implementation enhancements
        • @@ -561,11 +718,11 @@

        LL Drivers updates

      • Add new Helper macro for differential mode raw data to voltage conversion
    -

    Known Limitations

    +

    Known Limitations

    • N/A
    -

    Backward compatibility

    +

    Backward compatibility

    • N/A
    @@ -574,7 +731,7 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • HAL and LL drivers official Release for STM32U5F7xx/STM32U5G7xx, STM32U5F9xx/STM32U5G9xx, STM32U535xx/STM32U545xx, STM32U575xx/STM32U585xx, STM32U595xx/STM32U5A5xx and STM32U599xx/STM32U5A9xx devices
    • Add 2 new HAL drivers : GFXTIM and JPEG highlighting the graphics aspect of STM32U5F7/STM32U5G7/STM32U5F9/STM32U5G9 devices
      • @@ -664,11 +821,11 @@

      LL Drivers updates

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -677,7 +834,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • HAL and LL drivers Official Release for STM32U535xx / STM32U545xx, STM32U575xx / STM32U585xx, STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices.
  • Update STM32U545xx_User_Manual, STM32U585xx_User_Manual and STM32U5A9xx_User_Manual CHM User Manuals
    • @@ -877,11 +1034,11 @@

    LL Drivers updates

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -890,7 +1047,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • HAL and LL drivers Maintenance Release for STM32U575xx / STM32U585xx devices and new support of STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices
  • Add New LTDC, GFXMMU, DSI, GPU2D HAL drivers highlighting the graphics aspect of STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices
    • @@ -1117,11 +1274,11 @@

    LL Drivers updates

Backward compatibility ensured by legacy defines

-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -1130,7 +1287,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • Patch release V1.0.2 of HAL and LL drivers for STM32U575xx / STM32U585xx devices
@@ -1146,11 +1303,11 @@

LL Drivers updates

  • Backward compatibility ensured by legacy defines
    • -

    Known Limitations

    +

    Known Limitations

    • N/A
    -

    Backward compatibility

    +

    Backward compatibility

    • N/A
    @@ -1159,7 +1316,7 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • Patch release V1.0.1 of HAL and LL drivers for STM32U575xx / STM32U585xx devices
    @@ -1208,11 +1365,11 @@

    LL Drivers updates

  • Add LL_I2C_EnableFastModePlus, LL_I2C_DisableFastModePlus and LL_I2C_IsEnabledFastModePlus APIs
    • -

    Known Limitations

    +

    Known Limitations

    • N/A
    -

    Backward compatibility

    +

    Backward compatibility

    • N/A
    @@ -1221,11 +1378,11 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • First official release of HAL and LL drivers for STM32U575xx / STM32U585xx devices
    -

    Known Limitations

    +

    Known Limitations

    • N/A
    diff --git a/system/Drivers/STM32U5xx_HAL_Driver/SW_Security_Level.md b/system/Drivers/STM32U5xx_HAL_Driver/SW_Security_Level.md new file mode 100644 index 0000000000..2cc2ed61c0 --- /dev/null +++ b/system/Drivers/STM32U5xx_HAL_Driver/SW_Security_Level.md @@ -0,0 +1,47 @@ + + +## Copyright (c) 2026 STMicroelectronics. +## All rights reserved +
    +
    + +## SW Security Classification + +[STM32Trust software security policies](https://wiki.st.com/stm32mcu/wiki/Security:STM32Trust_software_security_policies) define four levels of SW Security classification, each level defines a set of security policies for the applicable SW. + +| SW | SW Security Level +|:--------- |:-------| +| **STM32U5xx HAL Driver** | Medium| + + +
    + +## IMPORTANT SECURITY NOTICE + +The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that: + +- ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified. + +- Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product. + +- Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies. + +- While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application. + +- All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. + +AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise. + +
    + +## IMPORTANT NOTICE - READ CAREFULLY + +STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgment. + +Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers' products. +No license, express or implied, to any intellectual property right is granted by ST herein. +Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. +ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. +Information in this document supersedes and replaces information previously supplied in any prior versions of this document. + +Copyright (c) 2026 STMicroelectronics - All rights reserved \ No newline at end of file diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c index cb2e9c1662..3bbb5ed540 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c @@ -52,11 +52,11 @@ * @{ */ /** - * @brief STM32U5xx HAL Driver version number 1.6.2 + * @brief STM32U5xx HAL Driver version number 1.6.3 */ #define __STM32U5xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ #define __STM32U5xx_HAL_VERSION_SUB1 (0x06UL) /*!< [23:16] sub1 version */ -#define __STM32U5xx_HAL_VERSION_SUB2 (0x02UL) /*!< [15:8] sub2 version */ +#define __STM32U5xx_HAL_VERSION_SUB2 (0x03UL) /*!< [15:8] sub2 version */ #define __STM32U5xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\ |(__STM32U5xx_HAL_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc.c index dc8d8e7d28..257311c5d9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc.c @@ -1674,11 +1674,11 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } + + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); #endif /* ADC_MULTIMODE_SUPPORT */ } - - /* Start ADC group regular conversion */ - LL_ADC_REG_StartConversion(hadc->Instance); } else { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc.c index cf7374a1be..cf804b4804 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc.c @@ -64,8 +64,8 @@ /** @defgroup CRC_Private_Functions CRC Private Functions * @{ */ -static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength); -static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t const pBuffer[], uint32_t BufferLength); +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t const pBuffer[], uint32_t BufferLength); /** * @} */ @@ -284,7 +284,7 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ -uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength) { uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ @@ -304,11 +304,12 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ break; case CRC_INPUTDATA_FORMAT_BYTES: - temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + temp = CRC_Handle_8(hcrc, (uint8_t const *)pBuffer, BufferLength); break; case CRC_INPUTDATA_FORMAT_HALFWORDS: - temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + temp = + CRC_Handle_16(hcrc, (uint16_t const *)(void const *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: break; @@ -336,7 +337,7 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ -uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength) { uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ @@ -361,12 +362,13 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t case CRC_INPUTDATA_FORMAT_BYTES: /* Specific 8-bit input data handling */ - temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + temp = CRC_Handle_8(hcrc, (uint8_t const *)pBuffer, BufferLength); break; case CRC_INPUTDATA_FORMAT_HALFWORDS: /* Specific 16-bit input data handling */ - temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + temp = + CRC_Handle_16(hcrc, (uint16_t const *)(void const *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: @@ -429,7 +431,7 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc) * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ -static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t const pBuffer[], uint32_t BufferLength) { uint32_t i; /* input data buffer index */ uint16_t data; @@ -484,7 +486,7 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ -static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t const pBuffer[], uint32_t BufferLength) { uint32_t i; /* input data buffer index */ __IO uint16_t *pReg; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp.c index 054ba9240e..5a38137dec 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp.c @@ -383,6 +383,7 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static void CRYP_CopyPartialOutputWord(uint32_t *pOutputWord, uint32_t word, uint32_t dataType, uint32_t validBytes); #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output); static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input); @@ -393,6 +394,49 @@ static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *I static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ +static void CRYP_CopyPartialOutputWord(uint32_t *pOutputWord, uint32_t word, uint32_t dataType, uint32_t validBytes) +{ + uint8_t *pDst = (uint8_t *)pOutputWord; + uint8_t *pSrc = (uint8_t *)&word; + uint32_t dstIndex = 0U; + uint32_t index; + uint32_t maskValue; + /* DataType-dependent byte maps used to keep only valid bytes from the last partial CCM word. */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; + + if (validBytes >= 4U) + { + *pOutputWord = word; + return; + } + + /* Select bytes that are valid for the active DataType, then compact them at output start. */ + maskValue = mask[(dataType * 2U) + validBytes]; + + for (index = 0U; index < 4U; index++) + { + if ((maskValue & ((uint32_t)0xFFU << (index * 8U))) != 0U) + { + pDst[dstIndex] = pSrc[index]; + dstIndex++; + if (dstIndex == validBytes) + { + break; + } + } + } + + for (index = dstIndex; index < 4U; index++) + { + /* Zero-fill trailing bytes to keep deterministic output for non-aligned payload sizes. */ + pDst[index] = 0U; + } +} + /** * @} @@ -3035,10 +3079,11 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) uint32_t loopcounter; uint32_t headersize_in_bytes; uint32_t tmp; - const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; uint32_t algo; /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit @@ -3145,8 +3190,9 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) uint32_t count; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t mode; + uint32_t crypoutcount; CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; @@ -3221,7 +3267,17 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) count = 0U; while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (count < 4U)) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count]; + crypoutcount = hcryp->CrypOutCount; + if ((((hcryp->Size % 4U) != 0U) && (crypoutcount == ((((uint32_t)hcryp->Size + 3U) / 4U) - 1U))) + && (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[count], + hcryp->Init.DataType, (((uint32_t)hcryp->Size) % 4U)); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count]; + } hcryp->CrypOutCount++; count++; } @@ -3467,8 +3523,9 @@ static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t i; + uint32_t crypoutcount; /* Write the input block in the IN FIFO */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); @@ -3504,7 +3561,17 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) i = 0U; while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + crypoutcount = hcryp->CrypOutCount; + if ((((hcryp->Size % 4U) != 0U) && (crypoutcount == ((((uint32_t)hcryp->Size + 3U) / 4U) - 1U))) + && (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[i], + hcryp->Init.DataType, (((uint32_t)hcryp->Size) % 4U)); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + } hcryp->CrypOutCount++; i++; } @@ -3520,7 +3587,7 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) */ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) { - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t i; if (hcryp->State == HAL_CRYP_STATE_BUSY) @@ -3711,12 +3778,20 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t tickstart; uint32_t wordsize = ((uint32_t)hcryp->Size / 4U); uint32_t npblb; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t index; - uint32_t lastwordsize; + uint32_t tmp; + uint32_t lastwordsize ; + uint32_t lastoutputwordsize; + uint32_t nolastpaddingbytes; uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32- bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 1- bit data type */ + }; if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { if (hcryp->KeyIVConfig == 1U) @@ -3840,14 +3915,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); } /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } + lastwordsize = (16U - npblb) / 4U; + /* last block optionally pad the data with zeros*/ for (index = 0U; index < lastwordsize; index ++) { @@ -3855,6 +3924,16 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } + + if ((npblb % 4U) != 0U) + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + tmp &= mask[((hcryp->Init.DataType) * 2U) + ((16U - npblb) % 4U)]; + hcryp->Instance->DINR = tmp; + index++; + } + while (index < 4U) { /* pad the data with zeros to have a complete block */ @@ -3876,6 +3955,17 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + /* Number of words in last block to read from DOUT*/ + if ((npblb % 4U) == 0U) + { + lastoutputwordsize = (16U - npblb) / 4U; + } + else + { + lastoutputwordsize = ((16U - npblb) / 4U) + 1U; + } + + /*Read the output block from the output FIFO */ for (index = 0U; index < 4U; index++) { @@ -3883,9 +3973,20 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t get CrypOutBuff from temporary buffer */ temp[index] = hcryp->Instance->DOUTR; } - for (index = 0U; index < lastwordsize; index++) + for (index = 0U; index < lastoutputwordsize; index++) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index]; + if ((index == (lastoutputwordsize - 1U)) && ((npblb % 4U) != 0U) + && (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + nolastpaddingbytes = npblb % 4U; + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[index], + hcryp->Init.DataType, 4U - nolastpaddingbytes); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index]; + } + hcryp->CrypOutCount++; } } @@ -3908,10 +4009,11 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ uint32_t headersize_in_bytes; uint32_t tmp; - const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -4374,10 +4476,17 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t loopcounter; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t lastoutputwordsize; + uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ + uint32_t tmp; uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32- bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 1- bit data type */ + }; if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { @@ -4504,14 +4613,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t } /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } + lastwordsize = (16U - npblb) / 4U; /* Write the last input block in the IN FIFO */ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++) @@ -4519,6 +4621,15 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } + if ((npblb % 4U) != 0U) + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + /* Keep only valid bytes of the last partial input word, according to DataType byte ordering. */ + tmp &= mask[(hcryp->Init.DataType * 2U) + ((16U - npblb) % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + } /* Pad the data with zeros to have a complete block */ while (loopcounter < 4U) @@ -4526,6 +4637,15 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t hcryp->Instance->DINR = 0U; loopcounter++; } + /* Number of words in last block to read from DOUT*/ + if ((npblb % 4U) == 0U) + { + lastoutputwordsize = (16U - npblb) / 4U; + } + else + { + lastoutputwordsize = ((16U - npblb) / 4U) + 1U; + } /* just wait for hash computation */ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { @@ -4540,9 +4660,17 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t get CrypOutBuff from temporary buffer */ temp[loopcounter] = hcryp->Instance->DOUTR; } - for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + for (loopcounter = 0U; loopcounter < lastoutputwordsize; loopcounter++) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter]; + if ((loopcounter == (lastoutputwordsize - 1U)) && ((npblb % 4U) != 0U)) + { + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[loopcounter], + hcryp->Init.DataType, 4U - (npblb % 4U)); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter]; + } hcryp->CrypOutCount++; } } @@ -4567,10 +4695,11 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ uint32_t headersize_in_bytes; uint32_t tmp; - const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -5023,13 +5152,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) { uint32_t loopcounter; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t lastwordsize; uint32_t npblb; uint32_t mode; uint16_t incount; /* Temporary CrypInCount Value */ uint16_t outcount; /* Temporary CrypOutCount Value */ uint32_t i; + uint32_t crypoutcount; /***************************** Payload phase *******************************/ @@ -5042,7 +5172,17 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) i = 0U; while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + crypoutcount = hcryp->CrypOutCount; + if ((((hcryp->Size % 4U) != 0U) && (crypoutcount == ((((uint32_t)hcryp->Size + 3U) / 4U) - 1U))) + && (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[i], + hcryp->Init.DataType, (((uint32_t)hcryp->Size) % 4U)); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + } hcryp->CrypOutCount++; i++; } @@ -5167,7 +5307,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr uint32_t index; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t count; uint32_t reg; @@ -5263,7 +5403,16 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr } for (index = 0U; index < lastwordsize; index++) { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; + if ((index == (lastwordsize - 1U)) && ((npblb % 4U) != 0U) + && (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + CRYP_CopyPartialOutputWord(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount, temp[index], + hcryp->Init.DataType, 4U - (npblb % 4U)); + } + else + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; + } hcryp->CrypOutCount++; } @@ -5297,10 +5446,11 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u uint32_t loopcounter; uint32_t size_in_bytes; uint32_t tmp; - const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; /***************************** Header phase for GCM/GMAC or CCM *********************************/ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) @@ -5431,10 +5581,11 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry uint32_t loopcounter; uint32_t headersize_in_bytes; uint32_t tmp; - const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; /***************************** Header phase for GCM/GMAC or CCM *********************************/ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) @@ -5553,10 +5704,11 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) uint32_t mode; uint32_t headersize_in_bytes; uint32_t tmp; - const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) { @@ -5779,9 +5931,10 @@ static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout { uint32_t count = Timeout; - do + /* Wait until CCF is set or timeout occurs */ + while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) { - count-- ; + if (count == 0U) { /* Disable the CRYP peripheral clock */ @@ -5801,8 +5954,11 @@ static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout /*Call legacy weak error callback*/ HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + return; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); + + count-- ; + } /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -5871,7 +6027,7 @@ static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t /* In case of GCM payload phase encryption, check that suspension can be carried out */ if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD | AES_CR_GCMPH | AES_CR_MODE)) == (CRYP_AES_GCM_GMAC | - AES_CR_GCMPH_1 | 0x0)) + AES_CR_GCMPH_1 | 0x0UL)) { /* Wait for BUSY flag to be cleared */ @@ -6053,7 +6209,7 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) /* Select header phase */ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount) >= 4U)) + if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)) { /* Write the input block in the IN FIFO */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c index f75b812b2a..a553c8bb40 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c @@ -1186,7 +1186,10 @@ uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel) uint32_t result; /* Check the DAC peripheral handle */ - assert_param(hdac != NULL); + if (hdac == NULL) + { + return (uint32_t)HAL_ERROR; + } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcache.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcache.c index 9f18fd11c3..b57d26cb9f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcache.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcache.c @@ -192,6 +192,13 @@ HAL_StatusTypeDef HAL_DCACHE_Init(DCACHE_HandleTypeDef *hdcache) assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); assert_param(IS_DCACHE_READ_BURST_TYPE(hdcache->Init.ReadBurstType)); +#if defined (DCACHE2) + if (hdcache->Instance == DCACHE2) + { + HAL_DCACHE_Invalidate(hdcache); + } +#endif /* DCACHE2 */ + if (hdcache->State == HAL_DCACHE_STATE_RESET) { /* Init the DCACHE Callback settings with legacy weak */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcmi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcmi.c index 828fbb74bd..bdd42e767e 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcmi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcmi.c @@ -785,6 +785,10 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) /* Clear the VSYNC flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI); + if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_CONTINUOUS) + { + hdcmi->XferCount = hdcmi->XferTransferNumber; + } /* VSYNC Callback */ #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) /*Call registered DCMI vsync event callback*/ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c index 12bfe615a5..b8b4fc96d7 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c @@ -2930,7 +2930,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQLis uint32_t cllr_offset; uint32_t currentnode_addr; DMA_NodeTypeDef context_node; - DMA_NodeInQInfoTypeDef node_info; + DMA_NodeInQInfoTypeDef node_info = {0U}; /* Check the queue parameter */ if (pQList == NULL) @@ -3903,6 +3903,18 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, (((uint32_t)pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO); } /********************************************************************************* CBR2 register value is updated */ + + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_2D_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ + } + else + { + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_LINEAR_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ } /* Update node information value ************************************************************************************/ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c index 5ca5d8fee4..60503bfdeb 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c @@ -2017,18 +2017,21 @@ HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan) */ HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) { - uint32_t Counter = 0U; + uint32_t tickstart; if (hfdcan->State == HAL_FDCAN_STATE_BUSY) { /* Request initialisation */ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait until the INIT bit into CCCR register is set */ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) { /* Check for the Timeout */ - if (Counter > FDCAN_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; @@ -2038,22 +2041,19 @@ HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) return HAL_ERROR; } - - /* Increment counter */ - Counter++; } - /* Reset counter */ - Counter = 0U; - /* Exit from Sleep mode */ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait until FDCAN exits sleep mode */ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) { /* Check for the Timeout */ - if (Counter > FDCAN_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; @@ -2063,9 +2063,6 @@ HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) return HAL_ERROR; } - - /* Increment counter */ - Counter++; } /* Enable configuration change */ @@ -2217,7 +2214,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R uint32_t *RxAddress; uint8_t *pData; uint32_t ByteCounter; - uint32_t GetIndex = 0; + uint32_t GetIndex; HAL_FDCAN_StateTypeDef state = hfdcan->State; /* Check function parameters */ @@ -2237,19 +2234,20 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R } else { + /* Calculate Rx FIFO 0 element index */ + GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); + /* Check that the Rx FIFO 0 is full & overwrite mode is on */ if (((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U) { if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F0OM) >> FDCAN_RXGFC_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) { /* When overwrite status is on discard first message in FIFO */ - GetIndex = 1U; + /* GetIndex is incremented by one and wraps to 0 in case it overflows the FIFO size */ + GetIndex = (GetIndex + 1U) % SRAMCAN_RF0_NBR; } } - /* Calculate Rx FIFO 0 element index */ - GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); - /* Calculate Rx FIFO 0 element address */ RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * SRAMCAN_RF0_SIZE)); } @@ -2266,18 +2264,20 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R } else { + /* Calculate Rx FIFO 1 element index */ + GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); + /* Check that the Rx FIFO 1 is full & overwrite mode is on */ if (((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U) { if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F1OM) >> FDCAN_RXGFC_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) { /* When overwrite status is on discard first message in FIFO */ - GetIndex = 1U; + /* GetIndex is incremented by one and wraps to 0 in case it overflows the FIFO size */ + GetIndex = (GetIndex + 1U) % SRAMCAN_RF1_NBR; } } - /* Calculate Rx FIFO 1 element index */ - GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); /* Calculate Rx FIFO 1 element address */ RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * SRAMCAN_RF1_SIZE)); } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c index 7a8ab2cb0b..8a4a773fa4 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c @@ -52,6 +52,10 @@ (#) Flash Memory IO Programming functions: (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and HAL_FLASH_Lock() functions + (++) Lock and unlock the non-secure FLASH control registers using + HAL_FLASH_Unlock_NS() and HAL_FLASH_Lock_NS() functions in secure context + (++) Lock and unlock the secure FLASH control registers using + HAL_FLASH_Unlock_S() and HAL_FLASH_Lock_S() functions in secure context (++) Program functions: quad-words and burst program (8 quad-words) (++) There are two modes of programming : (+++) Polling mode using HAL_FLASH_Program() function @@ -513,6 +517,96 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) return status; } +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Unlock the non-secure FLASH control register access in secure context. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock_NS(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (READ_BIT(FLASH->NSCR, FLASH_NSCR_LOCK) != 0U) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->NSKEYR, FLASH_KEY1); + WRITE_REG(FLASH->NSKEYR, FLASH_KEY2); + + /* verify Flash is unlocked */ + if (READ_BIT(FLASH->NSCR, FLASH_NSCR_LOCK) != 0U) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Lock the non-secure FLASH control register access in secure context. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock_NS(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->NSCR, FLASH_NSCR_LOCK); + + /* verify Flash is locked */ + if (READ_BIT(FLASH->NSCR, FLASH_NSCR_LOCK) != 0U) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Unlock the secure FLASH control register access in secure context. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock_S(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (READ_BIT(FLASH->SECCR, FLASH_SECCR_LOCK) != 0U) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->SECKEYR, FLASH_KEY1); + WRITE_REG(FLASH->SECKEYR, FLASH_KEY2); + + /* verify Flash is unlocked */ + if (READ_BIT(FLASH->SECCR, FLASH_SECCR_LOCK) != 0U) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Lock the secure FLASH control register access in secure context. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock_S(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->SECCR, FLASH_SECCR_LOCK); + + /* verify Flash is locked */ + if (READ_BIT(FLASH->SECCR, FLASH_SECCR_LOCK) != 0U) + { + status = HAL_OK; + } + + return status; +} +#endif /* __ARM_FEATURE_CMSE */ + /** * @brief Unlock the FLASH Option Bytes Registers access. * @retval HAL Status diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash_ex.c index df267a7062..f1faa39120 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash_ex.c @@ -39,6 +39,10 @@ (#) Flash Memory Erase functions: (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and HAL_FLASH_Lock() functions + (++) Lock and unlock the non-secure FLASH control registers using + HAL_FLASH_Unlock_NS() and HAL_FLASH_Lock_NS() functions in secure context + (++) Lock and unlock the secure FLASH control registers using + HAL_FLASH_Unlock_S() and HAL_FLASH_Lock_S() functions in secure context (++) Erase function: page Erase and Bank/Mass Erase (++) There are two modes of erase : (+++) Polling Mode using HAL_FLASHEx_Erase() @@ -1553,12 +1557,12 @@ static uint32_t FLASH_OB_GetRDP(void) * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST, * @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, - * @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK, + * @ref FLASH_OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK, * @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC, * @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST, * @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, * @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV, - * @ref FLASH_OB_USER_IO_VDDIO2_HSLV and @ref OB_USER_TZEN + * @ref FLASH_OB_USER_IO_VDDIO2_HSLV and @ref FLASH_OB_USER_TZEN */ static uint32_t FLASH_OB_GetUser(void) { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c index f14b6670da..b3fda368e0 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c @@ -788,8 +788,6 @@ HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hhcd); if (hhcd->State == HAL_HCD_STATE_READY) { @@ -855,12 +853,11 @@ HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, { /* Update the error code */ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hhcd); return status; } @@ -883,9 +880,6 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hhcd); - /* Setup Legacy weak Callbacks */ if (hhcd->State == HAL_HCD_STATE_READY) { @@ -958,8 +952,6 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hhcd); return status; } @@ -983,9 +975,6 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef * return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hhcd); - if (hhcd->State == HAL_HCD_STATE_READY) { hhcd->HC_NotifyURBChangeCallback = pCallback; @@ -999,9 +988,6 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef * status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hhcd); - return status; } @@ -1016,9 +1002,6 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hhcd); - if (hhcd->State == HAL_HCD_STATE_READY) { hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */ @@ -1032,9 +1015,6 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hhcd); - return status; } #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ @@ -2999,8 +2979,6 @@ HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hhcd); if (hhcd->State == HAL_HCD_STATE_READY) { @@ -3070,8 +3048,6 @@ HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hhcd); return status; } @@ -3095,9 +3071,6 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hhcd); - /* Setup Legacy weak Callbacks */ if (hhcd->State == HAL_HCD_STATE_READY) { @@ -3170,8 +3143,6 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hhcd); return status; } @@ -3195,9 +3166,6 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef * return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hhcd); - if (hhcd->State == HAL_HCD_STATE_READY) { hhcd->HC_NotifyURBChangeCallback = pCallback; @@ -3211,9 +3179,6 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef * status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hhcd); - return status; } @@ -3228,9 +3193,6 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hhcd); - if (hhcd->State == HAL_HCD_STATE_READY) { hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */ @@ -3244,9 +3206,6 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hhcd); - return status; } #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ @@ -4215,39 +4174,11 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) */ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { - uint32_t FnrReg = hhcd->Instance->FNR; uint32_t IstrReg = hhcd->Instance->ISTR; - /* SE0 detected USB Disconnected state */ - if ((FnrReg & (USB_FNR_RXDP | USB_FNR_RXDM)) == 0U) + /* SE0 detected USB Disconnected state */ + if ((IstrReg & USB_ISTR_DCON_STAT) == USB_ISTR_DCON_STAT) { - /* Host Port State */ - hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; - - /* Clear all allocated virtual channel */ - HAL_HCD_ClearPhyChannel(hhcd); - - /* Reset the PMA current pointer */ - (void)HAL_HCD_PMAReset(hhcd); - - /* Reset Ep0 Pma allocation state */ - hhcd->ep0_PmaAllocState = 0U; - - /* Disconnection Callback */ -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->DisconnectCallback(hhcd); -#else - HAL_HCD_Disconnect_Callback(hhcd); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - - return; - } - - if ((hhcd->HostState == HCD_HCD_STATE_DISCONNECTED) != 0U) - { - /* J-state or K-state detected & LastState=Disconnected */ - if (((FnrReg & USB_FNR_RXDP) != 0U) || ((IstrReg & USB_ISTR_LS_DCONN) != 0U)) - { hhcd->HostState = HCD_HCD_STATE_CONNECTED; #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) @@ -4255,32 +4186,27 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) #else HAL_HCD_Connect_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - } } else { - /* J-state or K-state detected & lastState=Connected: a Missed disconnection is detected */ - if (((FnrReg & USB_FNR_RXDP) != 0U) || ((IstrReg & USB_ISTR_LS_DCONN) != 0U)) - { - /* Host Port State */ - hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; + /* Host Port State */ + hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; - /* clear all allocated virtual channel */ - HAL_HCD_ClearPhyChannel(hhcd); + /* clear all allocated virtual channel */ + HAL_HCD_ClearPhyChannel(hhcd); - /* Reset the PMA current pointer */ - (void)HAL_HCD_PMAReset(hhcd); + /* Reset the PMA current pointer */ + (void)HAL_HCD_PMAReset(hhcd); - /* reset Ep0 PMA allocation state */ - hhcd->ep0_PmaAllocState = 0U; + /* reset Ep0 PMA allocation state */ + hhcd->ep0_PmaAllocState = 0U; - /* Disconnection Callback */ + /* Disconnection Callback */ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->DisconnectCallback(hhcd); + hhcd->DisconnectCallback(hhcd); #else - HAL_HCD_Disconnect_Callback(hhcd); + HAL_HCD_Disconnect_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - } } } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c index eab49cd8cc..f0bd766fbe 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c @@ -3458,8 +3458,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0UL; - HAL_StatusTypeDef status = HAL_OK; - FlagStatus tmp1; FlagStatus tmp2; @@ -3526,10 +3524,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Reset the error code for next trial */ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; } - else - { - status = HAL_ERROR; - } } else { @@ -3556,11 +3550,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - status = HAL_ERROR; - } - else + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) == HAL_OK) { /* Clear STOP Flag, auto generated with autoend*/ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -3569,12 +3559,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Increment Trials */ I2C_Trials++; - - if ((I2C_Trials < Trials) && (status == HAL_ERROR)) - { - status = HAL_OK; - } - } while (I2C_Trials < Trials); /* Update I2C state */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_lptim.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_lptim.c index 821aaea8fa..856f21e3a9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_lptim.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_lptim.c @@ -464,6 +464,11 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) /* Disable the LPTIM Peripheral Clock */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + hlptim->Instance->CFGR = 0; hlptim->Instance->CFGR2 = 0; @@ -621,6 +626,11 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Chann /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Set the LPTIM channel state */ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); @@ -738,6 +748,11 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Ch /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); @@ -1017,6 +1032,11 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Set the LPTIM channel state */ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); @@ -1134,6 +1154,11 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); @@ -1258,6 +1283,11 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t C /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Set the LPTIM channel state */ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); @@ -1373,6 +1403,11 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_ /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); @@ -1489,6 +1524,11 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; @@ -1575,6 +1615,11 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; /* Enable the Peripheral */ @@ -1664,6 +1709,11 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; @@ -1748,6 +1798,11 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; @@ -1769,6 +1824,12 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; @@ -1828,6 +1889,11 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; @@ -1899,6 +1965,11 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); @@ -3541,6 +3612,135 @@ void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma) hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; } +/** + * @brief Disable LPTIM HW instance. + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @note The following sequence is required to solve LPTIM disable HW limitation. + * Please check Errata Sheet ES0335 for more details under "MCU may remain + * stuck in LPTIM interrupt when entering Stop mode" section. + * @retval None + */ +void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) +{ + uint32_t tmpDIER; + uint32_t tmpCFGR; + uint32_t tmpCCR1; + uint32_t tmpARR; + uint32_t primask_bit; + uint32_t tmpCFGR2; + uint32_t tmpRCR; + uint32_t tmpCCMR1; + uint32_t tmpCCR2; + + /* Enter critical section */ + primask_bit = __get_PRIMASK(); + __set_PRIMASK(1) ; + + /* Save LPTIM configuration registers */ + tmpDIER = hlptim->Instance->DIER; + tmpCFGR = hlptim->Instance->CFGR; + tmpCCR1 = hlptim->Instance->CCR1; + tmpARR = hlptim->Instance->ARR; + tmpCFGR2 = hlptim->Instance->CFGR2; + tmpRCR = hlptim->Instance->RCR; + tmpCCMR1 = hlptim->Instance->CCMR1; + tmpCCR2 = hlptim->Instance->CCR2; + + /*********** Reset LPTIM ***********/ + switch ((uint32_t)hlptim->Instance) + { + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_FORCE_RESET(); + __HAL_RCC_LPTIM1_RELEASE_RESET(); + break; + case LPTIM2_BASE: + __HAL_RCC_LPTIM2_FORCE_RESET(); + __HAL_RCC_LPTIM2_RELEASE_RESET(); + break; + case LPTIM3_BASE: + __HAL_RCC_LPTIM3_FORCE_RESET(); + __HAL_RCC_LPTIM3_RELEASE_RESET(); + break; + case LPTIM4_BASE: + __HAL_RCC_LPTIM4_FORCE_RESET(); + __HAL_RCC_LPTIM4_RELEASE_RESET(); + break; + default: + break; + } + + /*********** Restore LPTIM Config ***********/ + if ((tmpCCR1 != 0UL) || (tmpCCR2 != 0UL) || (tmpARR != 0UL) || (tmpRCR != 0UL)) + { + if (tmpCCR1 != 0UL) + { + /* Restore tmpCCR1 register (LPTIM should be enabled first) */ + hlptim->Instance->CR |= LPTIM_CR_ENABLE; + hlptim->Instance->CCR1 = tmpCCR1; + + /* Wait for the completion of the write operation to the LPTIM_CCR1 register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT) + { + hlptim->State = HAL_LPTIM_STATE_TIMEOUT; + } + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK); + } + + if (tmpCCR2 != 0UL) + { + /* Restore tmpCCR1 register (LPTIM should be enabled first) */ + hlptim->Instance->CR |= LPTIM_CR_ENABLE; + hlptim->Instance->CCR2 = tmpCCR2; + + /* Wait for the completion of the write operation to the LPTIM_CCR2 register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) == HAL_TIMEOUT) + { + hlptim->State = HAL_LPTIM_STATE_TIMEOUT; + } + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK); + } + + if (tmpARR != 0UL) + { + /* Restore ARR register (LPTIM should be enabled first) */ + hlptim->Instance->CR |= LPTIM_CR_ENABLE; + hlptim->Instance->ARR = tmpARR; + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + hlptim->State = HAL_LPTIM_STATE_TIMEOUT; + } + + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + } + + if (tmpRCR != 0UL) + { + /* Restore RCR register (LPTIM should be enabled first) */ + hlptim->Instance->CR |= LPTIM_CR_ENABLE; + hlptim->Instance->RCR = tmpRCR; + + /* Wait for the completion of the write operation to the LPTIM_RCR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_REPOK) == HAL_TIMEOUT) + { + hlptim->State = HAL_LPTIM_STATE_TIMEOUT; + } + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK); + } + } + + /* Restore configuration registers (LPTIM should be disabled first) */ + hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE); + hlptim->Instance->DIER = tmpDIER; + hlptim->Instance->CFGR = tmpCFGR; + hlptim->Instance->CFGR2 = tmpCFGR2; + hlptim->Instance->CCMR1 = tmpCCMR1; + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} /** * @brief LPTimer Output Compare 1 configuration * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ltdc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ltdc.c index 5aa13bc818..f944616d0f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ltdc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ltdc.c @@ -188,7 +188,7 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, const LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); /* Private functions ---------------------------------------------------------*/ /** @defgroup LTDC_Exported_Functions LTDC Exported Functions @@ -279,24 +279,20 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); /* Set Synchronization size */ - hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); tmp = (hltdc->Init.HorizontalSync << 16U); - hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); + WRITE_REG(hltdc->Instance->SSCR, (tmp | hltdc->Init.VerticalSync)); /* Set Accumulated Back porch */ - hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); tmp = (hltdc->Init.AccumulatedHBP << 16U); - hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); + WRITE_REG(hltdc->Instance->BPCR, (tmp | hltdc->Init.AccumulatedVBP)); /* Set Accumulated Active Width */ - hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); tmp = (hltdc->Init.AccumulatedActiveW << 16U); - hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); + WRITE_REG(hltdc->Instance->AWCR, (tmp | hltdc->Init.AccumulatedActiveH)); /* Set Total Width */ - hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); tmp = (hltdc->Init.TotalWidth << 16U); - hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); + WRITE_REG(hltdc->Instance->TWCR, (tmp | hltdc->Init.TotalHeigh)); /* Set the background color value */ tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U); @@ -1351,7 +1347,9 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, u return HAL_OK; } /** + * * @brief Reconfigure the frame buffer Address. + * * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param Address new address value. @@ -1899,7 +1897,6 @@ HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t return HAL_OK; } - /** * @brief Configure the color keying without reloading. * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload. @@ -2130,7 +2127,7 @@ uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc) * This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval None */ -static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, const LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) { uint32_t tmp; uint32_t tmp1; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c index b395a3c149..d1d2cf0688 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c @@ -503,7 +503,14 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) hmmc->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; return HAL_ERROR; } - Init.ClockDiv = sdmmc_clk / (2U * MMC_INIT_FREQ); + if (sdmmc_clk <= MMC_INIT_FREQ) + { + Init.ClockDiv = 0U; + } + else + { + Init.ClockDiv = (sdmmc_clk / (2U * MMC_INIT_FREQ)) + 1U; + } #if (USE_SD_TRANSCEIVER != 0U) Init.TranceiverPresent = SDMMC_TRANSCEIVER_NOT_PRESENT; @@ -2418,7 +2425,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode) { uint32_t count; - SDMMC_InitTypeDef Init; + SDMMC_InitTypeDef Init = {0U}; uint32_t errorstate; uint32_t response = 0U; @@ -3596,7 +3603,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) HAL_MMC_CardCSDTypeDef CSD; uint32_t errorstate; uint16_t mmc_rca = 2U; - MMC_InitTypeDef Init; + MMC_InitTypeDef Init = {0U}; /* Check the power State */ if (SDMMC_GetPowerState(hmmc->Instance) == 0U) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nand.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nand.c index b6ef53653c..4801d2ae7d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nand.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nand.c @@ -523,9 +523,9 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_Ad uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numpagesread = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToRead; + uint32_t status; uint8_t *buff = pBuffer; /* Check the NAND controller state */ @@ -616,9 +616,11 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_Ad tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -626,9 +628,28 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_Ad /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } + + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Go back to read mode */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); @@ -642,9 +663,6 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_Ad buff++; } - /* Increment read pages number */ - numpagesread++; - /* Decrement pages to read */ nbpages--; @@ -681,9 +699,9 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_A uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numpagesread = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToRead; + uint32_t status; uint16_t *buff = pBuffer; /* Check the NAND controller state */ @@ -773,9 +791,11 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_A tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -783,9 +803,28 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_A /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } + + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Go back to read mode */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); @@ -810,9 +849,6 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_A buff++; } - /* Increment read pages number */ - numpagesread++; - /* Decrement pages to read */ nbpages--; @@ -849,9 +885,9 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_A uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numpageswritten = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToWrite; + uint32_t status; const uint8_t *buff = pBuffer; /* Check the NAND controller state */ @@ -949,9 +985,11 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_A tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -959,12 +997,28 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_A /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } - /* Increment written pages number */ - numpageswritten++; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Decrement pages to write */ nbpages--; @@ -1002,9 +1056,9 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_ uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numpageswritten = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToWrite; + uint32_t status; const uint16_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1113,9 +1167,11 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_ tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -1123,12 +1179,28 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_ /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } - /* Increment written pages number */ - numpageswritten++; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Decrement pages to write */ nbpages--; @@ -1166,10 +1238,10 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NA uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numsparearearead = 0U; uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaToRead; + uint32_t status; uint8_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1266,9 +1338,11 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NA tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -1276,9 +1350,28 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NA /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } + + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Go back to read mode */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); @@ -1292,9 +1385,6 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NA buff++; } - /* Increment read spare areas number */ - numsparearearead++; - /* Decrement spare areas to read */ nbspare--; @@ -1331,10 +1421,10 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const N uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numsparearearead = 0U; uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaToRead; + uint32_t status; uint16_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1431,9 +1521,11 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const N tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -1441,9 +1533,28 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const N /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } + + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Go back to read mode */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); @@ -1457,9 +1568,6 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const N buff++; } - /* Increment read spare areas number */ - numsparearearead++; - /* Decrement spare areas to read */ nbspare--; @@ -1496,10 +1604,10 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const N uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numspareareawritten = 0U; uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaTowrite; + uint32_t status; const uint8_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1606,9 +1714,11 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const N tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -1616,12 +1726,28 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const N /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } - /* Increment written spare areas number */ - numspareareawritten++; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Decrement spare areas to write */ nbspare--; @@ -1659,10 +1785,10 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numspareareawritten = 0U; uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaTowrite; + uint32_t status; const uint16_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1769,9 +1895,11 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -1779,12 +1907,28 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } - /* Increment written spare areas number */ - numspareareawritten++; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Decrement spare areas to write */ nbspare--; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nor.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nor.c index 36d83a84c9..445bafe01e 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nor.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nor.c @@ -24,7 +24,7 @@ [..] This driver is a generic layered driver which contains a set of APIs used to control NOR flash memories. It uses the FMC layer functions to interface - with NOR devices. This driver is used as follows: + with NOR 16-bit devices. The NOR 8-bit support is deprecated. This driver is used as follows: (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() with control and timing parameters for both normal and extended mode. @@ -127,11 +127,6 @@ */ /* Constants to define address to set to write a command */ -#define NOR_CMD_ADDRESS_FIRST_BYTE (uint16_t)0x0AAA -#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE (uint16_t)0x00AA -#define NOR_CMD_ADDRESS_SECOND_BYTE (uint16_t)0x0555 -#define NOR_CMD_ADDRESS_THIRD_BYTE (uint16_t)0x0AAA - #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA @@ -196,8 +191,6 @@ * @{ */ -static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; - /** * @} */ @@ -243,6 +236,12 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe return HAL_ERROR; } + /* Check if deprecated 8-bit support is used */ + if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8) + { + return HAL_ERROR; + } + if (hnor->State == HAL_NOR_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -275,16 +274,6 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe /* Enable the NORSRAM device */ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); - /* Initialize NOR Memory Data Width*/ - if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8) - { - uwNORMemoryDataWidth = NOR_MEMORY_8B; - } - else - { - uwNORMemoryDataWidth = NOR_MEMORY_16B; - } - /* Enable FMC Peripheral */ __FMC_ENABLE(); @@ -319,17 +308,9 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe else { /* Get the value of the command set */ - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), - NOR_CMD_DATA_CFI); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); + hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_ADDRESS_COMMAND_SET); status = HAL_NOR_ReturnToReadMode(hnor); } @@ -490,22 +471,9 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I /* Send read ID command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_AUTO_SELECT); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_AUTO_SELECT); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -520,13 +488,10 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I if (status != HAL_ERROR) { /* Read the NOR IDs */ - pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); - pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, - DEVICE_CODE1_ADDR); - pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, - DEVICE_CODE2_ADDR); - pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, - DEVICE_CODE3_ADDR); + pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, MC_ADDRESS); + pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, DEVICE_CODE1_ADDR); + pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, DEVICE_CODE2_ADDR); + pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, DEVICE_CODE3_ADDR); } /* Check the NOR controller state */ @@ -672,22 +637,9 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint /* Send read data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_READ_RESET); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_READ_RESET); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -702,7 +654,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint if (status != HAL_ERROR) { /* Read the data */ - *pData = (uint16_t)(*(__IO uint32_t *)pAddress); + *pData = *(__IO uint16_t *)pAddress; } /* Check the NOR controller state */ @@ -766,21 +718,9 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u /* Send program data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_PROGRAM); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -870,22 +810,9 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress /* Send read data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_READ_RESET); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_READ_RESET); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -978,20 +905,10 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - } - else - { - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - } + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + /* Write Buffer Load Command */ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); @@ -1091,26 +1008,15 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd /* Send block erase command sequence */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) @@ -1188,28 +1094,16 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) /* Send NOR chip erase command sequence */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), - NOR_CMD_DATA_CHIP_ERASE); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SIXTH), + NOR_CMD_DATA_CHIP_ERASE); } else { @@ -1280,20 +1174,13 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR } /* Send read CFI query command */ - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), - NOR_CMD_DATA_CFI); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + /* read the NOR CFI information */ - pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); - pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); - pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS); - pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS); + pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, CFI1_ADDRESS); + pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, CFI2_ADDRESS); + pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, CFI3_ADDRESS); + pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, CFI4_ADDRESS); /* Check the NOR controller state */ hnor->State = state; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c index 86b77be302..e19eb53f8e 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c @@ -134,6 +134,7 @@ [..] After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires. + HAL_OSPI_IsMemoryMapped() can be used to verify whether memory-mapped mode is configured or not. *** Errors management and abort functionality *** ================================================= @@ -1980,6 +1981,29 @@ HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMa return status; } +/** + * @brief Check whether the OCTOSPI is configured in Memory-mapped mode or not. + * @param hospi : OSPI handle + * @retval Status (0: Memory-mapped disabled or OCTOSPI not initialized, 1: Memory-mapped enabled) + */ +uint32_t HAL_OSPI_IsMemoryMapped(const OSPI_HandleTypeDef *hospi) +{ + /* Check the OSPI handle allocation */ + if (hospi == NULL) + { + return (0UL); + } + /* Check if driver is in Reset state */ + else if (hospi->State == HAL_OSPI_STATE_RESET) + { + return (0UL); + } + else + { + return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FMODE) == OCTOSPI_CR_FMODE) ? 1UL : 0UL); + } +} + /** * @brief Transfer Error callback. * @param hospi : OSPI handle @@ -2712,8 +2736,8 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * /********************* Deactivation of other instance *********************/ if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || ((cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && (cfg->DQSPort != 0U)) || - (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || - (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) + ((cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) && (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)) || + ((cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort) && (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE))) { if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_otfdec.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_otfdec.c index a67f01d8c5..148f0f0212 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_otfdec.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_otfdec.c @@ -525,9 +525,6 @@ __weak void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec) * @} */ - - - /** @defgroup OTFDEC_Exported_Functions_Group3 Peripheral Control functions * @brief Peripheral control functions. * @@ -1120,9 +1117,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint Config->EndAddress = READ_REG(region->REG_END_ADDR); /* Read Version */ - Config->Version = (READ_REG(region->REG_CONFIGR) & - OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos; - + Config->Version = (uint16_t)((READ_REG(region->REG_CONFIGR) & + OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos); /* Release Lock */ __HAL_UNLOCK(hotfdec); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c index d9216a6dff..86d5865cb9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c @@ -360,8 +360,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); if (hpcd->State == HAL_PCD_STATE_READY) { @@ -439,8 +437,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); return status; } @@ -465,9 +461,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - /* Setup Legacy weak Callbacks */ if (hpcd->State == HAL_PCD_STATE_READY) { @@ -548,8 +541,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); return status; } @@ -573,9 +564,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->DataOutStageCallback = pCallback; @@ -589,9 +577,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -605,9 +590,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */ @@ -621,9 +603,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -647,9 +626,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->DataInStageCallback = pCallback; @@ -663,9 +639,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -679,9 +652,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */ @@ -695,9 +665,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -721,9 +688,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->ISOOUTIncompleteCallback = pCallback; @@ -737,9 +701,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -754,9 +715,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */ @@ -770,9 +728,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -796,9 +751,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->ISOINIncompleteCallback = pCallback; @@ -812,9 +764,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -829,9 +778,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */ @@ -845,9 +791,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -870,9 +813,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdC return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->BCDCallback = pCallback; @@ -886,9 +826,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdC status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -902,9 +839,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback */ @@ -918,9 +852,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -943,9 +874,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmC return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->LPMCallback = pCallback; @@ -959,9 +887,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmC status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -975,9 +900,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */ @@ -991,9 +913,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ @@ -1664,6 +1583,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + /* store current frame number */ + hpcd->FrameNumber = USB_GetCurrentFrame(hpcd->Instance); + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else @@ -2555,6 +2477,9 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) count = 0U; #endif /* USE_USB_DOUBLE_BUFFER */ + /* store current frame number */ + hpcd->FrameNumber = USB_GetCurrentFrame(hpcd->Instance); + /* stay in loop while pending interrupts */ while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) { @@ -2563,6 +2488,11 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_IDN); + if (epindex >= 8U) + { + return HAL_ERROR; + } + if (epindex == 0U) { /* Decode and service control endpoint interrupt */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c index b93ae117da..b7b39266f7 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c @@ -2389,20 +2389,20 @@ void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef /* Move the input parameters pOp1 to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + ((in->OpSize + 3UL) / 4UL)); /* Move the exponent to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + ((in->expSize + 3UL) / 4UL)); /* Move the modulus to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + ((in->OpSize + 3UL) / 4UL)); /* Move the Montgomery parameter to PKA RAM */ PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, in->OpSize / 4UL); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + ((in->OpSize + 3UL) / 4UL)); } /** @@ -2420,19 +2420,19 @@ void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInT /* Move the input parameters pOp1 to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE], in->pOp1, in->OpSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + ((in->OpSize + 3UL) / 4UL)); /* Move the exponent to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT], in->pExp, in->expSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + (in->expSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + ((in->expSize + 3UL) / 4UL)); /* Move the modulus to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_MODULUS], in->pMod, in->OpSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_MODULUS + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_MODULUS + ((in->OpSize + 3UL) / 4UL)); /* Move Phi value to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI], in->pPhi, in->OpSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + ((in->OpSize + 3UL) / 4UL)); } /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c index 0d84eb060c..d00a369790 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c @@ -485,9 +485,6 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) /* Clear all interrupts flags */ WRITE_REG(RCC->CICR, 0xFFFFFFFFU); - /* Reset all CSR flags */ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); - /* Update the SystemCoreClock global variable */ SystemCoreClock = MSI_VALUE; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c index eaa87eceab..49d696b033 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c @@ -645,7 +645,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; /* Check if there is a seed error */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; @@ -665,6 +665,14 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t /* Check if data register contains valid random data */ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) { + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; + hrng->State = HAL_RNG_STATE_READY; + return HAL_ERROR; + } + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { /* New check to avoid false timeout detection in case of preemption */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c index 1458006886..ef651bf403 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c @@ -158,6 +158,14 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigT /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; + /*Check if seed error current status (SECS)is set */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_SR_SECS) != RESET) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; + return HAL_ERROR; + } + /* function status */ status = HAL_OK; } @@ -206,6 +214,7 @@ HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef pConf->NistCompliance = (hrng->Instance->CR & RNG_CR_NISTC); pConf->AutoReset = (hrng->Instance->CR & RNG_CR_ARDIS); pConf->HealthTest = (hrng->Instance->HTCR); + pConf->NoiseSource = (hrng->Instance->NSCR); /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; @@ -294,6 +303,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) { HAL_StatusTypeDef status; + HAL_RNG_StateTypeDef state; /* Check the RNG handle allocation */ if (hrng == NULL) @@ -301,8 +311,10 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) return HAL_ERROR; } + state = hrng->State; + /* Check RNG peripheral state */ - if (hrng->State == HAL_RNG_STATE_READY) + if ((state == HAL_RNG_STATE_READY) || (state == HAL_RNG_STATE_ERROR)) { /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc_ex.c index 3332178e8c..bb8994ccc6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc_ex.c @@ -1872,7 +1872,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetBoothardwareKey(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - WRITE_REG(TAMP->SECCFGR, TAMP_SECCFGR_BHKLOCK); + SET_BIT(TAMP->SECCFGR, TAMP_SECCFGR_BHKLOCK); return HAL_OK; } @@ -2743,7 +2743,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) void HAL_RTCEx_BKUPErase(RTC_HandleTypeDef *hrtc) { UNUSED(hrtc); - WRITE_REG(TAMP->CR2, TAMP_CR2_BKERASE); + SET_BIT(TAMP->CR2, TAMP_CR2_BKERASE); } /** @@ -2754,7 +2754,7 @@ void HAL_RTCEx_BKUPErase(RTC_HandleTypeDef *hrtc) void HAL_RTCEx_BKUPBlock_Enable(RTC_HandleTypeDef *hrtc) { UNUSED(hrtc); - WRITE_REG(TAMP->CR2, TAMP_CR2_BKBLOCK); + SET_BIT(TAMP->CR2, TAMP_CR2_BKBLOCK); } /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c index c9e8b610ab..cbe0f64ae0 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c @@ -482,7 +482,14 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; return HAL_ERROR; } - Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ); + if (sdmmc_clk <= SD_INIT_FREQ) + { + Init.ClockDiv = 0U; + } + else + { + Init.ClockDiv = (sdmmc_clk / (2U * SD_INIT_FREQ)) + 1U; + } #if (USE_SD_TRANSCEIVER != 0U) Init.TranceiverPresent = hsd->Init.TranceiverPresent; @@ -3106,7 +3113,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ errorstate = SDMMC_CmdOperCond(hsd->Instance); - if (errorstate == SDMMC_ERROR_TIMEOUT) /* No response to CMD8 */ + if (errorstate == SDMMC_ERROR_CMD_RSP_TIMEOUT) /* No response to CMD8 */ { hsd->SdCard.CardVersion = CARD_V1_X; /* CMD0: GO_IDLE_STATE */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sdio.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sdio.c index eda719c34c..a1fbe6d9f8 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sdio.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sdio.c @@ -231,11 +231,11 @@ #define SDIO_INIT_FREQ 400000U /*!< Initialization phase : 400 kHz max */ #define SDIO_TIMEOUT 1000U /*!< SDIO timeout millisecond */ -#define SDIO_FUNCTION_0 0x00U /*!< SDIO_Functions 0 */ -#define SDIO_FUNCTION_1 0x01U /*!< SDIO_Functions 1 */ +#define SDIO_FUNCTION_0 0x00UL /*!< SDIO_Functions 0 */ +#define SDIO_FUNCTION_1 0x01UL /*!< SDIO_Functions 1 */ -#define SDIO_READ 0x0U /*!< Read flag for cmd52 and cmd53 */ -#define SDIO_WRITE 0x1U /*!< Write flag for cmd52 and cmd53 */ +#define SDIO_READ 0x0UL /*!< Read flag for cmd52 and cmd53 */ +#define SDIO_WRITE 0x1UL /*!< Write flag for cmd52 and cmd53 */ #define SDIO_BUS_SPEED_SDR12 0x00U /*!< SDIO bus speed mode SDR12 */ #define SDIO_BUS_SPEED_SDR25 0x02U /*!< SDIO bus speed mode SDR25 */ @@ -244,8 +244,8 @@ #define SDIO_CCCR_REG_NUMBER 0x16U /*!< SDIO card cccr register number */ -#define SDIO_OCR_VDD_32_33 (1U << 20U) -#define SDIO_OCR_SDIO_S18R (1U << 24U) +#define SDIO_OCR_VDD_32_33 (1UL << 20U) +#define SDIO_OCR_SDIO_S18R (1UL << 24U) /** * @} */ @@ -278,7 +278,7 @@ static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t add uint8_t *pData); static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr, const uint8_t *pData); -static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg, +static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg, uint8_t *pData, uint16_t Size_byte); static uint8_t SDIO_Convert_Block_Size(const SDIO_HandleTypeDef *hsdio, uint32_t block_size); static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio); @@ -637,19 +637,19 @@ HAL_StatusTypeDef HAL_SDIO_SetSpeedMode(SDIO_HandleTypeDef *hsdio, uint32_t Data switch (DataRate) { case HAL_SDIOS_DATA_RATE_SDR25: - data = SDIO_BUS_SPEED_SDR25; + data = (uint8_t)SDIO_BUS_SPEED_SDR25; errorstate = SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR16_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data); break; case HAL_SDIOS_DATA_RATE_SDR50: - data = SDIO_BUS_SPEED_SDR50; + data = (uint8_t)SDIO_BUS_SPEED_SDR50; errorstate = SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2U) | (SDIO_FUNCTION_0 << 1U) | (SDIO_FUNCTION_0 << 14U) | SDMMC_SDIO_CCCR16_SD_BYTE3), HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data); MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED, SDMMC_CLKCR_BUSSPEED); break; case HAL_SDIOS_DATA_RATE_DDR50: - data = SDIO_BUS_SPEED_DDR50; + data = (uint8_t)SDIO_BUS_SPEED_DDR50; errorstate = SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2) | (SDIO_FUNCTION_0 << 1) | (SDIO_FUNCTION_0 << 14) | SDMMC_SDIO_CCCR16_SD_BYTE3), HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data); MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED, @@ -1018,7 +1018,14 @@ HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDI cmd |= Argument->Block_Mode << 27U; cmd |= Argument->OpCode << 26U; cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; - cmd |= (Size_byte & 0x1FFU); + if (Argument->Block_Mode == HAL_SDIO_MODE_BYTE) + { + cmd |= (((uint32_t)Size_byte) & 0x1FFU); + } + else /* HAL_SDIO_BLOCK_MODE_BLOCK */ + { + cmd |= nbr_of_block & 0x1FFU; + } errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); if (errorstate != HAL_SDIO_ERROR_NONE) { @@ -1163,7 +1170,7 @@ HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, const HAL_SD uint8_t byteCount; uint32_t data; uint32_t dataremaining; - uint8_t *u32tempbuff = pData; + uint32_t *u32tempbuff = (uint32_t *)(uint32_t)pData; uint32_t nbr_of_block; /* Check the parameters */ @@ -1223,7 +1230,14 @@ HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, const HAL_SD cmd |= Argument->Block_Mode << 27U; cmd |= Argument->OpCode << 26U; cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; - cmd |= (Size_byte & 0x1FFU); + if (Argument->Block_Mode == HAL_SDIO_MODE_BYTE) + { + cmd |= (((uint32_t)Size_byte) & 0x1FFU); + } + else /* HAL_SDIO_BLOCK_MODE_BLOCK */ + { + cmd |= nbr_of_block & 0x1FFU; + } errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); if (errorstate != HAL_SDIO_ERROR_NONE) { @@ -2498,7 +2512,7 @@ static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio) uint32_t errorstate; uint32_t timeout = 0U; uint16_t sdio_rca = 1U; - uint32_t Resp4; + uint32_t Resp4 = 0U; uint32_t nbr_of_func; /* Identify card operating voltage */ @@ -2653,7 +2667,7 @@ static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t ad * @param pData: pointer to write or read data * @retval HAL status */ -static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg, +static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg, uint8_t *pData, uint16_t Size_byte) { SDMMC_DataInitTypeDef config; @@ -2835,7 +2849,7 @@ static uint8_t SDIO_Convert_Block_Size(const SDIO_HandleTypeDef *hsdio, uint32_t static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio) { uint8_t count; - uint8_t pendingInt; + uint8_t pendingInt = 0U; if (hsdio->IOInterruptNbr == 1U) { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c index cb904b2194..70f0064708 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c @@ -2506,14 +2506,6 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard ((uint32_t)hsmartcard->Init.WordLength)); MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); - /*-------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = hsmartcard->Init.StopBits; - /* Synchronous mode is activated by default */ - tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; - tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; - tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; - MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); - /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure * - one-bit sampling method versus three samples' majority rule @@ -2535,6 +2527,14 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos)); MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg); + /*-------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = hsmartcard->Init.StopBits; + /* Synchronous mode is activated by default */ + tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; + tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; + tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); + /*-------------------------- USART RTOR Configuration ----------------------*/ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus.c index c4508ad72d..14c69146eb 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus.c @@ -1549,55 +1549,50 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Wait until STOPF flag is reset */ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Reset the error code for next trial */ + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - /* Device is ready */ - hsmbus->State = HAL_SMBUS_STATE_READY; + /* Device is ready */ + hsmbus->State = HAL_SMBUS_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - } - - /* Check if the maximum allowed number of trials has been reached */ - if (SMBUS_Trials == Trials) - { - /* Generate Stop */ - hsmbus->Instance->CR2 |= I2C_CR2_STOP; - /* Wait until STOPF flag is reset */ - if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) == HAL_OK) { - return HAL_ERROR; + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); } - - /* Clear STOP Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); } /* Increment Trials */ SMBUS_Trials++; } while (SMBUS_Trials < Trials); + /* Update SMBUS state */ hsmbus->State = HAL_SMBUS_STATE_READY; /* Update SMBUS error code */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c index e26b02892a..10ac74e540 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c @@ -212,7 +212,7 @@ HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t * @brief Set Autonomous Mode configuration * @param hspi Pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPIx peripheral. - * @param sConfig Pointer to a SPI_HandleTypeDef structure that contains + * @param sConfig Pointer to a SPI_AutonomousModeConfTypeDef structure that contains * the configuration information of the autonomous mode for the specified SPIx peripheral. * @retval HAL status */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c index 5b7027e1fa..773f190044 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c @@ -7300,6 +7300,9 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; + /* Ensure that the update event is generated before writing back CR1 register with URS = 0 */ + __DSB(); + TIMx->CR1 = tmpcr1; } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c index 3727cf0271..2f7fa716f4 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c @@ -644,8 +644,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - __HAL_UART_DISABLE(huart); - huart->Instance->CR1 = 0x0U; huart->Instance->CR2 = 0x0U; huart->Instance->CR3 = 0x0U; @@ -1169,7 +1167,15 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); pdata8bits++; } - huart->TxXferCount--; + if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX) + { + huart->TxXferCount--; + } + else + { + /* Process was aborted during the transmission */ + return HAL_ERROR; + } } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) @@ -1273,7 +1279,15 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); pdata8bits++; } - huart->RxXferCount--; + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + huart->RxXferCount--; + } + else + { + /* Process was aborted during the reception */ + return HAL_ERROR; + } } /* At end of Rx process, restore huart->RxState to Ready */ @@ -1833,10 +1847,6 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) } #endif /* HAL_DMA_MODULE_ENABLED */ - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -1907,9 +1917,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) } #endif /* HAL_DMA_MODULE_ENABLED */ - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { @@ -1976,9 +1983,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) } #endif /* HAL_DMA_MODULE_ENABLED */ - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -2110,10 +2114,6 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (abortcplt == 1U) { - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Clear ISR function pointers */ huart->RxISR = NULL; huart->TxISR = NULL; @@ -2196,8 +2196,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) } else { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -2218,9 +2216,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) else #endif /* HAL_DMA_MODULE_ENABLED */ { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -2297,9 +2292,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) } else { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; @@ -2326,9 +2318,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) else #endif /* HAL_DMA_MODULE_ENABLED */ { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; @@ -3936,7 +3925,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { - huart->TxXferCount = 0U; UART_EndTxTransfer(huart); } @@ -3944,7 +3932,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { - huart->RxXferCount = 0U; UART_EndRxTransfer(huart); } @@ -3968,7 +3955,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->RxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ @@ -4002,10 +3988,6 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) } } - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -4057,10 +4039,6 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } } - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -4098,8 +4076,6 @@ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->TxXferCount = 0U; - /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { @@ -4131,8 +4107,6 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_wwdg.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_wwdg.c index ad3ab327d7..cc95afa6fc 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_wwdg.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_wwdg.c @@ -95,7 +95,7 @@ and a pointer to the user callback function. (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to - the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback() + the default weak function. HAL_WWDG_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID. This function allows to reset following callbacks: (++) EwiCallback : callback for Early WakeUp Interrupt. @@ -103,14 +103,14 @@ [..] When calling HAL_WWDG_Init function, callbacks are reset to the - corresponding legacy weak (surcharged) functions: + corresponding legacy weak functions: HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have not been registered before. [..] When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. *** WWDG HAL driver macros list *** =================================== @@ -240,7 +240,7 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) /** * @brief Register a User WWDG Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @param hwwdg WWDG handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -282,7 +282,7 @@ HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_ /** * @brief Unregister a WWDG Callback - * WWDG Callback is redirected to the weak (surcharged) predefined callback + * WWDG Callback is redirected to the weak (overridden) predefined callback * @param hwwdg WWDG handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmc.c index 1281f5d1b9..06c50ea4d1 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmc.c @@ -512,7 +512,6 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device * @} */ #endif /* FMC_BANK1 */ - #if defined(FMC_BANK3) /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions @@ -788,7 +787,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCv */ #endif /* FMC_BANK3 */ - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lptim.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lptim.c index dca6a544f8..378e30366a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lptim.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lptim.c @@ -180,6 +180,125 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPT return result; } +/** + * @brief Disable the LPTIM instance + * @rmtoll CR ENABLE LL_LPTIM_Disable + * @param LPTIMx Low-Power Timer instance + * @note The following sequence is required to solve LPTIM disable HW limitation. + * Please check Errata Sheet ES0335 for more details under "MCU may remain + * stuck in LPTIM interrupt when entering Stop mode" section. + * @retval None + */ +void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) +{ + LL_RCC_ClocksTypeDef rcc_clock; + uint32_t tmpDIER; + uint32_t tmpCFGR; + uint32_t tmpCCR1; + uint32_t tmpARR; + uint32_t primask_bit; + uint32_t tmpCFGR2; + uint32_t tmpRCR; + uint32_t tmpCCMR1; + uint32_t tmpCCR2; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(LPTIMx)); + + /* Enter critical section */ + primask_bit = __get_PRIMASK(); + __set_PRIMASK(1) ; + + /* Save LPTIM configuration registers */ + tmpDIER = LPTIMx->DIER; + tmpCFGR = LPTIMx->CFGR; + tmpCCR1 = LPTIMx->CCR1; + tmpARR = LPTIMx->ARR; + tmpCFGR2 = LPTIMx->CFGR2; + tmpRCR = LPTIMx->RCR; + tmpCCMR1 = LPTIMx->CCMR1; + tmpCCR2 = LPTIMx->CCR2; + + /************* Reset LPTIM ************/ + (void)LL_LPTIM_DeInit(LPTIMx); + + /********* Restore LPTIM Config *******/ + LL_RCC_GetSystemClocksFreq(&rcc_clock); + + if ((tmpCCR1 != 0UL) || (tmpCCR2 != 0UL) || (tmpARR != 0UL) || (tmpRCR != 0UL)) + { + if (tmpCCR1 != 0UL) + { + /* Restore CMP and ARR registers (LPTIM should be enabled first) */ + LPTIMx->CR |= LPTIM_CR_ENABLE; + LPTIMx->CCR1 = tmpCCR1; + + /* Polling on CMP write ok status after above restore operation */ + do + { + rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ + } while (((LL_LPTIM_IsActiveFlag_CMP1OK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + + LL_LPTIM_ClearFlag_CMP1OK(LPTIMx); + } + + if (tmpCCR2 != 0UL) + { + /* Restore CMP and ARR registers (LPTIM should be enabled first) */ + LPTIMx->CR |= LPTIM_CR_ENABLE; + LPTIMx->CCR2 = tmpCCR2; + + /* Polling on CMP write ok status after above restore operation */ + do + { + rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ + } while (((LL_LPTIM_IsActiveFlag_CMP2OK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + + LL_LPTIM_ClearFlag_CMP2OK(LPTIMx); + } + + if (tmpARR != 0UL) + { + LPTIMx->CR |= LPTIM_CR_ENABLE; + LPTIMx->ARR = tmpARR; + + LL_RCC_GetSystemClocksFreq(&rcc_clock); + /* Polling on ARR write ok status after above restore operation */ + do + { + rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ + } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + + LL_LPTIM_ClearFlag_ARROK(LPTIMx); + } + + if (tmpRCR != 0UL) + { + LPTIMx->CR |= LPTIM_CR_ENABLE; + LPTIMx->RCR = tmpRCR; + + LL_RCC_GetSystemClocksFreq(&rcc_clock); + /* Polling on RCR write ok status after above restore operation */ + do + { + rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ + } while (((LL_LPTIM_IsActiveFlag_REPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + + LL_LPTIM_ClearFlag_REPOK(LPTIMx); + } + } + + /* Restore configuration registers (LPTIM should be disabled first) */ + LPTIMx->CR &= ~(LPTIM_CR_ENABLE); + LPTIMx->DIER = tmpDIER; + LPTIMx->CFGR = tmpCFGR; + LPTIMx->CFGR2 = tmpCFGR2; + LPTIMx->CCMR1 = tmpCCMR1; + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lpuart.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lpuart.c index db8a4dcd8b..cc1d8eeff0 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lpuart.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lpuart.c @@ -77,8 +77,8 @@ /* - fck must be in the range [3 x baudrate, 4096 x baudrate] */ /* - LPUART_BRR register value should be >= 0x300 */ /* - LPUART_BRR register value should be <= 0xFFFFF (20 bits) */ -/* Baudrate specified by the user should belong to [8, 33000000].*/ -#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 33000000U) && ((__BAUDRATE__) >= 8U)) +/* Baudrate specified by the user should belong to [8, 53000000].*/ +#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 53000000U) && ((__BAUDRATE__) >= 8U)) /* __VALUE__ BRR content must be greater than or equal to 0x300. */ #define IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c index 3fed68ca5d..99b8fbf5a9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c @@ -613,8 +613,6 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI * @note Channel 2 is configured in output PWM 2 mode. * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. * @note OC2REF is selected as trigger output on TRGO. - * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used - * when TIMx operates in Hall sensor interface mode. * @param TIMx Timer Instance * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor * interface configuration data structure) @@ -674,7 +672,7 @@ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_In /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); - tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + tmpccer |= (uint32_t)(TIM_CCER_CC1E); /* Write to TIMx CR2 */ LL_TIM_WriteReg(TIMx, CR2, tmpcr2); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c index 5b2e594bb0..e3c07fcdb4 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c @@ -99,6 +99,10 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c if (cfg.dma_enable == 1U) { + /* make sure to reserve 18 fifo Locations for DMA buffers */ + USBx->GDFIFOCFG &= ~(0xFFFFUL << 16); + USBx->GDFIFOCFG |= 0x3EEUL << 16; + USBx->GAHBCFG &= ~(USB_OTG_GAHBCFG_HBSTLEN); USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_INCR4; USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; @@ -937,10 +941,10 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { __IO uint32_t count = 0U; + __IO uint32_t RegVal; HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t dma_enable = (USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) >> 0x5U; - uint32_t RegVal; /* IN endpoint */ if (ep->is_in == 1U) @@ -2244,7 +2248,7 @@ HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) * @param ch_dir Host Channel direction * @retval HAL state */ -HAL_StatusTypeDef USB_HC_Activate(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t ch_dir) +HAL_StatusTypeDef USB_HC_Activate(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t ch_dir) { UNUSED(ch_dir); @@ -3308,6 +3312,16 @@ void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABu } } +/** + * @brief Return Current Frame number + * @param USBx Selected device + * @retval current frame number + */ +uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx) +{ + return (uint32_t)(USBx->FNR & 0x7FFU); +} + /*------------------------------------------------------------------------*/ /* HOST API */ @@ -3387,16 +3401,6 @@ uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx) } } -/** - * @brief Return Host Current Frame number - * @param USBx Selected device - * @retval current frame number - */ -uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx) -{ - return USBx->FNR & 0x7FFU; -} - #if defined (HAL_HCD_MODULE_ENABLED) /** * @brief Initialize a host channel diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 8aa4f78183..baab698932 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -18,7 +18,7 @@ * STM32MP1: 1.7.0 * STM32U0: 1.3.0 * STM32U3: 1.4.0 - * STM32U5: 1.6.2 + * STM32U5: 1.6.3 * STM32WB: 1.14.7 * STM32WB0: 1.5.0 * STM32WBA: 1.9.0