From 37d95778f6312fa93c4da3bebd8911f48f8a7f89 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Jul 2026 10:16:03 +0200 Subject: [PATCH 1/4] chore(wb0): update patch Signed-off-by: Frederic Pillon --- .../0001-fix-wb0-HAL-and-LL-warnings.patch | 72 ++++++------------- 1 file changed, 22 insertions(+), 50 deletions(-) diff --git a/CI/update/patch/HAL/WB0/0001-fix-wb0-HAL-and-LL-warnings.patch b/CI/update/patch/HAL/WB0/0001-fix-wb0-HAL-and-LL-warnings.patch index 4cc965211d..5a0f1fe36f 100644 --- a/CI/update/patch/HAL/WB0/0001-fix-wb0-HAL-and-LL-warnings.patch +++ b/CI/update/patch/HAL/WB0/0001-fix-wb0-HAL-and-LL-warnings.patch @@ -7,10 +7,8 @@ Signed-off-by: Frederic Pillon --- .../Inc/stm32wb0x_ll_dma.h | 40 +++++++++++++++++++ .../Inc/stm32wb0x_ll_radio_timer.h | 3 ++ - .../Src/stm32wb0x_hal_flash_ex.c | 2 +- .../Src/stm32wb0x_hal_radio_timer.c | 4 +- - .../Src/stm32wb0x_ll_adc.c | 2 +- - 5 files changed, 47 insertions(+), 4 deletions(-) + 3 files changed, 45 insertions(+), 2 deletions(-) diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_dma.h b/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_dma.h index bc237ac45..fff12f8c3 100644 @@ -23,7 +21,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } - + @@ -450,6 +451,7 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) @@ -31,7 +29,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } - + @@ -470,6 +472,7 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) @@ -191,7 +189,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } - + @@ -985,6 +1007,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) @@ -199,7 +197,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress); } - + @@ -1006,6 +1029,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) @@ -207,7 +205,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } - + @@ -1027,6 +1051,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) @@ -215,7 +213,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } - + @@ -1050,6 +1075,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) @@ -223,7 +221,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress); } - + @@ -1073,6 +1099,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) @@ -231,7 +229,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } - + @@ -1094,6 +1121,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) @@ -239,7 +237,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } - + @@ -1115,6 +1143,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) @@ -247,7 +245,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } - + @@ -1137,6 +1166,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) @@ -255,7 +253,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID, Request); } - + @@ -1158,6 +1188,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) @@ -263,7 +261,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID)); } - + @@ -1897,6 +1928,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) @@ -271,7 +269,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } - + @@ -1917,6 +1949,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) @@ -279,7 +277,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } - + @@ -1937,6 +1970,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) @@ -287,7 +285,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } - + @@ -1957,6 +1991,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) @@ -295,7 +293,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } - + @@ -1977,6 +2012,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) @@ -303,7 +301,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } - + @@ -1997,6 +2033,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) @@ -311,7 +309,7 @@ index bc237ac45..fff12f8c3 100644 + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } - + @@ -2017,6 +2054,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) @@ -357,26 +355,13 @@ index e3618cfc1..db5808c58 100644 return 0; #else return (uint32_t)(READ_REG(WAKEUP->BLUE_SLEEP_REQUEST_MODE) & WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE); -diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_flash_ex.c b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_flash_ex.c -index fe66a0a89..6bded19a1 100644 ---- a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_flash_ex.c -+++ b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_flash_ex.c -@@ -109,7 +109,7 @@ static void FLASH_KeyWrite(void); - */ - HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) - { -- HAL_StatusTypeDef status; -+ HAL_StatusTypeDef status = HAL_ERROR; - uint32_t index; - - /* Check the parameters */ diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c index 70219dc39..db269d88e 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c +++ b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c @@ -1131,7 +1131,7 @@ static void _get_calibration_data(CalibrationDataTypeDef *calibrationData) int32_t a2; - + period = LL_RADIO_TIMER_GetLSIPeriod(RADIO_CTRL); - while (period != LL_RADIO_TIMER_GetLSIPeriod(RADIO_CTRL) || period == 0) + while (period != (int32_t)LL_RADIO_TIMER_GetLSIPeriod(RADIO_CTRL) || period == 0) @@ -386,25 +371,12 @@ index 70219dc39..db269d88e 100644 @@ -1145,7 +1145,7 @@ static void _get_calibration_data(CalibrationDataTypeDef *calibrationData) mult = 0x753 ; freq = LL_RADIO_TIMER_GetLSIFrequency(RADIO_CTRL); - + - while (freq != LL_RADIO_TIMER_GetLSIFrequency(RADIO_CTRL) || freq == 0) + while (freq != (int32_t)LL_RADIO_TIMER_GetLSIFrequency(RADIO_CTRL) || freq == 0) { freq = LL_RADIO_TIMER_GetLSIFrequency(RADIO_CTRL); } -diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_ll_adc.c b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_ll_adc.c -index 5308d2980..c071750ba 100644 ---- a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_ll_adc.c -+++ b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_ll_adc.c -@@ -24,7 +24,7 @@ - #ifdef USE_FULL_ASSERT - #include "stm32_assert.h" - #else --#define assert_param(expr) ((void)0UL) -+#define assert_param(expr) ((void)0U) - #endif /* USE_FULL_ASSERT */ - - /** @addtogroup STM32WB0x_LL_Driver --- +-- 2.34.1 From c1cbfd9e17e80f0199c002bcf4248443557c065b Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Jul 2026 10:16:42 +0200 Subject: [PATCH 2/4] system(wb0) update STM32WB0x HAL Drivers to v1.5.0 Included in STM32CubeWB0 FW v1.5.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 17 +- .../STM32WB0x_HAL_Driver/Inc/stm32wb0x_hal.h | 2 +- .../Inc/stm32wb0x_hal_uart.h | 2 +- .../Inc/stm32wb0x_ll_dma.h | 40 ----- .../Inc/stm32wb0x_ll_radio_timer.h | 3 - .../Drivers/STM32WB0x_HAL_Driver/LICENSE.md | 2 +- system/Drivers/STM32WB0x_HAL_Driver/README.md | 4 +- .../STM32WB0x_HAL_Driver/Release_Notes.html | 145 +++++++++++++----- .../STM32WB0x_HAL_Driver/SW_Security_Level.md | 47 ++++++ .../Src/stm32wb0x_hal_flash.c | 4 +- .../Src/stm32wb0x_hal_flash_ex.c | 10 +- .../Src/stm32wb0x_hal_gpio.c | 6 +- .../Src/stm32wb0x_hal_radio.c | 3 +- .../Src/stm32wb0x_hal_radio_timer.c | 9 +- .../Src/stm32wb0x_hal_smartcard.c | 16 +- .../Src/stm32wb0x_hal_uart.c | 8 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 17 files changed, 203 insertions(+), 117 deletions(-) create mode 100644 system/Drivers/STM32WB0x_HAL_Driver/SW_Security_Level.md diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32WB0x_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 836d610016..35650fcc17 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32WB0x_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -363,7 +363,6 @@ extern "C" { #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI #elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) #define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI -#define LL_DMAMUX_REQ_PSSI LL_DMAMUX_REQ_DCMI_PSSI #endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4 */ @@ -1918,7 +1917,11 @@ extern "C" { #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +#define PWR_PVM_USB PWR_PVM_ENABLE +#define PWR_FLAG_PVMOUSB PWR_FLAG_PVMOVDDIO2 +#define PWR_FLAG_PVMO_USB PWR_FLAG_PVMO_VDDIO2 +#endif /* STM32G0C1xx || STM32G0B1xx */ #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING @@ -2031,6 +2034,9 @@ extern "C" { #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK #endif +#if defined (STM32H7RS) +#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO PWR_SMPS_1V8_SUPPLIES_EXT_VDD_SUPPLIES_LDO +#endif /** * @} @@ -2159,6 +2165,13 @@ extern "C" { #define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig #endif /* STM32H7RS || STM32N6 */ +#if defined(STM32N6) +/* alias CMSIS */ +#define CSI_PCR_PWRDOWN_Pos CSI_PCR_NPWRDOWN_Pos +#define CSI_PCR_PWRDOWN_Msk CSI_PCR_NPWRDOWN_Msk +#define CSI_PCR_PWRDOWN CSI_PCR_NPWRDOWN +#endif /* STM32N6 */ + /** * @} */ diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_hal.h b/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_hal.h index cfa9ae8924..1404696dde 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_hal.h +++ b/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_hal.h @@ -48,7 +48,7 @@ extern "C" { * @brief HAL Driver version number */ #define __STM32WB0x_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WB0x_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32WB0x_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ #define __STM32WB0x_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WB0x_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WB0x_HAL_VERSION ((__STM32WB0x_HAL_VERSION_MAIN << 24U)\ diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_hal_uart.h b/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_hal_uart.h index 4370a23f67..8da27811fa 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_hal_uart.h +++ b/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_hal_uart.h @@ -1343,7 +1343,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) * divided by the smallest oversampling used on the USART (i.e. 8) * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 2000001U) +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 2000000U) /** @brief Check UART assertion time. * @param __TIME__ 5-bit value assertion time. diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_dma.h b/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_dma.h index fff12f8c30..bc237ac451 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_dma.h +++ b/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_dma.h @@ -430,7 +430,6 @@ typedef struct */ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } @@ -451,7 +450,6 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } @@ -472,7 +470,6 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); } @@ -509,7 +506,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, Configuration); @@ -537,7 +533,6 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); } @@ -563,7 +558,6 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM)); } @@ -590,7 +584,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint */ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC, Mode); } @@ -614,7 +607,6 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_ */ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC)); } @@ -639,7 +631,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC, PeriphOrM2MSrcIncMode); } @@ -663,7 +654,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC)); } @@ -688,7 +678,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC, MemoryOrM2MDstIncMode); } @@ -712,7 +701,6 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC)); } @@ -738,7 +726,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE, PeriphOrM2MSrcDataSize); } @@ -763,7 +750,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE)); } @@ -789,7 +775,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE, MemoryOrM2MDstDataSize); } @@ -814,7 +799,6 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE)); } @@ -841,7 +825,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL, Priority); } @@ -867,7 +850,6 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL)); } @@ -892,7 +874,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3 */ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR, DMA_CNDTR_NDT, NbData); } @@ -916,7 +897,6 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR, DMA_CNDTR_NDT)); } @@ -948,7 +928,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { - (void)DMAx; /* Direction Memory to Periph */ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) { @@ -983,7 +962,6 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } @@ -1007,7 +985,6 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { - (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress); } @@ -1029,7 +1006,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } @@ -1051,7 +1027,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } @@ -1075,7 +1050,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress); } @@ -1099,7 +1073,6 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } @@ -1121,7 +1094,6 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } @@ -1143,7 +1115,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } @@ -1166,7 +1137,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID, Request); } @@ -1188,7 +1158,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID)); } @@ -1928,7 +1897,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } @@ -1949,7 +1917,6 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } @@ -1970,7 +1937,6 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } @@ -1991,7 +1957,6 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } @@ -2012,7 +1977,6 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } @@ -2033,7 +1997,6 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } @@ -2054,7 +2017,6 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); } @@ -2076,7 +2038,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); } @@ -2098,7 +2059,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_radio_timer.h b/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_radio_timer.h index db5808c58d..e3618cfc1d 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_radio_timer.h +++ b/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_radio_timer.h @@ -445,8 +445,6 @@ __STATIC_INLINE uint32_t LL_RADIO_TIMER_IsEnabledCPUWakeupTimerForceSleeping(WAK __STATIC_INLINE void LL_RADIO_TIMER_SetSleepRequestMode(WAKEUP_TypeDef *WAKEUPx, uint8_t mode) { #if defined(STM32WB09) - (void)WAKEUPx; // No operation for STM32WB09 - (void)mode; // No operation for STM32WB09 return; #else MODIFY_REG_FIELD(WAKEUP->BLUE_SLEEP_REQUEST_MODE, WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE, (mode & 0x7)); @@ -462,7 +460,6 @@ __STATIC_INLINE void LL_RADIO_TIMER_SetSleepRequestMode(WAKEUP_TypeDef *WAKEUPx, __STATIC_INLINE uint32_t LL_RADIO_TIMER_GetSleepRequestMode(WAKEUP_TypeDef *WAKEUPx) { #if defined(STM32WB09) - (void)WAKEUPx; // No operation for STM32WB09 return 0; #else return (uint32_t)(READ_REG(WAKEUP->BLUE_SLEEP_REQUEST_MODE) & WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE); diff --git a/system/Drivers/STM32WB0x_HAL_Driver/LICENSE.md b/system/Drivers/STM32WB0x_HAL_Driver/LICENSE.md index eb0b33cda6..85878f41ac 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/LICENSE.md +++ b/system/Drivers/STM32WB0x_HAL_Driver/LICENSE.md @@ -24,4 +24,4 @@ ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/system/Drivers/STM32WB0x_HAL_Driver/README.md b/system/Drivers/STM32WB0x_HAL_Driver/README.md index e2ee754c4a..d27c87224c 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/README.md +++ b/system/Drivers/STM32WB0x_HAL_Driver/README.md @@ -1,6 +1,6 @@ # STM32CubeWB0 HAL Driver MCU Component -![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32wb0x_hal_driver.svg?color=brightgreen) +![tag](https://img.shields.io/badge/tag-v1.5.0-brightgreen.svg) ## Overview @@ -33,4 +33,4 @@ The full **STM32CubeWB0** MCU package is available [here](https://github.com/STM ## Troubleshooting -Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. \ No newline at end of file diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Release_Notes.html b/system/Drivers/STM32WB0x_HAL_Driver/Release_Notes.html index 51aa0a80bc..72a48870bb 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32WB0x_HAL_Driver/Release_Notes.html @@ -40,7 +40,7 @@

Purpose

Update History

- +

Main Changes

    @@ -49,6 +49,71 @@

    Main Changes

    Contents

    HAL Drivers updates

      +
    • HAL FLASH driver +
        +
      • Initialize the status variable to avoid the warning when -Wall is enabled
        • +
      • +
    • HAL GPIO driver +
        +
      • Change returned type value of GPIO_GET_INDEX macro to avoid MISRA-C warning
        • +
      • +
    • HAL RADIO Timer driver +
        +
      • Removed warning with -Wall option in STM32CubeIDE
        • +
      • +
    +

    LL Drivers updates

    +
      +
    • LL ADC driver +
        +
      • Adjust assert_param macro to use 0U instead of 0UL
        +
        • +
      • +
    +

    Supported Devices and boards

    +
      +
    • Devices : +
        +
      • STM32WB05
        • +
      • STM32WB06
        • +
      • STM32WB07
        • +
      • STM32WB09
        • +
      • +
    • Boards : +
        +
      • NUCLEO-WB09KE
        • +
      • NUCLEO-WB07CC
        • +
      • NUCLEO-WB05KZ
        • +
      • +
    +

    Backward compatibility

    +
      +
    • Not applicable
      • +
    +

    Known Limitations

    +
      +
    • None
      • +
    +

    Dependencies

    +
      +
    • None
      • +
    +

    Notes

    +
      +
    • None
      • +
    +
+
+
+ +
+

Main Changes

+
    +
  • Release of STM32CubeWB0 Firmware package supporting STM32WB0x devices
    • +
+

Contents

+

HAL Drivers updates

+
  • HAL Radio Timer driver
    • Optimizations of the HAL_RADIO_TIMER_SetRadioTimerValue function.
      • @@ -72,7 +137,7 @@

      HAL Drivers updates


    -

    Supported Devices and boards

    +

    Supported Devices and boards

    • Devices :
        @@ -88,19 +153,19 @@

        Supported Devices and boards

      • NUCLEO-WB05KZ
    -

    Backward compatibility

    +

    Backward compatibility

    • Not applicable
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Dependencies

    +

    Dependencies

    • None
    -

    Notes

    +

    Notes

    • None
    @@ -109,12 +174,12 @@

    Notes

    -

    Main Changes

    +

    Main Changes

    • Release of STM32CubeWB0 Firmware package supporting STM32WB0x devices
    -

    Contents

    -

    HAL Drivers updates

    +

    Contents

    +

    HAL Drivers updates

    • HAL RCC driver
        @@ -125,7 +190,7 @@

        HAL Drivers updates

      • Fix in HAL_RADIO_TIMER_SetRadioCloseTimeout() for an issue that may happen in case LSE has high jitter.
    -

    LL Drivers updates

    +

    LL Drivers updates

    • LL RTC driver
        @@ -134,7 +199,7 @@

        LL Drivers updates


      -

      Supported Devices and boards

      +

      Supported Devices and boards

      • Devices :
          @@ -150,19 +215,19 @@

          Supported Devices and boards

        • NUCLEO-WB05KZ
      -

      Backward compatibility

      +

      Backward compatibility

      • Not applicable
      -

      Known Limitations

      +

      Known Limitations

      • None
      -

      Dependencies

      +

      Dependencies

      • None
      -

      Notes

      +

      Notes

      • None
      @@ -171,12 +236,12 @@

      Notes

      -

      Main Changes

      +

      Main Changes

      • Release of STM32CubeWB0 Firmware package supporting STM32WB0x devices
      -

      Contents

      -

      HAL Drivers updates

      +

      Contents

      +

      HAL Drivers updates

      • HAL RADIO TIMER driver
          @@ -214,7 +279,7 @@

          HAL Drivers updates

        • Align prescaler value used by default in USART_GET_DIV_FACTOR macro with RM
      -

      LL Drivers updates

      +

      LL Drivers updates

      • LL LPUART driver
          @@ -227,7 +292,7 @@

          LL Drivers updates


        -

        Supported Devices and boards

        +

        Supported Devices and boards

        • Devices :
            @@ -243,19 +308,19 @@

            Supported Devices and boards

          • NUCLEO-WB05KZ
        -

        Backward compatibility

        +

        Backward compatibility

        • Not applicable
        -

        Known Limitations

        +

        Known Limitations

        • None
        -

        Dependencies

        +

        Dependencies

        • None
        -

        Notes

        +

        Notes

        • None
        @@ -264,12 +329,12 @@

        Notes

        -

        Main Changes

        +

        Main Changes

        • Release of STM32CubeWB0 Firmware package supporting STM32WB0x devices
        -

        Contents

        -

        HAL Drivers updates

        +

        Contents

        +

        HAL Drivers updates

        • HAL ADC driver
            @@ -282,7 +347,7 @@

            HAL Drivers updates


          -

          LL Drivers updates

          +

          LL Drivers updates

          • LL ADC driver
              @@ -306,7 +371,7 @@

              LL Drivers updates

            • Fix incorrect values returned by LL_UTILS_GetPackageType() function due to invalid mask.
          -

          Supported Devices and boards

          +

          Supported Devices and boards

          • Devices :
              @@ -322,19 +387,19 @@

              Supported Devices and boards

            • NUCLEO-WB05KZ
          -

          Backward compatibility

          +

          Backward compatibility

          • Not applicable
          -

          Known Limitations

          +

          Known Limitations

          • None
          -

          Dependencies

          +

          Dependencies

          • None
          -

          Notes

          +

          Notes

          • None
          @@ -343,11 +408,11 @@

          Notes

          -

          Main Changes

          +

          Main Changes

          • First release of STM32CubeWB0 Firmware package supporting STM32WB0x devices
          -

          Contents

          +

          Contents

          First Release of HAL/LL Drivers for STM32WB0x series

          • HAL/LL Drivers are available for all peripherals: @@ -356,7 +421,7 @@

            First Release of

            LL: ADC, CRC, DMA, GPIO, I2C, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS

        -

        Supported Devices and boards

        +

        Supported Devices and boards

        • Devices :
            @@ -372,19 +437,19 @@

            Supported Devices and boards

          • NUCLEO-WB05KZ
        -

        Backward compatibility

        +

        Backward compatibility

        • Not applicable
        -

        Known Limitations

        +

        Known Limitations

        • None
        -

        Dependencies

        +

        Dependencies

        • None
        -

        Notes

        +

        Notes

        • None
        diff --git a/system/Drivers/STM32WB0x_HAL_Driver/SW_Security_Level.md b/system/Drivers/STM32WB0x_HAL_Driver/SW_Security_Level.md new file mode 100644 index 0000000000..de8f4b0302 --- /dev/null +++ b/system/Drivers/STM32WB0x_HAL_Driver/SW_Security_Level.md @@ -0,0 +1,47 @@ + + +## Copyright (c) 2026 STMicroelectronics. +## All rights reserved +
        +
        + +## SW Security Classification + +[STM32Trust software security policies](https://wiki.st.com/stm32mcu/wiki/Security:STM32Trust_software_security_policies) define four levels of SW Security classification, each level defines a set of security policies for the applicable SW. + +| SW | SW Security Level +|:--------- |:-------| +| **STM32WB0x HAL Driver** | Medium| + + +
        + +## IMPORTANT SECURITY NOTICE + +The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that: + +- ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified. + +- Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product. + +- Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies. + +- While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application. + +- All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. + +AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise. + +
        + +## IMPORTANT NOTICE - READ CAREFULLY + +STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgment. + +Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers' products. +No license, express or implied, to any intellectual property right is granted by ST herein. +Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. +ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. +Information in this document supersedes and replaces information previously supplied in any prior versions of this document. + +Copyright (c) 2026 STMicroelectronics - All rights reserved \ No newline at end of file diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_flash.c b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_flash.c index c02ca3dccc..81d7124407 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_flash.c +++ b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_flash.c @@ -144,7 +144,7 @@ static void FLASH_Program_Burst(uint32_t Address, uint32_t DataAddress) */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); @@ -204,7 +204,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint */ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_flash_ex.c b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_flash_ex.c index 6bded19a19..5030a868bd 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_flash_ex.c +++ b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_flash_ex.c @@ -109,7 +109,7 @@ static void FLASH_KeyWrite(void); */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status = HAL_OK; uint32_t index; /* Check the parameters */ @@ -167,7 +167,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t */ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_FLASH_TYPE_ERASE(pEraseInit->TypeErase)); @@ -225,7 +225,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) */ HAL_StatusTypeDef HAL_FLASHEx_OTPWrite(uint32_t Address, uint32_t Data) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_ADDR_ALIGNED_32BITS(Address)); @@ -357,7 +357,7 @@ HAL_StatusTypeDef HAL_FLASHEx_PageProtection(FLASH_PageProtectionTypeDef *pagePr */ HAL_StatusTypeDef HAL_FLASHEx_Protection_Config(uint32_t ProtectionLevel) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_PROTECTION_LEVEL(ProtectionLevel)); @@ -464,7 +464,7 @@ HAL_StatusTypeDef HAL_FLASHEx_MassRead(uint32_t pattern) */ HAL_StatusTypeDef HAL_FLASHEx_LFSRSignature(uint32_t *LFSR_Result) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_gpio.c b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_gpio.c index 5a91ceae42..4aad7bbc34 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_gpio.c +++ b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_gpio.c @@ -223,7 +223,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; - temp &= ~(0xFu << ((position & 0x07u) * 4u)); + temp &= ~(0xFUL << ((position & 0x07u) * 4u)); temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); GPIOx->AFR[position >> 3u] = temp; } @@ -396,7 +396,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u)); /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ; + GPIOx->AFR[position >> 3u] &= ~(0xFUL << ((position & 0x07u) * 4u)) ; /* Deactivate the Pull-up and Pull-down resistor for the current IO */ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); @@ -487,7 +487,7 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin * @brief Set and clear several pins of a dedicated port in same cycle. * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify * accesses. - * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WLxx family + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WB0x family * @param PinReset specifies the port bits to be reset * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. * @param PinSet specifies the port bits to be set diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio.c b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio.c index c9ce7292d5..f0374b4d55 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio.c +++ b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio.c @@ -22,7 +22,6 @@ /** @addtogroup STM32WB0x_HAL_Driver * @{ */ -#ifdef HAL_RADIO_MODULE_ENABLED /** @addtogroup RADIO * @{ @@ -1803,7 +1802,7 @@ void HAL_RADIO_TXRX_SEQ_IRQHandler(void) /** * @} */ -#endif /* HAL_RADIO_MODULE_ENABLED */ + /** * @} */ diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c index 37e2f5a53d..a3352fe2c6 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c +++ b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c @@ -56,7 +56,7 @@ /** @addtogroup STM32WB0x_HAL_Driver * @{ */ -#ifdef HAL_RADIO_TIMER_MODULE_ENABLED + /** @addtogroup RADIO_TIMER * @brief HAL RADIO TIMER module driver * @{ @@ -1112,7 +1112,7 @@ static void _get_calibration_data(CalibrationDataTypeDef *calibrationData) int32_t a2; period = LL_RADIO_TIMER_GetLSIPeriod(RADIO_CTRL); - while (period != (int32_t)LL_RADIO_TIMER_GetLSIPeriod(RADIO_CTRL) || period == 0) + while (period != LL_RADIO_TIMER_GetLSIPeriod(RADIO_CTRL) || period == 0) { period = LL_RADIO_TIMER_GetLSIPeriod(RADIO_CTRL); } @@ -1126,7 +1126,7 @@ static void _get_calibration_data(CalibrationDataTypeDef *calibrationData) mult = 0x753 ; freq = LL_RADIO_TIMER_GetLSIFrequency(RADIO_CTRL); - while (freq != (int32_t)LL_RADIO_TIMER_GetLSIFrequency(RADIO_CTRL) || freq == 0) + while (freq != LL_RADIO_TIMER_GetLSIFrequency(RADIO_CTRL) || freq == 0) { freq = LL_RADIO_TIMER_GetLSIFrequency(RADIO_CTRL); } @@ -1267,6 +1267,7 @@ static VTIMER_HandleType *_update_user_timeout(VTIMER_HandleType *rootNode, uint #if defined (STM32WB06) || defined (STM32WB07) bool share = FALSE; uint8_t dummy = _check_radio_activity(FALSE); + UNUSED(dummy); #endif delay = curr->expiryTime - RADIO_TIMER_Context.last_system_time; if (delay > 0) @@ -1825,7 +1826,7 @@ void HAL_RADIO_TIMER_ERROR_IRQHandler(void) /** * @} */ -#endif /* HAL_RADIO_TIMER_MODULE_ENABLED */ + /** * @} */ diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_smartcard.c b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_smartcard.c index 60e664eb8e..e44fa295f4 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_smartcard.c +++ b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_smartcard.c @@ -2388,14 +2388,6 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard ((uint32_t)hsmartcard->Init.WordLength)); MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); - /*-------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = hsmartcard->Init.StopBits; - /* Synchronous mode is activated by default */ - tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; - tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; - tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; - MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); - /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure * - one-bit sampling method versus three samples' majority rule @@ -2417,6 +2409,14 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos)); MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg); + /*-------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = hsmartcard->Init.StopBits; + /* Synchronous mode is activated by default */ + tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; + tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; + tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); + /*-------------------------- USART RTOR Configuration ----------------------*/ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_uart.c b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_uart.c index 0b595ed766..636247c2e4 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_uart.c +++ b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_uart.c @@ -644,8 +644,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - __HAL_UART_DISABLE(huart); - huart->Instance->CR1 = 0x0U; huart->Instance->CR2 = 0x0U; huart->Instance->CR3 = 0x0U; @@ -3716,6 +3714,8 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { + huart->TxXferCount = 0U; + /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -3766,6 +3766,8 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { + huart->RxXferCount = 0U; + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -3792,6 +3794,8 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = 0; + /* Check current nb of data still to be received on DMA side. DMA Normal mode, remaining nb of data will be 0 DMA Circular mode, remaining nb of data is reset to RxXferSize */ diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 1a099a3214..f6062dd373 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -20,7 +20,7 @@ * STM32U3: 1.2.0 * STM32U5: 1.6.2 * STM32WB: 1.14.7 - * STM32WB0: 1.4.0 + * STM32WB0: 1.5.0 * STM32WBA: 1.9.0 * STM32WL: 1.4.0 * STM32WL3: 1.3.1 From 3465fc072743da24fb060243743d7715d5296fd9 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Sat, 14 Jun 2025 09:59:56 +0200 Subject: [PATCH 3/4] fix(wb0): HAL and LL warnings Signed-off-by: Frederic Pillon --- .../Inc/stm32wb0x_ll_dma.h | 40 +++++++++++++++++++ .../Inc/stm32wb0x_ll_radio_timer.h | 3 ++ .../Src/stm32wb0x_hal_radio_timer.c | 4 +- 3 files changed, 45 insertions(+), 2 deletions(-) diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_dma.h b/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_dma.h index bc237ac451..fff12f8c30 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_dma.h +++ b/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_dma.h @@ -430,6 +430,7 @@ typedef struct */ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } @@ -450,6 +451,7 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } @@ -470,6 +472,7 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); } @@ -506,6 +509,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, Configuration); @@ -533,6 +537,7 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); } @@ -558,6 +563,7 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM)); } @@ -584,6 +590,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint */ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC, Mode); } @@ -607,6 +614,7 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_ */ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC)); } @@ -631,6 +639,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC, PeriphOrM2MSrcIncMode); } @@ -654,6 +663,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC)); } @@ -678,6 +688,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC, MemoryOrM2MDstIncMode); } @@ -701,6 +712,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC)); } @@ -726,6 +738,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE, PeriphOrM2MSrcDataSize); } @@ -750,6 +763,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE)); } @@ -775,6 +789,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE, MemoryOrM2MDstDataSize); } @@ -799,6 +814,7 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE)); } @@ -825,6 +841,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL, Priority); } @@ -850,6 +867,7 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL)); } @@ -874,6 +892,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3 */ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR, DMA_CNDTR_NDT, NbData); } @@ -897,6 +916,7 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR, DMA_CNDTR_NDT)); } @@ -928,6 +948,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { + (void)DMAx; /* Direction Memory to Periph */ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) { @@ -962,6 +983,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } @@ -985,6 +1007,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress); } @@ -1006,6 +1029,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } @@ -1027,6 +1051,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } @@ -1050,6 +1075,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress); } @@ -1073,6 +1099,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } @@ -1094,6 +1121,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } @@ -1115,6 +1143,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } @@ -1137,6 +1166,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID, Request); } @@ -1158,6 +1188,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID)); } @@ -1897,6 +1928,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } @@ -1917,6 +1949,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } @@ -1937,6 +1970,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } @@ -1957,6 +1991,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } @@ -1977,6 +2012,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } @@ -1997,6 +2033,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } @@ -2017,6 +2054,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); } @@ -2038,6 +2076,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); } @@ -2059,6 +2098,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_radio_timer.h b/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_radio_timer.h index e3618cfc1d..db5808c58d 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_radio_timer.h +++ b/system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_radio_timer.h @@ -445,6 +445,8 @@ __STATIC_INLINE uint32_t LL_RADIO_TIMER_IsEnabledCPUWakeupTimerForceSleeping(WAK __STATIC_INLINE void LL_RADIO_TIMER_SetSleepRequestMode(WAKEUP_TypeDef *WAKEUPx, uint8_t mode) { #if defined(STM32WB09) + (void)WAKEUPx; // No operation for STM32WB09 + (void)mode; // No operation for STM32WB09 return; #else MODIFY_REG_FIELD(WAKEUP->BLUE_SLEEP_REQUEST_MODE, WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE, (mode & 0x7)); @@ -460,6 +462,7 @@ __STATIC_INLINE void LL_RADIO_TIMER_SetSleepRequestMode(WAKEUP_TypeDef *WAKEUPx, __STATIC_INLINE uint32_t LL_RADIO_TIMER_GetSleepRequestMode(WAKEUP_TypeDef *WAKEUPx) { #if defined(STM32WB09) + (void)WAKEUPx; // No operation for STM32WB09 return 0; #else return (uint32_t)(READ_REG(WAKEUP->BLUE_SLEEP_REQUEST_MODE) & WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE); diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c index a3352fe2c6..07b83f4687 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c +++ b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c @@ -1112,7 +1112,7 @@ static void _get_calibration_data(CalibrationDataTypeDef *calibrationData) int32_t a2; period = LL_RADIO_TIMER_GetLSIPeriod(RADIO_CTRL); - while (period != LL_RADIO_TIMER_GetLSIPeriod(RADIO_CTRL) || period == 0) + while (period != (int32_t)LL_RADIO_TIMER_GetLSIPeriod(RADIO_CTRL) || period == 0) { period = LL_RADIO_TIMER_GetLSIPeriod(RADIO_CTRL); } @@ -1126,7 +1126,7 @@ static void _get_calibration_data(CalibrationDataTypeDef *calibrationData) mult = 0x753 ; freq = LL_RADIO_TIMER_GetLSIFrequency(RADIO_CTRL); - while (freq != LL_RADIO_TIMER_GetLSIFrequency(RADIO_CTRL) || freq == 0) + while (freq != (int32_t)LL_RADIO_TIMER_GetLSIFrequency(RADIO_CTRL) || freq == 0) { freq = LL_RADIO_TIMER_GetLSIFrequency(RADIO_CTRL); } From a2b8a68642ab00c00bea80dbbf9d6155b726fdbc Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Sat, 14 Jun 2025 14:46:20 +0200 Subject: [PATCH 4/4] fix(wb0): HAL radio module guards Signed-off-by: Frederic Pillon --- system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio.c | 3 ++- .../STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio.c b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio.c index f0374b4d55..c9ce7292d5 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio.c +++ b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio.c @@ -22,6 +22,7 @@ /** @addtogroup STM32WB0x_HAL_Driver * @{ */ +#ifdef HAL_RADIO_MODULE_ENABLED /** @addtogroup RADIO * @{ @@ -1802,7 +1803,7 @@ void HAL_RADIO_TXRX_SEQ_IRQHandler(void) /** * @} */ - +#endif /* HAL_RADIO_MODULE_ENABLED */ /** * @} */ diff --git a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c index 07b83f4687..1187685bb2 100644 --- a/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c +++ b/system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c @@ -56,7 +56,7 @@ /** @addtogroup STM32WB0x_HAL_Driver * @{ */ - +#ifdef HAL_RADIO_TIMER_MODULE_ENABLED /** @addtogroup RADIO_TIMER * @brief HAL RADIO TIMER module driver * @{ @@ -1826,7 +1826,7 @@ void HAL_RADIO_TIMER_ERROR_IRQHandler(void) /** * @} */ - +#endif /* HAL_RADIO_TIMER_MODULE_ENABLED */ /** * @} */