diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba20xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba20xx.h index 159e62e224..20871711e4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba20xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba20xx.h @@ -607,7 +607,10 @@ typedef struct __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ - __IO uint32_t HTCR[4]; /*!< RNG health test control register, Address offset: 0x10 - 0x1F */ + __IO uint32_t HTCR[4]; /*!< RNG health test control register, Address offset: 0x10 - 0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG noise source mask register, Address offset: 0x30 */ } RNG_TypeDef; /* @@ -6280,41 +6283,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -6351,7 +6354,6 @@ typedef struct #define RNG_NSCR_EN_OSC3_Pos (6UL) #define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< EN_OSC3[2:0] bits (Each bit drives one oscillator enable signal input of instance number 3, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */ - /****************** Bit definition for RNG_HTCR0 register *******************/ #define RNG_HTCR0_HTCFG_Pos (0UL) #define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFU << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ @@ -6372,10 +6374,114 @@ typedef struct #define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFU << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk /*!< health test configuration */ +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + /******************** RNG Nist Compliance Values *******************/ +#define RNG_HTCRx_VALUE (0x0003FFFF) #define RNG_CR_NIST_VALUE (0x00200F00U) #define RNG_NSCR_NIST_VALUE (0x000001FFU) #define RNG_HTCR_NIST_VALUE (0xA2B0U) +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE (0x08451F00) +#define RNG_CAND_NIST_NSCR_VALUE (0x000001FF) +#define RNG_CAND_NIST_HTCR_VALUE (0x0000AAC7) + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE (0x08301F00) +#define RNG_CAND_GermanBSI_NSCR_VALUE (0x000001FF) +#define RNG_CAND_GermanBSI_HTCR_VALUE (0x0000AAC7) /******************************************************************************/ /* */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba23xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba23xx.h index 0dc8144364..193526411f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba23xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba23xx.h @@ -696,7 +696,10 @@ typedef struct __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ - __IO uint32_t HTCR[4]; /*!< RNG health test control register, Address offset: 0x10 - 0x1F */ + __IO uint32_t HTCR[4]; /*!< RNG health test control register, Address offset: 0x10 - 0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG noise source mask register, Address offset: 0x30 */ } RNG_TypeDef; /* @@ -9312,41 +9315,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -9383,7 +9386,6 @@ typedef struct #define RNG_NSCR_EN_OSC3_Pos (6UL) #define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< EN_OSC3[2:0] bits (Each bit drives one oscillator enable signal input of instance number 3, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */ - /****************** Bit definition for RNG_HTCR0 register *******************/ #define RNG_HTCR0_HTCFG_Pos (0UL) #define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFU << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ @@ -9404,10 +9406,114 @@ typedef struct #define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFU << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk /*!< health test configuration */ +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + /******************** RNG Nist Compliance Values *******************/ +#define RNG_HTCRx_VALUE (0x0003FFFF) #define RNG_CR_NIST_VALUE (0x00200F00U) #define RNG_NSCR_NIST_VALUE (0x000001FFU) #define RNG_HTCR_NIST_VALUE (0xA2B0U) +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE (0x08451F00) +#define RNG_CAND_NIST_NSCR_VALUE (0x000001FF) +#define RNG_CAND_NIST_HTCR_VALUE (0x0000AAC7) + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE (0x08301F00) +#define RNG_CAND_GermanBSI_NSCR_VALUE (0x000001FF) +#define RNG_CAND_GermanBSI_HTCR_VALUE (0x0000AAC7) /******************************************************************************/ /* */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba25xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba25xx.h index 21659978d6..5bab770690 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba25xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba25xx.h @@ -739,7 +739,10 @@ typedef struct __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ - __IO uint32_t HTCR[4]; /*!< RNG health test control register, Address offset: 0x10 - 0x1F */ + __IO uint32_t HTCR[4]; /*!< RNG health test control register, Address offset: 0x10 - 0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG noise source mask register, Address offset: 0x30 */ } RNG_TypeDef; /* @@ -9748,41 +9751,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -9819,7 +9822,6 @@ typedef struct #define RNG_NSCR_EN_OSC3_Pos (6UL) #define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< EN_OSC3[2:0] bits (Each bit drives one oscillator enable signal input of instance number 3, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */ - /****************** Bit definition for RNG_HTCR0 register *******************/ #define RNG_HTCR0_HTCFG_Pos (0UL) #define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFU << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ @@ -9840,10 +9842,114 @@ typedef struct #define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFU << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk /*!< health test configuration */ +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + /******************** RNG Nist Compliance Values *******************/ +#define RNG_HTCRx_VALUE (0x0003FFFF) #define RNG_CR_NIST_VALUE (0x00200F00U) #define RNG_NSCR_NIST_VALUE (0x000001FFU) #define RNG_HTCR_NIST_VALUE (0xA2B0U) +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE (0x08451F00) +#define RNG_CAND_NIST_NSCR_VALUE (0x000001FF) +#define RNG_CAND_NIST_HTCR_VALUE (0x0000AAC7) + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE (0x08301F00) +#define RNG_CAND_GermanBSI_NSCR_VALUE (0x000001FF) +#define RNG_CAND_GermanBSI_HTCR_VALUE (0x0000AAC7) /******************************************************************************/ /* */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h index 5a0759e1dd..2bbc399b0d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h @@ -6637,41 +6637,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -6720,11 +6720,12 @@ typedef struct #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + /******************** RNG Nist Compliance Values *******************/ #define RNG_CR_NIST_VALUE (0x00F02D00U) #define RNG_NSCR_NIST_VALUE (0x0003FFFFU) #define RNG_HTCR_NIST_VALUE (0xAAC7U) - /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h index dc11bd09e0..88f8bf976f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h @@ -10539,41 +10539,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -10622,11 +10622,12 @@ typedef struct #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + /******************** RNG Nist Compliance Values *******************/ #define RNG_CR_NIST_VALUE (0x00F02D00U) #define RNG_NSCR_NIST_VALUE (0x0003FFFFU) #define RNG_HTCR_NIST_VALUE (0xAAC7U) - /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h index 79c7445edb..09db128ddb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h @@ -10902,41 +10902,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -10985,11 +10985,12 @@ typedef struct #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + /******************** RNG Nist Compliance Values *******************/ #define RNG_CR_NIST_VALUE (0x00F02D00U) #define RNG_NSCR_NIST_VALUE (0x0003FFFFU) #define RNG_HTCR_NIST_VALUE (0xAAC7U) - /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h index 8e365c2288..4a311df1b4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h @@ -10920,41 +10920,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -11003,11 +11003,12 @@ typedef struct #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + /******************** RNG Nist Compliance Values *******************/ #define RNG_CR_NIST_VALUE (0x00F02D00U) #define RNG_NSCR_NIST_VALUE (0x0003FFFFU) #define RNG_HTCR_NIST_VALUE (0xAAC7U) - /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba5mxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba5mxx.h index f1d80b66df..4e6fd69a74 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba5mxx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba5mxx.h @@ -10920,41 +10920,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -11003,11 +11003,12 @@ typedef struct #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + /******************** RNG Nist Compliance Values *******************/ #define RNG_CR_NIST_VALUE (0x00F02D00U) #define RNG_NSCR_NIST_VALUE (0x0003FFFFU) #define RNG_HTCR_NIST_VALUE (0xAAC7U) - /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba62xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba62xx.h index 72e0b5d19e..3318ed0a22 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba62xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba62xx.h @@ -779,7 +779,10 @@ typedef struct __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ - __IO uint32_t HTCR[4]; /*!< RNG health test control register, Address offset: 0x10 - 0x1F */ + __IO uint32_t HTCR[4]; /*!< RNG health test control register, Address offset: 0x10 - 0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG noise source mask register, Address offset: 0x30 */ } RNG_TypeDef; /* @@ -12715,41 +12718,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -12786,7 +12789,6 @@ typedef struct #define RNG_NSCR_EN_OSC3_Pos (6UL) #define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< EN_OSC3[2:0] bits (Each bit drives one oscillator enable signal input of instance number 3, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */ - /****************** Bit definition for RNG_HTCR0 register *******************/ #define RNG_HTCR0_HTCFG_Pos (0UL) #define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFU << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ @@ -12807,10 +12809,114 @@ typedef struct #define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFU << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk /*!< health test configuration */ +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + /******************** RNG Nist Compliance Values *******************/ +#define RNG_HTCRx_VALUE (0x0003FFFF) #define RNG_CR_NIST_VALUE (0x00200F00U) #define RNG_NSCR_NIST_VALUE (0x000001FFU) #define RNG_HTCR_NIST_VALUE (0xA2B0U) +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE (0x08451F00) +#define RNG_CAND_NIST_NSCR_VALUE (0x000001FF) +#define RNG_CAND_NIST_HTCR_VALUE (0x0000AAC7) + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE (0x08301F00) +#define RNG_CAND_GermanBSI_NSCR_VALUE (0x000001FF) +#define RNG_CAND_GermanBSI_HTCR_VALUE (0x0000AAC7) /******************************************************************************/ /* */ @@ -17697,8 +17803,8 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2UL) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ -#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3UL) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ #define USB_OTG_GCCFG_SESSVLD USB_OTG_GCCFG_SESSVLD_Msk /*!< VBUS session valid indicator Vbus voltage level */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba63xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba63xx.h index 969d9feca4..46fb12a902 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba63xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba63xx.h @@ -765,7 +765,10 @@ typedef struct __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ - __IO uint32_t HTCR[4]; /*!< RNG health test control register, Address offset: 0x10 - 0x1F */ + __IO uint32_t HTCR[4]; /*!< RNG health test control register, Address offset: 0x10 - 0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG noise source mask register, Address offset: 0x30 */ } RNG_TypeDef; /* @@ -11905,41 +11908,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -11976,7 +11979,6 @@ typedef struct #define RNG_NSCR_EN_OSC3_Pos (6UL) #define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< EN_OSC3[2:0] bits (Each bit drives one oscillator enable signal input of instance number 3, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */ - /****************** Bit definition for RNG_HTCR0 register *******************/ #define RNG_HTCR0_HTCFG_Pos (0UL) #define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFU << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ @@ -11997,10 +11999,114 @@ typedef struct #define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFU << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk /*!< health test configuration */ +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + /******************** RNG Nist Compliance Values *******************/ +#define RNG_HTCRx_VALUE (0x0003FFFF) #define RNG_CR_NIST_VALUE (0x00200F00U) #define RNG_NSCR_NIST_VALUE (0x000001FFU) #define RNG_HTCR_NIST_VALUE (0xA2B0U) +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE (0x08451F00) +#define RNG_CAND_NIST_NSCR_VALUE (0x000001FF) +#define RNG_CAND_NIST_HTCR_VALUE (0x0000AAC7) + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE (0x08301F00) +#define RNG_CAND_GermanBSI_NSCR_VALUE (0x000001FF) +#define RNG_CAND_GermanBSI_HTCR_VALUE (0x0000AAC7) /******************************************************************************/ /* */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba64xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba64xx.h index e1930ba527..b7fe9b9b41 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba64xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba64xx.h @@ -775,7 +775,10 @@ typedef struct __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ - __IO uint32_t HTCR[4]; /*!< RNG health test control register, Address offset: 0x10 - 0x1F */ + __IO uint32_t HTCR[4]; /*!< RNG health test control register, Address offset: 0x10 - 0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG noise source mask register, Address offset: 0x30 */ } RNG_TypeDef; /* @@ -12331,41 +12334,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -12402,7 +12405,6 @@ typedef struct #define RNG_NSCR_EN_OSC3_Pos (6UL) #define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< EN_OSC3[2:0] bits (Each bit drives one oscillator enable signal input of instance number 3, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */ - /****************** Bit definition for RNG_HTCR0 register *******************/ #define RNG_HTCR0_HTCFG_Pos (0UL) #define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFU << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ @@ -12423,10 +12425,114 @@ typedef struct #define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFU << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk /*!< health test configuration */ +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + /******************** RNG Nist Compliance Values *******************/ +#define RNG_HTCRx_VALUE (0x0003FFFF) #define RNG_CR_NIST_VALUE (0x00200F00U) #define RNG_NSCR_NIST_VALUE (0x000001FFU) #define RNG_HTCR_NIST_VALUE (0xA2B0U) +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE (0x08451F00) +#define RNG_CAND_NIST_NSCR_VALUE (0x000001FF) +#define RNG_CAND_NIST_HTCR_VALUE (0x0000AAC7) + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE (0x08301F00) +#define RNG_CAND_GermanBSI_NSCR_VALUE (0x000001FF) +#define RNG_CAND_GermanBSI_HTCR_VALUE (0x0000AAC7) /******************************************************************************/ /* */ @@ -17313,8 +17419,8 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2UL) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ -#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3UL) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ #define USB_OTG_GCCFG_SESSVLD USB_OTG_GCCFG_SESSVLD_Msk /*!< VBUS session valid indicator Vbus voltage level */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba65xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba65xx.h index 88a82b3842..2e207b5540 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba65xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba65xx.h @@ -779,7 +779,10 @@ typedef struct __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ - __IO uint32_t HTCR[4]; /*!< RNG health test control register, Address offset: 0x10 - 0x1F */ + __IO uint32_t HTCR[4]; /*!< RNG health test control register, Address offset: 0x10 - 0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG noise source mask register, Address offset: 0x30 */ } RNG_TypeDef; /* @@ -12733,41 +12736,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -12804,7 +12807,6 @@ typedef struct #define RNG_NSCR_EN_OSC3_Pos (6UL) #define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< EN_OSC3[2:0] bits (Each bit drives one oscillator enable signal input of instance number 3, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */ - /****************** Bit definition for RNG_HTCR0 register *******************/ #define RNG_HTCR0_HTCFG_Pos (0UL) #define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFU << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ @@ -12825,10 +12827,114 @@ typedef struct #define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFU << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk /*!< health test configuration */ +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + /******************** RNG Nist Compliance Values *******************/ +#define RNG_HTCRx_VALUE (0x0003FFFF) #define RNG_CR_NIST_VALUE (0x00200F00U) #define RNG_NSCR_NIST_VALUE (0x000001FFU) #define RNG_HTCR_NIST_VALUE (0xA2B0U) +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE (0x08451F00) +#define RNG_CAND_NIST_NSCR_VALUE (0x000001FF) +#define RNG_CAND_NIST_HTCR_VALUE (0x0000AAC7) + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE (0x08301F00) +#define RNG_CAND_GermanBSI_NSCR_VALUE (0x000001FF) +#define RNG_CAND_GermanBSI_HTCR_VALUE (0x0000AAC7) /******************************************************************************/ /* */ @@ -17715,8 +17821,8 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2UL) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ -#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3UL) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ #define USB_OTG_GCCFG_SESSVLD USB_OTG_GCCFG_SESSVLD_Msk /*!< VBUS session valid indicator Vbus voltage level */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba6mxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba6mxx.h index 0ad0c25658..a251fce4c7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba6mxx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba6mxx.h @@ -779,7 +779,10 @@ typedef struct __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ - __IO uint32_t HTCR[4]; /*!< RNG health test control register, Address offset: 0x10 - 0x1F */ + __IO uint32_t HTCR[4]; /*!< RNG health test control register, Address offset: 0x10 - 0x1C */ + __IO uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t NSMR; /*!< RNG noise source mask register, Address offset: 0x30 */ } RNG_TypeDef; /* @@ -12733,41 +12736,41 @@ typedef struct /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ #define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ #define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ #define RNG_CR_ARDIS_Pos (7UL) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ #define RNG_CR_RNG_CONFIG3_Pos (8UL) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ #define RNG_CR_NISTC_Pos (12UL) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ #define RNG_CR_RNG_CONFIG2_Pos (13UL) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ #define RNG_CR_CLKDIV_Pos (16UL) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20UL) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ #define RNG_CR_CONDRST_Pos (30UL) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ #define RNG_CR_CONFIGLOCK_Pos (31UL) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0UL) @@ -12804,7 +12807,6 @@ typedef struct #define RNG_NSCR_EN_OSC3_Pos (6UL) #define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< EN_OSC3[2:0] bits (Each bit drives one oscillator enable signal input of instance number 3, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */ - /****************** Bit definition for RNG_HTCR0 register *******************/ #define RNG_HTCR0_HTCFG_Pos (0UL) #define RNG_HTCR0_HTCFG_Msk (0xFFFFFFFFU << RNG_HTCR0_HTCFG_Pos) /*!< 0xFFFFFFFF */ @@ -12825,10 +12827,114 @@ typedef struct #define RNG_HTCR3_HTCFG_Msk (0xFFFFFFFFU << RNG_HTCR3_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR3_HTCFG RNG_HTCR3_HTCFG_Msk /*!< health test configuration */ +/************************************* Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/************************************* Bit definition for RNG_HTSR1 register **************************************/ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/************************************** Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + /******************** RNG Nist Compliance Values *******************/ +#define RNG_HTCRx_VALUE (0x0003FFFF) #define RNG_CR_NIST_VALUE (0x00200F00U) #define RNG_NSCR_NIST_VALUE (0x000001FFU) #define RNG_HTCR_NIST_VALUE (0xA2B0U) +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE (0x08451F00) +#define RNG_CAND_NIST_NSCR_VALUE (0x000001FF) +#define RNG_CAND_NIST_HTCR_VALUE (0x0000AAC7) + +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE (0x08301F00) +#define RNG_CAND_GermanBSI_NSCR_VALUE (0x000001FF) +#define RNG_CAND_GermanBSI_HTCR_VALUE (0x0000AAC7) /******************************************************************************/ /* */ @@ -17715,8 +17821,8 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2UL) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ -#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3UL) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ #define USB_OTG_GCCFG_SESSVLD USB_OTG_GCCFG_SESSVLD_Msk /*!< VBUS session valid indicator Vbus voltage level */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h index e0195b1dad..c3ac497b11 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h @@ -91,7 +91,7 @@ * @brief CMSIS Device version number */ #define __STM32WBA_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBA_CMSIS_VERSION_SUB1 (0x09U) /*!< [23:16] sub1 version */ +#define __STM32WBA_CMSIS_VERSION_SUB1 (0x0AU) /*!< [23:16] sub1 version */ #define __STM32WBA_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBA_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBA_CMSIS_VERSION ((__STM32WBA_CMSIS_VERSION_MAIN << 24U)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/LICENSE.md b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/LICENSE.md index 261eeb9e9f..f49a4e16e6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/LICENSE.md +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/LICENSE.md @@ -198,4 +198,4 @@ distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and - limitations under the License. + limitations under the License. \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/README.md b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/README.md index 9bc34430cf..2771a5bdbb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/README.md +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/README.md @@ -1,6 +1,6 @@ # STM32CubeWBA CMSIS Device MCU Component -![tag](https://img.shields.io/badge/tag-v1.9.0-brightgreen.svg) +![tag](https://img.shields.io/badge/tag-v1.10.0-brightgreen.svg) ## Overview @@ -33,4 +33,4 @@ The full **STM32CubeWBA** MCU package is available [here](https://github.com/STM ## Troubleshooting -Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html index 5adac8539a..779981ca35 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html @@ -5,24 +5,16 @@ Release Notes for STM32WBAxx CMSIS - + @@ -33,12 +25,10 @@

Release Notes for

STM32WBAxx CMSIS

Copyright © 2022-2025 STMicroelectronics

- +

Purpose

-

This driver provides the CMSIS device for the STM32WBAxx products. -This covers

+

This driver provides the CMSIS device for the STM32WBAxx products. This covers

-

This driver is composed of the description of the registers under -“Include” directory.

-

Various template file are provided to easily build an application. -They can be adapted to fit applications requirements.

+

This driver is composed of the description of the registers under “Include” directory.

+

Various template file are provided to easily build an application. They can be adapted to fit applications requirements.

-
-

Update History

+
+

Update History

- - +

Main Changes

-

Official -Release of STM32CubeWBA Firmware package supporting -STM32WBA2x, STM32WBA5x and -STM32WBA6x devices

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA2x, STM32WBA5x and STM32WBA6x devices

Contents

-

Official -Release of CMSIS devices drivers supporting -STM32WBA2x, STM32WBA5x and -STM32WBA6x devices

+

Official Release of CMSIS devices drivers supporting STM32WBA2x, STM32WBA5x and STM32WBA6x devices

    -
  • Add support of STM32WBA2xx devices
    • -
  • Update CMSIS devices drivers to include latest corrections -
      -
    • Set stack limit (MSPLIM) in CMSIS Device templates
      • -
    • Add missing NSCR feature
      • -
    • Update IS_USART__INSTANCE() macros with USART3 if -available
      • -
    • +
  • Fixed Error in USB_OTG_GCCFG_FSVMINUS_Msk definition
    • +
  • Updated registers and bit definition after update to RNG4.4


@@ -113,26 +82,19 @@

Notes

- - +

Main Changes

-

Official -Release of STM32CubeWBA Firmware package supporting -STM32WBA5x and STM32WBA6x devices

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA2x, STM32WBA5x and STM32WBA6x devices

Contents

-

Official -Release of CMSIS devices drivers supporting -STM32WBA5x and STM32WBA6x devices

+

Official Release of CMSIS devices drivers supporting STM32WBA2x, STM32WBA5x and STM32WBA6x devices

    +
  • Add support of STM32WBA2xx devices
  • Update CMSIS devices drivers to include latest corrections
      -
    • Update DMA request field to cover all possible requests
      • -
    • For WBA50, map only heap and stack in SRAM1, remaining data in -SRAM2
      • +
    • Set stack limit (MSPLIM) in CMSIS Device templates
      • +
    • Add missing NSCR feature
      • +
    • Update IS_USART__INSTANCE() macros with USART3 if available


@@ -152,30 +114,17 @@

Notes

- - +

Main Changes

-

Official -Release of STM32CubeWBA Firmware package supporting -STM32WBA5x and STM32WBA6x devices

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA5x and STM32WBA6x devices

Contents

-

Official -Release of CMSIS devices drivers supporting -STM32WBA5x and STM32WBA6x devices

+

Official Release of CMSIS devices drivers supporting STM32WBA5x and STM32WBA6x devices

    -
  • Update CMSIS devices drivers to add STM32WBA6M
  • Update CMSIS devices drivers to include latest corrections
      -
    • New VTOR management based on information from the linker files
      • -
    • MISRA-C 2012 warnings correction due to IAR version change
      • -
    • Activate LSI2 feature on WBA50/52
      • -
    • Add missing RNG busy bit define for WBA6 devices
      • -
    • Update linker files to split RAM area between SRAM1 and SRAM2
      • -
    • Add missing SPI2 in macro SPI for WBA6 devices
      • +
    • Update DMA request field to cover all possible requests
      • +
    • For WBA50, map only heap and stack in SRAM1, remaining data in SRAM2


@@ -195,26 +144,22 @@

Notes

- - +

Main Changes

-

Official -Release of STM32CubeWBA Firmware package supporting -STM32WBA5x and STM32WBA6x devices

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA5x and STM32WBA6x devices

Contents

-

Official -Release of CMSIS devices drivers supporting -STM32WBA5x and STM32WBA6x devices

+

Official Release of CMSIS devices drivers supporting STM32WBA5x and STM32WBA6x devices

    -
  • Update CMSIS devices drivers to add STM32WBA6x
    • +
  • Update CMSIS devices drivers to add STM32WBA6M
  • Update CMSIS devices drivers to include latest corrections
      -
    • Workaround for VREF_BUF issue : VREF_BUFF cannot be trimmed by -EngiBit (refer to Errata Sheet)
      • +
    • New VTOR management based on information from the linker files
      • +
    • MISRA-C 2012 warnings correction due to IAR version change
      • +
    • Activate LSI2 feature on WBA50/52
      • +
    • Add missing RNG busy bit define for WBA6 devices
      • +
    • Update linker files to split RAM area between SRAM1 and SRAM2
      • +
    • Add missing SPI2 in macro SPI for WBA6 devices


@@ -234,33 +179,17 @@

Notes

- - +

Main Changes

-

Official -Release of STM32CubeWBA Firmware package supporting -STM32WBA50xx, STM32WBA52xx, -STM32WBA54xx, STM32WBA55xx and -STM32WBA5Mxx devices

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA5x and STM32WBA6x devices

Contents

-

Official -Release of CMSIS devices drivers supporting -STM32WBA50xx, STM32WBA52xx, -STM32WBA54xx, STM32WBA55xx and -STM32WBA5Mxx devices

+

Official Release of CMSIS devices drivers supporting STM32WBA5x and STM32WBA6x devices

    -
  • Update CMSIS device to add STM32WBA5Mxx devices
    • -
  • Update CMSIS device to include latest corrections +
  • Update CMSIS devices drivers to add STM32WBA6x
    • +
  • Update CMSIS devices drivers to include latest corrections
      -
    • Additional TAMP register bit ATCKSEL[3] inside TAMP_ATCR1
      • -
    • Update to use #include "core_cm33.h" instead of #include -<core_cm33.h> to force the first searches for the core_cm33.h file -in the same directory as the file that contains the #include directive -(Drivers\CMSIS\Core\Include)
      • +
    • Workaround for VREF_BUF issue : VREF_BUFF cannot be trimmed by EngiBit (refer to Errata Sheet)


@@ -280,31 +209,18 @@

Notes

- - +

Main Changes

-

Official -Release of STM32CubeWBA Firmware package supporting -STM32WBA50xx, STM32WBA52xx, -STM32WBA54xx and STM32WBA55xx -devices

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and STM32WBA5Mxx devices

Contents

-

Official -Release of CMSIS devices drivers supporting -STM32WBA50xx, STM32WBA52xx, -STM32WBA54xx and STM32WBA55xx -devices

+

Official Release of CMSIS devices drivers supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and STM32WBA5Mxx devices

    -
  • Update CMSIS devices to include latest corrections +
  • Update CMSIS device to add STM32WBA5Mxx devices
    • +
  • Update CMSIS device to include latest corrections
      -
    • Properly mark sections readonly for GCC
      • -
    • Add RNG (CR, HTCR) Nist Compliance Values
      • -
    • Update IS_TIM_OCXREF_CLEAR_INSTANCE macro to support of -TIM16/TIM17
      • +
    • Additional TAMP register bit ATCKSEL[3] inside TAMP_ATCR1
      • +
    • Update to use #include "core_cm33.h" instead of #include <core_cm33.h> to force the first searches for the core_cm33.h file in the same directory as the file that contains the #include directive (Drivers\CMSIS\Core\Include)


@@ -324,30 +240,18 @@

Notes

- - +

Main Changes

-

Official -Release of STM32CubeWBA Firmware package supporting -STM32WBA52xx and STM32WBA55xx -devices

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices

Contents

-

Official -Release of CMSIS devices drivers supporting -STM32WBA52xx and STM32WBA55xx -devices

+

Official Release of CMSIS devices drivers supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices

  • Update CMSIS devices to include latest corrections
      -
    • Update IS_TIM_32B_COUNTER_INSTANCE macro to remove 16-bit counter -TIM3
      • -
    • Update IS_TIM_OCXREF_CLEAR_INSTANCE macro as feature is supported by -TIM16 and TIM17
      • -
    • Add IS_TIM_OCCS_INSTANCE macro for Secure context
      • +
    • Properly mark sections readonly for GCC
      • +
    • Add RNG (CR, HTCR) Nist Compliance Values
      • +
    • Update IS_TIM_OCXREF_CLEAR_INSTANCE macro to support of TIM16/TIM17


@@ -367,32 +271,18 @@

Notes

- - +

Main Changes

-

Official -Release of STM32CubeWBA Firmware package supporting -STM32WBA52xx and STM32WBA55xx -devices

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

Contents

-

Official -Release of CMSIS devices drivers supporting -STM32WBA52xx and STM32WBA55xx -devices

+

Official Release of CMSIS devices drivers supporting STM32WBA52xx and STM32WBA55xx devices

  • Update CMSIS devices to include latest corrections
      -
    • Add support of WKUP_S_IRQn and RCC_AUDIOSYNC_IRQn interrupts in -CMSIS devices, startup_stm32wba5xxx.s and partition_stmwba5xxx.h -files
      • -
    • Update Licensing header in partition_stm325xxx.h files based on -partition_ARMCM33.h
      • -
    • Update declaration of g_pfnVectors size in -gcc/startup_stm32wba5xxx.s files
      • +
    • Update IS_TIM_32B_COUNTER_INSTANCE macro to remove 16-bit counter TIM3
      • +
    • Update IS_TIM_OCXREF_CLEAR_INSTANCE macro as feature is supported by TIM16 and TIM17
      • +
    • Add IS_TIM_OCCS_INSTANCE macro for Secure context


@@ -412,24 +302,18 @@

Notes

- - +

Main Changes

-

Official -Release of STM32CubeWBA Firmware package supporting -STM32WBA52xx devices

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

Contents

-

Official -Release of CMSIS devices drivers supporting -STM32WBA52xx devices

+

Official Release of CMSIS devices drivers supporting STM32WBA52xx and STM32WBA55xx devices

  • Update CMSIS devices to include latest corrections
      -
    • Align SAU region end address on Flash end address
      • +
    • Add support of WKUP_S_IRQn and RCC_AUDIOSYNC_IRQn interrupts in CMSIS devices, startup_stm32wba5xxx.s and partition_stmwba5xxx.h files
      • +
    • Update Licensing header in partition_stm325xxx.h files based on partition_ARMCM33.h
      • +
    • Update declaration of g_pfnVectors size in gcc/startup_stm32wba5xxx.s files


@@ -449,22 +333,20 @@

Notes

- - +

Main Changes

-

First -Official Release of STM32CubeWBA Firmware package -supporting STM32WBA52xx devices

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

Contents

+

Official Release of CMSIS devices drivers supporting STM32WBA52xx devices

    -
  • First official release of CMSIS devices drivers +
  • Update CMSIS devices to include latest corrections
      -
    • Support of STM32WBA52xx devices
      • +
    • Align SAU region end address on Flash end address
+


+

Known Limitations

  • None
    • @@ -479,17 +361,39 @@

    Notes

-
+
+ +
+

Main Changes

+

First Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

+

Contents

+ +

Known Limitations

+ +

Dependencies

+ +

Notes

+ +
+
+