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MaurizioCascianoMaurizioCasciano
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topology2: ipc3: add Cherry Trail RT5677 topology
Add topology2 support for generating and deploying IPC3 topology files alongside the existing IPC4 production set. Describe the Yoga Book RT5677 SSP2 playback, capture, low-latency and deep-buffer paths while preserving the Cherry Trail memory, scheduler and hardware configuration required by the legacy IPC3 firmware. Keep the four-slot, 25-bit frame geometry but activate only slots 0 and 1 for the stereo stream. The generated topology is byte-identical to the artifact validated on a Lenovo Yoga Book YB1-X91L with PCM0 playback and capture in S16_LE, S24_LE and S32_LE at 48 kHz stereo, plus PCM1 deep-buffer playback. Signed-off-by: Maurizio Casciano <mauriziocasciano7@gmail.com>
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‎tools/topology/topology2/CMakeLists.txt‎

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# Create directory structure to be provided for deployment
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COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/target/sof-ipc4-tplg
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COMMAND ${CMAKE_COMMAND} -E create_symlink sof-ipc4-tplg ${CMAKE_CURRENT_BINARY_DIR}/target/sof-ace-tplg
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COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/target/sof-tplg
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COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/target/development
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# copy the topology files only to target, preserving symbolic links
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COMMAND sh -c "cp -a production/*.tplg \"${CMAKE_CURRENT_BINARY_DIR}/target/sof-ipc4-tplg/\""
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COMMAND sh -c "cp -a production/ipc3/*.tplg \"${CMAKE_CURRENT_BINARY_DIR}/target/sof-tplg/\""
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COMMAND sh -c "cp -a development/*.tplg \"${CMAKE_CURRENT_BINARY_DIR}/target/development/\""
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)
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@@ -37,6 +39,18 @@ add_custom_target(abi_target
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DEPENDS abi.conf
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)
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# Atom platforms use IPC3 even when the source topology is written using the
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# topology2 object model. Keep a separate ABI manifest so IPC3 and IPC4 output
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# can be built together without changing the existing production topologies.
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add_custom_command(OUTPUT abi-ipc3.conf
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COMMAND > abi-ipc3.conf ${CMAKE_CURRENT_SOURCE_DIR}/get_abi.sh
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${SOF_ROOT_SOURCE_DIRECTORY} "ipc3"
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DEPENDS ${SOF_ROOT_SOURCE_DIRECTORY}/src/include/kernel/abi.h
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)
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add_custom_target(abi_ipc3_target
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DEPENDS abi-ipc3.conf
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)
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add_dependencies(topologies2 topology2_dev topology2_prod)
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add_subdirectory(development)
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add_subdirectory(production)

‎tools/topology/topology2/README.md‎

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@@ -395,12 +395,29 @@ target is a semicolon-separated tuple:
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Select the cmake file matching the target platform generation:
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| Platform | CMake Target File |
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| Target family | CMake target file |
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|---|---|
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| IPC3 | `tplg-targets-ipc3.cmake` |
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| Tiger Lake / Alder Lake | `tplg-targets-cavs25.cmake` |
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| Meteor Lake | `tplg-targets-ace1.cmake` |
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| Lunar Lake | `tplg-targets-ace2.cmake` |
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| Panther Lake | `tplg-targets-ace3.cmake` |
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| HDA generic | `tplg-targets-hda-generic.cmake` |
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### IPC3 topology targets
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Topology2 source files can also target firmware that uses IPC3. Register IPC3
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targets in `production/tplg-targets-ipc3.cmake`; they are built with a separate
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IPC3 ABI manifest and installed under `target/sof-tplg` instead of the IPC4/ACE
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topology directory.
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Build an individual registered IPC3 target with:
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```bash
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cmake --build . --target topology2_prod_ipc3_OUTPUT_NAME
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```
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Replace `OUTPUT_NAME` with the target's output name from
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`tplg-targets-ipc3.cmake`.
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Development and testing topologies go in `development/tplg-targets.cmake`.

‎tools/topology/topology2/cht-rt5677.conf‎

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# SPDX-License-Identifier: BSD-3-Clause
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<searchdir:include>
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<searchdir:include/common>
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<searchdir:include/components>
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<searchdir:include/dais>
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<searchdir:include/pipelines>
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<searchdir:platform>
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<searchdir:platform/intel>
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<vendor-token.conf>
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<tokens.conf>
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<manifest.conf>
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<data.conf>
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<pcm.conf>
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<pcm_caps.conf>
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<fe_dai.conf>
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<route.conf>
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<common_definitions.conf>
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<virtual.conf>
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<ipc3/volume-playback.conf>
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<ipc3/mixer-volume-dai-playback.conf>
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<ipc3/volume-dai-capture.conf>
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<ssp.conf>
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<intel/cht-hw-config.conf>
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Define {
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# Cherry Trail uses the first-generation SSP configuration blob and IPC3.
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SSP_BLOB_VERSION $SSP_BLOB_VERSION_1_0
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}
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# The machine driver connects the RT5677 AIF routes through these platform
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# widgets. They mirror the widgets exposed by the legacy Cherry Trail topology.
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Object.Widget.virtual [
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{ name "codec_out0" type "output" index 1 }
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{ name "codec_out1" type "output" index 2 }
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{ name "codec_in0" type "input" index 3 }
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{ name "codec_in1" type "input" index 4 }
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{ name "ssp2 Rx" type "input" index 5 }
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{ name "ssp2 Tx" type "output" index 6 }
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]
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# SSP2 carries the RT5677 AIF1 stream. The bit and frame clocks are driven by
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# the Cherry Trail SSP; the codec consumes both clocks.
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Object.Dai.SSP [
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{
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id 0
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dai_index 2
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direction "duplex"
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name "SSP2-Codec"
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default_hw_config_id 0
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sample_bits 24
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Object.Base.hw_config.1 {
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name "SSP2"
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id 0
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format "DSP_B"
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mclk "codec_mclk_in"
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mclk_freq 19200000
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bclk "codec_consumer"
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bclk_freq 4800000
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# Match SND_SOC_DAIFMT_IB_NF in the machine driver:
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# invert BCLK while leaving the frame clock non-inverted.
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bclk_invert "true"
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fsync "codec_consumer"
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fsync_freq 48000
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fsync_invert "false"
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tdm_slots 4
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tdm_slot_width 25
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# The frame has four slots, but the stereo stream uses slots 0 and 1.
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# IPC3 derives the DAI channel count from these active-slot masks.
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tx_slots 3
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rx_slots 3
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}
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}
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]
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Object.Pipeline {
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ipc3-mixer-volume-dai-playback.1 {
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index 1
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format "s24le"
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channels 2
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dai_type "SSP"
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dai_index 2
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periods 2
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# Two 1 ms periods at 48 kHz, stereo, four bytes per sample.
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size 768
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Object.Widget.pipeline.1 {
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stream_name "dai.SSP.2.playback"
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priority 1
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core 0
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frames 0
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mips 5000
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}
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Object.Widget.dai.playback {
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format "s24le"
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stream_name "SSP2-Codec"
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core_id 0
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}
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Object.Widget.pga.1 {
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ramp_step_ms 20
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Object.Control.mixer.1 {
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name "1 Master Playback Volume"
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Object.Base.tlv.vtlv_m64s2 {
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Object.Base.scale.m64s2 {}
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}
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}
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}
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Object.Base.route.4 {
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source "buffer.1.2"
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sink "dai.SSP.2.playback"
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}
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}
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ipc3-volume-dai-capture.2 {
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index 2
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format "s32le"
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channels 2
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dai_type "SSP"
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dai_index 2
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periods 2
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# Two 1 ms periods at 48 kHz, stereo, four bytes per sample.
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size 768
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Object.Widget.pipeline.1 {
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stream_name "dai.SSP.2.capture"
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priority 0
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core 0
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frames 0
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mips 5000
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}
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Object.Widget.dai.capture {
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format "s24le"
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stream_name "SSP2-Codec"
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core_id 0
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}
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Object.Widget.host.capture {
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stream_name "Low Latency Capture 0"
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core_id 0
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}
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Object.Widget.pga.1 {
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ramp_step_ms 250
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Object.Control.mixer.1 {
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name "2 PCM 0 Capture Volume"
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max 40
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Object.Base.channel.1 {
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name "fl"
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reg 0
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shift 0
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}
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Object.Base.channel.2 {
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name "fr"
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reg 0
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shift 1
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}
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Object.Base.tlv.vtlv_m64s2 {
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Object.Base.scale.m64s2 {}
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}
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}
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}
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Object.Base.route.4 {
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source "dai.SSP.2.capture"
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sink "buffer.2.1"
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}
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}
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ipc3-volume-playback.3 {
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index 3
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format "s32le"
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channels 2
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period 1000
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time_domain "dma"
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Object.Widget.pipeline.1 {
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priority 0
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core 0
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frames 0
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mips 100000
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stream_name "dai.SSP.2.playback"
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}
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Object.Widget.host.playback {
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stream_name "Playback 0"
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core_id 0
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period_sink_count 0
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period_source_count 2
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}
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Object.Widget.pga.1 {
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ramp_step_ms 20
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period_sink_count 2
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period_source_count 2
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Object.Control.mixer.1 {
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name "3 Playback Volume"
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Object.Base.tlv.vtlv_m64s2 {
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Object.Base.scale.m64s2 {}
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}
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}
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}
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Object.Widget.buffer.1 {
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caps "ram_dma_cache"
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# IPC3 needs SOF_TKN_BUF_SIZE serialized explicitly. An object
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# value takes precedence over the class's automatic size value.
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size 768
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}
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Object.Widget.buffer.2 {
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caps "ram_dma_cache"
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size 768
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}
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}
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ipc3-volume-playback.4 {
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index 4
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format "s32le"
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channels 2
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period 5000
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time_domain "dma"
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Object.Widget.pipeline.1 {
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priority 0
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core 0
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frames 0
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mips 100000
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stream_name "dai.SSP.2.playback"
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}
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Object.Widget.host.playback {
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stream_name "Playback 1"
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core_id 0
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period_sink_count 0
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period_source_count 2
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}
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Object.Widget.pga.1 {
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ramp_step_ms 20
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period_sink_count 2
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period_source_count 2
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Object.Control.mixer.1 {
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name "4 Playback Volume"
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Object.Base.tlv.vtlv_m64s2 {
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Object.Base.scale.m64s2 {}
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}
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}
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}
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Object.Widget.buffer.1 {
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caps "ram_dma_cache"
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# Five milliseconds at 48 kHz, two channels and four bytes per
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# sample, with two periods: 5 ms * 48 * 2 * 4 * 2 = 3840.
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size 3840
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}
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Object.Widget.buffer.2 {
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caps "ram_dma_cache"
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size 3840
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}
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}
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}
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# Both playback front ends feed the low-latency SSP2 mixer.
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Object.Base.route [
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{ source "buffer.3.2" sink "ipc3-mixer.1.1" }
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{ source "buffer.4.2" sink "ipc3-mixer.1.1" }
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]
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Object.PCM.pcm [
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{
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name "PCM"
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id 0
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direction "duplex"
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Object.Base.fe_dai.1 {
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name "PCM 0"
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}
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Object.PCM.pcm_caps.playback {
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direction "playback"
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name "Playback 0"
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formats "S16_LE,S24_LE,S32_LE"
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rates "48000"
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rate_min 48000
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rate_max 48000
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channels_min 2
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channels_max 2
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# Match the proven Cherry Trail IPC3 topology instead of the
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# much larger generic topology2 PCM capability defaults.
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periods_min 2
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periods_max 16
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period_size_min 192
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period_size_max 16384
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buffer_size_min 65536
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buffer_size_max 65536
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}
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Object.PCM.pcm_caps.capture {
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direction "capture"
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name "Low Latency Capture 0"
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formats "S16_LE,S24_LE,S32_LE"
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rates "48000"
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rate_min 48000
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rate_max 48000
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channels_min 2
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channels_max 2
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periods_min 2
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# The low-latency capture path supports fewer queued periods
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# than playback in the legacy Cherry Trail topology.
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periods_max 4
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period_size_min 192
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period_size_max 16384
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buffer_size_min 65536
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buffer_size_max 65536
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}
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}
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{
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name "PCM Deep Buffer"
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id 1
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direction "playback"
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Object.Base.fe_dai.1 {
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name "PCM Deep Buffer 1"
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}
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Object.PCM.pcm_caps.playback {
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direction "playback"
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name "Playback 1"
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formats "S16_LE,S24_LE,S32_LE"
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rates "48000"
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rate_min 48000
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rate_max 48000
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channels_min 2
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channels_max 2
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# Keep userspace constraints identical for the low-latency and
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# deep-buffer playback PCMs, as on the legacy CHT topology.
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periods_min 2
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periods_max 16
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period_size_min 192
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period_size_max 16384
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buffer_size_min 65536
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buffer_size_max 65536
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}
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}
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]

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