simd(avx2): native __m256i for U32x8 / U32x16 — the ARX lane (TD-T22) - #261
simd(avx2): native __m256i for U32x8 / U32x16 — the ARX lane (TD-T22)#261AdaWorldAPI wants to merge 2 commits into
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The invariant: all SIMD types come from `crate::simd::*`; the ops layer never reaches into a backend module. `simd_int_ops.rs` violated it at five sites inside `#[cfg(target_arch = "aarch64")]` blocks. Four are corrected: `use crate::simd_neon::I8x16` → `use crate::simd::I8x16`. Sound because `I8x16` is a registry key on every arm (simd.rs exports it on v4, v3, aarch64, wasm32+simd128, and scalar), so this is a pure path swap with no type change. The fifth (`I16x8`, line 158) is NOT corrected and is documented in place instead. `I16x8` is not a registry key at all — it exists only as `simd_neon.rs:1311` `pub struct I16x8(pub int16x8_t)` and no arm of `simd.rs` re-exports it. Trampolining it requires registering the type in the dispatch arms plus a counterpart for the arms that have none — a registry change, not a path swap. Left visible rather than half-fixed. Not compile-verified for aarch64 locally (target not installed on this x86 host); the qemu neon-simd/parity job is what proves it.
Replaces the `avx2_int_type!` scalar-storage polyfills for the two u32
lanes with real AVX2 registers, mirroring the shipped `U16x16` lowering
in the same file.
- `U32x8(pub __m256i)` — one register, 8 lanes.
- `U32x16(pub U32x8, pub U32x8)` — two halves, the same composition
`F32x16(pub f32x8, pub f32x8)` already uses here. (NEON's four-quarter
`[U32x4; 4]` is the same idea at a different register width, not a
competing convention.)
Public surface is unchanged: every method and operator the macro emitted
is reimplemented with identical semantics, including the WRAPPING
`reduce_sum` and wrapping Add/Sub. Type names and lowercase aliases are
untouched, so both `simd.rs` dispatch arms and the `simd_avx512.rs`
re-export pick these up with no edits.
`rotate_left` is `n % 32` then `sll(n) | srl(32 - n)`. No branch for
n = 0: the ISA defines a shift count >= 32 as yielding zero, so
`sll(0) | srl(32)` is the identity. Rotate amounts in ARX ciphers are
public constants, so a runtime `n` carries no timing concern.
Why this lane: `U32x16` Add/BitXor/rotate_left is the ChaCha20/BLAKE ARX
triple that `vendor/chacha20` rides. It was already native on AVX-512
(VPROLVD), NEON, and wasm — AVX2 was the last tier still doing it in
scalar Rust, which is the default tier for CI and for any x86 build
without an explicit v4 config.
Also trampolines `U16x16::to_f32x8_{lo,hi}` to return `crate::simd::F32x8`
instead of `crate::simd_avx512::F32x8` — a public signature in the v3
backend must not name another backend's module.
Tests: 16 new, each against an inline scalar reference, with inputs
chosen so a wrong implementation fails — distinct per-lane values
(catches lane-order bugs), operands that overflow and underflow u32,
products exceeding 32 bits, rotate amounts including 0/31/32/33 (proves
the mod-32 wrap), a reduce_sum that wraps, and a U32x16 half-seam case
where lanes 7 and 8 differ (catches a lo/hi swap).
📝 WalkthroughWalkthroughAVX2 ChangesAVX2 U32 SIMD
Estimated code review effort: 4 (Complex) | ~60 minutes Possibly related PRs
Suggested reviewers: Poem
🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
✨ Finishing Touches📝 Generate docstrings
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| pub fn to_f32x8_lo(self) -> crate::simd::F32x8 { | ||
| // SAFETY: AVX2 baseline. | ||
| crate::simd_avx512::F32x8(unsafe { _mm256_cvtepi32_ps(_mm256_cvtepu16_epi32(_mm256_castsi256_si128(self.0))) }) | ||
| crate::simd::F32x8(unsafe { _mm256_cvtepi32_ps(_mm256_cvtepu16_epi32(_mm256_castsi256_si128(self.0))) }) |
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When the supported nightly-simd feature is enabled on x86-64, crate::simd::F32x8 resolves to simd_nightly::F32x8, whose tuple field is core::simd::f32x8, but this expression supplies an AVX __m256. Because simd_avx2 is still compiled on x86-64 even when nightly dispatch replaces it, the repository's nightly-simd-polyfill cargo check fails with a constructor type mismatch; keep this backend-internal conversion concrete or exclude it from that feature configuration.
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| #[cfg(target_arch = "aarch64")] | ||
| { | ||
| use crate::simd_neon::I8x16; | ||
| use crate::simd::I8x16; |
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When cross-compiling for AArch64 with nightly-simd, this import is unresolved because that dispatch arm does not export an I8x16 at all, while the previous simd_neon::I8x16 remains available on AArch64. The same replacement occurs in the other three i8 blocks, so this supported portable-SIMD configuration cannot compile; either register a nightly I8x16 first or retain a feature-specific NEON import.
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Actionable comments posted: 3
🧹 Nitpick comments (1)
src/simd_avx2.rs (1)
1785-1786: 📐 Maintainability & Code Quality | 🔵 Trivial | ⚡ Quick winNew public API lacks
///docs with examples.
U32x8::{splat, zero, from_slice, from_array, to_array, copy_to_slice}have no doc comments, andreduce_sum/rotate_left/shl/shrdocument behavior but carry no# Examplesblock (compareF32x8::mul_addinsrc/simd_avx512.rs:1352-1368). Same applies to the newU32x16surface at lines 1979-2034.As per coding guidelines: "All public APIs (public functions and methods) must have
///doc comments with examples".🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@src/simd_avx2.rs` around lines 1785 - 1786, Document every newly public U32x8 and U32x16 function and method with /// comments and runnable # Examples blocks, including splat, zero, from_slice, from_array, to_array, copy_to_slice, reduce_sum, rotate_left, shl, and shr. Follow the existing F32x8::mul_add documentation style and ensure examples demonstrate each API’s intended behavior.Source: Coding guidelines
🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
Inline comments:
In `@src/simd_avx2.rs`:
- Around line 1788-1822: Add a concise `// SAFETY:` comment to every bare
`unsafe` block in the AVX2 vector methods and operator implementations,
including `splat`, `zero`, `from_array`, `copy_to_slice`, and all operator
impls. Describe the relevant intrinsic or pointer-layout invariant, such as
fixed-width lane size, valid slice length, or register-only arithmetic, matching
the existing safety-comment style in `from_slice`, `to_array`, and related
methods.
- Around line 1979-2034: Add `Shl<Self>` and `Shr<Self>` implementations for
`U32x16`, matching the per-lane shift behavior exposed by `simd_avx512.rs` and
`simd_scalar.rs`; delegate each half to `U32x8::shl` or `U32x8::shr` using the
corresponding lane-wise count values, and add parity coverage for `U32x16`
shifts across tiers.
- Around line 1824-1868: Add public U32x8 implementations of reduce_sum,
rotate_left, shl, and shr to the NEON and re-exported scalar U32x8 definitions,
matching the AVX2 semantics: wrapping lane sum, modulo-32 rotates, and
ISA-compatible logical shifts. Ensure crate::simd::U32x8 exposes these
operations on every backend. Add parity coverage for the new operations on
NEON/wasm or other scalar paths.
---
Nitpick comments:
In `@src/simd_avx2.rs`:
- Around line 1785-1786: Document every newly public U32x8 and U32x16 function
and method with /// comments and runnable # Examples blocks, including splat,
zero, from_slice, from_array, to_array, copy_to_slice, reduce_sum, rotate_left,
shl, and shr. Follow the existing F32x8::mul_add documentation style and ensure
examples demonstrate each API’s intended behavior.
🪄 Autofix (Beta)
Fix all unresolved CodeRabbit comments on this PR:
- Push a commit to this branch (recommended)
- Create a new PR with the fixes
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📒 Files selected for processing (2)
src/simd_avx2.rssrc/simd_int_ops.rs
| #[inline(always)] | ||
| pub fn splat(v: u32) -> Self { | ||
| Self(unsafe { _mm256_set1_epi32(v as i32) }) | ||
| } | ||
|
|
||
| #[inline(always)] | ||
| pub fn zero() -> Self { | ||
| Self(unsafe { _mm256_setzero_si256() }) | ||
| } | ||
|
|
||
| #[inline(always)] | ||
| pub fn from_slice(s: &[u32]) -> Self { | ||
| assert!(s.len() >= 8); | ||
| // SAFETY: 8 × u32 = 32 bytes = one __m256i. Unaligned load. | ||
| Self(unsafe { _mm256_loadu_si256(s.as_ptr() as *const __m256i) }) | ||
| } | ||
|
|
||
| #[inline(always)] | ||
| pub fn from_array(arr: [u32; 8]) -> Self { | ||
| Self(unsafe { _mm256_loadu_si256(arr.as_ptr() as *const __m256i) }) | ||
| } | ||
|
|
||
| #[inline(always)] | ||
| pub fn to_array(self) -> [u32; 8] { | ||
| let mut arr = [0u32; 8]; | ||
| // SAFETY: store 32 bytes into 8 × u32. | ||
| unsafe { _mm256_storeu_si256(arr.as_mut_ptr() as *mut __m256i, self.0) }; | ||
| arr | ||
| } | ||
|
|
||
| #[inline(always)] | ||
| pub fn copy_to_slice(self, s: &mut [u32]) { | ||
| assert!(s.len() >= 8); | ||
| unsafe { _mm256_storeu_si256(s.as_mut_ptr() as *mut __m256i, self.0) }; | ||
| } |
There was a problem hiding this comment.
📐 Maintainability & Code Quality | 🟡 Minor | ⚡ Quick win
Missing // SAFETY: comments on several unsafe blocks.
splat (1790), zero (1795), from_array (1807), copy_to_slice (1821) and every operator impl (1882, 1889, 1896, 1902, 1908, 1915, 1922, 1929, 1935, 1941, 1947, 1954) use bare unsafe { … }. from_slice/to_array/rotate_left/shl/shr in the same block do carry them, so this is an internal inconsistency as well.
As per coding guidelines: "Every unsafe block must include a // SAFETY: comment explaining why the unsafe code is required and how memory safety is preserved".
📝 Example fixes
#[inline(always)]
pub fn splat(v: u32) -> Self {
+ // SAFETY: AVX2 baseline; register-only intrinsic, no memory access.
Self(unsafe { _mm256_set1_epi32(v as i32) })
} #[inline(always)]
pub fn from_array(arr: [u32; 8]) -> Self {
+ // SAFETY: 8 × u32 = 32 bytes = one __m256i; unaligned load from a
+ // fully-initialized local array.
Self(unsafe { _mm256_loadu_si256(arr.as_ptr() as *const __m256i) })
} #[inline(always)]
pub fn copy_to_slice(self, s: &mut [u32]) {
assert!(s.len() >= 8);
+ // SAFETY: length checked above; stores exactly 32 bytes unaligned.
unsafe { _mm256_storeu_si256(s.as_mut_ptr() as *mut __m256i, self.0) };
} impl Add for U32x8 {
type Output = Self;
#[inline(always)]
fn add(self, rhs: Self) -> Self {
+ // SAFETY: AVX2 baseline; register-only lane-wise add, wrapping.
Self(unsafe { _mm256_add_epi32(self.0, rhs.0) })
}
}Also applies to: 1878-1956
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
In `@src/simd_avx2.rs` around lines 1788 - 1822, Add a concise `// SAFETY:`
comment to every bare `unsafe` block in the AVX2 vector methods and operator
implementations, including `splat`, `zero`, `from_array`, `copy_to_slice`, and
all operator impls. Describe the relevant intrinsic or pointer-layout invariant,
such as fixed-width lane size, valid slice length, or register-only arithmetic,
matching the existing safety-comment style in `from_slice`, `to_array`, and
related methods.
Source: Coding guidelines
| /// Horizontal sum of all 8 lanes — WRAPPING, matching the retired | ||
| /// `avx2_int_type!` macro's `wrapping_add` fold (unlike `U16x16::reduce_sum`, | ||
| /// which widens to `u32` and cannot overflow; `u32` has nowhere wider to | ||
| /// widen to here without changing the return type). | ||
| #[inline(always)] | ||
| pub fn reduce_sum(self) -> u32 { | ||
| self.to_array().iter().fold(0u32, |a, &v| a.wrapping_add(v)) | ||
| } | ||
|
|
||
| /// Lane-wise left-rotate by `n` bits — the ARX rotate (matches | ||
| /// `u32::rotate_left` for every `n`, including `n == 0` and `n >= 32`). | ||
| /// `n` is first reduced mod 32 (matching `u32::rotate_left`'s own | ||
| /// wraparound), then built from `sll(n) | srl(32 - n)`. At `n == 0` this is | ||
| /// `sll(0) | srl(32)`: per the ISA, `_mm256_srl_epi32` with a shift count | ||
| /// `>= 32` produces all-zero lanes, so the `srl` term vanishes and the | ||
| /// `sll(0)` term (identity) is exactly `self` — no branch needed. As with | ||
| /// the AVX-512 `VPROLVD` rotate, ARX rotate amounts are public constants | ||
| /// (never secret), so a runtime `n` carries no timing concern. | ||
| #[inline(always)] | ||
| pub fn rotate_left(self, n: u32) -> Self { | ||
| let n = n % 32; | ||
| // SAFETY: AVX2 baseline. `_mm256_sll_epi32`/`_mm256_srl_epi32` take a | ||
| // runtime shift count from the low 64 bits of an xmm register. | ||
| unsafe { | ||
| let cnt_lo = _mm_cvtsi32_si128(n as i32); | ||
| let cnt_hi = _mm_cvtsi32_si128((32 - n) as i32); | ||
| Self(_mm256_or_si256(_mm256_sll_epi32(self.0, cnt_lo), _mm256_srl_epi32(self.0, cnt_hi))) | ||
| } | ||
| } | ||
|
|
||
| /// Logical left shift each 32-bit lane by `imm` (matches `U16x16::shl`; | ||
| /// runtime lane count, so every shift amount in `0..32` works — an | ||
| /// `imm >= 32` yields all-zero lanes per the ISA). | ||
| #[inline(always)] | ||
| pub fn shl(self, imm: u32) -> Self { | ||
| // SAFETY: AVX2 baseline. | ||
| Self(unsafe { _mm256_sll_epi32(self.0, _mm_cvtsi32_si128(imm as i32)) }) | ||
| } | ||
|
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||
| /// Logical right shift each 32-bit lane by `imm` (matches `U16x16::shr`). | ||
| #[inline(always)] | ||
| pub fn shr(self, imm: u32) -> Self { | ||
| // SAFETY: AVX2 baseline. | ||
| Self(unsafe { _mm256_srl_epi32(self.0, _mm_cvtsi32_si128(imm as i32)) }) | ||
| } |
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🗄️ Data Integrity & Integration | 🟠 Major | ⚡ Quick win
🧩 Analysis chain
🏁 Script executed:
#!/bin/bash
# U32x8 definitions and method sets per backend
rg -nP --type=rust -C2 'pub struct U32x8\b'
for f in $(fd -t f 'simd_.*\.rs' src); do
echo "== $f"; ast-grep outline "$f" --match 'U32x8' --items all 2>/dev/null | rg -n 'rotate_left|shl|shr|reduce_sum' || true
done
# Parity test referenced in the doc comment
rg -nP --type=rust -C4 'u32x16_arx_ops_match_scalar'Repository: AdaWorldAPI/ndarray
Length of output: 157
🏁 Script executed:
#!/bin/bash
set -e
echo "Tracked SIMD-related files under src:"
git ls-files 'src/*simd*.rs' | sed -n '1,120p'
echo
echo "Search U32x8 symbols (all files, case sensitive):"
rg -n 'U32x8' . --glob '*.rs' --glob '!target/**' || true
echo
echo "Search public rotate/shl/shr/reduce_sum in Rust SIMD files:"
for f in $(git ls-files 'src/*simd*.rs' 'src/**/*.rs' | sort); do
if grep -qE 'pub .* (rotate_left|shl|shr|reduce_sum)\b' "$f"; then
echo "== $f =="
grep -nE 'pub .* (rotate_left|shl|shr|reduce_sum)\b' "$f" | sed -n '1,160p'
fi
done
echo
echo "Tests mentioning arx_ops or u32x16:"
rg -n 'u32x16|arx_ops|parrot|rotate_left|reduce_sum' . --glob '*.rs' --glob '!target/**' || trueRepository: AdaWorldAPI/ndarray
Length of output: 37454
🏁 Script executed:
#!/bin/bash
set -e
for f in src/simd_avx2.rs src/simd_neon.rs src/simd_scalar.rs src/simd_avx512.rs; do
echo "== $f U32x8 =="
sed -n '1760,1880p' "$f" 2>/dev/null || true
done
echo
echo "== imports/public export around u32x16 parity =="
sed -n '220,250p' src/simd.rs
sed -n '376,430p' src/simd.rs
sed -n '704,745p' src/simd.rs
echo
echo "== simd_neon U8x/U16/U32 exports =="
rg -n -C3 'pub (struct|type|enum) (U8x|U16x|U32x|u8x|u16x|u32x)' src/simd_neon.rs src/simd_scalar.rs src/simd_avx512.rs src/simd_avx2.rsRepository: AdaWorldAPI/ndarray
Length of output: 28948
Add the missing U32x8 operations for the non-AVX2 SIMD paths.
U32x8 is exported from simd_avx2, simd_avx512, and simd_scalar, but NEON/re-exported scalar U32x8 types are missing. The AVX2-only rotate_left, shl, shr, wrapping reduce_sum methods therefore break crate::simd::U32x8 consumers on NEON/other scalar paths where that pub type resolves elsewhere, and there is no NEON/wasm u32x8 parity test for these new public ops.
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
In `@src/simd_avx2.rs` around lines 1824 - 1868, Add public U32x8 implementations
of reduce_sum, rotate_left, shl, and shr to the NEON and re-exported scalar
U32x8 definitions, matching the AVX2 semantics: wrapping lane sum, modulo-32
rotates, and ISA-compatible logical shifts. Ensure crate::simd::U32x8 exposes
these operations on every backend. Add parity coverage for the new operations on
NEON/wasm or other scalar paths.
Source: Coding guidelines
| impl U32x16 { | ||
| pub const LANES: usize = 16; | ||
|
|
||
| #[inline(always)] | ||
| pub fn splat(v: u32) -> Self { | ||
| Self(U32x8::splat(v), U32x8::splat(v)) | ||
| } | ||
|
|
||
| #[inline(always)] | ||
| pub fn zero() -> Self { | ||
| Self(U32x8::zero(), U32x8::zero()) | ||
| } | ||
|
|
||
| #[inline(always)] | ||
| pub fn from_slice(s: &[u32]) -> Self { | ||
| assert!(s.len() >= 16); | ||
| Self(U32x8::from_slice(&s[..8]), U32x8::from_slice(&s[8..16])) | ||
| } | ||
|
|
||
| #[inline(always)] | ||
| pub fn from_array(a: [u32; 16]) -> Self { | ||
| Self(U32x8::from_array(a[..8].try_into().unwrap()), U32x8::from_array(a[8..].try_into().unwrap())) | ||
| } | ||
|
|
||
| #[inline(always)] | ||
| pub fn to_array(self) -> [u32; 16] { | ||
| let mut out = [0u32; 16]; | ||
| out[..8].copy_from_slice(&self.0.to_array()); | ||
| out[8..].copy_from_slice(&self.1.to_array()); | ||
| out | ||
| } | ||
|
|
||
| #[inline(always)] | ||
| pub fn copy_to_slice(self, s: &mut [u32]) { | ||
| assert!(s.len() >= 16); | ||
| s[..8].copy_from_slice(&self.0.to_array()); | ||
| s[8..16].copy_from_slice(&self.1.to_array()); | ||
| } | ||
|
|
||
| /// Horizontal sum of all 16 lanes — WRAPPING (matches the retired | ||
| /// `avx2_int_type!` macro semantics). | ||
| #[inline(always)] | ||
| pub fn reduce_sum(self) -> u32 { | ||
| self.to_array().iter().fold(0u32, |a, &v| a.wrapping_add(v)) | ||
| } | ||
|
|
||
| /// Lane-wise left-rotate by `n` bits — the ARX rotate (matches | ||
| /// `u32::rotate_left`), completing `Add` + `BitXor` for ChaCha20/BLAKE. | ||
| /// Delegates to the native `U32x8::rotate_left` per half — bit-identical | ||
| /// to the scalar tier and to the native `VPROLVD` path, the shared parity | ||
| /// reference (see `simd.rs::u32x16_arx_ops_match_scalar`). | ||
| #[inline(always)] | ||
| pub fn rotate_left(self, n: u32) -> Self { | ||
| Self(self.0.rotate_left(n), self.1.rotate_left(n)) | ||
| } | ||
| } |
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🗄️ Data Integrity & Integration | 🟡 Minor | ⚡ Quick win
🧩 Analysis chain
🏁 Script executed:
#!/bin/bash
# 1) What shift/other trait impls exist per backend for U32x8 / U32x16?
rg -nP --type=rust -B2 -A6 'impl\s+(Shl|Shr|ShlAssign|ShrAssign|Index|Eq)\b[^{]*\bU32x(8|16)\b'
# 2) What did the retired macro generate?
ast-grep run --pattern 'macro_rules! avx2_int_type { $$$ }' --lang rust src/simd_avx2.rs
# 3) Any consumer using shifts on U32x16/U32x8?
rg -nP --type=rust -C3 '\bU32x(8|16)\b.*(<<|>>)|(<<|>>).*\bU32x(8|16)\b'
rg -nP --type=rust -C3 '\.(shl|shr)\s*\(' -g 'src/**/*.rs'Repository: AdaWorldAPI/ndarray
Length of output: 157
🏁 Script executed:
#!/bin/bash
set -u
echo "Files containing simd_avx2/A avx512:"
git ls-files | rg '(^|/)simd_(avx2|neon|scalar|avx512)\.rs$|Cargo\.toml|rustfmt\.toml' || true
echo
echo "Locate avx2_int_type macro in tracked files:"
rg -n --type=rust 'avx2_int_type|macro_rules!\s+avx2_int_type' . || true
echo
echo "Candidate files around U32x8/U32x16 implementations:"
for f in src/simd_avx2.rs src/simd_avx512.rs src/simd_neon.rs src/simd_scalar.rs; do
if [ -f "$f" ]; then
echo "--- $f: occurrences of U32x8/U32x16/Shl/Shr/shl/shr ---"
rg -n -C2 '\bU32x(8|16)\b|impl\s+(Shl|Shr|ShlAssign|ShrAssign|Index|Eq)\b|fn\s+(shl|shr|rotate_left)' "$f" || true
fi
done
echo
echo "Search shift call sites across Rust sources:"
rg -n -C3 '\bU32x(8|16)\b.*(<<|>>)|(<<|>>).*\bU32x(8|16)\b|\.(shl|shr)\s*\(' --type=rust . || true
echo
echo "Outline simd_avx2 if installed:"
if command -v ast-grep >/tmp/ast-skip 2>/dev/null && [ -f src/simd_avx2.rs ]; then
ast-grep outline src/simd_avx2.rs --match 'U32x16' --view expanded || true
fiRepository: AdaWorldAPI/ndarray
Length of output: 33010
🏁 Script executed:
#!/bin/bash
set -u
echo "U32x8 macro around impls:"
sed -n '1772,1968p' src/simd_avx2.rs | cat -n
echo
echo "U32x16 current impl section:"
sed -n '2036,2136p' src/simd_avx2.rs | cat -n
echo
echo "AVX512 re-exports and feature gates:"
sed -n '1,80p' src/simd_avx512.rs | cat -n
sed -n '2308,2326p' src/simd_avx512.rs | cat -n
sed -n '1,80p' src/lib.rs | cat -n 2>/dev/null || sed -n '1,120p' Cargo.toml | cat -n
echo
echo "Top-level exports likely affecting backend selection:"
rg -n 'cfg.*avx512|avx512|sim[dFf]*|U32x16|u32x16' src/lib.rs src/**/*.rs --glob '*.rs' | head -n 120 || trueRepository: AdaWorldAPI/ndarray
Length of output: 30912
Keep U32x16 shift operator compatibility across tiers.
src/simd_avx512.rs and src/simd_scalar.rs provide Shl<Self>/Shr<Self> for U32x16, while the new AVX-2 U32x16 has no shift operators and the U32x8 halves only expose U32x8::shl(imm: u32) / U32x8::shr(imm: u32) with the same scalar count. Existing consumers using u32x16 >> u32x16 won’t compile on the AVX-2 path. Add a per-lane shift API/parity test for AVX-2 U32x16, or drop/replace the trait surface in the AVX-512 implementation before this path is widely used.
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
In `@src/simd_avx2.rs` around lines 1979 - 2034, Add `Shl<Self>` and `Shr<Self>`
implementations for `U32x16`, matching the per-lane shift behavior exposed by
`simd_avx512.rs` and `simd_scalar.rs`; delegate each half to `U32x8::shl` or
`U32x8::shr` using the corresponding lane-wise count values, and add parity
coverage for `U32x16` shifts across tiers.
2 participants
Closed — the premise was false. Not merging this.
Rejected on the operator's ruling: a
U32x8type composing aU32x16whenU32x16already exists is an absolute no-go. The lane the substrate cares about isU32x16; introducing a half-width type as its building block splits the vocabulary for no gain.Independent of that, adversarial review found the justification did not survive contact with the assembler:
The codegen gap did not exist.
.cargo/config.tomlpins-Ctarget-cpu=x86-64-v3for every x86_64 build, sosimd_avx2.rsnever compiled to scalar code. Assembly diffs of the retiredavx2_int_type!body vs the hand-written intrinsics are identical —vpaddd,vpxor,vpsrld/vpslld/vpor, and the samevpshufbstrength-reduction of rotate-by-16. A 10-round ChaCha-shaped loop over the old type compiled fully unrolled, 100% ymm, zero spills, with LLVM splitting it into two 256-bit halves on its own. The⏳in the parity matrix marked a source-level artifact, not a codegen gap.The cited consumer never routed through it.
vendor/chacha20/src/backends.rsselects thendarray_simdbackend only underavx512forwasm32+simd128; on the AVX2 tier it uses RustCrypto's ownavx2.rs. The RFC 8439 vectors cited in the original PR body as "end-to-end proof" never executed this code.Same pattern confirmed elsewhere in the file.
F32x16::mul_addon AVX2 is also ato_array→ scalar loop →from_arraysource form, and it emits realvfmadd213ps. Source-level scalar is not binary-level scalar anywhere in this backend.Silent layout regression.
#[repr(align(64))]→#[repr(transparent)]measured asU32x8size 64→32,U32x16align 64→32, against 9repr(align(64))sites in the scalar/NEON/wasm backends.size_of::<crate::simd::U32x8>()would have become architecture-dependent.Consumer-contract failures. Against
.claude/knowledge/vertical-simd-consumer-contract.md: no cross-backend parity test (the correct pattern already exists atsimd.rs:718u32x16_arx_ops_match_scalar), no bench or recorded ratio, and the newU32x8methods had no caller anywhere in the workspace.What TD-T22 actually asked for was an investigation —
td-simd-tier-audit.md:339reads "Investigation only", andCHACHA20_MATRYOSHKA_PLAN.md:104calls the lowering "still optional". The right deliverable was an asm-diff artifact and a one-paragraph finding, with zero newunsafe. That remains open and is the correct next step.Branch deleted; nothing merged.