chore(deps): update dependency flashinfer-python to v0.6.17 - #123
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This PR contains the following updates:
==0.6.14→==0.6.17Release Notes
flashinfer-ai/flashinfer (flashinfer-python)
v0.6.17Compare Source
These highlights are also published at flashinfer.ai/releases.
v0.6.17 Highlights
This release brings MoE expert parallelism into serving engines, refreshes the Blackwell SM12x fused-MoE kernels with an FP4 accuracy fix, extends the unified MoE API to MXFP4 W4A8/W4A16 and shared experts, and adds decode coverage for Kimi K3 MLA and MiniMax-M3 sparse attention on vLLM.
MoE expert parallelism production-ready in vLLM
The MegaMoE path in
flashinfer.moe_epis ready for serving engines: full CUDA-graph capture and replay, a fused single-launch quantize-and-stage hot path, prequantized weight packs, symmetric-buffer workspaces pooled across layers, and a persistent knob cache that resolves tuned knobs by lookup, so production sessions run with no in-engine autotuning. An opt-in fault-tolerance rank mask, available over both NCCL-EP and NIXL-EP, masks and skips a peer that times out during dispatch or combine, keeping the job alive when a rank dies. Deployment gets simpler too: the CuTe-DSL runtime floor returns to 4.5.2, the version vLLM 0.25.1 pins, and a newBootstrapConfig.devicelets the host framework pin each worker's CUDA device.Blackwell SM12x fused MoE refreshed, with an FP4 accuracy fix
W4A4 serving on DGX Spark and RTX PRO parts (GB10, SM120/SM121) now delivers the output quality its benchmark scores imply, with two NVFP4 quantization bugs fixed and a new
input_global_scalethat lets integrators pass a checkpoint's weight scale directly. The SM12x fused-MoE families are synced to current b12x: the NVFP4 W4A4 backend reaches kernel parity across decode and prefill, and the W4A16 family adds cooperative persistent launches, a tensor-core decode path for small batches, and shape-stable route packing that keeps decode batch-size changes recompile-free.Unified MoE API adds MXFP4 W4A8 and W4A16, shared experts, and SiTU
TRTLLM-gen MXFP4 weights now run through the unified
MoELayerAPI against both MXFP8 activations (W4A8) and BF16 activations (W4A16), completing the FP8 series begun in 0.6.16, alongside per-tensor routed FP8. Routing adds an unpacked pre-routed FP4 mode that acceptstopk_idsandtopk_weightsas separate contiguous tensors. TRTLLM-gen FP4 MoE also gains shared-expert fusion, extending to FP4 what 0.6.15 added for FP8, plus SiTU activation for MXFP4 x MXFP8 and NVFP4 x NVFP4.Kimi K3 MLA decode, and MiniMax-M3 sparse attention under vLLM
Blackwell decode now covers Kimi K3's MLA geometry — 96 global query heads against one KV head, TP-local head counts down to 6, speculative query lengths up to 8, and context parallelism for long contexts — by packing query-token and query-head rows into shared CuTe-DSL tiles, adding compact variable-length Q, and extending TRTLLM-gen dense and sparse MLA to non-power-of-two head counts. Sparse MLA decode also serves the no-rotary-tail shape (
kv_lora_rank=512,qk_rope_head_dim=0) natively. MiniMax Sparse Attention accepts vLLM's packed paged KV layout for MiniMax-M3, unblocking the vLLM integration on SM120/SM121, with lower per-call overhead on paged decode.Ulysses sequence parallelism for long-context and video diffusion
Ulysses sequence parallelism gets its head-scatter / sequence-gather all-to-all as a public API, for video diffusion transformers and other long-sequence attention workloads. A fused NVLink-P2P kernel folds the layout permutation directly into the cross-GPU writes over CUDA IPC for a single coalesced push, with automatic NCCL fallback when P2P is unavailable.
What's Changed
New Contributors
Full Changelog: flashinfer-ai/flashinfer@v0.6.16rc5...v0.6.17
v0.6.16.post4Compare Source
v0.6.16.post4
Restores
import flashinfer.common Python 3.10 and 3.11. A type annotation inflashinfer/comm/fd_exchange.pyevaluated only on Python 3.12+, andflashinfer.commimports that module at import time, so the package failed to import on interpreters
inside the supported range. Downstream packages that touch
flashinfer.commduringtheir own initialization were affected as well.
Upgrade to this release if you run FlashInfer on Python 3.10 or 3.11.
Full Changelog: flashinfer-ai/flashinfer@v0.6.16.post3...v0.6.16.post4
v0.6.16.post3Compare Source
What's Changed
Full Changelog: flashinfer-ai/flashinfer@v0.6.16.post2...v0.6.16.post3
v0.6.16.post2Compare Source
FlashInfer 0.6.16.post2 includes the tvm-ffi v0.1.13-post2 hotfix regarding its ABI compatibility. We recommend upgrading to this latest version.
Full Changelog: flashinfer-ai/flashinfer@v0.6.16.post1...v0.6.16.post2
v0.6.16.post1Compare Source
Full Changelog: flashinfer-ai/flashinfer@v0.6.16...v0.6.16.post1
v0.6.16Compare Source
These highlights are also published at flashinfer.ai/releases.
v0.6.16 Highlights
This release delivers the MegaMoE kernels promised for expert parallelism in 0.6.15 and extends Blackwell model coverage — MiniMax-M3 sparse attention on Blackwell RTX and DGX Spark, and a unified MoE API that now executes per-tensor FP8, block-scale FP8, and B12x NVFP4/W4A16 — plus distributed serving under Confidential Computing with multicast-free all-reduce fusion. Under the hood, an on-disk JIT cache for CuTe-DSL kernels cuts cold-start compilation and shrinks the install.
We recommend upgrading to the latest 0.6.16 post-release.
MegaMoE kernels land in expert parallelism (
moe_ep)The
MoEEpLayernow unifies the split and mega execution paths under one entry point and adds three mega backends —deep_gemm_mega(FP8/FP4),nvfp4_cutedsl, andmxfp8_cutedsl— each fusing expert-parallel communication with the local MoE in a single symmetric-memory kernel (Blackwell SM100+, NVSHMEM). In a microbenchmark, on a GB200 node (EP=4, DeepSeek-V3-like geometry) the tuned CuTeDSL NVFP4 backend with in-register FP4 combine reaches up to 1.89× the throughput ofdeep_gemm_megaat 8192 tokens/rank. NIXL-EP transport gaps and combine deadlocks blocking the vLLM Fleet/Handle adapters are also closed.MiniMax Sparse Attention (MSA) on Blackwell RTX and DGX Spark
MiniMax-M3's MSA — a proxy/top-k indexer plus sparse prefill, decode, and combine — now runs on Blackwell RTX and DGX Spark (SM120/121) GPUs. The tensor-core kernels are rebuilt on SM12x warp-level
mma.sync, top-k and combine are rewritten in CuTe-DSL, and an optional NVFP4 indexer is available, with prefill/decode accepting FP8 or NVFP4 KV (paged or flat). New APIs live underflashinfer.msa_ops.XQA decode adds sliding-window, attention sinks, and ragged Q for speculative decode
The XQA decode kernel — used on Blackwell RTX and DGX Spark (SM120/121) for models with attention sinks — expands coverage for sliding-window attention and ragged Q, across causal and non-causal draft-block mask modes and combinations of them. Ragged Q lets each request in a batch verify a different number of draft tokens, and sliding-window masking is now computed per draft-token row, making the kernel useful for speculative-decoding workloads across models on SM120/121.
Unified MoE API reaches parity with the legacy FP8 and NVFP4 paths
The unified
MoELayerAPI continues to expand quantization formats to reach parity with legacy flat APIs: TRTLLM per-tensor FP8 (SM100/SM103, with Llama4 routing-scale-on-input), DeepSeek FP8 and MXFP8 block-scale (SM100/SM103), and SM120/SM121 B12x NVFP4 and W4A16 backends. In-kernel routing (FromLogits) is now wired through the unified API and fuzzer, so precomputed and in-kernel routing share one path with CUDA-graph and autotuning coverage.Confidential Computing: multicast-free all-reduce fusion and FP8 AllReduce
The TRT-LLM AllReduce-fusion workspace now allocates a multicast-free IPC workspace when NVIDIA Confidential Computing is detected (
is_confidential_compute(), overridable viaFLASHINFER_CONFIDENTIAL_COMPUTE), so one-shot Lamport and two-shot sync fusion run under CC wherecuMulticastsetup otherwise fails. Separately, a newflashinfer.comm.quantized_all_reduce()halves AllReduce transfer volume by quantizing activations to FP8 before P2P transfer over symmetric memory (SM90+, NVSwitch).Faster JIT cold-start and smaller install
CuTe-DSL kernels now persist to an on-disk cache (
JitSpecgains aJitSpecCuteDslbackend) and reload via JITLink in about 3–30 ms instead of recompiling in every new process;mm_fp4autotuning additionally compiles tactics in parallel and reuses the shared disk cache, cutting autotune wall time. Pruning architecture gencode that dispatch can never load removes roughly 1.6 GB of installed size from the CUDA-13 aarch64 JIT-cache wheel.What's Changed
set_autotune_process_groupto synchronize tactic choice across ranks by @thanhhao98 in #3187topk_weights(copy-free) by @jdebache in #37636517769) by @kahyunnam in #4189New Contributors
Full Changelog: flashinfer-ai/flashinfer@v0.6.15rc4...v0.6.16
v0.6.15.post1Compare Source
Full Changelog: <h
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