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7c3abf6
[Common] More CuTeDSL MXFP8 special kernels
kainzhong Oct 7, 2026
6e854d5
Merge branch 'main' into more_cutedsl_mxfp8_specialized
kainzhong Oct 7, 2026
1be6447
wip
kainzhong Oct 8, 2026
1995fea
wip
kainzhong Oct 8, 2026
3e7a653
refactor
kainzhong Oct 9, 2026
79c5d53
refactor
kainzhong Oct 9, 2026
c51a3b8
refactor
kainzhong Oct 9, 2026
f14e433
[pre-commit.ci] auto fixes from pre-commit.com hooks
pre-commit-ci[bot] Oct 9, 2026
5f9ece2
fix
kainzhong Oct 9, 2026
870b23c
disable invariant temporarily
kainzhong Oct 9, 2026
4ef3404
fix
kainzhong Oct 10, 2026
ef9877d
refactor
kainzhong Oct 12, 2026
d6bb258
[pre-commit.ci] auto fixes from pre-commit.com hooks
pre-commit-ci[bot] Oct 12, 2026
fffc874
fix
kainzhong Oct 12, 2026
2fd0aca
fix
kainzhong Oct 12, 2026
8afd230
also support swizzled scale for g2r bidim
kainzhong Oct 12, 2026
87ab24e
lint
kainzhong Oct 12, 2026
cae94f5
add tests
kainzhong Oct 12, 2026
f67b1e5
fix
kainzhong Oct 12, 2026
177647e
nit
kainzhong Oct 12, 2026
8f4c54d
refactor
kainzhong Oct 13, 2026
fddd076
refactor
kainzhong Oct 14, 2026
3a8a882
more refactor
kainzhong Oct 14, 2026
30c92ab
g2r bidim can also support colwise only
kainzhong Oct 14, 2026
5c3465a
make g2r support activations
kainzhong Oct 15, 2026
b1db277
fix
kainzhong Oct 15, 2026
dcd8b08
fix
kainzhong Oct 15, 2026
86233c8
+0 and -0 should both legal
kainzhong Oct 15, 2026
dba8dbf
nit
kainzhong Oct 15, 2026
287505f
fix
kainzhong Oct 17, 2026
2c6f6ec
fix
kainzhong Oct 20, 2026
53bc647
close fp32 perf gap
kainzhong Oct 21, 2026
bfdb240
can always use static tile num
kainzhong Oct 21, 2026
c5662d2
Read BF16 GeLU, SiLU and their derivatives from lookup tables in MXFP…
tdophung Oct 13, 2026
02d2d10
Add an experimental exact dSiLU activation table
tdophung Oct 13, 2026
59d831c
[Common] Add a register-tiled MXFP8 activation kernel that reads the …
tdophung Oct 14, 2026
e3181ab
[Common] Build the activation tables in TE common on first use
tdophung Oct 14, 2026
cb0b9a7
[Common] Make the activation tables opt-in and compute them in the ge…
tdophung Oct 15, 2026
bc2afc0
[Common] Extend the register-tiled MXFP8 activation kernel to row and…
tdophung Oct 15, 2026
473771d
[Common] Use the register-tiled MXFP8 kernel without activation tables
tdophung Oct 16, 2026
3ea31c0
[Common] Fuse dbias into the register-tiled MXFP8 activation kernel
tdophung Oct 15, 2026
ae11aff
[Common] Support amax, noop and E5M2 output in the register-tiled MXF…
tdophung Oct 16, 2026
41ec7d3
[Common] Take FP16 inputs in the register-tiled MXFP8 kernel for dSiL…
tdophung Oct 16, 2026
41eaeaa
[Common] Speed up the dbias reduction of the MXFP8 quantize
tdophung Oct 16, 2026
124ce8a
[Common] Add a register-tiled MXFP8 kernel for SwiGLU and its gradient
tdophung Oct 16, 2026
04fd4fe
[Common] Take FP32 inputs in the register-tiled MXFP8 activation kernel
tdophung Oct 16, 2026
03a7e78
[Common] Compute both dSwiGLU gradient halves in one pass in the regi…
tdophung Oct 16, 2026
008b345
[Common] Support E5M2 output in the register-tiled SwiGLU kernel
tdophung Oct 16, 2026
a03e83b
[Common] Build the activation tables with fast math in fast-math builds
tdophung Oct 16, 2026
c10bd97
Drop NVTE_MXFP8_REGTILE and the regtile-vs-generic tests
tdophung Oct 26, 2026
142b403
Template the activation tables on the input type
tdophung Oct 26, 2026
cf172ea
[Common] Read the activation tables in the CuTeDSL MXFP8 kernels
tdophung Oct 27, 2026
8f58ccf
[Common] Fuse dbias into the register-resident CuTeDSL MXFP8 kernel
tdophung Oct 27, 2026
849eb50
[Common] Reduce amax in the register-resident CuTeDSL MXFP8 kernel
tdophung Oct 27, 2026
71f42ab
[Common] Take any row count in the register-resident CuTeDSL MXFP8 ke…
tdophung Oct 27, 2026
b17bd8c
[Common] Use 256-column tiles for derivatives in the CuTeDSL register…
tdophung Oct 27, 2026
3a3fe44
[Common] Take column tails in the register-resident CuTeDSL MXFP8 kernel
tdophung Oct 27, 2026
a287452
[Common] Take FP16 and FP32 inputs in the CuTeDSL register-resident M…
tdophung Oct 27, 2026
944fbe7
[Common] Match the CUDA kernels in CuTeDSL SiLU, dbias order and NaN-…
tdophung Oct 28, 2026
e17f61e
[Common] Drop the CUDA register-tiled activation kernel; keep the gat…
tdophung Oct 28, 2026
e7a36da
[pre-commit.ci] auto fixes from pre-commit.com hooks
pre-commit-ci[bot] Oct 28, 2026
6d7e361
[Common] Add CuTeDSL gated MXFP8 kernels, including a register-reside…
tdophung Nov 3, 2026
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14 changes: 13 additions & 1 deletion docs/envvars.rst
Original file line number Diff line number Diff line change
Expand Up @@ -150,7 +150,7 @@ General
:Type: ``int`` (0 or 1)
:Default: ``0``
:Description: Use CuTeDSL kernel implementations when available. This requires that Transformer Engine was built with ``NVTE_WITH_CUTEDSL=1``.
It also requires ``apache-tvm-ffi``, ``nvidia-cutlass-dsl`` to be installed and you are using CPython 3.10 or later.
It also requires ``apache-tvm-ffi`` and ``nvidia-cutlass-dsl>=4.8.0`` to be installed and you are using CPython 3.10 or later.
If these requirements are not met, Transformer Engine will fall back to using CUDA C++ kernels if possible.

.. envvar:: NVTE_WARN_IF_CUTEDSL_BACKEND_NOT_CHOSEN
Expand Down Expand Up @@ -342,6 +342,18 @@ Kernel Configuration
:Default: ``0``
:Description: Disable NVRTC (CUDA Runtime Compilation) support. When set to ``1``, runtime kernel compilation is disabled. Existing transpose operations select their static fallback automatically. NVFP4 4over6 quantization, fused softmax, and normalization paths require their corresponding ``NVTE_BUILD_LEGACY_STATIC_NVFP4``, ``NVTE_BUILD_LEGACY_STATIC_FUSED_SOFTMAX``, or ``NVTE_BUILD_LEGACY_STATIC_NORM`` CMake option to have been enabled when the library was built; otherwise no static fallback is available.

.. envvar:: NVTE_ACTIVATION_TABLE

:Type: ``int`` (0 or 1)
:Default: ``0``
:Description: Experimental. When set to ``1``, read GeLU, SiLU and their derivatives from lookup tables when BF16 inputs are quantized to MXFP8. Each table is built on its first use and kept, once per device and process (under 64 KB per device in total), outside the framework's memory allocator. Results match the computed activations, except that GeLU and SiLU of ``-inf`` give ``-0`` instead of NaN, and derivatives of inputs with ``|x| < 2^-12`` (GeLU) or ``|x| < 2^-9`` (SiLU) are within 1 ulp (GeLU) or 2 ulp (SiLU) of the computed ones. When set to ``0``, the activations are computed. Read on every call.

.. envvar:: NVTE_ACTIVATION_TABLE_EXACT_DSILU

:Type: ``int`` (0 or 1)
:Default: ``0``
:Description: Experimental. Choose the SiLU-derivative lookup table (see :envvar:`NVTE_ACTIVATION_TABLE`). By default the 16 KB table covers ``|x| >= 2^-9`` and smaller inputs use the linear term ``0.5 + x/2``, which is within 2 ulp of the computed derivative. When set to ``1``, a 32 KB table covers ``|x| >= 2^-25``, and the derivative matches the computed one for every input. Read once per process, when the table is built.

.. envvar:: NVTE_USE_CUTLASS_GROUPED_GEMM

:Type: ``int`` (0 or 1)
Expand Down
1 change: 1 addition & 0 deletions tests/cpp/operator/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,7 @@ add_executable(test_operator
test_cast_mxfp8_gated_swiglu.cu
test_qdq.cu
test_cast_mxfp8.cu
test_cast_mxfp8_act_exact.cu
test_cast_mxfp8_grouped.cu
test_cast_mxfp8_grouped_scaled_swiglu.cu
test_cast_nvfp4_transpose.cu
Expand Down
3 changes: 3 additions & 0 deletions tests/cpp/operator/test_cast_mxfp8.cu
Original file line number Diff line number Diff line change
Expand Up @@ -699,6 +699,9 @@ std::vector<std::vector<size_t>> matrix_sizes = {
{1, 16},
{16, 48},
{128, 128},
// This case will cover cast_rowwise's last row being partial case, in which
// the kernel will reshape the input tensor with last dim being 1024 so the last row
// is not a full row due to 993*512 % 1024 != 0
{993, 512},
{1024},
{8, 32, 1024},
Expand Down
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