[libcpu][bsp] Fix RISC-V SMP ticket spinlock stalls and enable 8 CPUs on SpacemiT K1

bsp/README.md

@@ -809,6 +809,12 @@ This document is based on the RT-Thread mainline repository and categorizes the
 | [ch569w-evt](wch/risc-v/ch569w-evt) | ✅ | ✅ | - | - | - | - | - | ✅ | - | ✅ | - | - | - | - | - |
 | [yd-ch32v307vct6](wch/risc-v/yd-ch32v307vct6) | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - |
 
+#### 🟢 Spacemit
+
+| BSP Name | GPIO | UART | ADC | I2C | SPI | WDT | HWTimer | PWM | RTC | SDIO | CAN | PCI | DMA | Ethernet | Audio | Display | Crypto |
+|----------|------|------|-----|-----|-----|-----|---------|-----|-----|------|-----|-----|-----|----------|-------|---------|--------|
+| [k1](spacemit/k1) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
+
 #### 🟡 Ultrarisc (RT-Smart) (SMP)
 | BSP Name | GPIO | UART | ADC | I2C | SPI | WDT |
 |----------|------|------|-----|-----|-----|-----|

bsp/spacemit/k1/.config

@@ -112,7 +112,7 @@ CONFIG_RT_NAME_MAX=24
 # CONFIG_RT_USING_SMART is not set
 # CONFIG_RT_USING_AMP is not set
 CONFIG_RT_USING_SMP=y
-CONFIG_RT_CPUS_NR=4
+CONFIG_RT_CPUS_NR=8
 CONFIG_RT_ALIGN_SIZE=8
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
 CONFIG_RT_THREAD_PRIORITY_32=y

bsp/spacemit/k1/README.md

@@ -8,7 +8,7 @@ SpacemiT K1（进迭时空 K1）是一款 64 位 RISC-V SoC，集成 8 个 X60 C
 支持浮点和向量扩展，并提供 SD/eMMC、PCIe、以太网、显示及音频等外设接口。
 
 本 BSP 基于 RT-Thread 标准版和设备模型，通过 Device Tree 描述板级硬件，
-由 U-Boot/OpenSBI 引导，在 S-mode 下运行。默认启用 MMU 和 4 核 SMP，
+由 U-Boot/OpenSBI 引导，在 S-mode 下运行。默认启用 MMU 和 8 核 SMP，
 支持存储、网络、多媒体及电源管理等功能。
 
 验证平台为 **Banana Pi BPI-F3 SBC**。早期控制台使用 SBI，正常控制台为
@@ -18,11 +18,11 @@ UART0，串口参数为 115200 8N1。下文启动命令仅适用于该板原厂
 
 | 功能 | 状态 | 说明 |
 | --- | --- | --- |
-| MMU / SMP | 支持 | 默认启用 4 个 CPU 核心 |
+| MMU / SMP | 支持 | 默认启用 8 个 CPU 核心 |
 | UART / early console | 支持 | UART0、SBI 早期输出 |
 | Clock / reset / power domain | 支持 | 时钟、复位及电源域控制 |
 | GPIO / pinctrl / I2C / PWM | 支持 | 引脚配置及基础外设 |
-| SPI / QSPI | 已移植，验证中 | SPI NOR 读 ID 问题排查中 |
+| SPI / QSPI | 支持 | SPI NOR |
 | SD / eMMC | 支持 | SDHCI、eMMC HS400 |
 | RTC / ADC / 电源键 | 支持 | SpacemiT PMIC 子设备 |
 | PCIe / NVMe | 支持 | PCIe host、NVMe 块设备 |

bsp/spacemit/k1/README_en.md

@@ -10,7 +10,7 @@ display, and audio.
 
 This BSP uses the RT-Thread standard edition and device model, with board
 hardware described by a Device Tree. U-Boot/OpenSBI boots RT-Thread in S-mode.
-The default configuration enables the MMU and four-core SMP, with support for
+The default configuration enables the MMU and eight-core SMP, with support for
 storage, networking, multimedia, and power management.
 
 The validation platform is the **Banana Pi BPI-F3 SBC**. SBI provides early
@@ -21,11 +21,11 @@ only to this board's vendor firmware environment.
 
 | Feature | Status | Notes |
 | --- | --- | --- |
-| MMU / SMP | Supported | Four CPU cores enabled by default |
+| MMU / SMP | Supported | Eight CPU cores enabled by default |
 | UART / early console | Supported | UART0 and SBI early output |
 | Clock / reset / power domain | Supported | Clock, reset, and power domain control |
 | GPIO / pinctrl / I2C / PWM | Supported | Pin configuration and basic peripherals |
-| SPI / QSPI | Ported, validation in progress | SPI NOR ID read issue under investigation |
+| SPI / QSPI | Supported | SPI NOR |
 | SD / eMMC | Supported | SDHCI and eMMC HS400 |
 | RTC / ADC / power key | Supported | SpacemiT PMIC child devices |
 | PCIe / NVMe | Supported | PCIe host and NVMe block devices |

bsp/spacemit/k1/rtconfig.h

@@ -63,7 +63,7 @@
 /* end of klibc options */
 #define RT_NAME_MAX 24
 #define RT_USING_SMP
-#define RT_CPUS_NR 4
+#define RT_CPUS_NR 8
 #define RT_ALIGN_SIZE 8
 #define RT_THREAD_PRIORITY_32
 #define RT_THREAD_PRIORITY_MAX 32

libcpu/risc-v/common/cpuport.c

@@ -70,22 +70,18 @@ void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
 
 void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
 {
-    unsigned long tmp, new_val, mask;
+    unsigned long tmp;
     unsigned short ticket;
 
+    /*
+     * The two 16-bit counters occupy the low word, also on RV64.
+     * Use an AMO so ticket allocation cannot livelock with an unlock
+     * retrying LR/SC on the same reservation. Word width wraps next at 16 bits.
+     */
     __asm__ volatile (
-            "1:\n\t"
-            "   lr." REG_WIDTH ".aq %0, (%3)\n\t"
-            "   srli    %1, %0, 16\n\t"
-            "   addi    %1, %1, 1\n\t"
-            "   slli    %1, %1, 16\n\t"
-            "   li      %2, 0xffff\n\t"
-            "   and     %2, %0, %2\n\t"
-            "   or      %1, %1, %2\n\t"
-            "   sc." REG_WIDTH ".rl %1, %1, (%3)\n\t"
-            "   bnez    %1, 1b"
-            : "=&r" (tmp), "=&r" (new_val), "=&r" (mask)
-            : "r" (&lock->slock)
+            "amoadd.w.aqrl %0, %2, (%1)"
+            : "=&r" (tmp)
+            : "r" (&lock->slock), "r" (1UL << 16)
             : "memory");
 
     ticket = (tmp >> 16) & 0xffff;
@@ -94,26 +90,20 @@ void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
     {
         __asm__ volatile (OPC_PAUSE_I);
     }
+
+    /* Order critical-section accesses after observing the owner's release. */
+    rt_hw_barrier();
 }
 
 void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
 {
-    unsigned long tmp, new_val, mask;
-
-    __asm__ volatile (
-            "1:\n\t"
-            "   lr." REG_WIDTH ".aq %0, (%3)\n\t"
-            "   addi    %1, %0, 1\n\t"
-            "   li      %2, 0xffff\n\t"
-            "   and     %1, %1, %2\n\t"
-            "   slli    %2, %2, 16\n\t"
-            "   and     %0, %0, %2\n\t"
-            "   or      %1, %0, %1\n\t"
-            "   sc." REG_WIDTH ".rl %1, %1, (%3)\n\t"
-            "   bnez    %1, 1b"
-            : "=&r" (tmp), "=&r" (new_val), "=&r" (mask)
-            : "r" (&lock->slock)
-            : "memory");
+    /*
+     * Only the holder writes owner. Publish critical-section accesses before
+     * advancing it; a halfword store preserves concurrently allocated tickets.
+     */
+    rt_hw_barrier();
+    HWREG16(&lock->tickets.owner) =
+            (unsigned short)(HWREG16(&lock->tickets.owner) + 1);
 
     rt_hw_barrier();
 }