Fix sky130 LitePCI clock period parsing

CLAUDE.md

@@ -156,7 +156,7 @@ Designs in this repo carry workarounds for upstream tool bugs. Update this table
 | **PSM-0069 power/ground net not reaching boundary row** — `Grid::makeVias` silently drops via candidates connecting a power/ground stripe to the boundary cell row when signal IO pins on an intermediate layer have their spacing-expanded obstruction overlapping that row's via area; the stripe terminates short of the boundary row, leaving all its cells with disconnected power/ground. No PDN-0110 fires for obstruction removal (PDN-0110 is for via geometry failures only); manifests as a PSM-0039 flood on boundary-row instances and PSM-0069 at `_final`. | sky130hd `floonoc` | Reduce `edge_margin` in `io.tcl` until the IO-pin obstruction clears the boundary-row via area; threshold: `edge_margin < core_yMin − row_height/2 − met_spacing`. See DECISIONS.md for platform-specific values. | `bbc7fd0` | None filed upstream |
 | ~~**CTS-0122** false skip~~ **RESOLVED 2026-06** — `dbNet::getFirstOutput()` skipped the driver of clock nets sourced by a `clock: true` macro output. Fixed upstream ([#10549], `cd4f5041`); the OpenROAD `299f3015` pin is past it, so the local `patches/openroad-cts-0122-fix.patch` was **dropped**. litepci-asap7 went from WNS −883 ps (broken clock tree) to +944 ps. | sky130hd/nangate45/asap7 `litepci` | (removed — fix in pin) | (this PR) | [OpenROAD#10549](https://github.com/The-OpenROAD-Project/OpenROAD/pull/10549) (merged `cd4f5041`) |
 | **New-resizer post-GRT `repair_timing` non-convergence on structurally-unfixable reg2reg** (OpenROAD b65c274c) — when the worst reg2reg path is structural and unrepairable (a macro-placement-bound path, or a LiteX forwarded-clock io-feedthrough), the post-GRT `repair_timing` never terminates: it keeps buffering while TNS decays asymptotically, and per-iteration incremental STA time grows past an hour, so the stage runs for many hours with no closure. Distinct from the older RTL-bounded `repair_timing` non-convergence row above — this one is the *new resizer* chewing on a path it cannot fix. | asap7 `cnn` (macro-bound, Fmax−49 %); asap7/nangate45 `litepci` (forwarded-clock WNS≈−898 ps) | `SKIP_INCREMENTAL_REPAIR = 1` — GRT then finishes in minutes and the design reaches `_final`. (litepci-asap7's BUILD.bazel had *described* this skip in a comment but never actually set the arg — now set.) The unfixable path remains (documented per-design), but the design finishes instead of spinning. | (this PR) | None filed yet |
-| **SDC clock-period sed poisoning** — ORFS derives the ABC target clock period from the SDC with a naive sed (`variables.mk`: `s/^set\s+clk_period\s+(\S+)\|.*-period\s+(\S+)/…/`) that takes the **first** `-period <n>` or `set clk_period <n>` token in the file. A quoted example in a *comment* above the real clock line (e.g. a backtick-wrapped `` `-period 10000` ``) is captured verbatim — the trailing backtick then makes `echo <val> > clock_period.txt` an unterminated shell command-substitution → **make Error 2**, killing synth before floorplan. | nangate45 `litepci` (comment quoted a backtick `-period` example) | Keep any hyphen-period token and any backtick out of SDC comments that precede the real `set clk_period` line; put the real assignment first. Reworded `constraint.sdc`. | (this PR) | None (ORFS parsing fragility) |
+| **SDC clock-period sed poisoning** — ORFS derives the ABC target clock period from the SDC with a naive sed (`variables.mk`: `s/^set\s+clk_period\s+(\S+)\|.*-period\s+(\S+)/…/`) that takes the **first** `-period <n>` or `set clk_period <n>` token in the file. A quoted example in a *comment* above the real clock line can be captured verbatim; a trailing backtick then makes `echo <val> > clock_period.txt` an unterminated shell command-substitution → **make Error 2**, killing synth before floorplan. | nangate45 / sky130hd `litepci` | Put the real `set clk_period` assignment before historical syntax, and keep the parser's conflicting token out of preceding comments. The nangate45 note was already reworded; sky130hd now puts the assignment first and rewords its note. | nangate45: existing; sky130hd: this PR | [HighTide#238](https://github.com/VLSIDA/HighTide/issues/238) |
 | **Stale yosys-slang `slang-elab` tarball checksum** — GitHub regenerated the archive tarball for the OpenROAD-vendored yosys-slang submodule (commit `82effc8d`), changing its gzip and thus its sha256 (`d319a1f…` → `ea31b4a…`; same source content, verified byte-identical after extraction). The stale pin in the `openroad` `archive_override` `patch_cmds` breaks **every fresh bazel fetch** (k8s pods, fresh output_bases) at repo-mapping time; only output_bases that cached the old tarball keep building. | any fresh build (all designs, on k8s / new output_base) | Update the sha256 in `MODULE.bazel` (the mirrored `patch_cmds` for `openroad`) to the current value. If GitHub flips it again, re-fetch and re-pin. | (this PR) | GitHub archive-tarball checksum instability |
 
 ### Useful ORFS env vars for these workarounds

designs/sky130hd/litepci/constraint.sdc

@@ -6,15 +6,17 @@ current_design litepcie_core
 # `set_output_delay` timing the CTS buffer tree as data.
 
 set clk_name      sys_clk
-# 20 ns / 50 MHz — sky130hd baseline.  Real critical path is FakeRAM
-# clk-to-Q + DMA datapath.
-# NOTE: previously `set clk_period 20000` and refclk `-period 10000` — those
-# were ps-magnitude values in an ns-unit file (1000x unit error). Corrected to
-# 20 ns (sys_clk) / 10 ns (100 MHz PCIe refclk). This design still does not
-# route on the new GRT (issue #204), independent of the clock.
 set clk_period    20
 set clk_io_pct    0.2
 
+# 20 ns / 50 MHz — sky130hd baseline.  Real critical path is FakeRAM
+# clk-to-Q + DMA datapath.
+# Earlier 20000 ps and 10000 ps values were used for the user and reference
+# clocks. Those values were written in picoseconds in this nanosecond-unit file.
+# The user clock is now 20 ns and the 100 MHz PCIe reference clock is 10 ns.
+# This design still does not route on the new GRT (issue #204), independent of
+# the clock.
+
 create_clock -name $clk_name -period $clk_period [get_pins pcie_us/user_clk]
 create_clock -name pcie_refclk -period 10 [get_ports pcie_clk_p]
 set_clock_groups -asynchronous \

designs/src/litepci/DECISIONS.md

@@ -288,6 +288,16 @@ Two new-tools issues surfaced (both k8s-verified fixes):
 **sky130hd**: still **flagged — does not route** (GRT congestion, unchanged from the 553c1c3
 section above; its stage ODBs also bust the Cloudflare cache cap). asap7 + nangate45 pass.
 
+### 2026-09: sky130hd clock-period parser regression
+
+The sky130hd SDC placed a historical reference-clock example before the real 20 ns
+clock-period assignment. The extraction expression in the pinned ORFS revision therefore
+returned `10000` with a trailing backtick instead of `20`, stopping the synthesis rule
+while generating `clock_period.txt` ([HighTide#238](https://github.com/VLSIDA/HighTide/issues/238)).
+The real assignment now precedes the historical note, and the note no longer contains the
+parser's conflicting token. This restores synthesis startup only; the later sky130hd GRT
+congestion tracked in [HighTide#204](https://github.com/VLSIDA/HighTide/issues/204) is unchanged.
+
 ## Bug workarounds in the real-FakeRAM build
 
 | Knob | Reason |