ECE undergrad at BITS Pilani Goa (2028), working at the intersection of robotics, computer vision and hardware acceleration.
Currently building a monocular Visual SLAM pipeline with loop closure and pose graph optimization, evaluated on KITTI and a 2D systolic array accelerator in Verilog for dense matrix workloads.
Interests: SLAM, ML accelerators, embedded CV, RTL design.
RTL implementation of an 8×8 2D systolic array in Verilog for dense matrix multiplication workloads. Synthesized on FPGA with timing and area reports.
Designed and implemented a 5-stage pipelined RV32I RISC-V processor in Verilog with hazard detection, forwarding, and branch handling. Verified functionality using comprehensive testbenches and FPGA deployment, demonstrating a complete end-to-end processor implementation.
Monocular visual SLAM system with ORB feature tracking, bundle adjustment, loop closure detection, and pose graph optimization. Evaluated on KITTI sequence 00. Implements map save/load and relocalization.
Multi-threaded perception pipeline on Jetson AGX Orin integrating YOLOv3 (object detection), DeepFace (facial recognition), and ResNet SSD (person detection). Achieved ~76% reduction in end-to-end inference latency through parallel execution.
