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d-ragul/README.md

Ragul D

M.Tech Student in VLSI and Embedded Systems Engineering

Focused on ASIC design flow,system verilog coding, digital system design, ARM Cortex-M architecture, and hardware-oriented system engineering.


Current Focus

  • FreeRTOS and Embedded Runtime Systems
  • RTL Design and Digital System Verification
  • ARM Cortex-M Bare-Metal Firmware
  • STM32 Peripheral Driver Development
  • Virtual Platform Simulation using Renode
  • OpenTitan Architecture Exploration

Technical Skills

Programming Languages

  • C
  • C++
  • Python
  • Verilog HDL
  • system verilog

Embedded Systems

  • STM32
  • UART
  • SPI
  • I²C
  • GPIO
  • DMA
  • Bare-Metal Firmware
  • Embedded System Debugging

VLSI and Digital Design

  • ASIC design flow
  • RTL Design
  • FPGA Design
  • Digital System Design
  • UART/PWM/ALU/RAM Design
  • Simulation and Verification

Tools and Platforms

  • Renode
  • STM32CubeIDE
  • Icarus Verilog
  • Yosys
  • GTKWave
  • Altium Designer
  • LTspice
  • MATLAB
  • VS Code
  • Git
  • Ubuntu Linux

Featured Projects

Virtual Smart Embedded Monitoring System

Bare-metal ARM Cortex-M4 firmware simulation using Renode with UART runtime monitoring, GPIO register-level control, virtual sensor simulation, and state-machine based fault handling.

STM32 UART DAC Waveform Analyzer

PC-based arbitrary waveform generator using STM32 DAC, UART communication, DMA, and Python GUI with RMS and THD analysis.

Digital Design using Verilog HDL

Implemented and verified digital modules including UART transmitter, PWM generator, RAM, VGA controller, LED matrix controller, and ALU using HDL simulation workflows.

Implemented an Asic uart transmitter complete ASIC design flow

Implemented an 8-bit UART (Universal Asynchronous Receiver Transmitter) Transmitter in Verilog HDL and demonstrates a complete RTL-to-GDSII ASIC design flow using the Sky130 technology node and OpenLane.

The design was verified through simulation, synthesized using Yosys, physically implemented using OpenLane, and successfully generated a final GDSII layout.

CUDA-Based Image Processing

Implemented GPU-accelerated image filtering and parallel processing workflows for real-time embedded vision and hardware-oriented computing applications.


Open Source Contribution

OpenTitan

Contributor to the OpenTitan open-source silicon Root-of-Trust project with exposure to large-scale hardware-oriented development workflows and collaborative engineering practices.


Engineering Interests

  • Embedded Firmware Engineering
  • ARM Cortex-M Architecture
  • RTOS-Based Systems
  • Digital IC Design
  • Hardware-Software Co-Design
  • Virtual Hardware Platforms
  • Embedded Linux
  • System-Level Engineering

Education

M.Tech — VLSI and Embedded Systems Engineering
MACE Kothamangalam

B.Tech — Electrical and Electronics Engineering
NSS College of Engineering Palakkad

Pinned Loading

  1. renode-virtual-embedded-monitoring-system renode-virtual-embedded-monitoring-system Public

    Bare-metal ARM Cortex-M4 firmware simulation using Renode with UART runtime monitoring, GPIO control, state-machine based fault handling, and virtual sensor simulation.

    C

  2. stm32-uart-dac-waveform-analyzer stm32-uart-dac-waveform-analyzer Public

    UART-controlled waveform generation and real-time RMS & THD analysis using STM32 DAC, DMA, and Python GUI

    C 1 1

  3. STM-32-DRIVER-EXPERIMENTS STM-32-DRIVER-EXPERIMENTS Public

    this repo explains various driver codes of stm32g431cbt6

    C

  4. opentitan opentitan Public

    Forked from lowRISC/opentitan

    OpenTitan: Open source silicon root of trust

    SystemVerilog 1

  5. tt-uart-transmitter-asic tt-uart-transmitter-asic Public

    Verilog 1

  6. uart-firmware-log-analyser uart-firmware-log-analyser Public

    Built a live UART log monitoring dashboard using Python and Streamlit for firmware log parsing, real-time diagnostics, error detection, and visualization.

    Python