Refactor: derive tmr scheduler thread/core dims from platform_config - #1735
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📝 WalkthroughWalkthroughThe scheduler runtime now derives worker capacity, core-layout calculations, validation, and dummy-drain thread eligibility from platform configuration constants in both the a2a3 and a5 trees. ChangesScheduler dimension alignment
Estimated code review effort: 2 (Simple) | ~10 minutes Possibly related PRs
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Inline comments:
In
`@src/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_cold_path.cpp`:
- Line 903: Make semantic cluster-width handling consistent with
PLATFORM_CORES_PER_BLOCKDIM in assign_own_clusters() and
assign_cores_to_threads() across both files:
src/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_cold_path.cpp
at lines 903, 803, and 1154-1158, and
src/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_cold_path.cpp
at lines 900, 800, and 1135-1139. Replace remaining c * 3, sub < 3, N/3, and
multiple-of-3 logic and diagnostics with the platform-derived width, or isolate
any intentional fixed bitmask offsets behind a named constant with an explicit
invariant; keep AIC-count division and downstream traversal aligned.
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📒 Files selected for processing (10)
src/a2a3/runtime/tensormap_and_ringbuffer/runtime/runtime.hsrc/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_cold_path.cppsrc/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_context.hsrc/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cppsrc/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_types.hsrc/a5/runtime/tensormap_and_ringbuffer/runtime/runtime.hsrc/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_cold_path.cppsrc/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_context.hsrc/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cppsrc/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_types.h
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Fixes hw-native-sys#1734 Three hardware-derived dimensions in the tensormap_and_ringbuffer scheduler were written as bare numeric literals even though platform_config.h already defines the exact named constant they equal. The literals obscured that a2a3 and a5 share one rule, read as divergences when they are not, and would go silently wrong if a platform constant changed. Every value below is identical to the prior literal on both arches, so there is no behavior change. - Dummy-drain gate: `thread_idx < 3` (a2a3) / `thread_idx < 4` (a5) -> `thread_idx < PLATFORM_MAX_AICPU_THREADS - 1` ("every scheduler thread except the last"; MAX is 4 / 5). - RUNTIME_MAX_WORKER: `72` / `108` -> `PLATFORM_MAX_CORES`. Changed in both the authoritative runtime.h define and the scheduler_context.h `#ifndef` fallback: the runtime.h define is unguarded, so leaving it a literal while the fallback expands to the constant is a mismatched macro redefinition that -Werror rejects. - Cores-per-cluster: every semantic cluster-width site -> PLATFORM_CORES_PER_BLOCKDIM (== 3). This covers `core_num()`'s `cluster_count_ * 3`, the `cores_total_num_ / 3` AIC-count divisions, the `% 3 != 0` validity check (its error text now interpolates the constant), the CoreTracker cluster strides (`cli * 3`, `c * 3`, `c * 3 + sub`, `max_clusters_per_thread * 3`) and the per-cluster loop bound (`sub < 3`). The within-cluster core offsets (`+ 1` / `+ 2`) and the fixed 1:2 AIC:AIV ratio (`aic_n + 2 * ci`, sub_block_id 0/0/1/1) stay literal -- they encode the block structure, not the block width. Both trees now read identically at every changed site.
Fixes #1734
Three hardware-derived dimensions in the
tensormap_and_ringbufferscheduler were written as bare numeric literals even thoughplatform_config.halready defines the exact named constant they equal. The literals obscured that a2a3 and a5 share one rule, read as divergences when they are not, and would go silently wrong if a platform constant changed. Landed across both trees in one commit percodestyle.mdrule 10.No behavior change — every derived value equals the current literal on both arches today (
PLATFORM_MAX_AICPU_THREADS= 4/5,PLATFORM_CORES_PER_BLOCKDIM= 3,PLATFORM_MAX_CORES= 72/108).Changes
G — dummy-drain thread gate (
scheduler_dispatch.cpp)thread_idx < 3(a2a3) /thread_idx < 4(a5) →thread_idx < PLATFORM_MAX_AICPU_THREADS - 1— "every scheduler thread except the last".M1 —
RUNTIME_MAX_WORKER(runtime.h+scheduler_context.h)72/108→PLATFORM_MAX_CORES. Both the authoritative unguarded define inruntime.hand the#ifndeffallback inscheduler_context.hare changed: theruntime.hdefine is unguarded, so leaving it a literal while the fallback expands to the constant is a mismatched macro redefinition that-Werrorrejects. (The issue's Location listed onlyscheduler_context.h;runtime.hhad to move with it for the tree to compile.)M2 — cores-per-cluster
3(scheduler_types.h+scheduler_cold_path.cpp)The semantic
cluster_count_ * 3(core_num()), the twocores_total_num_ / 3, and the% 3 != 0validity check →PLATFORM_CORES_PER_BLOCKDIM; the "multiple of 3" error text now interpolates the constant with%d. The self-documentingbit(i*3+k)/core_id_map_[cluster_idx*3+k]bitmask-layout arithmetic is left as-is, per the issue's scope note.Both trees now read identically at every changed site.
Testing
Rebuilt both runtimes (
pip install --no-build-isolation -e .) and ran tmr sim scene tests on both arches:dummy_taskavailable_aicore_countsmixed_example