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FROMLIST: arm64: dts: qcom: Fix PCIe wake GPIO polarity#799

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FROMLIST: arm64: dts: qcom: Fix PCIe wake GPIO polarity#799
ziyuezhang-123 wants to merge 36 commits into
qualcomm-linux:qcom-6.18.yfrom
ziyuezhang-123:for-6.18/arm64-dts-qcom-fix-pcie-wake-gpio-polarity

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Fix PCIe wake GPIO polarity across multiple Qualcomm SoC DTS files.

PCIe WAKE# is an active-low signal per the PCIe specification, but many
DTS files incorrectly specify it as GPIO_ACTIVE_HIGH. This series fixes
the polarity to GPIO_ACTIVE_LOW for all affected platforms, and also
moves PCIe PHY and GPIO definitions to the correct PCIe port nodes.

Platforms fixed: sdx55, msm8996, sdm845, sc8180x, sm8150, sm8250,
sm8350, sm8450, sm8550, sm8650, sm8750, kaanapali, sar2130p, monaco,
lemans, sa8540p, kodiak, talos, msm8998, qcs404, qcs8550, sa8295p,
sa8540p, sc8280xp, sc8280xp, sdm845, sm8150, sm8250, sm8350, sm8450,
sm8550, sm8650, kodiak, msm8996.

Signed-off-by: Krishna Chaitanya Chundru krishna.chundru@oss.qualcomm.com

Link: https://lore.kernel.org/all/5a65ea59-b38d-4cc0-901a-01c239381d91@oss.qualcomm.com/

The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-1-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-2-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-3-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-4-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-5-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-6-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-7-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-8-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-9-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-10-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-11-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-13-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-14-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-15-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-16-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-17-2744251b1181@oss.qualcomm.com/
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Link: https://lore.kernel.org/all/20260611-wake-v2-18-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys from the controller to pcieport0 and
pcieport1. Add the missing pcieport1 label to the pcie1 root port
node to allow board-level overrides. Move perst-gpios/wake-gpios from
the &pcie0/&pcie1 controller overrides to the respective &pcieport0/
&pcieport1 nodes in the board files, renaming perst-gpios to reset-gpios
to match the binding used in the root port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-19-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst GPIO property are per root port
and belong in the root port node (pcie@0), not in the RC controller
node. Move phys, phy-names, and perst-gpios from the controller to
pcie0_port0, adding a label to this node to allow board-level
overrides, and renaming perst-gpios to reset-gpios to match the
binding used in the root port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-20-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst GPIO property are per root port
and belong in the root port node (pcie@0), not in the RC controller
node. Move phys and phy-names from the controller to pcie0_port0,
adding a label to this node to allow board-level overrides. Move
perst-gpios from the &pcie controller override to &pcie0_port0 in
the board file, renaming perst-gpios to reset-gpios to match the
binding used in the root port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-21-2744251b1181@oss.qualcomm.com/
The perst/wake GPIO properties are per root port and belong in the
root port node, not in the RC controller node. Move perst-gpios/
wake-gpios from the &pcie0/&pcie1 controller overrides to the
respective &pcieport0/&pcie1_port0 nodes, renaming perst-gpios to
reset-gpios to match the binding used in the root port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-22-2744251b1181@oss.qualcomm.com/
The perst/wake GPIO properties are per root port and belong in the
root port node, not in the RC controller node. Move perst-gpios/
wake-gpios from the &pcie2a, &pcie3a, &pcie3b, and &pcie4 controller
overrides to the respective &pcie2a_port0, &pcie3a_port0,
&pcie3b_port0, and &pcie4_port0 nodes, renaming perst-gpios to
reset-gpios to match the binding used in the root port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-23-2744251b1181@oss.qualcomm.com/
The perst/wake GPIO properties are per root port and belong in the
root port node, not in the RC controller node. Move perst-gpios/
wake-gpios from the &pcie2a and &pcie3a controller overrides to the
respective &pcie2a_port0 and &pcie3a_port0 nodes, renaming
perst-gpios to reset-gpios to match the binding used in the root
port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-24-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
the existing pcieport0 and newly labeled pcie1_port0, allowing
board-level overrides. Move perst-gpios/wake-gpios from the &pcie0
controller override to &pcieport0 in the board file, renaming
perst-gpios to reset-gpios to match the binding used in the root
port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-25-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
pcie0_port0, pcie1_port0, pcie2_port0, and pcie3_port0, adding
labels to these nodes to allow board-level overrides. Move
perst-gpios/wake-gpios from the controller overrides to the
respective port nodes in the board files, renaming perst-gpios to
reset-gpios to match the binding used in the root port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-26-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
the existing pcie2a_port0, pcie2b_port0, pcie3a_port0, pcie3b_port0,
and pcie4_port0 nodes. Move perst-gpios/wake-gpios from the
controller overrides to the respective port nodes in the board files,
renaming perst-gpios to reset-gpios to match the binding used in the
root port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-27-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
pcie0_port0 and pcie1_port0, adding labels to these nodes to allow
board-level overrides. Move perst-gpios/wake-gpios from the
controller overrides to the respective port nodes in the board files,
renaming perst-gpios to reset-gpios to match the binding used in the
root port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-28-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios
from the controller to pcie0_port0 and pcie1_port0, adding labels to
these nodes to allow board-level overrides, and renaming perst-gpios
to reset-gpios to match the binding used in the root port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-29-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios
from the controller to the existing pcieport0 and newly labeled
pcie1_port0 and pcie2_port0, allowing board-level overrides. Rename
perst-gpios to reset-gpios to match the binding used in the root
port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-30-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
pcie0_port0 and pcie1_port0, adding labels to these nodes to allow
board-level overrides. Move perst-gpios/wake-gpios from the
controller overrides to the respective port nodes in the board file,
renaming perst-gpios to reset-gpios to match the binding used in the
root port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-31-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios
from the controller to the existing pcieport0 and newly labeled
pcie1_port0, allowing board-level overrides. Rename perst-gpios to
reset-gpios to match the binding used in the root port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-32-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
the existing pcieport0 and newly labeled pcie1_port0, allowing
board-level overrides. Move perst-gpios/wake-gpios from the
controller overrides to the respective port nodes in the board files,
renaming perst-gpios to reset-gpios to match the binding used in the
root port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-33-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys from the controller to pcie_port0, and
move perst-gpios/wake-gpios from the &pcie controller overrides to the
&pcie_port0 node in the board files, renaming perst-gpios to reset-gpios
to match the binding used in the root port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-34-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
the existing pcieport0 and pcie1_port0, allowing board-level
overrides. Move perst-gpios/wake-gpios from the controller overrides
to the respective port nodes in the board files, renaming perst-gpios
to reset-gpios to match the binding used in the root port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-35-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are
per-root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys from the controller to pcie0_port and
pcie1_port0, and move perst-gpios/wake-gpios from the &pcie0/&pcie1
controller overrides to the respective &pcie0_port/&pcie1_port0 nodes
in the board files, renaming perst-gpios to reset-gpios to match the
binding used in the root port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-36-2744251b1181@oss.qualcomm.com/
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
pcie0_port0, pcie1_port0, and pcie2_port0, adding labels to these
nodes to allow board-level overrides. Move perst-gpios/wake-gpios
from the controller overrides to the respective port nodes in the
board files, renaming perst-gpios to reset-gpios to match the binding
used in the root port context.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>

Link: https://lore.kernel.org/all/20260611-wake-v2-37-2744251b1181@oss.qualcomm.com/
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Merge Check Failed: No CR Numbers Found

Error: No Change Request numbers were found.

Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests.

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PR #799 — validate-patch

PR: #799

Verdict Issues Detailed Report
0 Full report

Final Summary

  1. Lore link present: Yes — all 36 commits have lore.kernel.org links following pattern 20260611-wake-v2-{N}-2744251b1181@oss.qualcomm.com

  2. Lore link matches PR commits: Cannot verify — lore links are dated June 11, 2026 (future date) and return empty responses. However, the corruption in commits 18-36 means the PR diffs cannot match any valid upstream patches.

  3. Upstream patch status: Cannot determine — lore links inaccessible due to future date (2026-06-11). The FROMLIST prefix indicates patches were posted to mailing list but not yet merged to mainline.

  4. PR present in qcom-next: Not checked — given the severe corruption in commits 18-36, these patches cannot be present in qcom-next in their current form as they would fail to apply and build.

Recommendation:

  • Split this PR into two parts:
    • Part 1: Commits 1-17 (wake GPIO fixes) - appear valid, can be reviewed separately
    • Part 2: Commits 18-36 (phy/GPIO migration) - must be completely regenerated with correct diffs
Verdict: ❌ — click to expand

🔍 Patch Validation

PR: #799 - PCIe wake GPIO fixes and phy/GPIO property migration (36 commits)
Upstream commit: Series at https://lore.kernel.org/all/20260611-wake-v2-{1..37}-2744251b1181@oss.qualcomm.com/
Verdict: ❌ FAIL

Commit Message

Check Status Note
Subject matches upstream ⚠️ Cannot verify - lore links dated June 11, 2026 (future date, not accessible)
Body preserves rationale Commits 1-17: Clear rationale about PCIe WAKE# active-low per spec
Fixes tag present/correct N/A No Fixes tags (new feature/cleanup series)
Authorship preserved Krishna Chaitanya Chundru krishna.chundru@oss.qualcomm.com consistent
Backport note (if applicable) N/A FROMLIST prefix indicates patches posted but not yet merged upstream

Diff Analysis by Commit Range

Commits 1-17: Wake GPIO Polarity Fixes ✅

Commit Platform Status Notes
01 sdx55 Clean diff: GPIO_ACTIVE_HIGH → GPIO_ACTIVE_LOW
02 msm8996 Clean diff: 2 files updated correctly
03 sdm845 Clean diff: db845c updated
04 sc8180x Clean diff: 2 files updated
05 sm8150 Clean diff: dtsi updated
06 sm8250 Clean diff: 3 PCIe controllers updated
07 sm8350 Clean diff: hdk updated
08 sm8450 Clean diff: dtsi updated
09 sm8550 Clean diff: 6 board files updated
10 sm8650 Clean diff: 4 board files updated
11 sm8750 Clean diff: 3 board files updated
12 sar2130p Clean diff: wake GPIO fix
13 monaco Clean diff: idp updated
14 lemans Clean diff: adas updated
15 sa8540p-ride Clean diff: wake GPIO fix
16 kodiak Clean diff: 5 board files updated
17 talos Clean diff: 2 board files updated

Commits 18-36: Move PCIe phy and GPIOs ❌ CORRUPTED

Commit Platform Status Critical Issue
18 lemans CORRUPTED DIFF: SPDX header replaced with &pcieport1 {&pcieport0 {// SPDX-License-Identifier
19 msm8998 CORRUPTED DIFF: SPDX header mangled
20 qcs404 CORRUPTED DIFF: SPDX header replaced with &pcie0_port0 {// SPDX-License-Identifier
21 qcs8550 CORRUPTED DIFF: Multiple files with SPDX corruption
22 sa8295p CORRUPTED DIFF: SPDX header replaced with node labels
23 sa8540p CORRUPTED DIFF: SPDX header mangled
24 sar2130p CORRUPTED DIFF: SPDX header replaced with reset-gpios line
25 sc8180x CORRUPTED DIFF: Multiple files corrupted
26 sc8280xp CORRUPTED DIFF: Extensive SPDX corruption across many files
27 sdm845 CORRUPTED DIFF: SPDX headers destroyed
28 sm8150 CORRUPTED DIFF: SPDX header mangled
29 sm8250 CORRUPTED DIFF: Multiple files corrupted
30 sm8350 CORRUPTED DIFF: SPDX headers replaced
31 sm8450 CORRUPTED DIFF: SPDX corruption
32 sm8550 CORRUPTED DIFF: 6 files with SPDX header corruption
33 talos CORRUPTED DIFF: SPDX headers replaced with node labels
34 sm8650 CORRUPTED DIFF: 5 files corrupted
35 kodiak CORRUPTED DIFF: Multiple files with SPDX destruction
36 msm8996 CORRUPTED DIFF: SPDX headers mangled

Issues

CRITICAL: Corrupted Diffs in Commits 18-36

All commits from 18 onwards contain severely malformed diffs where:

  1. SPDX License Headers Are Destroyed: The first line of files (SPDX license identifier) is being replaced with device tree node references

    Example from commit 32 (arch/arm64/boot/dts/qcom/sm8550-hdk.dts:1):

    -// SPDX-License-Identifier: BSD-3-Clause
    +&pcie1_port0 {	reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;// SPDX-License-Identifier: BSD-3-Clause
  2. Invalid Syntax: The resulting files would have device tree node labels prepended to the SPDX comment, creating invalid C/DTS syntax

  3. Build Breakage: These patches would fail to compile if applied, as the file headers would be malformed

  4. Widespread Impact: 22 instances of this corruption pattern across 19 commits affecting ~40+ device tree files

Root Cause: This appears to be a patch generation or git format-patch error where device tree node labels that should be added as separate hunks are instead being incorrectly merged with the first line of files.

Example of Corruption Pattern:

# What should happen:
+&pcie1_port0 {
+	reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+};

# What actually happened:
-// SPDX-License-Identifier: BSD-3-Clause
+&pcie1_port0 {	reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;// SPDX-License-Identifier: BSD-3-Clause

Verdict

REJECT - Cannot merge due to corrupted diffs

  • Commits 1-17: Clean and appear valid (wake GPIO polarity fixes)
  • Commits 18-36: Severely corrupted and would break the build

Required Action: The patch series must be regenerated. Commits 18-36 need to be completely redone with proper diff generation.

Final Summary

  1. Lore link present: Yes — all 36 commits have lore.kernel.org links following pattern 20260611-wake-v2-{N}-2744251b1181@oss.qualcomm.com

  2. Lore link matches PR commits: Cannot verify — lore links are dated June 11, 2026 (future date) and return empty responses. However, the corruption in commits 18-36 means the PR diffs cannot match any valid upstream patches.

  3. Upstream patch status: Cannot determine — lore links inaccessible due to future date (2026-06-11). The FROMLIST prefix indicates patches were posted to mailing list but not yet merged to mainline.

  4. PR present in qcom-next: Not checked — given the severe corruption in commits 18-36, these patches cannot be present in qcom-next in their current form as they would fail to apply and build.

Recommendation:

  • Split this PR into two parts:
    • Part 1: Commits 1-17 (wake GPIO fixes) - appear valid, can be reviewed separately
    • Part 2: Commits 18-36 (phy/GPIO migration) - must be completely regenerated with correct diffs

@qlijarvis

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PR #799 — checker-log-analyzer

PR: #799
Checker run: https://github.com/qualcomm-linux/kernel-config/actions/runs/28439279796

Checker Result Summary
Checker Result Summary
checkpatch Email mismatch warnings + malformed SPDX headers in multiple commits
dt-binding-check No DT binding changes
dtb-check CRITICAL: Syntax errors in multiple DTS files - malformed patches
sparse-check ⏭️ Skipped (no C code changes)
check-uapi-headers ⏭️ Skipped (no UAPI changes)
check-patch-compliance 13 commits differ from upstream lore links
tag-check N/A Not run (no separate job)
qcom-next-check All commits properly tagged FROMLIST:

Detailed report: Full report

Checker analysis — click to expand

🤖 CI Checker Analysis (checker-log-analyzer)

PR: #799 - PCIe wake GPIO polarity fixes and phy/GPIO reorganization (36 commits)
Source: https://github.com/qualcomm-linux/kernel-config/actions/runs/28439279796

Checker Result Summary
checkpatch Email mismatch warnings + malformed SPDX headers in multiple commits
dt-binding-check No DT binding changes
dtb-check CRITICAL: Syntax errors in multiple DTS files - malformed patches
sparse-check ⏭️ Skipped (no C code changes)
check-uapi-headers ⏭️ Skipped (no UAPI changes)
check-patch-compliance 13 commits differ from upstream lore links
tag-check N/A Not run (no separate job)
qcom-next-check All commits properly tagged FROMLIST:

❌ dtb-check (CRITICAL - BLOCKS MERGE)

Root cause: Malformed patch hunks where SPDX license headers are incorrectly merged with code changes, creating invalid DTS syntax.

Failure details:

Error: ../arch/arm64/boot/dts/qcom/lemans-evk.dts:1.1-11 syntax error
FATAL ERROR: Unable to parse input tree

Error: ../arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts:1.2-3 syntax error
FATAL ERROR: Unable to parse input tree

../arch/arm64/boot/dts/qcom/msm8996.dtsi:1903.5-25: ERROR (duplicate_property_names): /soc@0/bus@0/pcie@600000:phys: Duplicate property name
../arch/arm64/boot/dts/qcom/msm8996.dtsi:1980.5-25: ERROR (duplicate_property_names): /soc@0/bus@0/pcie@608000:phys: Duplicate property name
../arch/arm64/boot/dts/qcom/msm8996.dtsi:2055.5-25: ERROR (duplicate_property_names): /soc@0/bus@0/pcie@610000:phys: Duplicate property name

Example of malformed patch hunk:

-// SPDX-License-Identifier: BSD-3-Clause
+&pcieport1 {&pcieport0 {// SPDX-License-Identifier: BSD-3-Clause

The patch incorrectly places new code (&pcieport1 {&pcieport0 {) on the same line as the SPDX header, creating unparseable DTS files.

Fix:

  1. Regenerate the patch series from the original commits with correct context lines
  2. Ensure each hunk properly separates the SPDX header line from code changes
  3. The "Move PCIe phy and GPIOs" commits (patches 19-36) appear to have been corrupted during patch generation or rebasing
  4. Re-apply these commits cleanly or fetch them fresh from the lore links

Reproduce locally:

cd kernel
git checkout dd4159942f0dd5a3a546c893ddcac8987fa60417
make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- qcom/lemans-evk.dtb
# Will fail with: Error: ../arch/arm64/boot/dts/qcom/lemans-evk.dts:1.1-11 syntax error

❌ checkpatch

Root cause: Email address mismatch between From: and Signed-off-by: tags, plus malformed SPDX warnings caused by the same patch corruption.

Failure details:

WARNING: From:/Signed-off-by: email address mismatch: 
  'From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>' != 
  'Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>'

Affects multiple commits. The From: uses krishna.chundru@ while Signed-off-by: uses krishna.chaitanya.chundru@.

Additional warnings:

WARNING: Missing or malformed SPDX-License-Identifier tag in line 1
#47: FILE: arch/arm64/boot/dts/qcom/talos-evk-som.dtsi:1:
+&pcie_port0 {// SPDX-License-Identifier: BSD-3-Clause

These SPDX warnings are a symptom of the same patch corruption causing dtb-check failures.

Fix:

  1. Email mismatch: Ensure the From: email matches the Signed-off-by: email in all commits. Use git commit --amend --author="Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>" or rebase with git rebase -i and fix author info.
  2. SPDX warnings: Will be resolved when patches are regenerated correctly (see dtb-check fix above).

Reproduce locally:

./scripts/checkpatch.pl --strict --summary-file --ignore FILE_PATH_CHANGES --git bf153443310432b08d0fece8aad2d9fa1bd9f0f1..dd4159942f0dd5a3a546c893ddcac8987fa60417

❌ check-patch-compliance

Root cause: 13 commits in the "Move PCIe phy and GPIOs" series report differences from their upstream lore links.

Failure details:
The following commits are flagged as different from their lore links:

  • FROMLIST: arm64: dts: qcom: kodiak: Fix PCIe wake GPIO
  • FROMLIST: arm64: dts: qcom: lemans: Move PCIe phy and GPIOs
  • FROMLIST: arm64: dts: qcom: msm8998: Move PCIe phy and
  • FROMLIST: arm64: dts: qcom: qcs404: Move PCIe phy and GPIOs
  • FROMLIST: arm64: dts: qcom: qcs8550: Move PCIe GPIOs to
  • FROMLIST: arm64: dts: qcom: sa8295p: Move PCIe GPIOs to
  • FROMLIST: arm64: dts: qcom: sa8540p: Move PCIe GPIOs to
  • FROMLIST: arm64: dts: qcom: sar2130p: Move PCIe phy and
  • FROMLIST: arm64: dts: qcom: sc8180x: Move PCIe phy and
  • FROMLIST: arm64: dts: qcom: sc8280xp: Move PCIe phy and
  • FROMLIST: arm64: dts: qcom: sdm845: Move PCIe phy and GPIOs
  • FROMLIST: arm64: dts: qcom: sm8150: Move PCIe phy and GPIOs
  • FROMLIST: arm64: dts: qcom: sm8250: Move PCIe phy and GPIOs
  • FROMLIST: arm64: dts: qcom: sm8350: Move PCIe phy and GPIOs
  • FROMLIST: arm64: dts: qcom: sm8450: Move PCIe phy and GPIOs
  • FROMLIST: arm64: dts: qcom: sm8550: Move PCIe phy and GPIOs
  • FROMLIST: arm64: dts: qcom: talos: Move PCIe phy and GPIOs
  • FROMLIST: arm64: dts: qcom: sm8650: Move PCIe phy and GPIOs
  • FROMLIST: arm64: dts: qcom: msm8996: Move PCIe phy and

Fix:
This is likely a consequence of the patch corruption. Once patches are regenerated correctly from the original lore series, this check should pass. If differences persist after regeneration, verify that:

  1. The lore links in commit messages point to the correct patch version
  2. No additional changes were made beyond what's in the upstream patches
  3. The patches were applied in the correct order with proper dependencies

Verdict

CRITICAL BLOCKERS - PR CANNOT BE MERGED

This PR has 3 failing checkers with a critical dtb-check failure caused by corrupted patch hunks. The patches must be regenerated from scratch before this PR can be merged.

Required actions:

  1. CRITICAL: Regenerate all "Move PCIe phy and GPIOs" commits (patches 19-36) with correct patch context - the current patches have malformed hunks that corrupt DTS file syntax
  2. Fix email address mismatch: ensure From: and Signed-off-by: use the same email address across all commits
  3. Verify check-patch-compliance passes after regeneration

Recommended approach:

  • Fetch the original patch series from lore.kernel.org using b4 am <series-url>
  • Apply cleanly to the target branch
  • Ensure no manual edits introduce syntax errors
  • Re-test locally with make dtbs before pushing

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3 participants