[WIP] Implementation for TMVA SOFIE running on ALICE EPNs

[ChSonnabend]

This Pull request:

This PR implements the usage of the ALICE event processing nodes for GPU inference of neural networks with SOFIE

• Stream allocation for HIP GPUs
• Support for simple GeMM and dense layer operations (all we need for now)
• Memory allocation in scratch memory for model internal memory allocations during execution. No internal cuda / hip mallocs
• No usage of ROOT header in GPU kernel code needed. All is done via host code allocations, including the inference call
• Compilation of GPU code from .onnx files
• Support for FP16 and FP32 execution

Tested on ALICE event processing nodes with small network used during online TPC cluster finding (ReLU, 6 layers, 32 neurons per layer). It compiles and runs.

This PR links to ALICE pull requests (mentioning for completeness):

• alidist PR: [WIP] Implementation for TMVA SOFIE running on GPUs alisw/alidist#6369
• O2 PR: [WIP] Implementation for TMVA SOFIE running on GPUs AliceO2Group/AliceO2#15913

Changes or fixes:

Checklist:

• tested changes locally
• updated the docs (if necessary)

This PR fixes #