net: l2: ppp: act on a received Protocol-Reject

.ruff-excludes.toml

@@ -14,6 +14,21 @@
 "./boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py" = [
     "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
 ]
+"./doc/_extensions/moderncmakedomain/cmake.py" = [
+    "B904",     # https://docs.astral.sh/ruff/rules/raise-without-from-inside-except
+    "B905",     # https://docs.astral.sh/ruff/rules/zip-without-explicit-strict
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM115",   # https://docs.astral.sh/ruff/rules/open-file-with-context-handler
+    "SIM201",   # https://docs.astral.sh/ruff/rules/negate-equal-op
+    "UP006",    # https://docs.astral.sh/ruff/rules/non-pep585-annotation
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP024",    # https://docs.astral.sh/ruff/rules/os-error-alias
+    "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
+]
+"./doc/_extensions/moderncmakedomain/colors.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP009",    # https://docs.astral.sh/ruff/rules/utf8-encoding-declaration
+]
 "./doc/_scripts/redirects.py" = [
     "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
 ]
@@ -719,6 +734,8 @@
 exclude = [
     "./arch/x86/zefi/zefi.py",
     "./boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py",
+    "./doc/_extensions/moderncmakedomain/cmake.py",
+    "./doc/_extensions/moderncmakedomain/colors.py",
     "./doc/_scripts/gen_devicetree_rest.py",
     "./doc/_scripts/redirects.py",
     "./doc/conf.py",

CMakeLists.txt

@@ -1938,6 +1938,9 @@ endif()
 
 set(KERNEL_META_PATH  ${PROJECT_BINARY_DIR}/${KERNEL_META_NAME} CACHE INTERNAL "")
 if(CONFIG_BUILD_OUTPUT_META)
+  # SBOM tooling reads CMake's object model alongside this metadata.
+  cmake_file_api(QUERY API_VERSION 1 CODEMODEL 2 TOOLCHAINS 1)
+
   list(APPEND
     post_build_commands
     COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/zephyr_module.py
@@ -2315,7 +2318,6 @@ if(HEX_FILES_TO_MERGE)
     )
 
   add_custom_target(mergehex ALL DEPENDS ${MERGED_HEX_NAME})
-  list(APPEND RUNNERS_DEPS mergehex)
 
   message(VERBOSE "Merging hex files: ${HEX_FILES_TO_MERGE}")
 endif()

MAINTAINERS.yml

@@ -1358,12 +1358,13 @@ Device Driver Model:
     - init
 
 Devicetree:
-  status: odd fixes
+  status: maintained
+  maintainers:
+    - maass-hamburg
   collaborators:
     - mbolivar
     - rruuaanng
     - kylebonnici
-    - maass-hamburg
   files-regex:
     - ^dts/bindings/.*zephyr.*
     - ^dts/bindings/[^,]+$
@@ -3488,6 +3489,7 @@ Infineon Platforms:
     - MerinMGeorge
     - ifx-rmcs
     - parthitce
+    - stites-infineon
   files:
     - boards/cypress/
     - boards/infineon/
@@ -3844,7 +3846,6 @@ LiteX Platforms:
     - maass-hamburg
   collaborators:
     - kgugala
-    - mateusz-holenko
   files:
     - boards/enjoydigital/litex_vexriscv/
     - drivers/*/*litex*
@@ -6218,6 +6219,21 @@ TI Stellaris Platforms:
   labels:
     - "platform: TI Stellaris"
 
+TI Tiva C Platforms:
+  status: maintained
+  maintainers:
+    - srisurya1
+  files:
+    - soc/ti/tiva_c/
+    - boards/ti/tm4c123gxl/
+    - dts/arm/ti/tm4c*
+    - dts/bindings/*/*tiva-c*
+    - drivers/*/*tiva_c*
+    - include/zephyr/dt-bindings/pinctrl/tiva-c*
+    - modules/Kconfig.tiva_c
+  labels:
+    - "platform: TI Tiva C"
+
 Task Watchdog:
   status: maintained
   maintainers:
@@ -6283,7 +6299,7 @@ Testing with Renode:
   # This area is to be converted to a subarea
   status: odd fixes
   collaborators:
-    - mateusz-holenko
+    - PiotrZierhoffer
     - fkokosinski
   files:
     - cmake/emu/renode.cmake
@@ -6959,6 +6975,7 @@ West:
     - lauracarlesso
     - MerinMGeorge
     - ifx-rmcs
+    - stites-infineon
   files:
     - modules/Kconfig.infineon
     - modules/hal_infineon/
@@ -7739,7 +7756,6 @@ hawkBit:
   files:
     - subsys/mgmt/hawkbit/
     - include/zephyr/mgmt/hawkbit/
-    - include/zephyr/mgmt/hawkbit.h
     - samples/subsys/mgmt/hawkbit/
   labels:
     - "area: hawkBit"

arch/Kconfig

@@ -69,6 +69,8 @@ config ARM64
 	select ARCH_HAS_ISR_TABLES_LOCAL_DECLARATION
 	select ARCH_SUPPORTS_ROM_OFFSET
 	select ARCH_HAS_CPU_IDLE_HOOKS
+	# Backed by the GIC distributor ICPENDR/ISPENDR registers.
+	select ARCH_HAS_IRQ_PENDING_OPS if !ARM_CUSTOM_INTERRUPT_CONTROLLER
 	help
 	  ARM64 (AArch64) architecture
 
@@ -852,6 +854,23 @@ config ARCH_HAS_IRQ_OFFLOAD_NESTED
 	  synchronous nested interrupt on the current CPU. It gates the default
 	  value of CONFIG_IRQ_OFFLOAD_NESTED.
 
+config ARCH_HAS_IRQ_PENDING_OPS
+	bool
+	help
+	  Selected by architectures whose interrupt controller can set, clear
+	  and query the latched pending state of an individual interrupt
+	  line, providing arch_irq_set_pending(), arch_irq_clear_pending()
+	  and arch_irq_is_pending() and therefore the k_irq_*_pending() API.
+
+config ARCH_HAS_IRQ_GET_ACTIVE
+	bool
+	help
+	  Selected by architectures that can report the interrupt line being
+	  serviced on the local CPU through arch_irq_get_active() and
+	  therefore k_irq_get_active(). Some interrupt controllers expose
+	  this in a register; others record it in the interrupt dispatch
+	  path.
+
 config ARCH_HAS_SEMIHOST
 	bool
 	help

arch/arm/core/Kconfig

@@ -27,6 +27,10 @@ config CPU_CORTEX_M
 	select ARCH_HAS_RAMFUNC_SUPPORT
 	select ARCH_HAS_VECTOR_TABLE_RELOCATION if CPU_CORTEX_M_HAS_VTOR
 	select ARCH_HAS_NESTED_EXCEPTION_DETECTION
+	# The NVIC exposes per-line pending state via ISPR/ICPR. With a custom
+	# or multi-level controller these operations belong to the SoC layer.
+	select ARCH_HAS_IRQ_PENDING_OPS if !ARM_CUSTOM_INTERRUPT_CONTROLLER && \
+		!MULTI_LEVEL_INTERRUPTS
 	select SWAP_NONATOMIC
 	select ARCH_HAS_EXTRA_EXCEPTION_INFO
 	select ARCH_HAS_TIMING_FUNCTIONS if CPU_CORTEX_M_HAS_DWT
@@ -48,6 +52,9 @@ config CPU_AARCH32_CORTEX_R
 	select ARCH_HAS_USERSPACE if ARM_MPU && !USE_SWITCH
 	select ARCH_HAS_EXTRA_EXCEPTION_INFO if !USE_SWITCH
 	select ARCH_HAS_CODE_DATA_RELOCATION
+	# Backed by the GIC distributor ICPENDR/ISPENDR registers.
+	select ARCH_HAS_IRQ_PENDING_OPS if !ARM_CUSTOM_INTERRUPT_CONTROLLER && \
+		!MULTI_LEVEL_INTERRUPTS
 	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_HAS_DCACHE
 	select ARCH_SUPPORTS_ROM_START
 	select USE_SWITCH_SUPPORTED
@@ -69,6 +76,9 @@ config CPU_AARCH32_CORTEX_A
 	select ARCH_HAS_BIT_REV
 	select ARCH_HAS_EXTRA_EXCEPTION_INFO if !USE_SWITCH
 	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT
+	# Backed by the GIC distributor ICPENDR/ISPENDR registers.
+	select ARCH_HAS_IRQ_PENDING_OPS if !ARM_CUSTOM_INTERRUPT_CONTROLLER && \
+		!MULTI_LEVEL_INTERRUPTS
 	select USE_SWITCH_SUPPORTED
 	# GDBSTUB has not yet been tested on Cortex M or R SoCs
 	select ARCH_HAS_GDBSTUB
@@ -77,6 +87,17 @@ config CPU_AARCH32_CORTEX_A
 	help
 	  This option signifies the use of a CPU of the Cortex-A family.
 
+config ARM_TRACK_ACTIVE_IRQ
+	bool "Track the active IRQ in the ISR wrapper"
+	depends on CPU_AARCH32_CORTEX_A || CPU_AARCH32_CORTEX_R
+	select ARCH_HAS_IRQ_GET_ACTIVE
+	help
+	  Provide k_irq_get_active() on Cortex-A/R. The GIC has no register
+	  that reports the INTID being serviced after acknowledge, so the
+	  ISR wrapper records it per CPU, at the cost of a few instructions
+	  on every interrupt entry and exit. Works with both the GIC and a
+	  custom interrupt controller.
+
 config GDBSTUB_BUF_SZ
 	# GDB for ARM expects up to 18 4-byte plus 8 12-byte
 	# registers - 336 HEX letters

arch/arm/core/cortex_a_r/irq_manage.c

@@ -63,6 +63,29 @@ int arm_irq_is_enabled(unsigned int irq)
 	return arm_gic_irq_is_enabled(irq);
 }
 
+#if defined(CONFIG_ARCH_HAS_IRQ_PENDING_OPS)
+void arm_irq_clear_pending(unsigned int irq)
+{
+	__ASSERT(irq < CONFIG_NUM_IRQS, "IRQ %u out of range", irq);
+
+	arm_gic_irq_clear_pending(irq);
+}
+
+void arm_irq_set_pending(unsigned int irq)
+{
+	__ASSERT(irq < CONFIG_NUM_IRQS, "IRQ %u out of range", irq);
+
+	arm_gic_irq_set_pending(irq);
+}
+
+bool arm_irq_is_pending(unsigned int irq)
+{
+	__ASSERT(irq < CONFIG_NUM_IRQS, "IRQ %u out of range", irq);
+
+	return arm_gic_irq_is_pending(irq);
+}
+#endif
+
 /**
  * @internal
  *
@@ -80,6 +103,19 @@ void arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 
 #endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */
 
+#if defined(CONFIG_ARM_TRACK_ACTIVE_IRQ)
+unsigned int arch_irq_get_active(void)
+{
+	/*
+	 * The ISR wrapper stores the INTID biased by one so that the
+	 * zero-initialized boot state reads as "none" on every CPU.
+	 */
+	uint32_t biased = _current_cpu->arch.active_irq;
+
+	return (biased == 0U) ? K_IRQ_ACTIVE_NONE : (biased - 1U);
+}
+#endif
+
 void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf);
 
 /**

arch/arm/core/cortex_a_r/isr_wrapper.S

@@ -183,6 +183,22 @@ _idle_state_cleared:
 #endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */
 	push {r0, r1}
 
+#ifdef CONFIG_ARM_TRACK_ACTIVE_IRQ
+	/*
+	 * Publish the acknowledged INTID for arch_irq_get_active(). The value
+	 * is stored biased by one so that the zero-initialized boot state
+	 * reads as "no interrupt active" on every CPU. The previous value
+	 * and the CPU pointer are kept on the stack so the exit path
+	 * unwinds a nested interrupt to the preempted INTID and the
+	 * outermost exit back to "none".
+	 */
+	get_cpu r2
+	ldr r1, [r2, #_cpu_offset_to_active_irq]
+	add r3, r0, #1
+	str r3, [r2, #_cpu_offset_to_active_irq]
+	push {r1, r2}
+#endif /* CONFIG_ARM_TRACK_ACTIVE_IRQ */
+
 #if CONFIG_GIC_VER >= 3
 	/*
 	 * Ignore GIC special INTIDs (1020-1023), which do not represent
@@ -230,6 +246,12 @@ oob:
 	cpsid i
 
 spurious_continue:
+#ifdef CONFIG_ARM_TRACK_ACTIVE_IRQ
+	/* Unwind the published active INTID to the preempted context's */
+	pop {r1, r2}
+	str r1, [r2, #_cpu_offset_to_active_irq]
+#endif /* CONFIG_ARM_TRACK_ACTIVE_IRQ */
+
 	/* Signal end-of-interrupt */
 	pop {r0, r1}
 #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
@@ -314,6 +336,18 @@ _idle_state_cleared:
 
 	push {r0, r1}
 
+#ifdef CONFIG_ARM_TRACK_ACTIVE_IRQ
+	/*
+	 * Publish the acknowledged INTID for arch_irq_get_active(). See the
+	 * comment in the non-USE_SWITCH variant above.
+	 */
+	get_cpu r2
+	ldr r1, [r2, #_cpu_offset_to_active_irq]
+	add r3, r0, #1
+	str r3, [r2, #_cpu_offset_to_active_irq]
+	push {r1, r2}
+#endif /* CONFIG_ARM_TRACK_ACTIVE_IRQ */
+
 #if CONFIG_GIC_VER >= 3
 	/*
 	 * Ignore Special INTIDs 1020..1023 see 2.2.1 of Arm Generic Interrupt Controller
@@ -351,6 +385,12 @@ oob:
 	cpsid i
 
 spurious_continue:
+#ifdef CONFIG_ARM_TRACK_ACTIVE_IRQ
+	/* Unwind the published active INTID to the preempted context's */
+	pop {r1, r2}
+	str r1, [r2, #_cpu_offset_to_active_irq]
+#endif /* CONFIG_ARM_TRACK_ACTIVE_IRQ */
+
 	/* Signal end-of-interrupt */
 	pop {r0, r1}
 #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)

arch/arm/core/cortex_m/Kconfig

@@ -1,7 +1,7 @@
 # ARM Cortex-M platform configuration options
 
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
-# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# Copyright 2025-2026 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 # NOTE: We have the specific core implementations first and outside of the
@@ -228,7 +228,7 @@ config ARMV7_M_ARMV8_M_MAINLINE
 	select CPU_CORTEX_M_HAS_VTOR
 	select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
 	select CPU_CORTEX_M_HAS_SYSTICK
-	select USE_SWITCH_SUPPORTED
+	select USE_SWITCH_SUPPORTED if !TRUSTED_EXECUTION_NONSECURE
 	select ARCH_HAS_LLEXT_VENEERS
 	select ARCH_HAS_BIT_REV
 	help

arch/arm/core/cortex_m/irq_manage.c

@@ -68,6 +68,29 @@ int arm_irq_is_enabled(unsigned int irq)
 	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
 }
 
+#if defined(CONFIG_ARCH_HAS_IRQ_PENDING_OPS)
+void arm_irq_clear_pending(unsigned int irq)
+{
+	__ASSERT(irq < CONFIG_NUM_IRQS, "IRQ %u out of range", irq);
+
+	NVIC_ClearPendingIRQ((IRQn_Type)irq);
+}
+
+void arm_irq_set_pending(unsigned int irq)
+{
+	__ASSERT(irq < CONFIG_NUM_IRQS, "IRQ %u out of range", irq);
+
+	NVIC_SetPendingIRQ((IRQn_Type)irq);
+}
+
+bool arm_irq_is_pending(unsigned int irq)
+{
+	__ASSERT(irq < CONFIG_NUM_IRQS, "IRQ %u out of range", irq);
+
+	return NVIC_GetPendingIRQ((IRQn_Type)irq) != 0U;
+}
+#endif
+
 /**
  * @internal
  *

arch/arm/core/offsets/offsets_aarch32.c

@@ -42,6 +42,9 @@ GEN_OFFSET_SYM(_thread_arch_t, pac_keys);
 #if defined(CONFIG_CPU_AARCH32_CORTEX_A) || defined(CONFIG_CPU_AARCH32_CORTEX_R)
 GEN_OFFSET_SYM(_thread_arch_t, exception_depth);
 GEN_OFFSET_SYM(_cpu_arch_t, exc_depth);
+#if defined(CONFIG_ARM_TRACK_ACTIVE_IRQ)
+GEN_OFFSET_SYM(_cpu_arch_t, active_irq);
+#endif
 #endif
 
 #if defined(CONFIG_ARM_STORE_EXC_RETURN) || defined(CONFIG_USERSPACE)

arch/arm/include/offsets_short_arch.h

@@ -30,6 +30,11 @@
 
 #define _cpu_offset_to_exc_depth \
 	(___cpu_t_arch_OFFSET + ___cpu_arch_t_exc_depth_OFFSET)
+
+#if defined(CONFIG_ARM_TRACK_ACTIVE_IRQ)
+#define _cpu_offset_to_active_irq \
+	(___cpu_t_arch_OFFSET + ___cpu_arch_t_active_irq_OFFSET)
+#endif
 #endif
 
 #if defined(CONFIG_USERSPACE) || defined(CONFIG_FPU_SHARING)