Skip to content

chore(u5): update to latest STM32CubeU5 v1.9.0 #3006

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
fpistm merged 2 commits into from
Jul 2, 2026
Merged

chore(u5): update to latest STM32CubeU5 v1.9.0 #3006

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
7d99b41
system(u5) update STM32U5xx HAL Drivers to v1.6.3
fpistm Jul 2, 2026
89e4a2d
system(u5): update STM32U5xx CMSIS Drivers to v1.4.3
fpistm Jul 2, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
46 changes: 22 additions & 24 deletions system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3100,11 +3100,11 @@ typedef struct

/* Specific ADC4 */
#define ADC4_CFGR1_EXTSEL_Pos (6UL)
#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */
#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */
#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */

#define ADC4_CFGR1_CHSELRMOD_Pos (21UL)
#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */
Expand Down Expand Up @@ -4792,8 +4792,9 @@ typedef struct
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
/******************** RNG Nist Compliance Values *******************/
#define RNG_CR_NIST_VALUE (0x00F00D00U)
#define RNG_HTCR_NIST_VALUE (0xAAC7U)
#define RNG_CR_NIST_VALUE (0x00F11F00U)
#define RNG_HTCR_NIST_VALUE (0x76B3U)
#define RNG_NSCR_NIST_VALUE (0x24C2U)

/******************************************************************************/
/* */
Expand Down Expand Up @@ -15165,33 +15166,33 @@ typedef struct
#define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000004 */
#define RCC_CCIPR3_SPI3SEL_Pos (3UL)
#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */
#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */
#define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */
#define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */
#define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */
#define RCC_CCIPR3_I2C3SEL_Pos (6UL)
#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000300 */
#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */
#define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */
#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */
#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */
#define RCC_CCIPR3_LPTIM34SEL_Pos (8UL)
#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x0000E000 */
#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000300 */
#define RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */
#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR3_LPTIM1SEL_Pos (10UL)
#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x0000E000 */
#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */
#define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */
#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */
#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */
#define RCC_CCIPR3_ADCDACSEL_Pos (12UL)
#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00030000 */
#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00007000 */
#define RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */
#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00020000 */
#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00040000 */
#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00001000 */
#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR3_DAC1SEL_Pos (15UL)
#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00300000 */
#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00008000 */
#define RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk /*!< DAC1 Sample & Hold Clock Source Selection */
#define RCC_CCIPR3_ADF1SEL_Pos (16UL)
#define RCC_CCIPR3_ADF1SEL_Msk (0x7UL << RCC_CCIPR3_ADF1SEL_Pos) /*!< 0x00070000 */
Expand Down Expand Up @@ -19646,9 +19647,6 @@ typedef struct
#define I2C_CR1_ANFOFF_Pos (12UL)
#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST_Pos (13UL)
#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
#define I2C_CR1_TXDMAEN_Pos (14UL)
#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
Expand Down
46 changes: 22 additions & 24 deletions system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u545xx.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3264,11 +3264,11 @@ typedef struct

/* Specific ADC4 */
#define ADC4_CFGR1_EXTSEL_Pos (6UL)
#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */
#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */
#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */

#define ADC4_CFGR1_CHSELRMOD_Pos (21UL)
#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */
Expand Down Expand Up @@ -4956,8 +4956,9 @@ typedef struct
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
/******************** RNG Nist Compliance Values *******************/
#define RNG_CR_NIST_VALUE (0x00F00D00U)
#define RNG_HTCR_NIST_VALUE (0xAAC7U)
#define RNG_CR_NIST_VALUE (0x00F11F00U)
#define RNG_HTCR_NIST_VALUE (0x76B3U)
#define RNG_NSCR_NIST_VALUE (0x24C2U)

/******************************************************************************/
/* */
Expand Down Expand Up @@ -15717,33 +15718,33 @@ typedef struct
#define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000004 */
#define RCC_CCIPR3_SPI3SEL_Pos (3UL)
#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */
#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */
#define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */
#define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */
#define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */
#define RCC_CCIPR3_I2C3SEL_Pos (6UL)
#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000300 */
#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */
#define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */
#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */
#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */
#define RCC_CCIPR3_LPTIM34SEL_Pos (8UL)
#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x0000E000 */
#define RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000300 */
#define RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */
#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR3_LPTIM1SEL_Pos (10UL)
#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x0000E000 */
#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */
#define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */
#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */
#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */
#define RCC_CCIPR3_ADCDACSEL_Pos (12UL)
#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00030000 */
#define RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00007000 */
#define RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */
#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00020000 */
#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00040000 */
#define RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00001000 */
#define RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR3_DAC1SEL_Pos (15UL)
#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00300000 */
#define RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) /*!< 0x00008000 */
#define RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk /*!< DAC1 Sample & Hold Clock Source Selection */
#define RCC_CCIPR3_ADF1SEL_Pos (16UL)
#define RCC_CCIPR3_ADF1SEL_Msk (0x7UL << RCC_CCIPR3_ADF1SEL_Pos) /*!< 0x00070000 */
Expand Down Expand Up @@ -20242,9 +20243,6 @@ typedef struct
#define I2C_CR1_ANFOFF_Pos (12UL)
#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST_Pos (13UL)
#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
#define I2C_CR1_TXDMAEN_Pos (14UL)
#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
Expand Down
Loading
Loading