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chore(wl3): update to latest STM32CubeWL3 v1.5.0 #3009

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Merged
fpistm merged 7 commits into from
Jul 2, 2026
Merged

chore(wl3): update to latest STM32CubeWL3 v1.5.0 #3009

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13109a7
chore(wl3): update patch
fpistm Jul 2, 2026
9b8d4cb
system(wl3) update STM32WL3x HAL Drivers to v1.5.0
fpistm Jul 2, 2026
bfe639c
system(wl3): update STM32WL3x CMSIS Drivers to v1.5.0
fpistm Jul 2, 2026
a1bc76f
fix(wl3): HAL and LL warnings
fpistm Sep 23, 2025
9226878
feat(wl3): add __libc_init_array call to startup
fpistm Sep 23, 2025
e5d986f
chore(wl3): update system source
fpistm Jul 2, 2026
4e873ef
chore(wl3): remove ROM info from the linker script
fpistm Jul 2, 2026
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182 changes: 84 additions & 98 deletions CI/update/patch/HAL/WL3/0001-fix-wl3-HAL-and-LL-warnings.patch
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61 changes: 40 additions & 21 deletions system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3rx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -398,7 +398,7 @@ typedef struct{ /*!< PWR Structure */
__IO uint32_t RESERVED2[10];
__IO uint32_t DBGR; /*!< (@ 0x00000084) DBGR register */
__IO uint32_t EXTSRR; /*!< (@ 0x00000088) EXTSRR register */
__IO uint32_t RESERVED3;
__IO uint32_t DBGSMPS; /*!< (@ 0x0000008C) DBGSMPS register */
__IO uint32_t TRIMR; /*!< (@ 0x00000090) TRIMR register */
__IO uint32_t ENGTRIM; /*!< (@ 0x00000094) ENGTRIM register */
__IO uint32_t RESERVED4[2];
Expand Down Expand Up @@ -702,7 +702,7 @@ typedef struct{ /*!< MR_SUBG_RADIO Structure */
__IO uint32_t IQC_CTRL1; /*!< (@ 0x00000044) IQC_CTRL1 register */
__IO uint32_t IQC_CTRL2; /*!< (@ 0x00000048) IQC_CTRL2 register */
__IO uint32_t IQC_CTRL3; /*!< (@ 0x0000004C) IQC_CTRL3 register */
__IO uint32_t RESERVED;
__IO uint32_t AGC_ANA_ENG; /*!< (@ 0x00000050) AGC_ANA_ENG register */
__IO uint32_t AGC0_CTRL; /*!< (@ 0x00000054) AGC0_CTRL register */
__IO uint32_t AGC1_CTRL; /*!< (@ 0x00000058) AGC1_CTRL register */
__IO uint32_t AGC2_CTRL; /*!< (@ 0x0000005C) AGC2_CTRL register */
Expand Down Expand Up @@ -906,9 +906,9 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */

/*!< Peripheral memory map */
#define APB0PERIPH_BASE PERIPH_BASE
#define APB1PERIPH_BASE (PERIPH_BASE + 0x01000000LU)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x08000000LU)
#define APB2PERIPH_BASE (PERIPH_BASE + 0x09000000LU)
#define APB1PERIPH_BASE (PERIPH_BASE + 0x01000000UL)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x08000000UL)
#define APB2PERIPH_BASE (PERIPH_BASE + 0x09000000UL)


/*!< APB0 peripherals */
Expand Down Expand Up @@ -7516,6 +7516,19 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */
#define PWR_EXTSRR_DEEPSTOPF_Msk (0x200UL) /*!< PWR EXTSRR: DEEPSTOPF (Bitfield-Mask: 0x01) */
#define PWR_EXTSRR_DEEPSTOPF PWR_EXTSRR_DEEPSTOPF_Msk

/* ===================================================== DBGSMPS =====================================================*/
#define PWR_DBGSMPS_BOF_CUR_SEL_Pos (14UL) /*!<PWR DBGSMPS: BOF_CUR_SEL (Bit 14) */
#define PWR_DBGSMPS_BOF_CUR_SEL_Msk (0xc000UL) /*!< PWR DBGSMPS: BOF_CUR_SEL (Bitfield-Mask: 0x03) */
#define PWR_DBGSMPS_BOF_CUR_SEL PWR_DBGSMPS_BOF_CUR_SEL_Msk
#define PWR_DBGSMPS_BOF_CUR_SEL_0 (0x1U << PWR_DBGSMPS_BOF_CUR_SEL_Pos)
#define PWR_DBGSMPS_BOF_CUR_SEL_1 (0x2U << PWR_DBGSMPS_BOF_CUR_SEL_Pos)
#define PWR_DBGSMPS_ILIM_BOOST_Pos (13UL) /*!<PWR DBGSMPS: ILIM_BOOST (Bit 13) */
#define PWR_DBGSMPS_ILIM_BOOST_Msk (0x2000UL) /*!< PWR DBGSMPS: ILIM_BOOST (Bitfield-Mask: 0x01) */
#define PWR_DBGSMPS_ILIM_BOOST PWR_DBGSMPS_ILIM_BOOST_Msk
#define PWR_DBGSMPS_DIS_ILIM_Pos (12UL) /*!<PWR DBGSMPS: DIS_ILIM (Bit 12) */
#define PWR_DBGSMPS_DIS_ILIM_Msk (0x1000UL) /*!< PWR DBGSMPS: DIS_ILIM (Bitfield-Mask: 0x01) */
#define PWR_DBGSMPS_DIS_ILIM PWR_DBGSMPS_DIS_ILIM_Msk

/* ===================================================== TRIMR =====================================================*/
#define PWR_TRIMR_SMPS_TRIM_Pos (8UL) /*!<PWR TRIMR: SMPS_TRIM (Bit 8) */
#define PWR_TRIMR_SMPS_TRIM_Msk (0x700UL) /*!< PWR TRIMR: SMPS_TRIM (Bitfield-Mask: 0x07) */
Expand Down Expand Up @@ -7567,18 +7580,6 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */
#define PWR_ENGTRIM_TRIMRFDREGEN_Msk (0x1UL) /*!< PWR ENGTRIM: TRIMRFDREGEN (Bitfield-Mask: 0x01) */
#define PWR_ENGTRIM_TRIMRFDREGEN PWR_ENGTRIM_TRIMRFDREGEN_Msk

/* ===================================================== ENGTRIM2 =====================================================*/
#define PWR_ENGTRIM2_BOF_TRIM_Pos (1UL) /*!<PWR ENGTRIM2: BOF_TRIM (Bit 1) */
#define PWR_ENGTRIM2_BOF_TRIM_Msk (0xeUL) /*!< PWR ENGTRIM2: BOF_TRIM (Bitfield-Mask: 0x07) */
#define PWR_ENGTRIM2_BOF_TRIM PWR_ENGTRIM2_BOF_TRIM_Msk
#define PWR_ENGTRIM2_BOF_TRIM_0 (0x1U << PWR_ENGTRIM2_BOF_TRIM_Pos)
#define PWR_ENGTRIM2_BOF_TRIM_1 (0x2U << PWR_ENGTRIM2_BOF_TRIM_Pos)
#define PWR_ENGTRIM2_BOF_TRIM_2 (0x4U << PWR_ENGTRIM2_BOF_TRIM_Pos)
#define PWR_ENGTRIM2_BOFTRIMEN_Pos (0UL) /*!<PWR ENGTRIM2: BOFTRIMEN (Bit 0) */
#define PWR_ENGTRIM2_BOFTRIMEN_Msk (0x1UL) /*!< PWR ENGTRIM2: BOFTRIMEN (Bitfield-Mask: 0x01) */
#define PWR_ENGTRIM2_BOFTRIMEN PWR_ENGTRIM2_BOFTRIMEN_Msk


/* ============================================================================================================================*/
/*===================== RNG =====================*/
/* ============================================================================================================================*/
Expand Down Expand Up @@ -9050,9 +9051,9 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */
#define MR_SUBG_GLOB_DYNAMIC_VCO_CAL_CONFIG_VCO_CALAMP_EXT_13 (0x2000U << MR_SUBG_GLOB_DYNAMIC_VCO_CAL_CONFIG_VCO_CALAMP_EXT_Pos)

/* ===================================================== RX_TIMER =====================================================*/
#define MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_nAND_SELECT_Pos (31UL) /*!<MR_SUBG_GLOB_DYNAMIC RX_TIMER: RX_OR_nAND_SELECT (Bit 31) */
#define MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_nAND_SELECT_Msk (0x80000000UL) /*!< MR_SUBG_GLOB_DYNAMIC RX_TIMER: RX_OR_nAND_SELECT (Bitfield-Mask: 0x01) */
#define MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_nAND_SELECT MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_nAND_SELECT_Msk
#define MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_NAND_SELECT_Pos (31UL) /*!<MR_SUBG_GLOB_DYNAMIC RX_TIMER: RX_OR_NAND_SELECT (Bit 31) */
#define MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_NAND_SELECT_Msk (0x80000000UL) /*!< MR_SUBG_GLOB_DYNAMIC RX_TIMER: RX_OR_NAND_SELECT (Bitfield-Mask: 0x01) */
#define MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_NAND_SELECT MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_NAND_SELECT_Msk
#define MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_SQI_TIMEOUT_MASK_Pos (30UL) /*!<MR_SUBG_GLOB_DYNAMIC RX_TIMER: RX_SQI_TIMEOUT_MASK (Bit 30) */
#define MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_SQI_TIMEOUT_MASK_Msk (0x40000000UL) /*!< MR_SUBG_GLOB_DYNAMIC RX_TIMER: RX_SQI_TIMEOUT_MASK (Bitfield-Mask: 0x01) */
#define MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_SQI_TIMEOUT_MASK MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_SQI_TIMEOUT_MASK_Msk
Expand Down Expand Up @@ -10902,6 +10903,24 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */
#define MR_SUBG_RADIO_IQC_CTRL3_FAST_TIME_2 (0x4U << MR_SUBG_RADIO_IQC_CTRL3_FAST_TIME_Pos)
#define MR_SUBG_RADIO_IQC_CTRL3_FAST_TIME_3 (0x8U << MR_SUBG_RADIO_IQC_CTRL3_FAST_TIME_Pos)

/* ===================================================== AGC_ANA_ENG =====================================================*/
#define MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_PGA_AGCGAIN_Pos (5UL) /*!<MR_SUBG_RADIO AGC_ANA_ENG: RFD_RX_PGA_AGCGAIN (Bit 5) */
#define MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_PGA_AGCGAIN_Msk (0xe0UL) /*!< MR_SUBG_RADIO AGC_ANA_ENG: RFD_RX_PGA_AGCGAIN (Bitfield-Mask: 0x07) */
#define MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_PGA_AGCGAIN MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_PGA_AGCGAIN_Msk
#define MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_PGA_AGCGAIN_0 (0x1U << MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_PGA_AGCGAIN_Pos)
#define MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_PGA_AGCGAIN_1 (0x2U << MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_PGA_AGCGAIN_Pos)
#define MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_PGA_AGCGAIN_2 (0x4U << MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_PGA_AGCGAIN_Pos)
#define MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_ATTEN_AGCGAIN_Pos (1UL) /*!<MR_SUBG_RADIO AGC_ANA_ENG: RFD_RX_ATTEN_AGCGAIN (Bit 1) */
#define MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_ATTEN_AGCGAIN_Msk (0x1eUL) /*!< MR_SUBG_RADIO AGC_ANA_ENG: RFD_RX_ATTEN_AGCGAIN (Bitfield-Mask: 0x0f) */
#define MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_ATTEN_AGCGAIN MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_ATTEN_AGCGAIN_Msk
#define MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_ATTEN_AGCGAIN_0 (0x1U << MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_ATTEN_AGCGAIN_Pos)
#define MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_ATTEN_AGCGAIN_1 (0x2U << MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_ATTEN_AGCGAIN_Pos)
#define MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_ATTEN_AGCGAIN_2 (0x4U << MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_ATTEN_AGCGAIN_Pos)
#define MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_ATTEN_AGCGAIN_3 (0x8U << MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_ATTEN_AGCGAIN_Pos)
#define MR_SUBG_RADIO_AGC_ANA_ENG_FORCE_AGC_GAINS_Pos (0UL) /*!<MR_SUBG_RADIO AGC_ANA_ENG: FORCE_AGC_GAINS (Bit 0) */
#define MR_SUBG_RADIO_AGC_ANA_ENG_FORCE_AGC_GAINS_Msk (0x1UL) /*!< MR_SUBG_RADIO AGC_ANA_ENG: FORCE_AGC_GAINS (Bitfield-Mask: 0x01) */
#define MR_SUBG_RADIO_AGC_ANA_ENG_FORCE_AGC_GAINS MR_SUBG_RADIO_AGC_ANA_ENG_FORCE_AGC_GAINS_Msk

/* ===================================================== AGC0_CTRL =====================================================*/
#define MR_SUBG_RADIO_AGC0_CTRL_AGC_EN_Pos (7UL) /*!<MR_SUBG_RADIO AGC0_CTRL: AGC_EN (Bit 7) */
#define MR_SUBG_RADIO_AGC0_CTRL_AGC_EN_Msk (0x80UL) /*!< MR_SUBG_RADIO AGC0_CTRL: AGC_EN (Bitfield-Mask: 0x01) */
Expand Down Expand Up @@ -11554,7 +11573,7 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */
#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES))


/** @} */ /* End of group STM32WBL3x_Peripheral_Exported_macros */
/** @} */ /* End of group STM32WL3x_Peripheral_Exported_macros */

/** @} */ /* End of group STM32WL3x */

Expand Down
6 changes: 3 additions & 3 deletions system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3x.h
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32WBxx device used in the target application
* - The device used in the target application (STM32WL3xx or STM32WL3Rx)
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
Expand Down Expand Up @@ -88,8 +88,8 @@
* @brief CMSIS Device version number
*/
#define __STM32WL3x_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32WL3x_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
#define __STM32WL3x_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32WL3x_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32WL3x_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32WL3x_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WL3x_CMSIS_VERSION ((__STM32WL3x_CMSIS_VERSION_MAIN << 24U)\
|(__STM32WL3x_CMSIS_VERSION_SUB1 << 16U)\
Expand Down
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