Experimental 3-tier silicon failure-fencing engine isolating volatile NaN/Inf bleeding via runtime CPython method table interception and timing-frozen JAX shard_map topologies.
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Updated
Aug 9, 2026 - Python
Experimental 3-tier silicon failure-fencing engine isolating volatile NaN/Inf bleeding via runtime CPython method table interception and timing-frozen JAX shard_map topologies.
Instruction-level Tensor Core micro-kernel engineering on SM75 (RTX 2070), including PTX manual emission, shared-memory staging, and hardware-aware auto-tuning.
Centralized 3-tier multi-framework control plane for AOT hardware compilation, zero-copy memory routing, and runtime CPython method table interception.
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