A robot-specific processing unit. Contains CPUs, FPGAs and GPUs and maps ROS efficiently to them for best performance.
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Updated
Apr 12, 2023
A robot-specific processing unit. Contains CPUs, FPGAs and GPUs and maps ROS efficiently to them for best performance.
A synthesizable 32-bit RISC-V RV32I single-cycle processor integrated with a memory-mapped MAC AI accelerator for hardware vector dot-product offloading, built in SystemVerilog with full verification and Python software toolchain.
Verilog implementation of RV32I SoC with 5-stage datapath, Wishbone B4 Classic interconnect, MAC accelerator, DMA controller; verified against official rv32ui test suite
Hardware accelerator for Image processing in FPGA
Hard Tech Fund
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