SPI-configurable HIPIMS pulse generator core for Cyclone IV E FPGA (VHDL) — dual-leg interlocked drive, anode PWM channel, fault-latch safety, paired with an STM32 SPI-master front-end.
-
Updated
Aug 19, 2026 - VHDL
SPI-configurable HIPIMS pulse generator core for Cyclone IV E FPGA (VHDL) — dual-leg interlocked drive, anode PWM channel, fault-latch safety, paired with an STM32 SPI-master front-end.
To associate your repository with the hipims topic, visit your repo's landing page and select "manage topics."