Add test for UCIe digital

software/Makefile

@@ -33,10 +33,10 @@ ARCHFLAGS = -march=$(ARCH) -mabi=$(ABI)
 # vector extension. Kept separate so it doesn't force V onto every program.
 VEC_ARCHFLAGS = -march=rv64gcv_zfh_zvfh -mabi=$(ABI)
 
-CFLAGS  = -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall -specs=htif_nano.specs
+CFLAGS  = -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall -specs=htif_nano.specs -Iinclude
 LDFLAGS = -specs=htif_nano.specs
 
-PROGRAMS = hello hello0 hello1 router ring-hello ucie-loopback tacit-always tacit-dma ucie-vec-memcpy
+PROGRAMS = hello hello0 hello1 router ring-hello ucie-loopback ucie-digital-loopback tacit-always tacit-dma ucie-vec-memcpy
 
 .DEFAULT_GOAL := default
 

software/ucie-digital-loopback.c

@@ -0,0 +1,70 @@
+#include <stdio.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <riscv-pk/encoding.h>
+#include "marchid.h"
+#include "mmio.h"
+#include "router.h"
+#include "ucie.h"
+
+#define UCIE0_REG_BASE 0x200000UL
+#define UCIE1_REG_BASE 0x208000UL
+#define ROUTER_MMIO 0x4000
+#define CHIP_ID_ADDR 0x4080
+#define OFFCHIP_OFFSET 0x800000000L
+
+uint32_t src[10] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9};
+uint32_t dest[10];
+uint32_t test[10];
+
+int rw_mem(uint64_t offset) {
+  // remote = dest on the other chip: same local address as our dest, tagged with target chip ID.
+  // offset = OFFCHIP_OFFSET * target_chipId (a byte offset, added via uint8_t* cast).
+  void *remote = (void *)((uint8_t *)dest + offset);
+
+  size_t write_start = rdcycle();
+  memcpy(remote, src, sizeof(src));
+  size_t write_end = rdcycle();
+
+  printf("Wrote %ld bytes in %ld cycles\n", sizeof(src), write_end - write_start);
+
+  size_t read_start = rdcycle();
+  memcpy(test, remote, sizeof(src));
+  size_t read_end = rdcycle();
+
+  for (int i = 0; i < 10; i++) {
+      if (src[i] != test[i]) {
+        printf("Remote write/read failed at index %d: wrote %x, read %x\n", i, src[i], test[i]);
+        exit(1);
+      }
+  }
+
+  printf("Read %ld bytes in %ld cycles\n", sizeof(src), read_end - read_start);
+
+  return 0;
+}
+
+int main(void) {
+
+  int chip_id = reg_read64(CHIP_ID_ADDR);
+
+  printf("Got chip ID: %d\n", chip_id);
+
+  printf("Setting up UCIe0 (digital controller)\n");
+  setup_ucie_digital(UCIE0_REG_BASE);
+  printf("Setting up UCIe1 (digital controller)\n");
+  setup_ucie_digital(UCIE1_REG_BASE);
+
+  printf("Testing UCIe at port 0\n");
+  program_router(0, 1, 0);
+  rw_mem(OFFCHIP_OFFSET);
+
+  printf("Testing UCIe at port 1\n");
+  program_router(0, 1, 1);
+  rw_mem(OFFCHIP_OFFSET);
+
+  printf("UCIe digital loopback test complete\n");
+
+  return 0;
+}

src/Iris.scala

@@ -512,13 +512,15 @@ class IrisConfig(sim: Boolean = false)
               address = 0x200000,
               managerWhere = SBUS,
               numLanes = 16,
-              includeDefaultModels = true
+              includeDefaultModels = true,
+              sim = sim
             )),
             UcieComplexPort(edu.berkeley.cs.uciedigital.tilelink.UcieTLParams(
               address = 0x208000,
               managerWhere = SBUS,
               numLanes = 16,
               includeDefaultModels = true,
+              sim = sim,
               moduleId = 1
             ))
         ))) ++

src/TinyIris.scala

@@ -258,13 +258,15 @@ class TinyIrisConfig(sim: Boolean = false)
               address = 0x200000,
               managerWhere = SBUS,
               numLanes = 16,
-              includeDefaultModels = true
+              includeDefaultModels = true,
+              sim = sim
             ),
             edu.berkeley.cs.uciedigital.tilelink.UcieTLParams(
               address = 0x208000,
               managerWhere = SBUS,
               numLanes = 16,
-              includeDefaultModels = true
+              includeDefaultModels = true,
+              sim = sim
             )
         ))) ++
 

test/src/IrisSpec.scala

@@ -152,7 +152,7 @@ class TestHarness(nChips: Int, binaryPaths: Seq[Path], plusArgs: Seq[Seq[String]
   val digitalFreqMHz = 500
   val digitalClock = freeRunningClock(digitalFreqMHz)
   val ucieBypassClock = freeRunningClock(8000)
-  val ucieDigitalBypassClock = freeRunningClock(800)
+  val ucieDigitalBypassClock = freeRunningClock(500) // previously was 800
   val ucieSidebandBypassClock = freeRunningClock(800)
   // The clocking tile's PLL reference, as in the UCIe repo's own harness.
   val ucieRefClock = freeRunningClock(100)
@@ -435,6 +435,26 @@ class IrisSpec extends AnyFunSpec {
       )
     }
 
+    it("should run ucie digital loopback test") {
+            implicit val p = new IrisConfig(sim = true)
+      val workDir = Utils.buildRoot / "Iris_should_run_ucie_digital_loopback_test"
+
+      val chipid0 = 1
+      val chipidReg = p(ChipletRoutingKey).get.routerParams.tableAddress + p(ChipletRoutingKey).get.routerParams.tableEntries * 32
+      val chip0PlusArgs = Seq(
+        f"+init_write=0x${chipidReg}%08x:0x${chipid0}%08x",
+      )
+
+      Utils.simulateTopWithBinaries(
+        workDir,
+        nChips = 1,
+        binaryPaths = Seq(Utils.root / "software/ucie-digital-loopback.riscv"),
+        plusArgs = Seq(chip0PlusArgs),
+        fast = true,
+        debug = true
+      )
+    }
+
     it("should run tacit always trace workload") {
       implicit val p = new IrisConfig(sim = true)
       val workDir = Utils.buildRoot / "Iris_should_run_tacit_always_trace"