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Tacit lossy - #40
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Tacit lossy#40
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iansseijelly
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Oct 21, 2026
iansseijelly
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- fix the stall threshold cycles on both rocket and shuttle
- add testing infrastructure for serTL characterization
- add a DMA node into FBUS to reach spad and L2 for characterization
- add a sync periodic mode for fault tolerance and wrap around behavior.
- tacit: merge origin/dev-lossy (lossy Pause/Resume mode, trap from/to privilege fixes, lossless stall-reserve +1 fix, extra perf counters, sim-only backpressure sink); strip BOOM arms again for iris; keep the DMA sink's 0xFFF page alignment. - rocket-chip: cherry-pick lossy control + perf bundle and the extended encoder controller registers from riscv-tacit/trace-lossy onto iris-tacit (ASID/TLB work intentionally left out). - shuttle: cherry-pick perf bundle routing (a989d13) onto iris-tacit-on-master (ASID/TLB work left out). - tacit_decoder: bump to origin/lossy (decodes Pause/Resume). Encoder stall parameters (stallQuiescenceCycles / maxPacketsPerCycle) in src/TacitConfigs.scala are unchanged here; to follow separately. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
… traps - shuttle: gate the trace ingress exception term to lane 0. ecall/ebreak commit with retire=1, so the CSR trace port also flagged lane 1 and every ecall/ebreak emitted a phantom trap packet from lane 1's stale uop. - TacitConfigs: the SRAM queue sizes its stall reserve from stallQuiescenceCycles (coreStages is unused there) and was taking the BOOM default of 3. Shuttle: 5 (3 retire groups past the register-read gate + 2 margin) with maxPacketsPerCycle = Some(1), which the lane-0 fix makes true. Rocket: 6 (3 past decode + 1 interrupt bypass + 2 margin). Shuttle now stalls at 11/16 entries instead of 9. Validated in Iris sim with the minimum reserve (Shuttle 3, Rocket 4) on the DMA sink: branch and ecall storms holding the queue at the stall point, an ecall/ebreak/illegal/load-fault/interrupt trap mix, a cross-core IPI storm and Embench (crc32, slre, statemate, nsichneu, edn, tarfind, md5sum), with no lossless-loss, enqueue-rate or lane-0 asserts and clean decodes. Standard tacit always/dma tests pass with the final values. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_016hkQa6XQJC6FcnvJ9ScQ9b
…xperiments Tapeout config: - WithIrisTacitTrace: one trace DMA per tile with a port on the FBUS and the MBUS (tacit 3a42024), chosen by its bus_select register. 0 (reset) writes through the FBUS into the SBUS, so the trace can go to the on-chip SBUS scratchpad or to DRAM through the L2; 1 writes DRAM below the L2 over serial TL. Soft-reset the DMA before switching. - software/tacit-dma.c: wait 4096 cycles after disabling tracing, past the DMA's partial-line flush. Tests (no RTL change): - TestHarness/SimTop/Utils: optional serialTLFreqMHz runs the serial-TL link, the harness memory and TSI on their own clock. - IrisSpec: "tacit dma trace workload on the tapeout serial TL" simulates the tapeout RTL (IrisConfig(sim = false): 16b serial TL, no TL monitors) with the link at 100 MHz. - IrisExperiments.scala: experiment-only overrides (DMA source count, shrunk L2, L2 outer latency) and a sim-only memory traffic monitor, built into build/Experiment_*. Nothing there is part of the tapeout configuration. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_016hkQa6XQJC6FcnvJ9ScQ9b
- rocket-chip: sync_interval controller register (0x60, bytes, 0 = off). - tacit: TacitParallelEncoder emits Sync Periodic checkpoints. - tacit_decoder: decodes them and resyncs wrapped ring-buffer dumps. Off by default (sync_interval resets to 0); software enables it by writing the controller's 0x60 before enabling tracing. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_016hkQa6XQJC6FcnvJ9ScQ9b
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