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perf(blosc): use NEON SIMD for byte-shuffle on aarch64 #864

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10 changes: 10 additions & 0 deletions docs/release.md
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,16 @@

## Unreleased

### Enhancements

* Blosc byte-shuffle and unshuffle now use NEON SIMD on aarch64 (Apple Silicon, AWS
Graviton, etc). c-blosc 1.x only ships SSE2/AVX2 kernels, so on ARM it previously fell
back to a scalar loop that dominated Blosc runtime. The NEON kernels are taken from
c-blosc2 and produce byte-identical output. On an Apple M5, decoding 1 MiB lz4+shuffle
chunks is ~5-6x faster and encoding ~2x faster. Controlled by the new `neon` meson
option (default `auto`).
By {user}`Davis Bennett <d-v-b>`.

(release_0.17.0)=

* Allow building against a system Zlib. Note, this is only required if blosc is still
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2 changes: 2 additions & 0 deletions meson.options
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Expand Up @@ -10,3 +10,5 @@ option('sse2', type: 'feature', value: 'auto',
description: 'Enable SSE2 SIMD optimizations')
option('avx2', type: 'feature', value: 'auto',
description: 'Enable AVX2 SIMD optimizations')
option('neon', type: 'feature', value: 'auto',
description: 'Enable NEON SIMD shuffle on aarch64')
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