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GPU/TPC: Increace assumed cacheline size to 128 byte in cluster finder #15545

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GPU/TPC: Increace assumed cacheline size to 128 byte in cluster finder #15545

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10 changes: 8 additions & 2 deletions GPU/GPUTracking/TPCClusterFinder/CfArray2D.h
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Original file line number Diff line number Diff line change
Expand Up @@ -86,10 +86,13 @@ class LinearLayout
template <tpccf::SizeT S>
struct GridSize;

// GridSize for 1 byte and 2 byte elements are adjusted for 128 byte cachelines,
// as these are prevelant on modern GPUs.

template <>
struct GridSize<1> {
enum {
Width = 8,
Width = 16,
Height = 8,
};
};
Expand All @@ -98,10 +101,13 @@ template <>
struct GridSize<2> {
enum {
Width = 8,
Height = 4,
Height = 8,
};
};

// GridSize for 4 bytes is only used for MC indexing on CPU.
// So assume 64 byte cachelines here instead.

template <>
struct GridSize<4> {
enum {
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1 change: 0 additions & 1 deletion GPU/GPUTracking/TPCClusterFinder/GPUTPCCFCheckPadBaseline.h
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Expand Up @@ -53,7 +53,6 @@ class GPUTPCCFCheckPadBaseline : public GPUKernelTemplate
TimebinsPerCacheline = TPCMapMemoryLayout<uint16_t>::Height,
EntriesPerCacheline = PadsPerCacheline * TimebinsPerCacheline,
NumOfCachedPads = GPUCA_WARP_SIZE / TimebinsPerCacheline,
NumCLsPerWarp = GPUCA_WARP_SIZE / EntriesPerCacheline,
NumOfCachedTBs = TimebinsPerCacheline * 8,
// Threads index shared memory as [iThread / MaxNPadsPerRow][iThread % MaxNPadsPerRow].
// Rounding up to a multiple of PadsPerCacheline ensures iThread / MaxNPadsPerRow < NumOfCachedTBs
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