Updated several gf12 designs to pass LEC - #4422
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Signed-off-by: Jeff Ng <jeffng@precisioninno.com>
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This pull request configures Logic Equivalence Checking (LEC) for several GF12 designs (bp_dual, bp_quad, bp_single, and coyote) by specifying Verilog stubs via LEC_AUX_VERILOG_FILES and removing corresponding Liberty files via REMOVE_LIBS_FOR_LEC. This resolves issues with register files that have pins referencing multiple clocks. Additionally, LEC is re-enabled for the coyote design. I have no feedback to provide as there are no review comments.
eder-matheus
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🔍 QoR checkMetrics reflect the PR merge build — i.e. what will land on the target branch. Advisory — results are log-only and do not affect build status. The authoritative QoR gate remains the local rules-file check. Commit 61 design(s) checked — 0 with regression(s), 0 without a comparable baseline.
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Updated gf12 bp_dual, bp_quad, bp_single and coyote to pass a blackbox verilog file instead of the liberty files to LEC. Works around KF issues with the RAM macros.
@joaomai , @eder-matheus I went ahead and updated the bp_* configs so that it should all go through with the OR update + halo updates.