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Updated several gf12 designs to pass LEC #4422

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Updated several gf12 designs to pass LEC #4422

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8 changes: 8 additions & 0 deletions flow/designs/gf12/bp_dual/config.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -68,3 +68,11 @@ export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl
export MACRO_PLACE_HALO = 7 7

export OPT_POST_GRT_WNS = 0

# Have to use Verilog stubs for LEC for some of the RF's, since they have
# a pin that has a condition that references multiple clocks. These two settings
# use the Verilog stubs and remove the Liberty files from the kepler-formal
# configuration file
export LEC_AUX_VERILOG_FILES = $(PLATFORM_DIR)/verilog/gf12_1r1w_d32_w64_m1.v
export REMOVE_LIBS_FOR_LEC = $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(OBJECTS_DIR)/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c_mod.lib
8 changes: 8 additions & 0 deletions flow/designs/gf12/bp_quad/config.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -70,3 +70,11 @@ export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl
export MACRO_PLACE_HALO = 7 7

export OPT_POST_GRT_WNS = 0

# Have to use Verilog stubs for LEC for some of the RF's, since they have
# a pin that has a condition that references multiple clocks. These two settings
# use the Verilog stubs and remove the Liberty files from the kepler-formal
# configuration file
export LEC_AUX_VERILOG_FILES = $(PLATFORM_DIR)/verilog/gf12_1r1w_d32_w64_m1.v
export REMOVE_LIBS_FOR_LEC = $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(OBJECTS_DIR)/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c_mod.lib
8 changes: 8 additions & 0 deletions flow/designs/gf12/bp_single/config.mk
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Expand Up @@ -72,3 +72,11 @@ export SETUP_SLACK_MARGIN ?= 100
export SWAP_ARITH_OPERATORS = 1
export OPENROAD_HIERARCHICAL = 1
export OPT_POST_GRT_WNS = 0

# Have to use Verilog stubs for LEC for some of the RF's, since they have
# a pin that has a condition that references multiple clocks. These two settings
# use the Verilog stubs and remove the Liberty files from the kepler-formal
# configuration file
export LEC_AUX_VERILOG_FILES = $(PLATFORM_DIR)/verilog/gf12_1r1w_d32_w64_m1.v
export REMOVE_LIBS_FOR_LEC = $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(OBJECTS_DIR)/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c_mod.lib
12 changes: 10 additions & 2 deletions flow/designs/gf12/coyote/config.mk
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Expand Up @@ -40,5 +40,13 @@ endif
export SWAP_ARITH_OPERATORS = 1
export OPENROAD_HIERARCHICAL = 1

# Temporarily disable LEC until RAM issue can be resolved with KF
export LEC_CHECK = 0
# Have to use Verilog stubs for LEC for some of the RF's, since they have
# a pin that has a condition that references multiple clocks. These two settings
# use the Verilog stubs and remove the Liberty files from the kepler-formal
# configuration file
export LEC_AUX_VERILOG_FILES = $(PLATFORM_DIR)/verilog/gf12_2rf_lg6_w44_bit.v \
$(PLATFORM_DIR)/verilog/gf12_2rf_lg8_w64_bit.v
export REMOVE_LIBS_FOR_LEC = $(PLATFORM_DIR)/lib/gf12_2rf_lg6_w44_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_2rf_lg8_w64_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(OBJECTS_DIR)/gf12_2rf_lg6_w44_bit_ffpg_sigcmin_0p88v_0p88v_m40c_mod.lib \
$(OBJECTS_DIR)/gf12_2rf_lg8_w64_bit_ffpg_sigcmin_0p88v_0p88v_m40c_mod.lib