drivers: modem: cellular: track 5GS registration separately - #3
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spi_ambiq_transceive() returned early when spi_config() failed, skipping the runtime PM put and leaking the usage count taken by the get; the device could then never runtime-suspend again. It also overwrote the transfer status with the return of pm_device_runtime_put_async(), hiding transfer errors from the caller, and continued into the HAL after a failed get. Route the config-failure path through the common exit, keep the put status in its own variable, and bail out when the get fails. Fixes zephyrproject-rtos#116324 Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
spi_config() stored the config in the context before calling am_hal_ios_configure(), so a failed HAL configure left the context marked as configured. The next transceive then passed the spi_context_configured() check and ran on unconfigured hardware, and the raw HAL status leaked through the SPI API as a positive value. Only publish the new config once the HAL accepts it and map a configure failure to -EIO. Fixes zephyrproject-rtos#116324 Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
The documentation coverage targets and the top-level group check only read the Doxygen XML tree. Both went through the 'doxygen' target, which also renders the complete API HTML and writes the tag file, so every run paid for output that nothing then looked at. The "Doxygen Checks" workflow pays it twice per pull request, once for the branch and once for its base, and configures the build with DOXYGEN_FORCE_SINGLE_THREAD=1 on top of that. Add a 'doxygen-xml' target that pulls in the generated Doxyfile with @include and switches off the outputs that are not needed, and point the two coverage targets at it. Because the overrides follow the @include, the run keeps the whole configuration the 'doxygen' target uses, including anything a ZEPHYR_DOXYGEN_OVERLAY adds. It writes to its own output directory rather than sharing one with 'doxygen', so building both cannot have two Doxygen processes writing to the same tree. Measured over the full INPUT set with Doxygen 1.17.0, the version CI pins, single-threaded as the coverage targets run it: 34s -> 20s, and 642M -> 221M of output. The generated XML is byte for byte identical apart from xml/Doxyfile.xml, which is Doxygen's dump of its own configuration and which neither coverxygen nor doxygen_toplevel_groups.py reads. Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org> Assisted-by: Claude:opus-5
Since commit 85a2085 ("pm: make IRQ-locked state-set the default") the PM core keeps IRQs masked across pm_state_set() and pm_state_exit_post_ops(), and an implementation that unmasks from those hooks has to opt out through PM_STATE_SET_IRQ_UNLOCKED. This SoC opted out, and its ordering was the reason to care: pm_state_exit_post_ops() called __enable_irq() as its very first statement, before clearing the SPC power-domain low-power request flag. A wake ISR could therefore observe that flag still set. Wrap both CMC low-power entries with arch_pm_state_set_prepare() and arch_pm_state_set_finish() instead of hand-rolling the PRIMASK/BASEPRI sequence, drop the post-op unmask so the flag is cleared under the PM core lock, and remove the opt-out from both SoC symbols. The CMC power domain config is hoisted out of the switch case because two branches now use it. Add frdm_mcxw72 to the power_mgmt_soc platform list so the SoC has representative coverage. Validated on frdm_mcxw72 with tests/subsys/pm/power_mgmt_soc: 3 of 3 cases pass, entering both light and deep sleep with timer wake. Signed-off-by: Holt Sun <holt.sun@nxp.com>
pm_state_set() carried a FIXME explaining that the kernel masks with BASEPRI, which blocks wake IRQs of non-zero priority, and worked around it by setting PRIMASK and clearing BASEPRI by hand. Zephyr now provides exactly that sequence as arch_pm_state_set_prepare() and arch_pm_state_set_finish(), with the kernel retaining ownership of the IRQ restore. Use the architecture helpers around POWER_EnterSleep() and POWER_EnterDeepSleep(), drop the __enable_irq() from pm_state_exit_post_ops(), and remove the PM_STATE_SET_IRQ_UNLOCKED opt-out. The HAL preserves PRIMASK across its internal WFI and restores it after wake, so wrapping the power API call is sufficient. Validated on mimxrt595_evk/mimxrt595s/cm33 with tests/subsys/pm/power_mgmt_soc: 3 of 3 cases pass, entering both light and deep sleep with timer wake. Signed-off-by: Holt Sun <holt.sun@nxp.com>
pm_state_set() cleared BASEPRI and masked with PRIMASK before calling into the power library, and pm_state_exit_post_ops() cleared PRIMASK again, which required the PM_STATE_SET_IRQ_UNLOCKED opt-out. Wrap the sleep, deep-sleep, and power-down entries with arch_pm_state_set_prepare() and arch_pm_state_set_finish() instead, drop the post-op unmask, and remove the opt-out. All three HAL entry paths preserve PRIMASK across their internal WFI and restore it after wake, so wrapping the calls themselves is sufficient. Validated on frdm_mcxw23 with tests/subsys/pm/power_mgmt_soc: 3 of 3 cases pass, entering both light and deep sleep with timer wake. Signed-off-by: Holt Sun <holt.sun@nxp.com>
pm_state_set() reached low power through k_cpu_idle(), which performs its own IRQ unlock, and pm_state_exit_post_ops() finished with irq_unlock(0). Nesting an unlock inside the region the PM core keeps locked is what PM_STATE_SET_IRQ_UNLOCKED had to paper over. Replace k_cpu_idle() with a raw WFI wrapped by arch_pm_state_set_prepare() and arch_pm_state_set_finish(), drop the post-op unlock, and remove the opt-out. The XIP path keeps its __ramfunc wrapper so the flash prefetch drain and the WFI still execute from RAM, with the helpers called from outside that body. Rename the wrapper to wait_for_flash_prefetch_and_wfi() since it no longer calls the kernel idle entry. Validated on twr_ke18f with tests/subsys/pm/power_mgmt_soc: builds with CONFIG_XIP=y and the RAM wrapper resident in .ramfunc. Signed-off-by: Holt Sun <holt.sun@nxp.com>
Same shape as the RT5xx CM33 hooks: pm_state_set() carried the FIXME about BASEPRI masking wake IRQs and worked around it with a hand-written PRIMASK sequence, pm_state_exit_post_ops() unmasked, and the SoC opted out through PM_STATE_SET_IRQ_UNLOCKED. Use arch_pm_state_set_prepare() and arch_pm_state_set_finish() around POWER_EnterSleep() and POWER_EnterDeepSleep(), drop the post-op unmask, and remove the opt-out. The HAL preserves PRIMASK across its internal WFI and restores it after wake. Add mimxrt685_evk/mimxrt685s/cm33 to the power_mgmt_soc platform list so the SoC has representative coverage. Validated on mimxrt685_evk/mimxrt685s/cm33 with tests/subsys/pm/power_mgmt_soc: 3 of 3 cases pass, entering both light and deep sleep with timer wake. Signed-off-by: Holt Sun <holt.sun@nxp.com>
system_enter_sleep() cleared BASEPRI and masked with PRIMASK around its WFI, and pm_state_exit_post_ops() cleared PRIMASK before logging the previous CM7 and CM4 GPC modes, so that reporting ran with interrupts already unmasked. Wrap the WFI with arch_pm_state_set_prepare() and arch_pm_state_set_finish(), drop the post-op unmask so the GPC state reporting stays under the PM core lock, and remove the PM_STATE_SET_IRQ_UNLOCKED opt-out. Add mimxrt1170_evk/mimxrt1176/cm7 to the power_mgmt_soc platform list so the SoC has representative coverage. Validated on mimxrt1170_evk rev B with tests/subsys/pm/power_mgmt_soc: 3 of 3 cases pass, entering both light and deep sleep with timer wake. Signed-off-by: Holt Sun <holt.sun@nxp.com>
The runtime-idle state reached low power through k_cpu_idle(), which performs its own IRQ unlock inside the region the PM core keeps locked. That is why SOC_LPC55S69_CPU0 selected PM_STATE_SET_IRQ_UNLOCKED. Replace it with a raw WFI wrapped by arch_pm_state_set_prepare() and arch_pm_state_set_finish(), and remove the opt-out. Only the CPU0 symbol is touched; the rest of the series is unaffected. Add lpcxpresso55s69/lpc55s69/cpu0 to the power_mgmt_soc platform list. The test references a cpu0 node label, which this board's devicetree does not define, so add a board overlay supplying it the same way other power management tests do. Validated on lpcxpresso55s69/lpc55s69/cpu0 with tests/subsys/pm/power_mgmt_soc: 3 of 3 cases pass with timer wake. Signed-off-by: Holt Sun <holt.sun@nxp.com>
pm_state_set() masked with PRIMASK and cleared BASEPRI by hand, with a comment explaining that BASEPRI masking prevents the core from waking out of WFI. pm_state_exit_post_ops() then cleared PRIMASK after restoring the SCMI CPU RUN mode, which required the PM_STATE_SET_IRQ_UNLOCKED opt-out. Factor the three SCMI sleep modes onto one enter_low_power() helper that sets the sleep mode and then wraps the WFI with arch_pm_state_set_prepare() and arch_pm_state_set_finish(). The SCMI wake-mask setup and the CPU RUN restoration stay where they were, now running entirely under the PM core lock, and the opt-out is removed. Validated on imx95_evk/mimx9596/m7: builds with the IRQ-locked default. Hardware validation of the SCMI wake mask and CPU mode transitions is still outstanding. Signed-off-by: Holt Sun <holt.sun@nxp.com>
These hooks are the i.MX95 M7 pattern, including the same hand-written PRIMASK workaround in pm_state_set() and the PRIMASK clear in pm_state_exit_post_ops(), so apply the same migration: one enter_low_power() helper wrapping the WFI with arch_pm_state_set_prepare() and arch_pm_state_set_finish(), SCMI wake-mask and CPU RUN restoration left under the PM core lock, and PM_STATE_SET_IRQ_UNLOCKED removed. Add imx952_evk/mimx9529/m7 to the power_mgmt_soc platform list. Validated on imx952_evk/mimx9529/m7: builds with the IRQ-locked default. Hardware validation of the SCMI wake mask and CPU mode transitions is still outstanding. Signed-off-by: Holt Sun <holt.sun@nxp.com>
Two things kept this SoC on the legacy IRQ-unlocked path. pm_state_set() cleared BASEPRI and masked with PRIMASK by hand, and pm_state_exit_post_ops() called gpio_mcux_lpc_trigger_cb() directly after a standby pin wake. The second one is not a mechanical fix: that call dispatches user callbacks synchronously, before the PM exit notifier, sys_clock_idle_exit(), and the CPU PM state teardown have run. Wrap the raw WFI and every returning POWER_EnterPowerMode() call with arch_pm_state_set_prepare() and arch_pm_state_set_finish(), and coalesce the wake pin mask into an atomic before handing it to a static system workqueue item, so the user callback runs after PM resume completes rather than from inside the post-op. The handler exchanges the pins out of the atomic, which preserves exactly-once delivery even if another wake lands while the work is still pending. The workqueue path needs multithreading, so keep PM_STATE_SET_IRQ_UNLOCKED and the previous synchronous dispatch under "if !MULTITHREADING" rather than forcing multithreading on. A single-threaded build therefore keeps its old behavior and still links. Validated on rd_rw612_bga with tests/subsys/pm/power_mgmt_soc: 3 of 3 cases pass, entering both light and deep sleep with timer wake. Also build-checked with CONFIG_MULTITHREADING=n. Signed-off-by: Holt Sun <holt.sun@nxp.com>
The Kconfig option FORCE_NO_ASSERT is going to be deprecated with the introduction of zassert.h. The FORCE_NO_ASSERT option was made to override the command line option of -D__ASSERT_ON=x, this command line option will now have no effect, thus the kconfig option is no longer needed. Setting the CONFIG_ASSERT option to 'n' is enough to disable asserts in the code. Signed-off-by: Måns Ansgariusson <mansgariusson@gmail.com>
The CONFIG_ASSERT_LEVEL=2 and CONFIG_ASSERT_VERBOSE=y are default values. Removing them to avoid build warnings when these options are deprecated. Signed-off-by: Måns Ansgariusson <mansgariusson@gmail.com>
The CONFIG_ASSERT_LEVEL=2 and CONFIG_ASSERT_VERBOSE=y are already the default values. Removing them from explicit configuration files to avoid build warnings when these options are deprecated in the future. Signed-off-by: Måns Ansgariusson <mansgariusson@gmail.com>
The CONFIG_ASSERT_VERBOSE and ASSERT_LEVEL=2 are already the default values. Removing them to prevent bulid warnings when these kconfigs are deprecated in the future. Signed-off-by: Måns Ansgariusson <mansgariusson@gmail.com>
The ASSERT_LEVEL=2 & ASSERT_VERBOSE=y are the default values. Removing them to avoid future build warnings when these Kconfig values are deprecated. Signed-off-by: Måns Ansgariusson <mansgariusson@gmail.com>
The ASSERT_LEVEL=2 and ASSERT_VERBOSE=y are the default options. Remove them to avoid future deprecation warnings. Signed-off-by: Måns Ansgariusson <mansgariusson@gmail.com>
Every heading used the same 24px margin, so the gap above an h5 was identical to the gap above an h2. The h2 and h3 rails came from the note admonition palette and measure 1.54:1 and 1.17:1 against the page in dark mode, where neither is visible; h4 and h5 carried an 8px transparent border, and h5 was set at weight 100, lighter than the body text it introduces. Give the levels a real spacing scale (56/40/30/26px), move the rails to dedicated tokens measured against the content background, and replace the invisible borders with a short marker on h4 and a plain small heading on h5. Where consecutive leaf sections are a list of entries - a shell command or a devicetree filter expression per section - separate them with a rule, and give an h5 that is nothing but an identifier the same colour a signature would give it. Also qualify the heading-code rule with code.literal: its color: inherit was losing on specificity to .rst-content code.literal, which is why code identifiers used as headings rendered in the inline-literal red. Verified against the rendered DOM of the Bluetooth Mesh Shell reference, the most deeply nested page in the docs (63 h4, 142 h5). Assisted-by: Claude:opus-5 Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Stock RTD styles every classed definition term as an API signature, and custom.css layered a pill, a floating dot and a code fill on top of it for every term in the documentation. A glossary entry, a "Purpose:" label and a CMake argument all rendered alike, and a dl with no class kept the full API chrome. Replace that with one set: a stacked word term by default, a two-column grid for the short repeated labels that field lists and colon-terminated definition lists both express, and a glossary that keeps the full measure for its paragraph definitions. The base rule puts its exclusions in :where() so they cost no specificity and the component rules that follow can be written normally instead of outranking it by accident. Sidebar cards stack instead, since two columns in a 215px card spend more than half the width on labels; the board card was clipping its own name. Measured on the Twister reference: the Expressions section drops from 2009px to 1367px and stops drawing "Purpose:" as an 807px bar. Assisted-by: Claude:opus-5 Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
A signature block carried four devices for one job: a 3px stock RTD tab border, a rounded-right pill, a floating dot and a nesting rail. The pill shrink-wrapped its text, so every block ended somewhere different down the page, and the permalink inherited RTD's #404040, which is 1.48:1 against the dark signature fill. Use one device instead: a bordered bar the width of the column, the body indented beneath it, and a rule between entries. A nested signature drops the fill, so a class reads as one object with a list of members rather than a stack of equal boxes. Key the rule on dt.sig, the marker Sphinx puts on every object description, rather than on domain names, so it covers py, cmake, kconfig, c and cpp instead of needing a selector each. Assisted-by: Claude:opus-5 Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The CMake domain runs its signatures through Pygments, so they land in a .highlight wrapper and pick up the theme's token colors. Other domains emit the same Pygments class names plus semantic ones, but without that wrapper, so a Python signature rendered monochrome. Map them onto the same variables, so a name is the same color whether it is a CMake command or a Python class. RTD also hard-codes color: #000 on .sig-name and .descname, which is invisible on a dark signature fill. Parameter names stay in the body color on purpose: --highlight-type2-color is a near neighbour of --highlight-type-color in this palette, so coloring them would only muddy the annotation beside them. Assisted-by: Claude:opus-5 Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The note under board_set_runner() was written as "NOTE:" followed by lines indented deeper than it, which docutils parses as a definition list: the whole first sentence became a 66-character definition term, and the rest its definition. Use a note directive instead, so it renders as an admonition and reads as one paragraph. Assisted-by: Claude:opus-5 Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add support for xG29-RB4413A (BRD4413A, EFR32MG29B230F1024CM40, +6 dBm boost DCDC). Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Move xg29_rb4412a, xg29_rb4413a, and bg29_rb4420a into boards/silabs/radio_boards/xg29 so they share board.cmake, Kconfig.defconfig, and the J-Link / Commander runners. Take the opportunity to also add xg29_rb4412a picture. Signed-off-by: Martin Hoff <martin.hoff@silabs.com> Assisted-by: Cursor:Grok 4.6
Extract the DTS nodes and pinctrl groups shared by the xG29 radio boards into common include files. Signed-off-by: Martin Hoff <martin.hoff@silabs.com> Assisted-by: codex:gpt-5.6-terra
Add copyright and SPDX headers to the xG29 radio board metadata, documentation, configuration, and OpenOCD files. Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Since this a "get" function that does not, and never should, modify the provided advertising set pointer, modify it to be const. Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
The NXP MCX N family integrates the same DWC Ethernet QoS controller as the MCXE31X series, but uses different clocks, PHY interface selection and interrupt lines. Extend the driver to also support the MCX N family by guarding the SoC-specific parts with CONFIG_SOC_FAMILY_MCXN. Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Add frdm_mcxn947/mcxn947/cpu0 to this test and disable CONFIG_ETH_NXP_ENET_QOS so the board is built against the generic dwc_mac driver. Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Add frdm_mcxn947/mcxn947/cpu0 to the dwmac test and disable CONFIG_ETH_NXP_ENET_QOS so the board is built against the generic dwc_mac driver. Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
The NXP MCX A family integrates the same DWC Ethernet QoS controller as the MCX N series, but uses different PHY interface selection. Extend the driver to also support the MCX A family by guarding the SoC-specific parts with CONFIG_SOC_FAMILY_MCXA. Add the PTP clock source and a ptp_clock child node to the MCXA5x ethernet controller node, so the dwc_mac PTP clock driver can be used. ETH_NXP_ENET_QOS does not support PTP for the MCX A family, so use the dwc_mac driver by default for the MCX A family, if PTP support is required. Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Add frdm_mcxa577 and frdm_mcxa577/mcxa577/t1s to the dwmac test. Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Replace direct NVIC pending-state calls with k_irq_set_pending()/ k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on cmsis_core.h where nothing else needed it. Assisted-by: Claude:claude-opus-5 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/ k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on cmsis_core.h where nothing else needed it. Assisted-by: Claude:claude-opus-5 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/ k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on cmsis_core.h where nothing else needed it. Assisted-by: Claude:claude-opus-5 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/ k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on cmsis_core.h where nothing else needed it. Assisted-by: Claude:claude-opus-5 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The driver always selected the XTAL reference, which only exists on v3.0 and newer silicon. On v1.3 the clock source switch falls through to abort() and the boot panics before any output. Select the legacy PLL_F20M source and its 20 MHz rate when the minimum supported revision is below v3.0. Assisted-by: Claude:opus-5 Signed-off-by: Jonathan Beri <jmberi@gmail.com> Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The controller reset faults if it reaches the peripheral before the bus clock enable has taken effect, and whether it does depends on unrelated code layout. Poll the clock state before issuing the reset and fail the setup if it never comes up. Assisted-by: Claude:opus-5 Signed-off-by: Jonathan Beri <jmberi@gmail.com> Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Added STM32CubeProgrammer as an SWD flashing option for the Weact Blackpill V.2 (STM32F411CEU6) Now we can use a stlink to program this board Tested with the samples/basic/blinky program by flashing multiple time with power cycle Signed-off-by: Asraful Islam Taj <asraful.islam.taj@gmail.com>
The default configuration for boards should not enable everything and anything that is supported for that board but only the base features to maintain a smaller footprint. The drivers are enabled where they are required (e.g. crypto and entropy tests) Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
The default configuration for boards should not enable everything and anything that is supported for that board but only the base features to maintain a smaller footprint. The drivers are enabled where they are required (e.g. crypto and entropy tests) Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
The DevKit carries a multicolor LED and a five position navigation joystick. Wire up the three LED channels and all five joystick switches, so that the blinky and button samples run on the board out of the box. The DesignWare GPIO driver does not implement both edge triggering, which the interrupt driven mode of the GPIO keys driver requires, so the keys are polled instead. Polling can be dropped once the driver gains both edge support. Signed-off-by: Silesh C V <silesh@alifsemi.com>
The Balletto SoCs use the Synopsys DesignWare GPIO controller, with one eight pin controller instance per port and one interrupt line per pin. Add GPIO0 to GPIO8 and LPGPIO, which is the full set the B1 carries. LPGPIO sits in the Always-On domain and is only two pins wide. The interrupt lines are described here for completeness, but the hardware requires the GPIO debounce logic to be enabled for interrupt detection to work correctly, which in turn needs the debounce clock running. That clock is off after reset and nothing turns it on, so enabling it is left to a follow-up change. Signed-off-by: Silesh C V <silesh@alifsemi.com>
The DevKit carries a multicolor LED and a five position navigation joystick. Wire up the three LED channels and all five joystick switches, so that the blinky and button samples run on the board out of the box. The DesignWare GPIO driver does not implement both edge triggering, which the interrupt driven mode of the GPIO keys driver requires, so the keys are polled instead. Polling can be dropped once the driver gains both edge support. Signed-off-by: Silesh C V <silesh@alifsemi.com>
I cleaned this up while reading the documentation. Signed-off-by: Remo Senekowitsch <remo@buenzli.dev>
I cleaned this up while reading the documentation. Signed-off-by: Remo Senekowitsch <remo@buenzli.dev>
settings_file_save_and_compress() stored -EIO on a failed fs_close() but then returned 0, so settings_save() reported success after a failed compress. Unlink the leftover .cmp file when the original settings file closed successfully, matching the rollback path. Signed-off-by: Dhruv Menon <dhruvmenon1104@gmail.com>
With CONFIG_UART_NS16550_DW8250_DW_APB, uart_ns16550_irq_tx_ready() reports the transmitter ready whenever USR.TFNF is set, i.e. as soon as the TX FIFO has room, while uart_ns16550_fifo_fill() writes up to fifo_size bytes without checking how much room there actually is. When the ISR runs with data left in the FIFO, the excess bytes are written to a full FIFO and lost. On the Silicon Labs SiWx917 (ulpuart, ns16550 with the DW8250 option) this happens right after boot and about once per thousand fills under load: the UART ISR is entered with no interrupt pending (IIR reads 0xC1) while the FIFO still holds 15 of the 16 bytes of the previous fill, so the fill loses up to 15 bytes. With the Bluetooth monitor in interrupt-driven mode on that UART the stream had a truncated New Index frame after every boot and lost 15-byte chunks every 1-2 seconds, while the polled mode was unaffected. Stop the DW8250 fill loop as soon as USR.TFNF clears, so that the driver never writes more than the FIFO can take and returns the number of bytes it actually accepted. Fixes zephyrproject-rtos#117777 Assisted-by: Claude:claude-fable-5 Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Add DEVICE_DT_GET_COMMA helper macro to include/zephyr/device.h to easily get a device pointer followed by a comma when expanding devicetree foreach iterators like DT_FOREACH_STATUS_OKAY. Update samples, drivers, and tests to use the common definition. Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com> Assisted-by: Antigravity:gemini-1.5-pro
The deinit toggles were missing when adding the SoC Signed-off-by: Camille BAUD <mail@massdriver.space>
PTP port timers expire in interrupt context, while eventfd writes acquire the file descriptor mutex. Defer timeout notifications to the system workqueue so eventfd signaling runs from thread context. Keep timeout bits in the ports as the source of pending events, allowing multiple timer expiries to share a queued wakeup. Add coverage that verifies the timeout path submits work before writing the eventfd. Signed-off-by: Philipp Steiner <philipp.steiner1987@gmail.com>
With the commit c3109b9 ("usb: device_next: cdc_acm: rx throughput improvements"), the CDC implementation queues as many buffers as are available. This may trigger an error log, "<err> udc_rpi_pico: Endpoint 0x01 busy". There is nothing wrong with the driver, it is just that another transfer is queued while an endpoint is busy. Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
modem_cellular_chat_on_cxreg() matches "+CREG: " and "+CGREG: " and files everything else into registration_status_lte. The handler is public and MODEM_CELLULAR_COMMON_UNSOL_MATCHES is meant to be extended by vendor drivers, so a driver that adds a "+C5GREG: " match ends up writing the 5GS registration state into the LTE slot. That is wrong in both directions on a module registered on 5G SA. Such a module answers "+CEREG: <n>,0" and "+C5GREG: <n>,1", so whichever of the two arrives last decides the state. The periodic script reads +CEREG?, which overwrites the good status with "not registered", modem_cellular_is_registered() turns false, and the driver tears the link down once per periodic cycle. Give 5GS its own registration_status_5g, dispatch "+C5GREG: " to it, clear it along with the others, and treat the modem as registered when any of the four accesses is registered home or roaming. This also lets cellular_get_registration_status() answer for CELLULAR_ACCESS_TECHNOLOGY_NR_5G_CN and CELLULAR_ACCESS_TECHNOLOGY_NG_RAN, which the driver previously had to report as -ENODATA. Signed-off-by: Ahnaf Shahriar <shahriarahnaf007@gmail.com>
Add a test for modem_cellular_chat_on_cxreg(), which is part of the cellular driver's public interface for vendor drivers. The test feeds "+C5GREG: <n>,<stat>" and "+CEREG: <n>,<stat>" answers into the handler and checks that they land in their own registration status, and that a modem registered on 5GS is not reported as deregistered when the periodic +CEREG? read answers "not registered". A deregistration with no other access registered is checked as well so that the negative case cannot pass by accident. Signed-off-by: Ahnaf Shahriar <shahriarahnaf007@gmail.com>
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The cellular driver selects MODEM_BACKEND_UART and UART_USE_RUNTIME_CONFIGURE, which depend on SERIAL and a UART API. Enable them so the test configures on native_sim, as the sibling cellular tests do. Signed-off-by: Ahnaf Shahriar <shahriarahnaf007@gmail.com>
…test UART_ASYNC_API is silently dropped on platforms whose UART does not support it, such as the PL011 on mps2/an385 and qemu_cortex_m3, which brings back the MODEM_BACKEND_UART dependency error. The interrupt driven API is available on native_sim and the Cortex-M targets alike. Signed-off-by: Ahnaf Shahriar <shahriarahnaf007@gmail.com>
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Review copy, scoped to this fork only. Not intended to be opened against zephyrproject-rtos/zephyr yet.
modem_cellular_chat_on_cxreg()files+CREG/+CGREG/anything else intoregistration_status_lte, andMODEM_CELLULAR_COMMON_UNSOL_MATCHESis meant to be extended by vendor drivers — so a driver adding a+C5GREGmatch writes 5GS state into the LTE slot. On a 5G-SA-registered modem that's wrong both ways:+CEREG: <n>,0and+C5GREG: <n>,1race, the periodic+CEREG?overwrites the good status,modem_cellular_is_registered()goes false, and the driver tears the link down every cycle.Give 5GS its own
registration_status_5g, dispatch+C5GREGto it, and treat the modem as registered if any of the four accesses is home/roaming. Also fixescellular_get_registration_status()forNR_5G_CN/NG_RAN, previously-ENODATA.Found running the driver against a simulated 5G-SA modem: link came up, then dropped on the first periodic script.
Note: no in-tree
+C5GREGproducer exists yet — reachable only from a vendor driver extending the common match table, which is what it's for.Verified:
west twister -p mps2/an385 -T tests/drivers/modem/modem_cellular— 3/3 pass; positive control for a real deregistration still passes. checkpatch clean.