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14 changes: 14 additions & 0 deletions tools/topology/topology2/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -7,9 +7,11 @@ add_custom_target(topologies2 ALL
# Create directory structure to be provided for deployment

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@MaurizioCasciano Thanks for the new PR! Can you check the git commit message formatting? We use Linux kernel style formatting (wrap lines at 72 chars). Rest looks good.

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Fixed in 050cf8e. The commit message is now wrapped at 72 columns; the source tree is unchanged. Thanks!

COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/target/sof-ipc4-tplg
COMMAND ${CMAKE_COMMAND} -E create_symlink sof-ipc4-tplg ${CMAKE_CURRENT_BINARY_DIR}/target/sof-ace-tplg
COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/target/sof-tplg
COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/target/development
# copy the topology files only to target, preserving symbolic links
COMMAND sh -c "cp -a production/*.tplg \"${CMAKE_CURRENT_BINARY_DIR}/target/sof-ipc4-tplg/\""
COMMAND sh -c "cp -a production/ipc3/*.tplg \"${CMAKE_CURRENT_BINARY_DIR}/target/sof-tplg/\""
COMMAND sh -c "cp -a development/*.tplg \"${CMAKE_CURRENT_BINARY_DIR}/target/development/\""
)

Expand Down Expand Up @@ -37,6 +39,18 @@ add_custom_target(abi_target
DEPENDS abi.conf
)

# Atom platforms use IPC3 even when the source topology is written using the
# topology2 object model. Keep a separate ABI manifest so IPC3 and IPC4 output
# can be built together without changing the existing production topologies.
add_custom_command(OUTPUT abi-ipc3.conf
COMMAND > abi-ipc3.conf ${CMAKE_CURRENT_SOURCE_DIR}/get_abi.sh
${SOF_ROOT_SOURCE_DIRECTORY} "ipc3"
DEPENDS ${SOF_ROOT_SOURCE_DIRECTORY}/src/include/kernel/abi.h
)
add_custom_target(abi_ipc3_target
DEPENDS abi-ipc3.conf
)

add_dependencies(topologies2 topology2_dev topology2_prod)
add_subdirectory(development)
add_subdirectory(production)
17 changes: 17 additions & 0 deletions tools/topology/topology2/README.md
Original file line number Diff line number Diff line change
Expand Up @@ -397,10 +397,27 @@ Select the cmake file matching the target platform generation:

| Platform | CMake Target File |
|---|---|
| IPC3 | `tplg-targets-ipc3.cmake` |
| Tiger Lake / Alder Lake | `tplg-targets-cavs25.cmake` |
| Meteor Lake | `tplg-targets-ace1.cmake` |
| Lunar Lake | `tplg-targets-ace2.cmake` |
| Panther Lake | `tplg-targets-ace3.cmake` |
| HDA generic | `tplg-targets-hda-generic.cmake` |

### IPC3 topology targets

Topology2 source files can also target firmware that uses IPC3. Register IPC3
targets in `production/tplg-targets-ipc3.cmake`; they are built with a separate
IPC3 ABI manifest and installed under `target/sof-tplg` instead of the IPC4/ACE
topology directory.

Build an individual registered IPC3 target with:

```bash
cmake --build . --target topology2_prod_ipc3_OUTPUT_NAME
```

Replace `OUTPUT_NAME` with the target's output name from
`tplg-targets-ipc3.cmake`.

Development and testing topologies go in `development/tplg-targets.cmake`.
334 changes: 334 additions & 0 deletions tools/topology/topology2/cht-rt5677.conf
Original file line number Diff line number Diff line change
@@ -0,0 +1,334 @@
# SPDX-License-Identifier: BSD-3-Clause

<searchdir:include>
<searchdir:include/common>
<searchdir:include/components>
<searchdir:include/dais>
<searchdir:include/pipelines>
<searchdir:platform>
<searchdir:platform/intel>

<vendor-token.conf>
<tokens.conf>
<manifest.conf>
<data.conf>
<pcm.conf>
<pcm_caps.conf>
<fe_dai.conf>
<route.conf>
<common_definitions.conf>
<virtual.conf>
<ipc3/volume-playback.conf>
<ipc3/mixer-volume-dai-playback.conf>
<ipc3/volume-dai-capture.conf>
<ssp.conf>
<intel/cht-hw-config.conf>

Define {
# Cherry Trail uses the first-generation SSP configuration blob and IPC3.
SSP_BLOB_VERSION $SSP_BLOB_VERSION_1_0
}

# The machine driver connects the RT5677 AIF routes through these platform
# widgets. They mirror the widgets exposed by the legacy Cherry Trail topology.
Object.Widget.virtual [
{ name "codec_out0" type "output" index 1 }
{ name "codec_out1" type "output" index 2 }
{ name "codec_in0" type "input" index 3 }
{ name "codec_in1" type "input" index 4 }
{ name "ssp2 Rx" type "input" index 5 }
{ name "ssp2 Tx" type "output" index 6 }
]

# SSP2 carries the RT5677 AIF1 stream. The bit and frame clocks are driven by
# the Cherry Trail SSP; the codec consumes both clocks.
Object.Dai.SSP [
{
id 0
dai_index 2
direction "duplex"
name "SSP2-Codec"
default_hw_config_id 0
sample_bits 24

Object.Base.hw_config.1 {
name "SSP2"
id 0
format "DSP_B"
mclk "codec_mclk_in"
mclk_freq 19200000
bclk "codec_consumer"
bclk_freq 4800000
# Match SND_SOC_DAIFMT_IB_NF in the machine driver:
# invert BCLK while leaving the frame clock non-inverted.
bclk_invert "true"
fsync "codec_consumer"
fsync_freq 48000
fsync_invert "false"
tdm_slots 4
tdm_slot_width 25
# The frame has four slots, but the stereo stream uses slots 0 and 1.
# IPC3 derives the DAI channel count from these active-slot masks.
tx_slots 3
rx_slots 3
}
}
]

Object.Pipeline {
ipc3-mixer-volume-dai-playback.1 {
index 1
format "s24le"
channels 2
dai_type "SSP"
dai_index 2
periods 2
# Two 1 ms periods at 48 kHz, stereo, four bytes per sample.
size 768

Object.Widget.pipeline.1 {
stream_name "dai.SSP.2.playback"
priority 1
core 0
frames 0
mips 5000
}
Object.Widget.dai.playback {
format "s24le"
stream_name "SSP2-Codec"
core_id 0
}
Object.Widget.pga.1 {
ramp_step_ms 20
Object.Control.mixer.1 {
name "1 Master Playback Volume"
Object.Base.tlv.vtlv_m64s2 {
Object.Base.scale.m64s2 {}
}
}
}
Object.Base.route.4 {
source "buffer.1.2"
sink "dai.SSP.2.playback"
}
}

ipc3-volume-dai-capture.2 {
index 2
format "s32le"
channels 2
dai_type "SSP"
dai_index 2
periods 2
# Two 1 ms periods at 48 kHz, stereo, four bytes per sample.
size 768

Object.Widget.pipeline.1 {
stream_name "dai.SSP.2.capture"
priority 0
core 0
frames 0
mips 5000
}
Object.Widget.dai.capture {
format "s24le"
stream_name "SSP2-Codec"
core_id 0
}
Object.Widget.host.capture {
stream_name "Low Latency Capture 0"
core_id 0
}
Object.Widget.pga.1 {
ramp_step_ms 250
Object.Control.mixer.1 {
name "2 PCM 0 Capture Volume"
max 40
Object.Base.channel.1 {
name "fl"
reg 0
shift 0
}
Object.Base.channel.2 {
name "fr"
reg 0
shift 1
}
Object.Base.tlv.vtlv_m64s2 {
Object.Base.scale.m64s2 {}
}
}
}
Object.Base.route.4 {
source "dai.SSP.2.capture"
sink "buffer.2.1"
}
}

ipc3-volume-playback.3 {
index 3
format "s32le"
channels 2
period 1000
time_domain "dma"

Object.Widget.pipeline.1 {
priority 0
core 0
frames 0
mips 100000
stream_name "dai.SSP.2.playback"
}
Object.Widget.host.playback {
stream_name "Playback 0"
core_id 0
period_sink_count 0
period_source_count 2
}
Object.Widget.pga.1 {
ramp_step_ms 20
period_sink_count 2
period_source_count 2
Object.Control.mixer.1 {
name "3 Playback Volume"
Object.Base.tlv.vtlv_m64s2 {
Object.Base.scale.m64s2 {}
}
}
}
Object.Widget.buffer.1 {
caps "ram_dma_cache"
# IPC3 needs SOF_TKN_BUF_SIZE serialized explicitly. An object
# value takes precedence over the class's automatic size value.
size 768
}
Object.Widget.buffer.2 {
caps "ram_dma_cache"
size 768
}
}

ipc3-volume-playback.4 {
index 4
format "s32le"
channels 2
period 5000
time_domain "dma"

Object.Widget.pipeline.1 {
priority 0
core 0
frames 0
mips 100000
stream_name "dai.SSP.2.playback"
}
Object.Widget.host.playback {
stream_name "Playback 1"
core_id 0
period_sink_count 0
period_source_count 2
}
Object.Widget.pga.1 {
ramp_step_ms 20
period_sink_count 2
period_source_count 2
Object.Control.mixer.1 {
name "4 Playback Volume"
Object.Base.tlv.vtlv_m64s2 {
Object.Base.scale.m64s2 {}
}
}
}
Object.Widget.buffer.1 {
caps "ram_dma_cache"
# Five milliseconds at 48 kHz, two channels and four bytes per
# sample, with two periods: 5 ms * 48 * 2 * 4 * 2 = 3840.
size 3840
}
Object.Widget.buffer.2 {
caps "ram_dma_cache"
size 3840
}
}
}

# Both playback front ends feed the low-latency SSP2 mixer.
Object.Base.route [
{ source "buffer.3.2" sink "ipc3-mixer.1.1" }
{ source "buffer.4.2" sink "ipc3-mixer.1.1" }
]

Object.PCM.pcm [
{
name "PCM"
id 0
direction "duplex"

Object.Base.fe_dai.1 {
name "PCM 0"
}
Object.PCM.pcm_caps.playback {
direction "playback"
name "Playback 0"
formats "S16_LE,S24_LE,S32_LE"
rates "48000"
rate_min 48000
rate_max 48000
channels_min 2
channels_max 2
# Match the proven Cherry Trail IPC3 topology instead of the
# much larger generic topology2 PCM capability defaults.
periods_min 2
periods_max 16
period_size_min 192
period_size_max 16384
buffer_size_min 65536
buffer_size_max 65536
}
Object.PCM.pcm_caps.capture {
direction "capture"
name "Low Latency Capture 0"
formats "S16_LE,S24_LE,S32_LE"
rates "48000"
rate_min 48000
rate_max 48000
channels_min 2
channels_max 2
periods_min 2
# The low-latency capture path supports fewer queued periods
# than playback in the legacy Cherry Trail topology.
periods_max 4
period_size_min 192
period_size_max 16384
buffer_size_min 65536
buffer_size_max 65536
}
}
{
name "PCM Deep Buffer"
id 1
direction "playback"

Object.Base.fe_dai.1 {
name "PCM Deep Buffer 1"
}
Object.PCM.pcm_caps.playback {
direction "playback"
name "Playback 1"
formats "S16_LE,S24_LE,S32_LE"
rates "48000"
rate_min 48000
rate_max 48000
channels_min 2
channels_max 2
# Keep userspace constraints identical for the low-latency and
# deep-buffer playback PCMs, as on the legacy CHT topology.
periods_min 2
periods_max 16
period_size_min 192
period_size_max 16384
buffer_size_min 65536
buffer_size_max 65536
}
}
]
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